2 * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
3 * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
5 * 2.6 port by Matt Porter <mporter@kernel.crashing.org>
7 * The documentation describes this as an SMBus controller, but it doesn't
8 * understand any of the SMBus protocol in hardware. It's really an I2C
9 * controller that could emulate most of the SMBus in software.
11 * This is just a skeleton adapter to use with the Au1550 PSC
12 * algorithm. It was developed for the Pb1550, but will work with
13 * any Au1550 board that has a similar PSC configuration.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 #include <linux/delay.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/init.h>
34 #include <linux/errno.h>
35 #include <linux/i2c.h>
37 #include <asm/mach-au1x00/au1000.h>
38 #include <asm/mach-pb1x00/pb1550.h>
39 #include <asm/mach-au1x00/au1xxx_psc.h>
41 #include "i2c-au1550.h"
44 wait_xfer_done(struct i2c_au1550_data *adap)
48 volatile psc_smb_t *sp;
50 sp = (volatile psc_smb_t *)(adap->psc_base);
52 /* Wait for Tx FIFO Underflow.
54 for (i = 0; i < adap->xfer_timeout; i++) {
55 stat = sp->psc_smbevnt;
57 if ((stat & PSC_SMBEVNT_TU) != 0) {
59 sp->psc_smbevnt = PSC_SMBEVNT_TU;
70 wait_ack(struct i2c_au1550_data *adap)
73 volatile psc_smb_t *sp;
75 if (wait_xfer_done(adap))
78 sp = (volatile psc_smb_t *)(adap->psc_base);
80 stat = sp->psc_smbevnt;
83 if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
90 wait_master_done(struct i2c_au1550_data *adap)
94 volatile psc_smb_t *sp;
96 sp = (volatile psc_smb_t *)(adap->psc_base);
98 /* Wait for Master Done.
100 for (i = 0; i < adap->xfer_timeout; i++) {
101 stat = sp->psc_smbevnt;
103 if ((stat & PSC_SMBEVNT_MD) != 0)
112 do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd)
114 volatile psc_smb_t *sp;
117 sp = (volatile psc_smb_t *)(adap->psc_base);
119 /* Reset the FIFOs, clear events.
121 stat = sp->psc_smbstat;
122 sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR;
125 if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) {
126 sp->psc_smbpcr = PSC_SMBPCR_DC;
129 stat = sp->psc_smbpcr;
131 } while ((stat & PSC_SMBPCR_DC) != 0);
135 /* Write out the i2c chip address and specify operation
141 /* Put byte into fifo, start up master.
143 sp->psc_smbtxrx = addr;
145 sp->psc_smbpcr = PSC_SMBPCR_MS;
153 wait_for_rx_byte(struct i2c_au1550_data *adap, u32 *ret_data)
157 volatile psc_smb_t *sp;
159 if (wait_xfer_done(adap))
162 sp = (volatile psc_smb_t *)(adap->psc_base);
164 j = adap->xfer_timeout * 100;
170 stat = sp->psc_smbstat;
172 if ((stat & PSC_SMBSTAT_RE) == 0)
177 data = sp->psc_smbtxrx;
185 i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
190 volatile psc_smb_t *sp;
195 /* A read is performed by stuffing the transmit fifo with
196 * zero bytes for timing, waiting for bytes to appear in the
197 * receive fifo, then reading the bytes.
200 sp = (volatile psc_smb_t *)(adap->psc_base);
203 while (i < (len-1)) {
206 if (wait_for_rx_byte(adap, &data))
213 /* The last byte has to indicate transfer done.
215 sp->psc_smbtxrx = PSC_SMBTXRX_STP;
217 if (wait_master_done(adap))
220 data = sp->psc_smbtxrx;
227 i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
232 volatile psc_smb_t *sp;
237 sp = (volatile psc_smb_t *)(adap->psc_base);
240 while (i < (len-1)) {
242 sp->psc_smbtxrx = data;
249 /* The last byte has to indicate transfer done.
252 data |= PSC_SMBTXRX_STP;
253 sp->psc_smbtxrx = data;
255 if (wait_master_done(adap))
261 au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
263 struct i2c_au1550_data *adap = i2c_adap->algo_data;
267 for (i = 0; !err && i < num; i++) {
269 err = do_address(adap, p->addr, p->flags & I2C_M_RD);
272 if (p->flags & I2C_M_RD)
273 err = i2c_read(adap, p->buf, p->len);
275 err = i2c_write(adap, p->buf, p->len);
278 /* Return the number of messages processed, or the error code.
286 au1550_func(struct i2c_adapter *adap)
291 static struct i2c_algorithm au1550_algo = {
292 .master_xfer = au1550_xfer,
293 .functionality = au1550_func,
297 * registering functions to load algorithms at runtime
298 * Prior to calling us, the 50MHz clock frequency and routing
299 * must have been set up for the PSC indicated by the adapter.
302 i2c_au1550_add_bus(struct i2c_adapter *i2c_adap)
304 struct i2c_au1550_data *adap = i2c_adap->algo_data;
305 volatile psc_smb_t *sp;
308 i2c_adap->algo = &au1550_algo;
310 /* Now, set up the PSC for SMBus PIO mode.
312 sp = (volatile psc_smb_t *)(adap->psc_base);
313 sp->psc_ctrl = PSC_CTRL_DISABLE;
315 sp->psc_sel = PSC_SEL_PS_SMBUSMODE;
318 sp->psc_ctrl = PSC_CTRL_ENABLE;
321 stat = sp->psc_smbstat;
323 } while ((stat & PSC_SMBSTAT_SR) == 0);
325 sp->psc_smbcfg = (PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 |
326 PSC_SMBCFG_DD_DISABLE);
328 /* Divide by 8 to get a 6.25 MHz clock. The later protocol
329 * timings are based on this clock.
331 sp->psc_smbcfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
332 sp->psc_smbmsk = PSC_SMBMSK_ALLMASK;
335 /* Set the protocol timer values. See Table 71 in the
336 * Au1550 Data Book for standard timing values.
338 sp->psc_smbtmr = PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \
339 PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \
340 PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \
341 PSC_SMBTMR_SET_CH(15);
344 sp->psc_smbcfg |= PSC_SMBCFG_DE_ENABLE;
346 stat = sp->psc_smbstat;
348 } while ((stat & PSC_SMBSTAT_DR) == 0);
350 return i2c_add_adapter(i2c_adap);
355 i2c_au1550_del_bus(struct i2c_adapter *adap)
357 return i2c_del_adapter(adap);
361 pb1550_reg(struct i2c_client *client)
367 pb1550_unreg(struct i2c_client *client)
372 static struct i2c_au1550_data pb1550_i2c_info = {
373 SMBUS_PSC_BASE, 200, 200
376 static struct i2c_adapter pb1550_board_adapter = {
377 name: "pb1550 adapter",
378 id: I2C_HW_AU1550_PSC,
380 algo_data: &pb1550_i2c_info,
381 client_register: pb1550_reg,
382 client_unregister: pb1550_unreg,
385 /* BIG hack to support the control interface on the Wolfson WM8731
386 * audio codec on the Pb1550 board. We get an address and two data
387 * bytes to write, create an i2c message, and send it across the
388 * i2c transfer function. We do this here because we have access to
389 * the i2c adapter structure.
391 static struct i2c_msg wm_i2c_msg; /* We don't want this stuff on the stack */
395 pb1550_wm_codec_write(u8 addr, u8 reg, u8 val)
397 wm_i2c_msg.addr = addr;
398 wm_i2c_msg.flags = 0;
399 wm_i2c_msg.buf = i2cbuf;
404 return pb1550_board_adapter.algo->master_xfer(&pb1550_board_adapter, &wm_i2c_msg, 1);
408 i2c_au1550_init(void)
410 printk(KERN_INFO "Au1550 I2C: ");
412 /* This is where we would set up a 50MHz clock source
413 * and routing. On the Pb1550, the SMBus is PSC2, which
414 * uses a shared clock with USB. This has been already
415 * configured by Yamon as a 48MHz clock, close enough
418 if (i2c_au1550_add_bus(&pb1550_board_adapter) < 0) {
419 printk("failed to initialize.\n");
423 printk("initialized.\n");
428 i2c_au1550_exit(void)
430 i2c_au1550_del_bus(&pb1550_board_adapter);
433 MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
434 MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
435 MODULE_LICENSE("GPL");
437 module_init (i2c_au1550_init);
438 module_exit (i2c_au1550_exit);