1 /**************************************************************************
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "vmwgfx_drv.h"
30 #include "ttm/ttm_placement.h"
32 bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
34 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
35 uint32_t fifo_min, hwversion;
37 if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
40 fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN);
41 if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
44 hwversion = ioread32(fifo_mem + SVGA_FIFO_3D_HWVERSION);
48 if (hwversion < SVGA3D_HWVERSION_WS8_B1)
51 /* Non-Screen Object path does not support surfaces */
52 if (!dev_priv->sou_priv)
58 bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
60 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
63 if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
66 caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
67 if (caps & SVGA_FIFO_CAP_PITCHLOCK)
73 int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
75 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
80 fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
81 fifo->static_buffer = vmalloc(fifo->static_buffer_size);
82 if (unlikely(fifo->static_buffer == NULL))
85 fifo->dynamic_buffer = NULL;
86 fifo->reserved_size = 0;
87 fifo->using_bounce_buffer = false;
89 mutex_init(&fifo->fifo_mutex);
90 init_rwsem(&fifo->rwsem);
93 * Allow mapping the first page read-only to user-space.
96 DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
97 DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
98 DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
100 mutex_lock(&dev_priv->hw_mutex);
101 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
102 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
103 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
104 vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
107 if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
108 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
114 iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
115 iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
117 iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD);
118 iowrite32(min, fifo_mem + SVGA_FIFO_STOP);
119 iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
122 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
123 mutex_unlock(&dev_priv->hw_mutex);
125 max = ioread32(fifo_mem + SVGA_FIFO_MAX);
126 min = ioread32(fifo_mem + SVGA_FIFO_MIN);
127 fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
129 DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
132 (unsigned int) fifo->capabilities);
134 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
135 iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
136 vmw_marker_queue_init(&fifo->marker_queue);
137 return vmw_fifo_send_fence(dev_priv, &dummy);
140 void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
142 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
144 mutex_lock(&dev_priv->hw_mutex);
146 if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
147 iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
148 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
151 mutex_unlock(&dev_priv->hw_mutex);
154 void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
156 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
158 mutex_lock(&dev_priv->hw_mutex);
160 while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
161 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
163 dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
165 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
166 dev_priv->config_done_state);
167 vmw_write(dev_priv, SVGA_REG_ENABLE,
168 dev_priv->enable_state);
169 vmw_write(dev_priv, SVGA_REG_TRACES,
170 dev_priv->traces_state);
172 mutex_unlock(&dev_priv->hw_mutex);
173 vmw_marker_queue_takedown(&fifo->marker_queue);
175 if (likely(fifo->static_buffer != NULL)) {
176 vfree(fifo->static_buffer);
177 fifo->static_buffer = NULL;
180 if (likely(fifo->dynamic_buffer != NULL)) {
181 vfree(fifo->dynamic_buffer);
182 fifo->dynamic_buffer = NULL;
186 static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
188 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
189 uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
190 uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
191 uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
192 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
194 return ((max - next_cmd) + (stop - min) <= bytes);
197 static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
198 uint32_t bytes, bool interruptible,
199 unsigned long timeout)
202 unsigned long end_jiffies = jiffies + timeout;
205 DRM_INFO("Fifo wait noirq.\n");
208 prepare_to_wait(&dev_priv->fifo_queue, &__wait,
210 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
211 if (!vmw_fifo_is_full(dev_priv, bytes))
213 if (time_after_eq(jiffies, end_jiffies)) {
215 DRM_ERROR("SVGA device lockup.\n");
219 if (interruptible && signal_pending(current)) {
224 finish_wait(&dev_priv->fifo_queue, &__wait);
225 wake_up_all(&dev_priv->fifo_queue);
226 DRM_INFO("Fifo noirq exit.\n");
230 static int vmw_fifo_wait(struct vmw_private *dev_priv,
231 uint32_t bytes, bool interruptible,
232 unsigned long timeout)
235 unsigned long irq_flags;
237 if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
240 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
241 if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
242 return vmw_fifo_wait_noirq(dev_priv, bytes,
243 interruptible, timeout);
245 mutex_lock(&dev_priv->hw_mutex);
246 if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
247 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
248 outl(SVGA_IRQFLAG_FIFO_PROGRESS,
249 dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
250 vmw_write(dev_priv, SVGA_REG_IRQMASK,
251 vmw_read(dev_priv, SVGA_REG_IRQMASK) |
252 SVGA_IRQFLAG_FIFO_PROGRESS);
253 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
255 mutex_unlock(&dev_priv->hw_mutex);
258 ret = wait_event_interruptible_timeout
259 (dev_priv->fifo_queue,
260 !vmw_fifo_is_full(dev_priv, bytes), timeout);
262 ret = wait_event_timeout
263 (dev_priv->fifo_queue,
264 !vmw_fifo_is_full(dev_priv, bytes), timeout);
266 if (unlikely(ret == 0))
268 else if (likely(ret > 0))
271 mutex_lock(&dev_priv->hw_mutex);
272 if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
273 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
274 vmw_write(dev_priv, SVGA_REG_IRQMASK,
275 vmw_read(dev_priv, SVGA_REG_IRQMASK) &
276 ~SVGA_IRQFLAG_FIFO_PROGRESS);
277 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
279 mutex_unlock(&dev_priv->hw_mutex);
285 * Reserve @bytes number of bytes in the fifo.
287 * This function will return NULL (error) on two conditions:
288 * If it timeouts waiting for fifo space, or if @bytes is larger than the
289 * available fifo space.
292 * Pointer to the fifo, or null on error (possible hardware hang).
294 void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
296 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
297 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
301 uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
304 mutex_lock(&fifo_state->fifo_mutex);
305 max = ioread32(fifo_mem + SVGA_FIFO_MAX);
306 min = ioread32(fifo_mem + SVGA_FIFO_MIN);
307 next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
309 if (unlikely(bytes >= (max - min)))
312 BUG_ON(fifo_state->reserved_size != 0);
313 BUG_ON(fifo_state->dynamic_buffer != NULL);
315 fifo_state->reserved_size = bytes;
318 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
319 bool need_bounce = false;
320 bool reserve_in_place = false;
322 if (next_cmd >= stop) {
323 if (likely((next_cmd + bytes < max ||
324 (next_cmd + bytes == max && stop > min))))
325 reserve_in_place = true;
327 else if (vmw_fifo_is_full(dev_priv, bytes)) {
328 ret = vmw_fifo_wait(dev_priv, bytes,
330 if (unlikely(ret != 0))
337 if (likely((next_cmd + bytes < stop)))
338 reserve_in_place = true;
340 ret = vmw_fifo_wait(dev_priv, bytes,
342 if (unlikely(ret != 0))
347 if (reserve_in_place) {
348 if (reserveable || bytes <= sizeof(uint32_t)) {
349 fifo_state->using_bounce_buffer = false;
352 iowrite32(bytes, fifo_mem +
354 return fifo_mem + (next_cmd >> 2);
361 fifo_state->using_bounce_buffer = true;
362 if (bytes < fifo_state->static_buffer_size)
363 return fifo_state->static_buffer;
365 fifo_state->dynamic_buffer = vmalloc(bytes);
366 return fifo_state->dynamic_buffer;
371 fifo_state->reserved_size = 0;
372 mutex_unlock(&fifo_state->fifo_mutex);
376 static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
377 __le32 __iomem *fifo_mem,
379 uint32_t max, uint32_t min, uint32_t bytes)
381 uint32_t chunk_size = max - next_cmd;
383 uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
384 fifo_state->dynamic_buffer : fifo_state->static_buffer;
386 if (bytes < chunk_size)
389 iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
391 memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
392 rest = bytes - chunk_size;
394 memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
398 static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
399 __le32 __iomem *fifo_mem,
401 uint32_t max, uint32_t min, uint32_t bytes)
403 uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
404 fifo_state->dynamic_buffer : fifo_state->static_buffer;
407 iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
408 next_cmd += sizeof(uint32_t);
409 if (unlikely(next_cmd == max))
412 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
414 bytes -= sizeof(uint32_t);
418 void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
420 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
421 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
422 uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
423 uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
424 uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
425 bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
427 BUG_ON((bytes & 3) != 0);
428 BUG_ON(bytes > fifo_state->reserved_size);
430 fifo_state->reserved_size = 0;
432 if (fifo_state->using_bounce_buffer) {
434 vmw_fifo_res_copy(fifo_state, fifo_mem,
435 next_cmd, max, min, bytes);
437 vmw_fifo_slow_copy(fifo_state, fifo_mem,
438 next_cmd, max, min, bytes);
440 if (fifo_state->dynamic_buffer) {
441 vfree(fifo_state->dynamic_buffer);
442 fifo_state->dynamic_buffer = NULL;
447 down_write(&fifo_state->rwsem);
448 if (fifo_state->using_bounce_buffer || reserveable) {
451 next_cmd -= max - min;
453 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
457 iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
459 up_write(&fifo_state->rwsem);
460 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
461 mutex_unlock(&fifo_state->fifo_mutex);
464 int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
466 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
467 struct svga_fifo_cmd_fence *cmd_fence;
470 uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
472 fm = vmw_fifo_reserve(dev_priv, bytes);
473 if (unlikely(fm == NULL)) {
474 *seqno = atomic_read(&dev_priv->marker_seq);
476 (void)vmw_fallback_wait(dev_priv, false, true, *seqno,
482 *seqno = atomic_add_return(1, &dev_priv->marker_seq);
483 } while (*seqno == 0);
485 if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
488 * Don't request hardware to send a fence. The
489 * waiting code in vmwgfx_irq.c will emulate this.
492 vmw_fifo_commit(dev_priv, 0);
496 *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
497 cmd_fence = (struct svga_fifo_cmd_fence *)
498 ((unsigned long)fm + sizeof(__le32));
500 iowrite32(*seqno, &cmd_fence->fence);
501 vmw_fifo_commit(dev_priv, bytes);
502 (void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
503 vmw_update_seqno(dev_priv, fifo_state);