2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/gpio.h>
13 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/clk/tegra.h>
24 struct host1x_client client;
25 struct tegra_output output;
28 struct regulator *vdd;
29 struct regulator *pll;
34 struct clk *clk_parent;
37 unsigned int audio_source;
38 unsigned int audio_freq;
42 struct drm_info_list *debugfs_files;
43 struct drm_minor *minor;
44 struct dentry *debugfs;
47 static inline struct tegra_hdmi *
48 host1x_client_to_hdmi(struct host1x_client *client)
50 return container_of(client, struct tegra_hdmi, client);
53 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
55 return container_of(output, struct tegra_hdmi, output);
58 #define HDMI_AUDIOCLK_FREQ 216000000
59 #define HDMI_REKEY_DEFAULT 56
67 static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
70 return readl(hdmi->regs + (reg << 2));
73 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
76 writel(val, hdmi->regs + (reg << 2));
79 struct tegra_hdmi_audio_config {
86 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
87 { 25200000, 4096, 25200, 24000 },
88 { 27000000, 4096, 27000, 24000 },
89 { 74250000, 4096, 74250, 24000 },
90 { 148500000, 4096, 148500, 24000 },
94 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
95 { 25200000, 5880, 26250, 25000 },
96 { 27000000, 5880, 28125, 25000 },
97 { 74250000, 4704, 61875, 20000 },
98 { 148500000, 4704, 123750, 20000 },
102 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
103 { 25200000, 6144, 25200, 24000 },
104 { 27000000, 6144, 27000, 24000 },
105 { 74250000, 6144, 74250, 24000 },
106 { 148500000, 6144, 148500, 24000 },
110 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
111 { 25200000, 11760, 26250, 25000 },
112 { 27000000, 11760, 28125, 25000 },
113 { 74250000, 9408, 61875, 20000 },
114 { 148500000, 9408, 123750, 20000 },
118 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
119 { 25200000, 12288, 25200, 24000 },
120 { 27000000, 12288, 27000, 24000 },
121 { 74250000, 12288, 74250, 24000 },
122 { 148500000, 12288, 148500, 24000 },
126 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
127 { 25200000, 23520, 26250, 25000 },
128 { 27000000, 23520, 28125, 25000 },
129 { 74250000, 18816, 61875, 20000 },
130 { 148500000, 18816, 123750, 20000 },
134 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
135 { 25200000, 24576, 25200, 24000 },
136 { 27000000, 24576, 27000, 24000 },
137 { 74250000, 24576, 74250, 24000 },
138 { 148500000, 24576, 148500, 24000 },
150 static const struct tmds_config tegra2_tmds_config[] = {
151 { /* slow pixel clock modes */
153 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
154 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
155 SOR_PLL_TX_REG_LOAD(3),
156 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
157 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
158 PE_CURRENT1(PE_CURRENT_0_0_mA) |
159 PE_CURRENT2(PE_CURRENT_0_0_mA) |
160 PE_CURRENT3(PE_CURRENT_0_0_mA),
161 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
162 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
163 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
164 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
166 { /* high pixel clock modes */
168 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
169 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
170 SOR_PLL_TX_REG_LOAD(3),
171 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
172 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
173 PE_CURRENT1(PE_CURRENT_6_0_mA) |
174 PE_CURRENT2(PE_CURRENT_6_0_mA) |
175 PE_CURRENT3(PE_CURRENT_6_0_mA),
176 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
177 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
178 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
179 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
183 static const struct tmds_config tegra3_tmds_config[] = {
186 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
187 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
188 SOR_PLL_TX_REG_LOAD(0),
189 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
190 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
191 PE_CURRENT1(PE_CURRENT_0_0_mA) |
192 PE_CURRENT2(PE_CURRENT_0_0_mA) |
193 PE_CURRENT3(PE_CURRENT_0_0_mA),
194 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
195 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
196 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
197 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
198 }, { /* 720p modes */
200 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
201 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
202 SOR_PLL_TX_REG_LOAD(0),
203 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
204 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
205 PE_CURRENT1(PE_CURRENT_5_0_mA) |
206 PE_CURRENT2(PE_CURRENT_5_0_mA) |
207 PE_CURRENT3(PE_CURRENT_5_0_mA),
208 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
209 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
210 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
211 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
212 }, { /* 1080p modes */
214 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
215 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
216 SOR_PLL_TX_REG_LOAD(0),
217 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
218 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
219 PE_CURRENT1(PE_CURRENT_5_0_mA) |
220 PE_CURRENT2(PE_CURRENT_5_0_mA) |
221 PE_CURRENT3(PE_CURRENT_5_0_mA),
222 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
223 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
224 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
225 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
229 static const struct tegra_hdmi_audio_config *
230 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
232 const struct tegra_hdmi_audio_config *table;
234 switch (audio_freq) {
236 table = tegra_hdmi_audio_32k;
240 table = tegra_hdmi_audio_44_1k;
244 table = tegra_hdmi_audio_48k;
248 table = tegra_hdmi_audio_88_2k;
252 table = tegra_hdmi_audio_96k;
256 table = tegra_hdmi_audio_176_4k;
260 table = tegra_hdmi_audio_192k;
267 while (table->pclk) {
268 if (table->pclk == pclk)
277 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
279 const unsigned int freqs[] = {
280 32000, 44100, 48000, 88200, 96000, 176400, 192000
284 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
285 unsigned int f = freqs[i];
286 unsigned int eight_half;
297 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
298 value = AUDIO_FS_LOW(eight_half - delta) |
299 AUDIO_FS_HIGH(eight_half + delta);
300 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
304 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
306 struct device_node *node = hdmi->dev->of_node;
307 const struct tegra_hdmi_audio_config *config;
308 unsigned int offset = 0;
311 switch (hdmi->audio_source) {
313 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
317 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
321 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
325 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
326 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
327 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
328 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
330 value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
331 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
333 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
334 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
335 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
338 config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
340 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
341 hdmi->audio_freq, pclk);
345 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
347 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
348 AUDIO_N_VALUE(config->n - 1);
349 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
351 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
352 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
354 value = ACR_SUBPACK_CTS(config->cts);
355 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
357 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
358 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
360 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
361 value &= ~AUDIO_N_RESETF;
362 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
364 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
365 switch (hdmi->audio_freq) {
367 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
371 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
375 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
379 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
383 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
387 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
391 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
395 tegra_hdmi_writel(hdmi, config->aval, offset);
398 tegra_hdmi_setup_audio_fs_tables(hdmi);
403 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi,
404 unsigned int offset, u8 type,
405 u8 version, void *data, size_t size)
413 /* first byte of data is the checksum */
414 csum = type + version + size - 1;
416 for (i = 1; i < size; i++)
419 ptr[0] = 0x100 - csum;
421 value = INFOFRAME_HEADER_TYPE(type) |
422 INFOFRAME_HEADER_VERSION(version) |
423 INFOFRAME_HEADER_LEN(size - 1);
424 tegra_hdmi_writel(hdmi, value, offset);
426 /* The audio inforame only has one set of subpack registers. The hdmi
427 * block pads the rest of the data as per the spec so we have to fixup
428 * the length before filling in the subpacks.
430 if (offset == HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER)
433 /* each subpack 7 bytes devided into:
434 * subpack_low - bytes 0 - 3
435 * subpack_high - bytes 4 - 6 (with byte 7 padded to 0x00)
437 for (i = 0; i < size; i++) {
438 size_t index = i % 7;
441 memset(subpack, 0x0, sizeof(subpack));
443 ((u8 *)subpack)[index] = ptr[i];
445 if (index == 6 || (i + 1 == size)) {
446 unsigned int reg = offset + 1 + (i / 7) * 2;
448 tegra_hdmi_writel(hdmi, subpack[0], reg);
449 tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
454 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
455 struct drm_display_mode *mode)
457 struct hdmi_avi_infoframe frame;
458 unsigned int h_front_porch;
459 unsigned int hsize = 16;
460 unsigned int vsize = 9;
463 tegra_hdmi_writel(hdmi, 0,
464 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
468 h_front_porch = mode->hsync_start - mode->hdisplay;
469 memset(&frame, 0, sizeof(frame));
470 frame.r = HDMI_AVI_R_SAME;
472 switch (mode->vdisplay) {
474 if (mode->hdisplay == 640) {
475 frame.m = HDMI_AVI_M_4_3;
478 frame.m = HDMI_AVI_M_16_9;
484 if (((hsize * 10) / vsize) > 14) {
485 frame.m = HDMI_AVI_M_16_9;
488 frame.m = HDMI_AVI_M_4_3;
494 case 1470: /* stereo mode */
495 frame.m = HDMI_AVI_M_16_9;
497 if (h_front_porch == 110)
504 case 2205: /* stereo mode */
505 frame.m = HDMI_AVI_M_16_9;
507 switch (h_front_porch) {
523 frame.m = HDMI_AVI_M_16_9;
528 tegra_hdmi_write_infopack(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
529 HDMI_INFOFRAME_TYPE_AVI, HDMI_AVI_VERSION,
530 &frame, sizeof(frame));
532 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
533 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
536 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
538 struct hdmi_audio_infoframe frame;
541 tegra_hdmi_writel(hdmi, 0,
542 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
546 memset(&frame, 0, sizeof(frame));
547 frame.cc = HDMI_AUDIO_CC_2;
549 tegra_hdmi_write_infopack(hdmi,
550 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
551 HDMI_INFOFRAME_TYPE_AUDIO,
553 &frame, sizeof(frame));
555 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
556 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
559 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
561 struct hdmi_stereo_infoframe frame;
565 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
566 value &= ~GENERIC_CTRL_ENABLE;
567 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
571 memset(&frame, 0, sizeof(frame));
575 frame.hdmi_video_format = 2;
577 /* TODO: 74 MHz limit? */
579 frame._3d_structure = 0;
581 frame._3d_structure = 8;
582 frame._3d_ext_data = 0;
585 tegra_hdmi_write_infopack(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_HEADER,
586 HDMI_INFOFRAME_TYPE_VENDOR,
587 HDMI_VENDOR_VERSION, &frame, 6);
589 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
590 value |= GENERIC_CTRL_ENABLE;
591 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
594 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
595 const struct tmds_config *tmds)
599 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
600 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
601 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
603 value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE;
604 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
607 static int tegra_output_hdmi_enable(struct tegra_output *output)
609 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
610 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
611 struct drm_display_mode *mode = &dc->base.mode;
612 struct tegra_hdmi *hdmi = to_hdmi(output);
613 struct device_node *node = hdmi->dev->of_node;
614 unsigned int pulse_start, div82, pclk;
615 const struct tmds_config *tmds;
616 unsigned int num_tmds;
621 pclk = mode->clock * 1000;
622 h_sync_width = mode->hsync_end - mode->hsync_start;
623 h_back_porch = mode->htotal - mode->hsync_end;
624 h_front_porch = mode->hsync_start - mode->hdisplay;
626 err = regulator_enable(hdmi->vdd);
628 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
632 err = regulator_enable(hdmi->pll);
634 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
639 * This assumes that the display controller will divide its parent
640 * clock by 2 to generate the pixel clock.
642 err = tegra_output_setup_clock(output, hdmi->clk, pclk * 2);
644 dev_err(hdmi->dev, "failed to setup clock: %d\n", err);
648 err = clk_set_rate(hdmi->clk, pclk);
652 err = clk_enable(hdmi->clk);
654 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
658 tegra_periph_reset_assert(hdmi->clk);
659 usleep_range(1000, 2000);
660 tegra_periph_reset_deassert(hdmi->clk);
662 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
663 DC_DISP_DISP_TIMING_OPTIONS);
664 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
665 DC_DISP_DISP_COLOR_CONTROL);
667 /* video_preamble uses h_pulse2 */
668 pulse_start = 1 + h_sync_width + h_back_porch - 10;
670 tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
672 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
674 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
676 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
677 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
679 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
681 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
684 value = HDMI_SRC_DISPLAYB;
686 value = HDMI_SRC_DISPLAYA;
688 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
689 (mode->vdisplay == 576)))
690 tegra_hdmi_writel(hdmi,
691 value | ARM_VIDEO_RANGE_FULL,
692 HDMI_NV_PDISP_INPUT_CONTROL);
694 tegra_hdmi_writel(hdmi,
695 value | ARM_VIDEO_RANGE_LIMITED,
696 HDMI_NV_PDISP_INPUT_CONTROL);
698 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
699 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
700 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
703 err = tegra_hdmi_setup_audio(hdmi, pclk);
708 if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
710 * TODO: add ELD support
714 rekey = HDMI_REKEY_DEFAULT;
715 value = HDMI_CTRL_REKEY(rekey);
716 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
717 h_front_porch - rekey - 18) / 32);
720 value |= HDMI_CTRL_ENABLE;
722 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
725 tegra_hdmi_writel(hdmi, 0x0,
726 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
728 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
729 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
731 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
732 tegra_hdmi_setup_audio_infoframe(hdmi);
733 tegra_hdmi_setup_stereo_infoframe(hdmi);
736 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
737 num_tmds = ARRAY_SIZE(tegra3_tmds_config);
738 tmds = tegra3_tmds_config;
740 num_tmds = ARRAY_SIZE(tegra2_tmds_config);
741 tmds = tegra2_tmds_config;
744 for (i = 0; i < num_tmds; i++) {
745 if (pclk <= tmds[i].pclk) {
746 tegra_hdmi_setup_tmds(hdmi, &tmds[i]);
751 tegra_hdmi_writel(hdmi,
752 SOR_SEQ_CTL_PU_PC(0) |
753 SOR_SEQ_PU_PC_ALT(0) |
755 SOR_SEQ_PD_PC_ALT(8),
756 HDMI_NV_PDISP_SOR_SEQ_CTL);
758 value = SOR_SEQ_INST_WAIT_TIME(1) |
759 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
761 SOR_SEQ_INST_PIN_A_LOW |
762 SOR_SEQ_INST_PIN_B_LOW |
763 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
765 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
766 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
769 value &= ~SOR_CSTM_ROTCLK(~0);
770 value |= SOR_CSTM_ROTCLK(2);
771 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
773 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
774 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
775 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
778 tegra_hdmi_writel(hdmi,
779 SOR_PWR_NORMAL_STATE_PU |
780 SOR_PWR_NORMAL_START_NORMAL |
781 SOR_PWR_SAFE_STATE_PD |
782 SOR_PWR_SETTING_NEW_TRIGGER,
783 HDMI_NV_PDISP_SOR_PWR);
784 tegra_hdmi_writel(hdmi,
785 SOR_PWR_NORMAL_STATE_PU |
786 SOR_PWR_NORMAL_START_NORMAL |
787 SOR_PWR_SAFE_STATE_PD |
788 SOR_PWR_SETTING_NEW_DONE,
789 HDMI_NV_PDISP_SOR_PWR);
792 BUG_ON(--retries < 0);
793 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
794 } while (value & SOR_PWR_SETTING_NEW_PENDING);
796 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
797 SOR_STATE_ASY_OWNER_HEAD0 |
798 SOR_STATE_ASY_SUBOWNER_BOTH |
799 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
800 SOR_STATE_ASY_DEPOL_POS;
802 /* setup sync polarities */
803 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
804 value |= SOR_STATE_ASY_HSYNCPOL_POS;
806 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
807 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
809 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
810 value |= SOR_STATE_ASY_VSYNCPOL_POS;
812 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
813 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
815 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
817 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
818 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
820 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
821 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
822 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
823 HDMI_NV_PDISP_SOR_STATE1);
824 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
826 tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
828 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
829 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
830 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
832 value = DISP_CTRL_MODE_C_DISPLAY;
833 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
835 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
836 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
838 /* TODO: add HDCP support */
843 static int tegra_output_hdmi_disable(struct tegra_output *output)
845 struct tegra_hdmi *hdmi = to_hdmi(output);
847 tegra_periph_reset_assert(hdmi->clk);
848 clk_disable(hdmi->clk);
849 regulator_disable(hdmi->pll);
850 regulator_disable(hdmi->vdd);
855 static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
856 struct clk *clk, unsigned long pclk)
858 struct tegra_hdmi *hdmi = to_hdmi(output);
862 err = clk_set_parent(clk, hdmi->clk_parent);
864 dev_err(output->dev, "failed to set parent: %d\n", err);
868 base = clk_get_parent(hdmi->clk_parent);
871 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
872 * respectively, each of which divides the base pll_d by 2.
874 err = clk_set_rate(base, pclk * 2);
877 "failed to set base clock rate to %lu Hz\n",
883 static int tegra_output_hdmi_check_mode(struct tegra_output *output,
884 struct drm_display_mode *mode,
885 enum drm_mode_status *status)
887 struct tegra_hdmi *hdmi = to_hdmi(output);
888 unsigned long pclk = mode->clock * 1000;
892 parent = clk_get_parent(hdmi->clk_parent);
894 err = clk_round_rate(parent, pclk * 4);
896 *status = MODE_NOCLOCK;
903 static const struct tegra_output_ops hdmi_ops = {
904 .enable = tegra_output_hdmi_enable,
905 .disable = tegra_output_hdmi_disable,
906 .setup_clock = tegra_output_hdmi_setup_clock,
907 .check_mode = tegra_output_hdmi_check_mode,
910 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
912 struct drm_info_node *node = s->private;
913 struct tegra_hdmi *hdmi = node->info_ent->data;
915 #define DUMP_REG(name) \
916 seq_printf(s, "%-56s %#05x %08lx\n", #name, name, \
917 tegra_hdmi_readl(hdmi, name))
919 DUMP_REG(HDMI_CTXSW);
920 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
921 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
922 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
923 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
924 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
925 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
926 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
927 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
928 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
929 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
930 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
931 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
932 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
933 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
934 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
935 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
936 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
937 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
938 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
939 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
940 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
941 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
942 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
943 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
944 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
945 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
946 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
947 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
948 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
949 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
950 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
951 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
952 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
953 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
954 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
955 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
956 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
957 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
958 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
959 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
960 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
961 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
962 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
963 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
964 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
965 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
966 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
967 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
968 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
969 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
970 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
971 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
972 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
973 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
974 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
975 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
976 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
977 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
978 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
979 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
980 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
981 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
982 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
983 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
984 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
985 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
986 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
987 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
988 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
989 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
990 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
991 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
992 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
993 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
994 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
995 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
996 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
997 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
998 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
999 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1000 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1001 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
1002 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1003 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1004 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1005 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1006 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1007 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1008 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1009 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1010 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1011 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1012 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1013 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1014 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1015 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1016 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1017 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1018 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1019 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1020 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1021 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1022 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1023 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1024 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1025 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1026 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1027 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1028 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1029 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1030 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1031 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1032 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1033 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1034 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1035 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1036 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1037 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1038 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1039 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1040 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1041 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1042 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1043 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1044 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1045 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1046 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1047 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1048 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1049 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1050 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1051 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1052 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1053 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1054 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1055 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1056 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1057 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1058 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1059 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1060 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1061 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1062 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1063 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1064 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1065 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1066 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1067 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1068 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1069 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1070 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1071 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1072 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1073 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1074 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1075 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1082 static struct drm_info_list debugfs_files[] = {
1083 { "regs", tegra_hdmi_show_regs, 0, NULL },
1086 static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1087 struct drm_minor *minor)
1092 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1096 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1098 if (!hdmi->debugfs_files) {
1103 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1104 hdmi->debugfs_files[i].data = hdmi;
1106 err = drm_debugfs_create_files(hdmi->debugfs_files,
1107 ARRAY_SIZE(debugfs_files),
1108 hdmi->debugfs, minor);
1112 hdmi->minor = minor;
1117 kfree(hdmi->debugfs_files);
1118 hdmi->debugfs_files = NULL;
1120 debugfs_remove(hdmi->debugfs);
1121 hdmi->debugfs = NULL;
1126 static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1128 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1132 kfree(hdmi->debugfs_files);
1133 hdmi->debugfs_files = NULL;
1135 debugfs_remove(hdmi->debugfs);
1136 hdmi->debugfs = NULL;
1141 static int tegra_hdmi_drm_init(struct host1x_client *client,
1142 struct drm_device *drm)
1144 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1147 hdmi->output.type = TEGRA_OUTPUT_HDMI;
1148 hdmi->output.dev = client->dev;
1149 hdmi->output.ops = &hdmi_ops;
1151 err = tegra_output_init(drm, &hdmi->output);
1153 dev_err(client->dev, "output setup failed: %d\n", err);
1157 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1158 err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
1160 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1166 static int tegra_hdmi_drm_exit(struct host1x_client *client)
1168 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1171 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1172 err = tegra_hdmi_debugfs_exit(hdmi);
1174 dev_err(client->dev, "debugfs cleanup failed: %d\n",
1178 err = tegra_output_disable(&hdmi->output);
1180 dev_err(client->dev, "output failed to disable: %d\n", err);
1184 err = tegra_output_exit(&hdmi->output);
1186 dev_err(client->dev, "output cleanup failed: %d\n", err);
1193 static const struct host1x_client_ops hdmi_client_ops = {
1194 .drm_init = tegra_hdmi_drm_init,
1195 .drm_exit = tegra_hdmi_drm_exit,
1198 static int tegra_hdmi_probe(struct platform_device *pdev)
1200 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
1201 struct tegra_hdmi *hdmi;
1202 struct resource *regs;
1205 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1209 hdmi->dev = &pdev->dev;
1210 hdmi->audio_source = AUTO;
1211 hdmi->audio_freq = 44100;
1212 hdmi->stereo = false;
1215 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1216 if (IS_ERR(hdmi->clk)) {
1217 dev_err(&pdev->dev, "failed to get clock\n");
1218 return PTR_ERR(hdmi->clk);
1221 err = clk_prepare(hdmi->clk);
1225 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1226 if (IS_ERR(hdmi->clk_parent))
1227 return PTR_ERR(hdmi->clk_parent);
1229 err = clk_prepare(hdmi->clk_parent);
1233 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1235 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1239 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1240 if (IS_ERR(hdmi->vdd)) {
1241 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1242 return PTR_ERR(hdmi->vdd);
1245 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1246 if (IS_ERR(hdmi->pll)) {
1247 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1248 return PTR_ERR(hdmi->pll);
1251 hdmi->output.dev = &pdev->dev;
1253 err = tegra_output_parse_dt(&hdmi->output);
1257 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1261 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1262 if (IS_ERR(hdmi->regs))
1263 return PTR_ERR(hdmi->regs);
1265 err = platform_get_irq(pdev, 0);
1271 hdmi->client.ops = &hdmi_client_ops;
1272 INIT_LIST_HEAD(&hdmi->client.list);
1273 hdmi->client.dev = &pdev->dev;
1275 err = host1x_register_client(host1x, &hdmi->client);
1277 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1282 platform_set_drvdata(pdev, hdmi);
1287 static int tegra_hdmi_remove(struct platform_device *pdev)
1289 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
1290 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1293 err = host1x_unregister_client(host1x, &hdmi->client);
1295 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1300 clk_unprepare(hdmi->clk_parent);
1301 clk_unprepare(hdmi->clk);
1306 static struct of_device_id tegra_hdmi_of_match[] = {
1307 { .compatible = "nvidia,tegra30-hdmi", },
1308 { .compatible = "nvidia,tegra20-hdmi", },
1312 struct platform_driver tegra_hdmi_driver = {
1314 .name = "tegra-hdmi",
1315 .owner = THIS_MODULE,
1316 .of_match_table = tegra_hdmi_of_match,
1318 .probe = tegra_hdmi_probe,
1319 .remove = tegra_hdmi_remove,