2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/iommu.h>
13 #include <linux/reset.h>
15 #include <soc/tegra/pmc.h>
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_plane_helper.h>
25 struct tegra_dc_soc_info {
26 bool supports_border_color;
27 bool supports_interlacing;
29 bool supports_block_linear;
30 unsigned int pitch_align;
35 struct drm_plane base;
39 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
41 return container_of(plane, struct tegra_plane, base);
44 struct tegra_dc_state {
45 struct drm_crtc_state base;
54 static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
57 return container_of(state, struct tegra_dc_state, base);
62 struct tegra_plane_state {
63 struct drm_plane_state base;
65 struct tegra_bo_tiling tiling;
70 static inline struct tegra_plane_state *
71 to_tegra_plane_state(struct drm_plane_state *state)
74 return container_of(state, struct tegra_plane_state, base);
80 * Reads the active copy of a register. This takes the dc->lock spinlock to
81 * prevent races with the VBLANK processing which also needs access to the
82 * active copy of some registers.
84 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
89 spin_lock_irqsave(&dc->lock, flags);
91 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
92 value = tegra_dc_readl(dc, offset);
93 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
95 spin_unlock_irqrestore(&dc->lock, flags);
100 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
101 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
102 * Latching happens mmediately if the display controller is in STOP mode or
103 * on the next frame boundary otherwise.
105 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
106 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
107 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
108 * into the ACTIVE copy, either immediately if the display controller is in
109 * STOP mode, or at the next frame boundary otherwise.
111 void tegra_dc_commit(struct tegra_dc *dc)
113 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
114 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
117 static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
119 /* assume no swapping of fetched data */
121 *swap = BYTE_SWAP_NOSWAP;
124 case DRM_FORMAT_XBGR8888:
125 *format = WIN_COLOR_DEPTH_R8G8B8A8;
128 case DRM_FORMAT_XRGB8888:
129 *format = WIN_COLOR_DEPTH_B8G8R8A8;
132 case DRM_FORMAT_RGB565:
133 *format = WIN_COLOR_DEPTH_B5G6R5;
136 case DRM_FORMAT_UYVY:
137 *format = WIN_COLOR_DEPTH_YCbCr422;
140 case DRM_FORMAT_YUYV:
142 *swap = BYTE_SWAP_SWAP2;
144 *format = WIN_COLOR_DEPTH_YCbCr422;
147 case DRM_FORMAT_YUV420:
148 *format = WIN_COLOR_DEPTH_YCbCr420P;
151 case DRM_FORMAT_YUV422:
152 *format = WIN_COLOR_DEPTH_YCbCr422P;
162 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
165 case WIN_COLOR_DEPTH_YCbCr422:
166 case WIN_COLOR_DEPTH_YUV422:
172 case WIN_COLOR_DEPTH_YCbCr420P:
173 case WIN_COLOR_DEPTH_YUV420P:
174 case WIN_COLOR_DEPTH_YCbCr422P:
175 case WIN_COLOR_DEPTH_YUV422P:
176 case WIN_COLOR_DEPTH_YCbCr422R:
177 case WIN_COLOR_DEPTH_YUV422R:
178 case WIN_COLOR_DEPTH_YCbCr422RA:
179 case WIN_COLOR_DEPTH_YUV422RA:
192 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
195 fixed20_12 outf = dfixed_init(out);
196 fixed20_12 inf = dfixed_init(in);
217 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
218 inf.full -= dfixed_const(1);
220 dda_inc = dfixed_div(inf, outf);
221 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
226 static inline u32 compute_initial_dda(unsigned int in)
228 fixed20_12 inf = dfixed_init(in);
229 return dfixed_frac(inf);
232 static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
233 const struct tegra_dc_window *window)
235 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
236 unsigned long value, flags;
240 * For YUV planar modes, the number of bytes per pixel takes into
241 * account only the luma component and therefore is 1.
243 yuv = tegra_dc_format_is_yuv(window->format, &planar);
245 bpp = window->bits_per_pixel / 8;
247 bpp = planar ? 1 : 2;
249 spin_lock_irqsave(&dc->lock, flags);
251 value = WINDOW_A_SELECT << index;
252 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
254 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
255 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
257 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
258 tegra_dc_writel(dc, value, DC_WIN_POSITION);
260 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
261 tegra_dc_writel(dc, value, DC_WIN_SIZE);
263 h_offset = window->src.x * bpp;
264 v_offset = window->src.y;
265 h_size = window->src.w * bpp;
266 v_size = window->src.h;
268 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
269 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
272 * For DDA computations the number of bytes per pixel for YUV planar
273 * modes needs to take into account all Y, U and V components.
278 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
279 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
281 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
282 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
284 h_dda = compute_initial_dda(window->src.x);
285 v_dda = compute_initial_dda(window->src.y);
287 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
288 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
290 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
291 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
293 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
296 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
297 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
298 value = window->stride[1] << 16 | window->stride[0];
299 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
301 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
304 if (window->bottom_up)
305 v_offset += window->src.h - 1;
307 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
308 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
310 if (dc->soc->supports_block_linear) {
311 unsigned long height = window->tiling.value;
313 switch (window->tiling.mode) {
314 case TEGRA_BO_TILING_MODE_PITCH:
315 value = DC_WINBUF_SURFACE_KIND_PITCH;
318 case TEGRA_BO_TILING_MODE_TILED:
319 value = DC_WINBUF_SURFACE_KIND_TILED;
322 case TEGRA_BO_TILING_MODE_BLOCK:
323 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
324 DC_WINBUF_SURFACE_KIND_BLOCK;
328 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
330 switch (window->tiling.mode) {
331 case TEGRA_BO_TILING_MODE_PITCH:
332 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
333 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
336 case TEGRA_BO_TILING_MODE_TILED:
337 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
338 DC_WIN_BUFFER_ADDR_MODE_TILE;
341 case TEGRA_BO_TILING_MODE_BLOCK:
343 * No need to handle this here because ->atomic_check
344 * will already have filtered it out.
349 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
355 /* setup default colorspace conversion coefficients */
356 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
357 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
358 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
359 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
360 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
361 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
362 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
363 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
366 } else if (window->bits_per_pixel < 24) {
367 value |= COLOR_EXPAND;
370 if (window->bottom_up)
371 value |= V_DIRECTION;
373 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
376 * Disable blending and assume Window A is the bottom-most window,
377 * Window C is the top-most window and Window B is in the middle.
379 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
380 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
384 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
385 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
386 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
390 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
391 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
396 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
397 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
402 spin_unlock_irqrestore(&dc->lock, flags);
405 static void tegra_plane_destroy(struct drm_plane *plane)
407 struct tegra_plane *p = to_tegra_plane(plane);
409 drm_plane_cleanup(plane);
413 static const u32 tegra_primary_plane_formats[] = {
419 static void tegra_primary_plane_destroy(struct drm_plane *plane)
421 tegra_plane_destroy(plane);
424 static void tegra_plane_reset(struct drm_plane *plane)
426 struct tegra_plane_state *state;
428 if (plane->state && plane->state->fb)
429 drm_framebuffer_unreference(plane->state->fb);
434 state = kzalloc(sizeof(*state), GFP_KERNEL);
436 plane->state = &state->base;
437 plane->state->plane = plane;
441 static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
443 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
444 struct tegra_plane_state *copy;
446 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
451 drm_framebuffer_reference(copy->base.fb);
456 static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
457 struct drm_plane_state *state)
460 drm_framebuffer_unreference(state->fb);
465 static const struct drm_plane_funcs tegra_primary_plane_funcs = {
466 .update_plane = drm_atomic_helper_update_plane,
467 .disable_plane = drm_atomic_helper_disable_plane,
468 .destroy = tegra_primary_plane_destroy,
469 .reset = tegra_plane_reset,
470 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
471 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
474 static int tegra_plane_prepare_fb(struct drm_plane *plane,
475 struct drm_framebuffer *fb)
480 static void tegra_plane_cleanup_fb(struct drm_plane *plane,
481 struct drm_framebuffer *fb)
485 static int tegra_plane_state_add(struct tegra_plane *plane,
486 struct drm_plane_state *state)
488 struct drm_crtc_state *crtc_state;
489 struct tegra_dc_state *tegra;
491 /* Propagate errors from allocation or locking failures. */
492 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
493 if (IS_ERR(crtc_state))
494 return PTR_ERR(crtc_state);
496 tegra = to_dc_state(crtc_state);
498 tegra->planes |= WIN_A_ACT_REQ << plane->index;
503 static int tegra_plane_atomic_check(struct drm_plane *plane,
504 struct drm_plane_state *state)
506 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
507 struct tegra_bo_tiling *tiling = &plane_state->tiling;
508 struct tegra_plane *tegra = to_tegra_plane(plane);
509 struct tegra_dc *dc = to_tegra_dc(state->crtc);
512 /* no need for further checks if the plane is being disabled */
516 err = tegra_dc_format(state->fb->pixel_format, &plane_state->format,
521 err = tegra_fb_get_tiling(state->fb, tiling);
525 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
526 !dc->soc->supports_block_linear) {
527 DRM_ERROR("hardware doesn't support block linear mode\n");
532 * Tegra doesn't support different strides for U and V planes so we
533 * error out if the user tries to display a framebuffer with such a
536 if (drm_format_num_planes(state->fb->pixel_format) > 2) {
537 if (state->fb->pitches[2] != state->fb->pitches[1]) {
538 DRM_ERROR("unsupported UV-plane configuration\n");
543 err = tegra_plane_state_add(tegra, state);
550 static void tegra_plane_atomic_update(struct drm_plane *plane,
551 struct drm_plane_state *old_state)
553 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
554 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
555 struct drm_framebuffer *fb = plane->state->fb;
556 struct tegra_plane *p = to_tegra_plane(plane);
557 struct tegra_dc_window window;
560 /* rien ne va plus */
561 if (!plane->state->crtc || !plane->state->fb)
564 memset(&window, 0, sizeof(window));
565 window.src.x = plane->state->src_x >> 16;
566 window.src.y = plane->state->src_y >> 16;
567 window.src.w = plane->state->src_w >> 16;
568 window.src.h = plane->state->src_h >> 16;
569 window.dst.x = plane->state->crtc_x;
570 window.dst.y = plane->state->crtc_y;
571 window.dst.w = plane->state->crtc_w;
572 window.dst.h = plane->state->crtc_h;
573 window.bits_per_pixel = fb->bits_per_pixel;
574 window.bottom_up = tegra_fb_is_bottom_up(fb);
576 /* copy from state */
577 window.tiling = state->tiling;
578 window.format = state->format;
579 window.swap = state->swap;
581 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
582 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
584 window.base[i] = bo->paddr + fb->offsets[i];
585 window.stride[i] = fb->pitches[i];
588 tegra_dc_setup_window(dc, p->index, &window);
591 static void tegra_plane_atomic_disable(struct drm_plane *plane,
592 struct drm_plane_state *old_state)
594 struct tegra_plane *p = to_tegra_plane(plane);
599 /* rien ne va plus */
600 if (!old_state || !old_state->crtc)
603 dc = to_tegra_dc(old_state->crtc);
605 spin_lock_irqsave(&dc->lock, flags);
607 value = WINDOW_A_SELECT << p->index;
608 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
610 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
611 value &= ~WIN_ENABLE;
612 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
614 spin_unlock_irqrestore(&dc->lock, flags);
617 static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
618 .prepare_fb = tegra_plane_prepare_fb,
619 .cleanup_fb = tegra_plane_cleanup_fb,
620 .atomic_check = tegra_plane_atomic_check,
621 .atomic_update = tegra_plane_atomic_update,
622 .atomic_disable = tegra_plane_atomic_disable,
625 static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
629 * Ideally this would use drm_crtc_mask(), but that would require the
630 * CRTC to already be in the mode_config's list of CRTCs. However, it
631 * will only be added to that list in the drm_crtc_init_with_planes()
632 * (in tegra_dc_init()), which in turn requires registration of these
633 * planes. So we have ourselves a nice little chicken and egg problem
636 * We work around this by manually creating the mask from the number
637 * of CRTCs that have been registered, and should therefore always be
638 * the same as drm_crtc_index() after registration.
640 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
641 struct tegra_plane *plane;
642 unsigned int num_formats;
646 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
648 return ERR_PTR(-ENOMEM);
650 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
651 formats = tegra_primary_plane_formats;
653 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
654 &tegra_primary_plane_funcs, formats,
655 num_formats, DRM_PLANE_TYPE_PRIMARY);
661 drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
666 static const u32 tegra_cursor_plane_formats[] = {
670 static int tegra_cursor_atomic_check(struct drm_plane *plane,
671 struct drm_plane_state *state)
673 struct tegra_plane *tegra = to_tegra_plane(plane);
676 /* no need for further checks if the plane is being disabled */
680 /* scaling not supported for cursor */
681 if ((state->src_w >> 16 != state->crtc_w) ||
682 (state->src_h >> 16 != state->crtc_h))
685 /* only square cursors supported */
686 if (state->src_w != state->src_h)
689 if (state->crtc_w != 32 && state->crtc_w != 64 &&
690 state->crtc_w != 128 && state->crtc_w != 256)
693 err = tegra_plane_state_add(tegra, state);
700 static void tegra_cursor_atomic_update(struct drm_plane *plane,
701 struct drm_plane_state *old_state)
703 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
704 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
705 struct drm_plane_state *state = plane->state;
706 u32 value = CURSOR_CLIP_DISPLAY;
708 /* rien ne va plus */
709 if (!plane->state->crtc || !plane->state->fb)
712 switch (state->crtc_w) {
714 value |= CURSOR_SIZE_32x32;
718 value |= CURSOR_SIZE_64x64;
722 value |= CURSOR_SIZE_128x128;
726 value |= CURSOR_SIZE_256x256;
730 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
735 value |= (bo->paddr >> 10) & 0x3fffff;
736 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
738 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
739 value = (bo->paddr >> 32) & 0x3;
740 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
743 /* enable cursor and set blend mode */
744 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
745 value |= CURSOR_ENABLE;
746 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
748 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
749 value &= ~CURSOR_DST_BLEND_MASK;
750 value &= ~CURSOR_SRC_BLEND_MASK;
751 value |= CURSOR_MODE_NORMAL;
752 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
753 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
754 value |= CURSOR_ALPHA;
755 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
757 /* position the cursor */
758 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
759 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
763 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
764 struct drm_plane_state *old_state)
769 /* rien ne va plus */
770 if (!old_state || !old_state->crtc)
773 dc = to_tegra_dc(old_state->crtc);
775 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
776 value &= ~CURSOR_ENABLE;
777 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
780 static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
781 .update_plane = drm_atomic_helper_update_plane,
782 .disable_plane = drm_atomic_helper_disable_plane,
783 .destroy = tegra_plane_destroy,
784 .reset = tegra_plane_reset,
785 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
786 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
789 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
790 .prepare_fb = tegra_plane_prepare_fb,
791 .cleanup_fb = tegra_plane_cleanup_fb,
792 .atomic_check = tegra_cursor_atomic_check,
793 .atomic_update = tegra_cursor_atomic_update,
794 .atomic_disable = tegra_cursor_atomic_disable,
797 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
800 struct tegra_plane *plane;
801 unsigned int num_formats;
805 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
807 return ERR_PTR(-ENOMEM);
810 * We'll treat the cursor as an overlay plane with index 6 here so
811 * that the update and activation request bits in DC_CMD_STATE_CONTROL
816 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
817 formats = tegra_cursor_plane_formats;
819 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
820 &tegra_cursor_plane_funcs, formats,
821 num_formats, DRM_PLANE_TYPE_CURSOR);
827 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
832 static void tegra_overlay_plane_destroy(struct drm_plane *plane)
834 tegra_plane_destroy(plane);
837 static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
838 .update_plane = drm_atomic_helper_update_plane,
839 .disable_plane = drm_atomic_helper_disable_plane,
840 .destroy = tegra_overlay_plane_destroy,
841 .reset = tegra_plane_reset,
842 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
843 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
846 static const uint32_t tegra_overlay_plane_formats[] = {
856 static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
857 .prepare_fb = tegra_plane_prepare_fb,
858 .cleanup_fb = tegra_plane_cleanup_fb,
859 .atomic_check = tegra_plane_atomic_check,
860 .atomic_update = tegra_plane_atomic_update,
861 .atomic_disable = tegra_plane_atomic_disable,
864 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
868 struct tegra_plane *plane;
869 unsigned int num_formats;
873 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
875 return ERR_PTR(-ENOMEM);
877 plane->index = index;
879 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
880 formats = tegra_overlay_plane_formats;
882 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
883 &tegra_overlay_plane_funcs, formats,
884 num_formats, DRM_PLANE_TYPE_OVERLAY);
890 drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
895 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
897 struct drm_plane *plane;
900 for (i = 0; i < 2; i++) {
901 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
903 return PTR_ERR(plane);
909 void tegra_dc_enable_vblank(struct tegra_dc *dc)
911 unsigned long value, flags;
913 spin_lock_irqsave(&dc->lock, flags);
915 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
917 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
919 spin_unlock_irqrestore(&dc->lock, flags);
922 void tegra_dc_disable_vblank(struct tegra_dc *dc)
924 unsigned long value, flags;
926 spin_lock_irqsave(&dc->lock, flags);
928 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
929 value &= ~VBLANK_INT;
930 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
932 spin_unlock_irqrestore(&dc->lock, flags);
935 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
937 struct drm_device *drm = dc->base.dev;
938 struct drm_crtc *crtc = &dc->base;
939 unsigned long flags, base;
942 spin_lock_irqsave(&drm->event_lock, flags);
945 spin_unlock_irqrestore(&drm->event_lock, flags);
949 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
951 spin_lock(&dc->lock);
953 /* check if new start address has been latched */
954 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
955 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
956 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
957 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
959 spin_unlock(&dc->lock);
961 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
962 drm_crtc_send_vblank_event(crtc, dc->event);
963 drm_crtc_vblank_put(crtc);
967 spin_unlock_irqrestore(&drm->event_lock, flags);
970 void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
972 struct tegra_dc *dc = to_tegra_dc(crtc);
973 struct drm_device *drm = crtc->dev;
976 spin_lock_irqsave(&drm->event_lock, flags);
978 if (dc->event && dc->event->base.file_priv == file) {
979 dc->event->base.destroy(&dc->event->base);
980 drm_crtc_vblank_put(crtc);
984 spin_unlock_irqrestore(&drm->event_lock, flags);
987 static void tegra_dc_destroy(struct drm_crtc *crtc)
989 drm_crtc_cleanup(crtc);
992 static void tegra_crtc_reset(struct drm_crtc *crtc)
994 struct tegra_dc_state *state;
999 state = kzalloc(sizeof(*state), GFP_KERNEL);
1001 crtc->state = &state->base;
1004 static struct drm_crtc_state *
1005 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1007 struct tegra_dc_state *state = to_dc_state(crtc->state);
1008 struct tegra_dc_state *copy;
1010 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1014 copy->base.mode_changed = false;
1015 copy->base.planes_changed = false;
1016 copy->base.event = NULL;
1021 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1022 struct drm_crtc_state *state)
1027 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1028 .page_flip = drm_atomic_helper_page_flip,
1029 .set_config = drm_atomic_helper_set_config,
1030 .destroy = tegra_dc_destroy,
1031 .reset = tegra_crtc_reset,
1032 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1033 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1036 static void tegra_dc_stop(struct tegra_dc *dc)
1040 /* stop the display controller */
1041 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1042 value &= ~DISP_CTRL_MODE_MASK;
1043 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1045 tegra_dc_commit(dc);
1048 static bool tegra_dc_idle(struct tegra_dc *dc)
1052 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1054 return (value & DISP_CTRL_MODE_MASK) == 0;
1057 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1059 timeout = jiffies + msecs_to_jiffies(timeout);
1061 while (time_before(jiffies, timeout)) {
1062 if (tegra_dc_idle(dc))
1065 usleep_range(1000, 2000);
1068 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1072 static void tegra_crtc_disable(struct drm_crtc *crtc)
1074 struct tegra_dc *dc = to_tegra_dc(crtc);
1077 if (!tegra_dc_idle(dc)) {
1081 * Ignore the return value, there isn't anything useful to do
1082 * in case this fails.
1084 tegra_dc_wait_idle(dc, 100);
1088 * This should really be part of the RGB encoder driver, but clearing
1089 * these bits has the side-effect of stopping the display controller.
1090 * When that happens no VBLANK interrupts will be raised. At the same
1091 * time the encoder is disabled before the display controller, so the
1092 * above code is always going to timeout waiting for the controller
1095 * Given the close coupling between the RGB encoder and the display
1096 * controller doing it here is still kind of okay. None of the other
1097 * encoder drivers require these bits to be cleared.
1099 * XXX: Perhaps given that the display controller is switched off at
1100 * this point anyway maybe clearing these bits isn't even useful for
1104 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1105 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1106 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1107 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1110 drm_crtc_vblank_off(crtc);
1113 static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
1114 const struct drm_display_mode *mode,
1115 struct drm_display_mode *adjusted)
1120 static int tegra_dc_set_timings(struct tegra_dc *dc,
1121 struct drm_display_mode *mode)
1123 unsigned int h_ref_to_sync = 1;
1124 unsigned int v_ref_to_sync = 1;
1125 unsigned long value;
1127 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1129 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1130 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1132 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1133 ((mode->hsync_end - mode->hsync_start) << 0);
1134 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1136 value = ((mode->vtotal - mode->vsync_end) << 16) |
1137 ((mode->htotal - mode->hsync_end) << 0);
1138 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1140 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1141 ((mode->hsync_start - mode->hdisplay) << 0);
1142 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1144 value = (mode->vdisplay << 16) | mode->hdisplay;
1145 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1150 int tegra_dc_setup_clock(struct tegra_dc *dc, struct clk *parent,
1151 unsigned long pclk, unsigned int div)
1156 err = clk_set_parent(dc->clk, parent);
1158 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1162 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div);
1164 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
1165 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1170 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1171 struct drm_crtc_state *crtc_state,
1172 struct clk *clk, unsigned long pclk,
1175 struct tegra_dc_state *state = to_dc_state(crtc_state);
1184 static void tegra_dc_commit_state(struct tegra_dc *dc,
1185 struct tegra_dc_state *state)
1190 err = clk_set_parent(dc->clk, state->clk);
1192 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1195 * Outputs may not want to change the parent clock rate. This is only
1196 * relevant to Tegra20 where only a single display PLL is available.
1197 * Since that PLL would typically be used for HDMI, an internal LVDS
1198 * panel would need to be driven by some other clock such as PLL_P
1199 * which is shared with other peripherals. Changing the clock rate
1200 * should therefore be avoided.
1202 if (state->pclk > 0) {
1203 err = clk_set_rate(state->clk, state->pclk);
1206 "failed to set clock rate to %lu Hz\n",
1210 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1212 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1214 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1215 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1218 static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
1220 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1221 struct tegra_dc_state *state = to_dc_state(crtc->state);
1222 struct tegra_dc *dc = to_tegra_dc(crtc);
1225 tegra_dc_commit_state(dc, state);
1227 /* program display mode */
1228 tegra_dc_set_timings(dc, mode);
1230 if (dc->soc->supports_border_color)
1231 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1233 /* interlacing isn't supported yet, so disable it */
1234 if (dc->soc->supports_interlacing) {
1235 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1236 value &= ~INTERLACE_ENABLE;
1237 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1240 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1241 value &= ~DISP_CTRL_MODE_MASK;
1242 value |= DISP_CTRL_MODE_C_DISPLAY;
1243 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1245 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1246 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1247 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1248 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1250 tegra_dc_commit(dc);
1253 static void tegra_crtc_prepare(struct drm_crtc *crtc)
1255 struct tegra_dc *dc = to_tegra_dc(crtc);
1256 unsigned int syncpt;
1257 unsigned long value;
1259 drm_crtc_vblank_off(crtc);
1262 syncpt = SYNCPT_VBLANK1;
1264 syncpt = SYNCPT_VBLANK0;
1266 /* initialize display controller */
1267 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1268 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
1270 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
1271 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1273 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1274 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1275 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1277 /* initialize timer */
1278 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1279 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1280 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1282 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1283 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1284 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1286 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1287 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1289 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1290 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1293 static void tegra_crtc_commit(struct drm_crtc *crtc)
1295 drm_crtc_vblank_on(crtc);
1298 static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1299 struct drm_crtc_state *state)
1304 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc)
1306 struct tegra_dc *dc = to_tegra_dc(crtc);
1308 if (crtc->state->event) {
1309 crtc->state->event->pipe = drm_crtc_index(crtc);
1311 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1313 dc->event = crtc->state->event;
1314 crtc->state->event = NULL;
1318 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc)
1320 struct tegra_dc_state *state = to_dc_state(crtc->state);
1321 struct tegra_dc *dc = to_tegra_dc(crtc);
1323 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1324 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
1327 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1328 .disable = tegra_crtc_disable,
1329 .mode_fixup = tegra_crtc_mode_fixup,
1330 .mode_set = drm_helper_crtc_mode_set,
1331 .mode_set_nofb = tegra_crtc_mode_set_nofb,
1332 .mode_set_base = drm_helper_crtc_mode_set_base,
1333 .prepare = tegra_crtc_prepare,
1334 .commit = tegra_crtc_commit,
1335 .atomic_check = tegra_crtc_atomic_check,
1336 .atomic_begin = tegra_crtc_atomic_begin,
1337 .atomic_flush = tegra_crtc_atomic_flush,
1340 static irqreturn_t tegra_dc_irq(int irq, void *data)
1342 struct tegra_dc *dc = data;
1343 unsigned long status;
1345 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1346 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1348 if (status & FRAME_END_INT) {
1350 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1354 if (status & VBLANK_INT) {
1356 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1358 drm_crtc_handle_vblank(&dc->base);
1359 tegra_dc_finish_page_flip(dc);
1362 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1364 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1371 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1373 struct drm_info_node *node = s->private;
1374 struct tegra_dc *dc = node->info_ent->data;
1376 #define DUMP_REG(name) \
1377 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
1378 tegra_dc_readl(dc, name))
1380 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1381 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1382 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1383 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1384 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1385 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1386 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1387 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1388 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1389 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1390 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1391 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1392 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1393 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1394 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1395 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1396 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1397 DUMP_REG(DC_CMD_INT_STATUS);
1398 DUMP_REG(DC_CMD_INT_MASK);
1399 DUMP_REG(DC_CMD_INT_ENABLE);
1400 DUMP_REG(DC_CMD_INT_TYPE);
1401 DUMP_REG(DC_CMD_INT_POLARITY);
1402 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1403 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1404 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1405 DUMP_REG(DC_CMD_STATE_ACCESS);
1406 DUMP_REG(DC_CMD_STATE_CONTROL);
1407 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1408 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1409 DUMP_REG(DC_COM_CRC_CONTROL);
1410 DUMP_REG(DC_COM_CRC_CHECKSUM);
1411 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1412 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1413 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1414 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1415 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1416 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1417 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1418 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1419 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1420 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1421 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1422 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1423 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1424 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1425 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1426 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1427 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1428 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1429 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1430 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1431 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1432 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1433 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1434 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1435 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1436 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1437 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1438 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1439 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1440 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1441 DUMP_REG(DC_COM_SPI_CONTROL);
1442 DUMP_REG(DC_COM_SPI_START_BYTE);
1443 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1444 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1445 DUMP_REG(DC_COM_HSPI_CS_DC);
1446 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1447 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1448 DUMP_REG(DC_COM_GPIO_CTRL);
1449 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1450 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1451 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1452 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1453 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1454 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1455 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1456 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1457 DUMP_REG(DC_DISP_REF_TO_SYNC);
1458 DUMP_REG(DC_DISP_SYNC_WIDTH);
1459 DUMP_REG(DC_DISP_BACK_PORCH);
1460 DUMP_REG(DC_DISP_ACTIVE);
1461 DUMP_REG(DC_DISP_FRONT_PORCH);
1462 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1463 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1464 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1465 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1466 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1467 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1468 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1469 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1470 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1471 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1472 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1473 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1474 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1475 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1476 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1477 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1478 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1479 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1480 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1481 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1482 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1483 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1484 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1485 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1486 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1487 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1488 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1489 DUMP_REG(DC_DISP_M0_CONTROL);
1490 DUMP_REG(DC_DISP_M1_CONTROL);
1491 DUMP_REG(DC_DISP_DI_CONTROL);
1492 DUMP_REG(DC_DISP_PP_CONTROL);
1493 DUMP_REG(DC_DISP_PP_SELECT_A);
1494 DUMP_REG(DC_DISP_PP_SELECT_B);
1495 DUMP_REG(DC_DISP_PP_SELECT_C);
1496 DUMP_REG(DC_DISP_PP_SELECT_D);
1497 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1498 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1499 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1500 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1501 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1502 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1503 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1504 DUMP_REG(DC_DISP_BORDER_COLOR);
1505 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1506 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1507 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1508 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1509 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1510 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1511 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1512 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1513 DUMP_REG(DC_DISP_CURSOR_POSITION);
1514 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1515 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1516 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1517 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1518 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1519 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1520 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1521 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1522 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1523 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1524 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1525 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1526 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1527 DUMP_REG(DC_DISP_SD_CONTROL);
1528 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1529 DUMP_REG(DC_DISP_SD_LUT(0));
1530 DUMP_REG(DC_DISP_SD_LUT(1));
1531 DUMP_REG(DC_DISP_SD_LUT(2));
1532 DUMP_REG(DC_DISP_SD_LUT(3));
1533 DUMP_REG(DC_DISP_SD_LUT(4));
1534 DUMP_REG(DC_DISP_SD_LUT(5));
1535 DUMP_REG(DC_DISP_SD_LUT(6));
1536 DUMP_REG(DC_DISP_SD_LUT(7));
1537 DUMP_REG(DC_DISP_SD_LUT(8));
1538 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1539 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1540 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1541 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1542 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1543 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1544 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1545 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1546 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1547 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1548 DUMP_REG(DC_DISP_SD_BL_TF(0));
1549 DUMP_REG(DC_DISP_SD_BL_TF(1));
1550 DUMP_REG(DC_DISP_SD_BL_TF(2));
1551 DUMP_REG(DC_DISP_SD_BL_TF(3));
1552 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1553 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1554 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1555 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1556 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1557 DUMP_REG(DC_WIN_WIN_OPTIONS);
1558 DUMP_REG(DC_WIN_BYTE_SWAP);
1559 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1560 DUMP_REG(DC_WIN_COLOR_DEPTH);
1561 DUMP_REG(DC_WIN_POSITION);
1562 DUMP_REG(DC_WIN_SIZE);
1563 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1564 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1565 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1566 DUMP_REG(DC_WIN_DDA_INC);
1567 DUMP_REG(DC_WIN_LINE_STRIDE);
1568 DUMP_REG(DC_WIN_BUF_STRIDE);
1569 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1570 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1571 DUMP_REG(DC_WIN_DV_CONTROL);
1572 DUMP_REG(DC_WIN_BLEND_NOKEY);
1573 DUMP_REG(DC_WIN_BLEND_1WIN);
1574 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1575 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1576 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1577 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1578 DUMP_REG(DC_WINBUF_START_ADDR);
1579 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1580 DUMP_REG(DC_WINBUF_START_ADDR_U);
1581 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1582 DUMP_REG(DC_WINBUF_START_ADDR_V);
1583 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1584 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1585 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1586 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1587 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1588 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1589 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1590 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1591 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1598 static struct drm_info_list debugfs_files[] = {
1599 { "regs", tegra_dc_show_regs, 0, NULL },
1602 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1608 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1609 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1615 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1617 if (!dc->debugfs_files) {
1622 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1623 dc->debugfs_files[i].data = dc;
1625 err = drm_debugfs_create_files(dc->debugfs_files,
1626 ARRAY_SIZE(debugfs_files),
1627 dc->debugfs, minor);
1636 kfree(dc->debugfs_files);
1637 dc->debugfs_files = NULL;
1639 debugfs_remove(dc->debugfs);
1645 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1647 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1651 kfree(dc->debugfs_files);
1652 dc->debugfs_files = NULL;
1654 debugfs_remove(dc->debugfs);
1660 static int tegra_dc_init(struct host1x_client *client)
1662 struct drm_device *drm = dev_get_drvdata(client->parent);
1663 struct tegra_dc *dc = host1x_client_to_dc(client);
1664 struct tegra_drm *tegra = drm->dev_private;
1665 struct drm_plane *primary = NULL;
1666 struct drm_plane *cursor = NULL;
1669 if (tegra->domain) {
1670 err = iommu_attach_device(tegra->domain, dc->dev);
1672 dev_err(dc->dev, "failed to attach to domain: %d\n",
1677 dc->domain = tegra->domain;
1680 primary = tegra_dc_primary_plane_create(drm, dc);
1681 if (IS_ERR(primary)) {
1682 err = PTR_ERR(primary);
1686 if (dc->soc->supports_cursor) {
1687 cursor = tegra_dc_cursor_plane_create(drm, dc);
1688 if (IS_ERR(cursor)) {
1689 err = PTR_ERR(cursor);
1694 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1699 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1700 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1703 * Keep track of the minimum pitch alignment across all display
1706 if (dc->soc->pitch_align > tegra->pitch_align)
1707 tegra->pitch_align = dc->soc->pitch_align;
1709 err = tegra_dc_rgb_init(drm, dc);
1710 if (err < 0 && err != -ENODEV) {
1711 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1715 err = tegra_dc_add_planes(drm, dc);
1719 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1720 err = tegra_dc_debugfs_init(dc, drm->primary);
1722 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1725 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1726 dev_name(dc->dev), dc);
1728 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1737 drm_plane_cleanup(cursor);
1740 drm_plane_cleanup(primary);
1742 if (tegra->domain) {
1743 iommu_detach_device(tegra->domain, dc->dev);
1750 static int tegra_dc_exit(struct host1x_client *client)
1752 struct tegra_dc *dc = host1x_client_to_dc(client);
1755 devm_free_irq(dc->dev, dc->irq, dc);
1757 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1758 err = tegra_dc_debugfs_exit(dc);
1760 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1763 err = tegra_dc_rgb_exit(dc);
1765 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1770 iommu_detach_device(dc->domain, dc->dev);
1777 static const struct host1x_client_ops dc_client_ops = {
1778 .init = tegra_dc_init,
1779 .exit = tegra_dc_exit,
1782 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1783 .supports_border_color = true,
1784 .supports_interlacing = false,
1785 .supports_cursor = false,
1786 .supports_block_linear = false,
1788 .has_powergate = false,
1791 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1792 .supports_border_color = true,
1793 .supports_interlacing = false,
1794 .supports_cursor = false,
1795 .supports_block_linear = false,
1797 .has_powergate = false,
1800 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1801 .supports_border_color = true,
1802 .supports_interlacing = false,
1803 .supports_cursor = false,
1804 .supports_block_linear = false,
1806 .has_powergate = true,
1809 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1810 .supports_border_color = false,
1811 .supports_interlacing = true,
1812 .supports_cursor = true,
1813 .supports_block_linear = true,
1815 .has_powergate = true,
1818 static const struct of_device_id tegra_dc_of_match[] = {
1820 .compatible = "nvidia,tegra124-dc",
1821 .data = &tegra124_dc_soc_info,
1823 .compatible = "nvidia,tegra114-dc",
1824 .data = &tegra114_dc_soc_info,
1826 .compatible = "nvidia,tegra30-dc",
1827 .data = &tegra30_dc_soc_info,
1829 .compatible = "nvidia,tegra20-dc",
1830 .data = &tegra20_dc_soc_info,
1835 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1837 static int tegra_dc_parse_dt(struct tegra_dc *dc)
1839 struct device_node *np;
1843 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1845 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1848 * If the nvidia,head property isn't present, try to find the
1849 * correct head number by looking up the position of this
1850 * display controller's node within the device tree. Assuming
1851 * that the nodes are ordered properly in the DTS file and
1852 * that the translation into a flattened device tree blob
1853 * preserves that ordering this will actually yield the right
1856 * If those assumptions don't hold, this will still work for
1857 * cases where only a single display controller is used.
1859 for_each_matching_node(np, tegra_dc_of_match) {
1860 if (np == dc->dev->of_node)
1872 static int tegra_dc_probe(struct platform_device *pdev)
1874 const struct of_device_id *id;
1875 struct resource *regs;
1876 struct tegra_dc *dc;
1879 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1883 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1887 spin_lock_init(&dc->lock);
1888 INIT_LIST_HEAD(&dc->list);
1889 dc->dev = &pdev->dev;
1892 err = tegra_dc_parse_dt(dc);
1896 dc->clk = devm_clk_get(&pdev->dev, NULL);
1897 if (IS_ERR(dc->clk)) {
1898 dev_err(&pdev->dev, "failed to get clock\n");
1899 return PTR_ERR(dc->clk);
1902 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1903 if (IS_ERR(dc->rst)) {
1904 dev_err(&pdev->dev, "failed to get reset\n");
1905 return PTR_ERR(dc->rst);
1908 if (dc->soc->has_powergate) {
1910 dc->powergate = TEGRA_POWERGATE_DIS;
1912 dc->powergate = TEGRA_POWERGATE_DISB;
1914 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1917 dev_err(&pdev->dev, "failed to power partition: %d\n",
1922 err = clk_prepare_enable(dc->clk);
1924 dev_err(&pdev->dev, "failed to enable clock: %d\n",
1929 err = reset_control_deassert(dc->rst);
1931 dev_err(&pdev->dev, "failed to deassert reset: %d\n",
1937 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1938 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1939 if (IS_ERR(dc->regs))
1940 return PTR_ERR(dc->regs);
1942 dc->irq = platform_get_irq(pdev, 0);
1944 dev_err(&pdev->dev, "failed to get IRQ\n");
1948 INIT_LIST_HEAD(&dc->client.list);
1949 dc->client.ops = &dc_client_ops;
1950 dc->client.dev = &pdev->dev;
1952 err = tegra_dc_rgb_probe(dc);
1953 if (err < 0 && err != -ENODEV) {
1954 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1958 err = host1x_client_register(&dc->client);
1960 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1965 platform_set_drvdata(pdev, dc);
1970 static int tegra_dc_remove(struct platform_device *pdev)
1972 struct tegra_dc *dc = platform_get_drvdata(pdev);
1975 err = host1x_client_unregister(&dc->client);
1977 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1982 err = tegra_dc_rgb_remove(dc);
1984 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1988 reset_control_assert(dc->rst);
1990 if (dc->soc->has_powergate)
1991 tegra_powergate_power_off(dc->powergate);
1993 clk_disable_unprepare(dc->clk);
1998 struct platform_driver tegra_dc_driver = {
2001 .owner = THIS_MODULE,
2002 .of_match_table = tegra_dc_of_match,
2004 .probe = tegra_dc_probe,
2005 .remove = tegra_dc_remove,