2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
33 #include "radeon_asic.h"
35 #include "rv515_reg_safe.h"
37 /* This files gather functions specifics to: rv515 */
38 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
39 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
40 void rv515_gpu_init(struct radeon_device *rdev);
41 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
43 void rv515_debugfs(struct radeon_device *rdev)
45 if (r100_debugfs_rbbm_init(rdev)) {
46 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
48 if (rv515_debugfs_pipes_info_init(rdev)) {
49 DRM_ERROR("Failed to register debugfs file for pipes !\n");
51 if (rv515_debugfs_ga_info_init(rdev)) {
52 DRM_ERROR("Failed to register debugfs file for pipes !\n");
56 void rv515_ring_start(struct radeon_device *rdev)
60 r = radeon_ring_lock(rdev, 64);
64 radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
65 radeon_ring_write(rdev,
69 ISYNC_CPSCRATCH_IDLEGUI);
70 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
71 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
72 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
73 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
74 radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
75 radeon_ring_write(rdev, 0);
76 radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
77 radeon_ring_write(rdev, 0);
78 radeon_ring_write(rdev, PACKET0(R500_SU_REG_DEST, 0));
79 radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
80 radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
81 radeon_ring_write(rdev, 0);
82 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
83 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
84 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
85 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
86 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
87 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
88 radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
89 radeon_ring_write(rdev, 0);
90 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
91 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
92 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
93 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
94 radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
95 radeon_ring_write(rdev,
102 (6 << MSBD0_Y_SHIFT) |
103 (6 << MSBD0_X_SHIFT)));
104 radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
105 radeon_ring_write(rdev,
106 ((6 << MS_X3_SHIFT) |
112 (6 << MSBD1_SHIFT)));
113 radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
114 radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
115 radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
116 radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
117 radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
118 radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
119 radeon_ring_write(rdev, PACKET0(0x20C8, 0));
120 radeon_ring_write(rdev, 0);
121 radeon_ring_unlock_commit(rdev);
124 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
129 for (i = 0; i < rdev->usec_timeout; i++) {
131 tmp = RREG32_MC(MC_STATUS);
132 if (tmp & MC_STATUS_IDLE) {
140 void rv515_vga_render_disable(struct radeon_device *rdev)
142 WREG32(R_000300_VGA_RENDER_CONTROL,
143 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
146 void rv515_gpu_init(struct radeon_device *rdev)
148 unsigned pipe_select_current, gb_pipe_select, tmp;
150 if (r100_gui_wait_for_idle(rdev)) {
151 printk(KERN_WARNING "Failed to wait GUI idle while "
152 "reseting GPU. Bad things might happen.\n");
154 rv515_vga_render_disable(rdev);
155 r420_pipes_init(rdev);
156 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
157 tmp = RREG32(R300_DST_PIPE_CONFIG);
158 pipe_select_current = (tmp >> 2) & 3;
159 tmp = (1 << pipe_select_current) |
160 (((gb_pipe_select >> 8) & 0xF) << 4);
161 WREG32_PLL(0x000D, tmp);
162 if (r100_gui_wait_for_idle(rdev)) {
163 printk(KERN_WARNING "Failed to wait GUI idle while "
164 "reseting GPU. Bad things might happen.\n");
166 if (rv515_mc_wait_for_idle(rdev)) {
167 printk(KERN_WARNING "Failed to wait MC idle while "
168 "programming pipes. Bad things might happen.\n");
172 static void rv515_vram_get_type(struct radeon_device *rdev)
176 rdev->mc.vram_width = 128;
177 rdev->mc.vram_is_ddr = true;
178 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
181 rdev->mc.vram_width = 64;
184 rdev->mc.vram_width = 128;
187 rdev->mc.vram_width = 128;
192 void rv515_mc_init(struct radeon_device *rdev)
195 rv515_vram_get_type(rdev);
196 r100_vram_init_sizes(rdev);
197 radeon_vram_location(rdev, &rdev->mc, 0);
198 rdev->mc.gtt_base_align = 0;
199 if (!(rdev->flags & RADEON_IS_AGP))
200 radeon_gtt_location(rdev, &rdev->mc);
201 radeon_update_bandwidth_info(rdev);
204 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
208 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
209 r = RREG32(MC_IND_DATA);
210 WREG32(MC_IND_INDEX, 0);
214 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
216 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
217 WREG32(MC_IND_DATA, (v));
218 WREG32(MC_IND_INDEX, 0);
221 #if defined(CONFIG_DEBUG_FS)
222 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
224 struct drm_info_node *node = (struct drm_info_node *) m->private;
225 struct drm_device *dev = node->minor->dev;
226 struct radeon_device *rdev = dev->dev_private;
229 tmp = RREG32(GB_PIPE_SELECT);
230 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
231 tmp = RREG32(SU_REG_DEST);
232 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
233 tmp = RREG32(GB_TILE_CONFIG);
234 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
235 tmp = RREG32(DST_PIPE_CONFIG);
236 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
240 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
242 struct drm_info_node *node = (struct drm_info_node *) m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct radeon_device *rdev = dev->dev_private;
247 tmp = RREG32(0x2140);
248 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
249 radeon_asic_reset(rdev);
250 tmp = RREG32(0x425C);
251 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
255 static struct drm_info_list rv515_pipes_info_list[] = {
256 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
259 static struct drm_info_list rv515_ga_info_list[] = {
260 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
264 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
266 #if defined(CONFIG_DEBUG_FS)
267 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
273 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
275 #if defined(CONFIG_DEBUG_FS)
276 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
282 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
284 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
285 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
288 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
289 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
290 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
291 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
292 WREG32(R_006080_D1CRTC_CONTROL, 0);
293 WREG32(R_006880_D2CRTC_CONTROL, 0);
294 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
295 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
296 WREG32(R_000330_D1VGA_CONTROL, 0);
297 WREG32(R_000338_D2VGA_CONTROL, 0);
300 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
302 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
303 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
304 WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
305 WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
306 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
307 /* Unlock host access */
308 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
310 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
313 void rv515_mc_program(struct radeon_device *rdev)
315 struct rv515_mc_save save;
317 /* Stops all mc clients */
318 rv515_mc_stop(rdev, &save);
320 /* Wait for mc idle */
321 if (rv515_mc_wait_for_idle(rdev))
322 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
323 /* Write VRAM size in case we are limiting it */
324 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
325 /* Program MC, should be a 32bits limited address space */
326 WREG32_MC(R_000001_MC_FB_LOCATION,
327 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
328 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
329 WREG32(R_000134_HDP_FB_LOCATION,
330 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
331 if (rdev->flags & RADEON_IS_AGP) {
332 WREG32_MC(R_000002_MC_AGP_LOCATION,
333 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
334 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
335 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
336 WREG32_MC(R_000004_MC_AGP_BASE_2,
337 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
339 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
340 WREG32_MC(R_000003_MC_AGP_BASE, 0);
341 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
344 rv515_mc_resume(rdev, &save);
347 void rv515_clock_startup(struct radeon_device *rdev)
349 if (radeon_dynclks != -1 && radeon_dynclks)
350 radeon_atom_set_clock_gating(rdev, 1);
351 /* We need to force on some of the block */
352 WREG32_PLL(R_00000F_CP_DYN_CNTL,
353 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
354 WREG32_PLL(R_000011_E2_DYN_CNTL,
355 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
356 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
357 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
360 static int rv515_startup(struct radeon_device *rdev)
364 rv515_mc_program(rdev);
366 rv515_clock_startup(rdev);
367 /* Initialize GPU configuration (# pipes, ...) */
368 rv515_gpu_init(rdev);
369 /* Initialize GART (initialize after TTM so we can allocate
370 * memory through TTM but finalize after TTM) */
371 if (rdev->flags & RADEON_IS_PCIE) {
372 r = rv370_pcie_gart_enable(rdev);
377 /* allocate wb buffer */
378 r = radeon_wb_init(rdev);
383 if (!rdev->irq.installed) {
384 r = radeon_irq_kms_init(rdev);
390 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
392 r = r100_cp_init(rdev, 1024 * 1024);
394 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
397 r = r100_ib_init(rdev);
399 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
405 int rv515_resume(struct radeon_device *rdev)
407 /* Make sur GART are not working */
408 if (rdev->flags & RADEON_IS_PCIE)
409 rv370_pcie_gart_disable(rdev);
410 /* Resume clock before doing reset */
411 rv515_clock_startup(rdev);
412 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
413 if (radeon_asic_reset(rdev)) {
414 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
415 RREG32(R_000E40_RBBM_STATUS),
416 RREG32(R_0007C0_CP_STAT));
419 atom_asic_init(rdev->mode_info.atom_context);
420 /* Resume clock after posting */
421 rv515_clock_startup(rdev);
422 /* Initialize surface registers */
423 radeon_surface_init(rdev);
424 return rv515_startup(rdev);
427 int rv515_suspend(struct radeon_device *rdev)
429 r100_cp_disable(rdev);
430 radeon_wb_disable(rdev);
431 rs600_irq_disable(rdev);
432 if (rdev->flags & RADEON_IS_PCIE)
433 rv370_pcie_gart_disable(rdev);
437 void rv515_set_safe_registers(struct radeon_device *rdev)
439 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
440 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
443 void rv515_fini(struct radeon_device *rdev)
446 radeon_wb_fini(rdev);
448 radeon_gem_fini(rdev);
449 rv370_pcie_gart_fini(rdev);
450 radeon_agp_fini(rdev);
451 radeon_irq_kms_fini(rdev);
452 radeon_fence_driver_fini(rdev);
453 radeon_bo_fini(rdev);
454 radeon_atombios_fini(rdev);
459 int rv515_init(struct radeon_device *rdev)
463 /* Initialize scratch registers */
464 radeon_scratch_init(rdev);
465 /* Initialize surface registers */
466 radeon_surface_init(rdev);
467 /* TODO: disable VGA need to use VGA request */
468 /* restore some register to sane defaults */
469 r100_restore_sanity(rdev);
471 if (!radeon_get_bios(rdev)) {
472 if (ASIC_IS_AVIVO(rdev))
475 if (rdev->is_atom_bios) {
476 r = radeon_atombios_init(rdev);
480 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
483 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
484 if (radeon_asic_reset(rdev)) {
486 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
487 RREG32(R_000E40_RBBM_STATUS),
488 RREG32(R_0007C0_CP_STAT));
490 /* check if cards are posted or not */
491 if (radeon_boot_test_post_card(rdev) == false)
493 /* Initialize clocks */
494 radeon_get_clock_info(rdev->ddev);
496 if (rdev->flags & RADEON_IS_AGP) {
497 r = radeon_agp_init(rdev);
499 radeon_agp_disable(rdev);
502 /* initialize memory controller */
506 r = radeon_fence_driver_init(rdev);
510 r = radeon_bo_init(rdev);
513 r = rv370_pcie_gart_init(rdev);
516 rv515_set_safe_registers(rdev);
517 rdev->accel_working = true;
518 r = rv515_startup(rdev);
520 /* Somethings want wront with the accel init stop accel */
521 dev_err(rdev->dev, "Disabling GPU acceleration\n");
523 radeon_wb_fini(rdev);
525 radeon_irq_kms_fini(rdev);
526 rv370_pcie_gart_fini(rdev);
527 radeon_agp_fini(rdev);
528 rdev->accel_working = false;
533 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
535 int index_reg = 0x6578 + crtc->crtc_offset;
536 int data_reg = 0x657c + crtc->crtc_offset;
538 WREG32(0x659C + crtc->crtc_offset, 0x0);
539 WREG32(0x6594 + crtc->crtc_offset, 0x705);
540 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
541 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
542 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
543 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
544 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
545 WREG32(index_reg, 0x0);
546 WREG32(data_reg, 0x841880A8);
547 WREG32(index_reg, 0x1);
548 WREG32(data_reg, 0x84208680);
549 WREG32(index_reg, 0x2);
550 WREG32(data_reg, 0xBFF880B0);
551 WREG32(index_reg, 0x100);
552 WREG32(data_reg, 0x83D88088);
553 WREG32(index_reg, 0x101);
554 WREG32(data_reg, 0x84608680);
555 WREG32(index_reg, 0x102);
556 WREG32(data_reg, 0xBFF080D0);
557 WREG32(index_reg, 0x200);
558 WREG32(data_reg, 0x83988068);
559 WREG32(index_reg, 0x201);
560 WREG32(data_reg, 0x84A08680);
561 WREG32(index_reg, 0x202);
562 WREG32(data_reg, 0xBFF080F8);
563 WREG32(index_reg, 0x300);
564 WREG32(data_reg, 0x83588058);
565 WREG32(index_reg, 0x301);
566 WREG32(data_reg, 0x84E08660);
567 WREG32(index_reg, 0x302);
568 WREG32(data_reg, 0xBFF88120);
569 WREG32(index_reg, 0x400);
570 WREG32(data_reg, 0x83188040);
571 WREG32(index_reg, 0x401);
572 WREG32(data_reg, 0x85008660);
573 WREG32(index_reg, 0x402);
574 WREG32(data_reg, 0xBFF88150);
575 WREG32(index_reg, 0x500);
576 WREG32(data_reg, 0x82D88030);
577 WREG32(index_reg, 0x501);
578 WREG32(data_reg, 0x85408640);
579 WREG32(index_reg, 0x502);
580 WREG32(data_reg, 0xBFF88180);
581 WREG32(index_reg, 0x600);
582 WREG32(data_reg, 0x82A08018);
583 WREG32(index_reg, 0x601);
584 WREG32(data_reg, 0x85808620);
585 WREG32(index_reg, 0x602);
586 WREG32(data_reg, 0xBFF081B8);
587 WREG32(index_reg, 0x700);
588 WREG32(data_reg, 0x82608010);
589 WREG32(index_reg, 0x701);
590 WREG32(data_reg, 0x85A08600);
591 WREG32(index_reg, 0x702);
592 WREG32(data_reg, 0x800081F0);
593 WREG32(index_reg, 0x800);
594 WREG32(data_reg, 0x8228BFF8);
595 WREG32(index_reg, 0x801);
596 WREG32(data_reg, 0x85E085E0);
597 WREG32(index_reg, 0x802);
598 WREG32(data_reg, 0xBFF88228);
599 WREG32(index_reg, 0x10000);
600 WREG32(data_reg, 0x82A8BF00);
601 WREG32(index_reg, 0x10001);
602 WREG32(data_reg, 0x82A08CC0);
603 WREG32(index_reg, 0x10002);
604 WREG32(data_reg, 0x8008BEF8);
605 WREG32(index_reg, 0x10100);
606 WREG32(data_reg, 0x81F0BF28);
607 WREG32(index_reg, 0x10101);
608 WREG32(data_reg, 0x83608CA0);
609 WREG32(index_reg, 0x10102);
610 WREG32(data_reg, 0x8018BED0);
611 WREG32(index_reg, 0x10200);
612 WREG32(data_reg, 0x8148BF38);
613 WREG32(index_reg, 0x10201);
614 WREG32(data_reg, 0x84408C80);
615 WREG32(index_reg, 0x10202);
616 WREG32(data_reg, 0x8008BEB8);
617 WREG32(index_reg, 0x10300);
618 WREG32(data_reg, 0x80B0BF78);
619 WREG32(index_reg, 0x10301);
620 WREG32(data_reg, 0x85008C20);
621 WREG32(index_reg, 0x10302);
622 WREG32(data_reg, 0x8020BEA0);
623 WREG32(index_reg, 0x10400);
624 WREG32(data_reg, 0x8028BF90);
625 WREG32(index_reg, 0x10401);
626 WREG32(data_reg, 0x85E08BC0);
627 WREG32(index_reg, 0x10402);
628 WREG32(data_reg, 0x8018BE90);
629 WREG32(index_reg, 0x10500);
630 WREG32(data_reg, 0xBFB8BFB0);
631 WREG32(index_reg, 0x10501);
632 WREG32(data_reg, 0x86C08B40);
633 WREG32(index_reg, 0x10502);
634 WREG32(data_reg, 0x8010BE90);
635 WREG32(index_reg, 0x10600);
636 WREG32(data_reg, 0xBF58BFC8);
637 WREG32(index_reg, 0x10601);
638 WREG32(data_reg, 0x87A08AA0);
639 WREG32(index_reg, 0x10602);
640 WREG32(data_reg, 0x8010BE98);
641 WREG32(index_reg, 0x10700);
642 WREG32(data_reg, 0xBF10BFF0);
643 WREG32(index_reg, 0x10701);
644 WREG32(data_reg, 0x886089E0);
645 WREG32(index_reg, 0x10702);
646 WREG32(data_reg, 0x8018BEB0);
647 WREG32(index_reg, 0x10800);
648 WREG32(data_reg, 0xBED8BFE8);
649 WREG32(index_reg, 0x10801);
650 WREG32(data_reg, 0x89408940);
651 WREG32(index_reg, 0x10802);
652 WREG32(data_reg, 0xBFE8BED8);
653 WREG32(index_reg, 0x20000);
654 WREG32(data_reg, 0x80008000);
655 WREG32(index_reg, 0x20001);
656 WREG32(data_reg, 0x90008000);
657 WREG32(index_reg, 0x20002);
658 WREG32(data_reg, 0x80008000);
659 WREG32(index_reg, 0x20003);
660 WREG32(data_reg, 0x80008000);
661 WREG32(index_reg, 0x20100);
662 WREG32(data_reg, 0x80108000);
663 WREG32(index_reg, 0x20101);
664 WREG32(data_reg, 0x8FE0BF70);
665 WREG32(index_reg, 0x20102);
666 WREG32(data_reg, 0xBFE880C0);
667 WREG32(index_reg, 0x20103);
668 WREG32(data_reg, 0x80008000);
669 WREG32(index_reg, 0x20200);
670 WREG32(data_reg, 0x8018BFF8);
671 WREG32(index_reg, 0x20201);
672 WREG32(data_reg, 0x8F80BF08);
673 WREG32(index_reg, 0x20202);
674 WREG32(data_reg, 0xBFD081A0);
675 WREG32(index_reg, 0x20203);
676 WREG32(data_reg, 0xBFF88000);
677 WREG32(index_reg, 0x20300);
678 WREG32(data_reg, 0x80188000);
679 WREG32(index_reg, 0x20301);
680 WREG32(data_reg, 0x8EE0BEC0);
681 WREG32(index_reg, 0x20302);
682 WREG32(data_reg, 0xBFB082A0);
683 WREG32(index_reg, 0x20303);
684 WREG32(data_reg, 0x80008000);
685 WREG32(index_reg, 0x20400);
686 WREG32(data_reg, 0x80188000);
687 WREG32(index_reg, 0x20401);
688 WREG32(data_reg, 0x8E00BEA0);
689 WREG32(index_reg, 0x20402);
690 WREG32(data_reg, 0xBF8883C0);
691 WREG32(index_reg, 0x20403);
692 WREG32(data_reg, 0x80008000);
693 WREG32(index_reg, 0x20500);
694 WREG32(data_reg, 0x80188000);
695 WREG32(index_reg, 0x20501);
696 WREG32(data_reg, 0x8D00BE90);
697 WREG32(index_reg, 0x20502);
698 WREG32(data_reg, 0xBF588500);
699 WREG32(index_reg, 0x20503);
700 WREG32(data_reg, 0x80008008);
701 WREG32(index_reg, 0x20600);
702 WREG32(data_reg, 0x80188000);
703 WREG32(index_reg, 0x20601);
704 WREG32(data_reg, 0x8BC0BE98);
705 WREG32(index_reg, 0x20602);
706 WREG32(data_reg, 0xBF308660);
707 WREG32(index_reg, 0x20603);
708 WREG32(data_reg, 0x80008008);
709 WREG32(index_reg, 0x20700);
710 WREG32(data_reg, 0x80108000);
711 WREG32(index_reg, 0x20701);
712 WREG32(data_reg, 0x8A80BEB0);
713 WREG32(index_reg, 0x20702);
714 WREG32(data_reg, 0xBF0087C0);
715 WREG32(index_reg, 0x20703);
716 WREG32(data_reg, 0x80008008);
717 WREG32(index_reg, 0x20800);
718 WREG32(data_reg, 0x80108000);
719 WREG32(index_reg, 0x20801);
720 WREG32(data_reg, 0x8920BED0);
721 WREG32(index_reg, 0x20802);
722 WREG32(data_reg, 0xBED08920);
723 WREG32(index_reg, 0x20803);
724 WREG32(data_reg, 0x80008010);
725 WREG32(index_reg, 0x30000);
726 WREG32(data_reg, 0x90008000);
727 WREG32(index_reg, 0x30001);
728 WREG32(data_reg, 0x80008000);
729 WREG32(index_reg, 0x30100);
730 WREG32(data_reg, 0x8FE0BF90);
731 WREG32(index_reg, 0x30101);
732 WREG32(data_reg, 0xBFF880A0);
733 WREG32(index_reg, 0x30200);
734 WREG32(data_reg, 0x8F60BF40);
735 WREG32(index_reg, 0x30201);
736 WREG32(data_reg, 0xBFE88180);
737 WREG32(index_reg, 0x30300);
738 WREG32(data_reg, 0x8EC0BF00);
739 WREG32(index_reg, 0x30301);
740 WREG32(data_reg, 0xBFC88280);
741 WREG32(index_reg, 0x30400);
742 WREG32(data_reg, 0x8DE0BEE0);
743 WREG32(index_reg, 0x30401);
744 WREG32(data_reg, 0xBFA083A0);
745 WREG32(index_reg, 0x30500);
746 WREG32(data_reg, 0x8CE0BED0);
747 WREG32(index_reg, 0x30501);
748 WREG32(data_reg, 0xBF7884E0);
749 WREG32(index_reg, 0x30600);
750 WREG32(data_reg, 0x8BA0BED8);
751 WREG32(index_reg, 0x30601);
752 WREG32(data_reg, 0xBF508640);
753 WREG32(index_reg, 0x30700);
754 WREG32(data_reg, 0x8A60BEE8);
755 WREG32(index_reg, 0x30701);
756 WREG32(data_reg, 0xBF2087A0);
757 WREG32(index_reg, 0x30800);
758 WREG32(data_reg, 0x8900BF00);
759 WREG32(index_reg, 0x30801);
760 WREG32(data_reg, 0xBF008900);
763 struct rv515_watermark {
764 u32 lb_request_fifo_depth;
765 fixed20_12 num_line_pair;
766 fixed20_12 estimated_width;
767 fixed20_12 worst_case_latency;
768 fixed20_12 consumption_rate;
769 fixed20_12 active_time;
771 fixed20_12 priority_mark_max;
772 fixed20_12 priority_mark;
776 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
777 struct radeon_crtc *crtc,
778 struct rv515_watermark *wm)
780 struct drm_display_mode *mode = &crtc->base.mode;
782 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
783 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
785 if (!crtc->base.enabled) {
786 /* FIXME: wouldn't it better to set priority mark to maximum */
787 wm->lb_request_fifo_depth = 4;
791 if (crtc->vsc.full > dfixed_const(2))
792 wm->num_line_pair.full = dfixed_const(2);
794 wm->num_line_pair.full = dfixed_const(1);
796 b.full = dfixed_const(mode->crtc_hdisplay);
797 c.full = dfixed_const(256);
798 a.full = dfixed_div(b, c);
799 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
800 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
801 if (a.full < dfixed_const(4)) {
802 wm->lb_request_fifo_depth = 4;
804 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
807 /* Determine consumption rate
808 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
809 * vtaps = number of vertical taps,
810 * vsc = vertical scaling ratio, defined as source/destination
811 * hsc = horizontal scaling ration, defined as source/destination
813 a.full = dfixed_const(mode->clock);
814 b.full = dfixed_const(1000);
815 a.full = dfixed_div(a, b);
816 pclk.full = dfixed_div(b, a);
817 if (crtc->rmx_type != RMX_OFF) {
818 b.full = dfixed_const(2);
819 if (crtc->vsc.full > b.full)
820 b.full = crtc->vsc.full;
821 b.full = dfixed_mul(b, crtc->hsc);
822 c.full = dfixed_const(2);
823 b.full = dfixed_div(b, c);
824 consumption_time.full = dfixed_div(pclk, b);
826 consumption_time.full = pclk.full;
828 a.full = dfixed_const(1);
829 wm->consumption_rate.full = dfixed_div(a, consumption_time);
832 /* Determine line time
833 * LineTime = total time for one line of displayhtotal
834 * LineTime = total number of horizontal pixels
835 * pclk = pixel clock period(ns)
837 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
838 line_time.full = dfixed_mul(a, pclk);
840 /* Determine active time
841 * ActiveTime = time of active region of display within one line,
842 * hactive = total number of horizontal active pixels
843 * htotal = total number of horizontal pixels
845 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
846 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
847 wm->active_time.full = dfixed_mul(line_time, b);
848 wm->active_time.full = dfixed_div(wm->active_time, a);
850 /* Determine chunk time
851 * ChunkTime = the time it takes the DCP to send one chunk of data
852 * to the LB which consists of pipeline delay and inter chunk gap
853 * sclk = system clock(Mhz)
855 a.full = dfixed_const(600 * 1000);
856 chunk_time.full = dfixed_div(a, rdev->pm.sclk);
857 read_delay_latency.full = dfixed_const(1000);
859 /* Determine the worst case latency
860 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
861 * WorstCaseLatency = worst case time from urgent to when the MC starts
863 * READ_DELAY_IDLE_MAX = constant of 1us
864 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
865 * which consists of pipeline delay and inter chunk gap
867 if (dfixed_trunc(wm->num_line_pair) > 1) {
868 a.full = dfixed_const(3);
869 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
870 wm->worst_case_latency.full += read_delay_latency.full;
872 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
875 /* Determine the tolerable latency
876 * TolerableLatency = Any given request has only 1 line time
877 * for the data to be returned
878 * LBRequestFifoDepth = Number of chunk requests the LB can
879 * put into the request FIFO for a display
880 * LineTime = total time for one line of display
881 * ChunkTime = the time it takes the DCP to send one chunk
882 * of data to the LB which consists of
883 * pipeline delay and inter chunk gap
885 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
886 tolerable_latency.full = line_time.full;
888 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
889 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
890 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
891 tolerable_latency.full = line_time.full - tolerable_latency.full;
893 /* We assume worst case 32bits (4 bytes) */
894 wm->dbpp.full = dfixed_const(2 * 16);
896 /* Determine the maximum priority mark
897 * width = viewport width in pixels
899 a.full = dfixed_const(16);
900 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
901 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
902 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
904 /* Determine estimated width */
905 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
906 estimated_width.full = dfixed_div(estimated_width, consumption_time);
907 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
908 wm->priority_mark.full = wm->priority_mark_max.full;
910 a.full = dfixed_const(16);
911 wm->priority_mark.full = dfixed_div(estimated_width, a);
912 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
913 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
917 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
919 struct drm_display_mode *mode0 = NULL;
920 struct drm_display_mode *mode1 = NULL;
921 struct rv515_watermark wm0;
922 struct rv515_watermark wm1;
924 u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
925 u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
926 fixed20_12 priority_mark02, priority_mark12, fill_rate;
929 if (rdev->mode_info.crtcs[0]->base.enabled)
930 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
931 if (rdev->mode_info.crtcs[1]->base.enabled)
932 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
933 rs690_line_buffer_adjust(rdev, mode0, mode1);
935 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
936 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
938 tmp = wm0.lb_request_fifo_depth;
939 tmp |= wm1.lb_request_fifo_depth << 16;
940 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
942 if (mode0 && mode1) {
943 if (dfixed_trunc(wm0.dbpp) > 64)
944 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
946 a.full = wm0.num_line_pair.full;
947 if (dfixed_trunc(wm1.dbpp) > 64)
948 b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
950 b.full = wm1.num_line_pair.full;
952 fill_rate.full = dfixed_div(wm0.sclk, a);
953 if (wm0.consumption_rate.full > fill_rate.full) {
954 b.full = wm0.consumption_rate.full - fill_rate.full;
955 b.full = dfixed_mul(b, wm0.active_time);
956 a.full = dfixed_const(16);
957 b.full = dfixed_div(b, a);
958 a.full = dfixed_mul(wm0.worst_case_latency,
959 wm0.consumption_rate);
960 priority_mark02.full = a.full + b.full;
962 a.full = dfixed_mul(wm0.worst_case_latency,
963 wm0.consumption_rate);
964 b.full = dfixed_const(16 * 1000);
965 priority_mark02.full = dfixed_div(a, b);
967 if (wm1.consumption_rate.full > fill_rate.full) {
968 b.full = wm1.consumption_rate.full - fill_rate.full;
969 b.full = dfixed_mul(b, wm1.active_time);
970 a.full = dfixed_const(16);
971 b.full = dfixed_div(b, a);
972 a.full = dfixed_mul(wm1.worst_case_latency,
973 wm1.consumption_rate);
974 priority_mark12.full = a.full + b.full;
976 a.full = dfixed_mul(wm1.worst_case_latency,
977 wm1.consumption_rate);
978 b.full = dfixed_const(16 * 1000);
979 priority_mark12.full = dfixed_div(a, b);
981 if (wm0.priority_mark.full > priority_mark02.full)
982 priority_mark02.full = wm0.priority_mark.full;
983 if (dfixed_trunc(priority_mark02) < 0)
984 priority_mark02.full = 0;
985 if (wm0.priority_mark_max.full > priority_mark02.full)
986 priority_mark02.full = wm0.priority_mark_max.full;
987 if (wm1.priority_mark.full > priority_mark12.full)
988 priority_mark12.full = wm1.priority_mark.full;
989 if (dfixed_trunc(priority_mark12) < 0)
990 priority_mark12.full = 0;
991 if (wm1.priority_mark_max.full > priority_mark12.full)
992 priority_mark12.full = wm1.priority_mark_max.full;
993 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
994 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
995 if (rdev->disp_priority == 2) {
996 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
997 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1000 if (dfixed_trunc(wm0.dbpp) > 64)
1001 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
1003 a.full = wm0.num_line_pair.full;
1004 fill_rate.full = dfixed_div(wm0.sclk, a);
1005 if (wm0.consumption_rate.full > fill_rate.full) {
1006 b.full = wm0.consumption_rate.full - fill_rate.full;
1007 b.full = dfixed_mul(b, wm0.active_time);
1008 a.full = dfixed_const(16);
1009 b.full = dfixed_div(b, a);
1010 a.full = dfixed_mul(wm0.worst_case_latency,
1011 wm0.consumption_rate);
1012 priority_mark02.full = a.full + b.full;
1014 a.full = dfixed_mul(wm0.worst_case_latency,
1015 wm0.consumption_rate);
1016 b.full = dfixed_const(16);
1017 priority_mark02.full = dfixed_div(a, b);
1019 if (wm0.priority_mark.full > priority_mark02.full)
1020 priority_mark02.full = wm0.priority_mark.full;
1021 if (dfixed_trunc(priority_mark02) < 0)
1022 priority_mark02.full = 0;
1023 if (wm0.priority_mark_max.full > priority_mark02.full)
1024 priority_mark02.full = wm0.priority_mark_max.full;
1025 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1026 if (rdev->disp_priority == 2)
1027 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1029 if (dfixed_trunc(wm1.dbpp) > 64)
1030 a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
1032 a.full = wm1.num_line_pair.full;
1033 fill_rate.full = dfixed_div(wm1.sclk, a);
1034 if (wm1.consumption_rate.full > fill_rate.full) {
1035 b.full = wm1.consumption_rate.full - fill_rate.full;
1036 b.full = dfixed_mul(b, wm1.active_time);
1037 a.full = dfixed_const(16);
1038 b.full = dfixed_div(b, a);
1039 a.full = dfixed_mul(wm1.worst_case_latency,
1040 wm1.consumption_rate);
1041 priority_mark12.full = a.full + b.full;
1043 a.full = dfixed_mul(wm1.worst_case_latency,
1044 wm1.consumption_rate);
1045 b.full = dfixed_const(16 * 1000);
1046 priority_mark12.full = dfixed_div(a, b);
1048 if (wm1.priority_mark.full > priority_mark12.full)
1049 priority_mark12.full = wm1.priority_mark.full;
1050 if (dfixed_trunc(priority_mark12) < 0)
1051 priority_mark12.full = 0;
1052 if (wm1.priority_mark_max.full > priority_mark12.full)
1053 priority_mark12.full = wm1.priority_mark_max.full;
1054 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1055 if (rdev->disp_priority == 2)
1056 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1059 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1060 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1061 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1062 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1065 void rv515_bandwidth_update(struct radeon_device *rdev)
1068 struct drm_display_mode *mode0 = NULL;
1069 struct drm_display_mode *mode1 = NULL;
1071 radeon_update_display_priority(rdev);
1073 if (rdev->mode_info.crtcs[0]->base.enabled)
1074 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1075 if (rdev->mode_info.crtcs[1]->base.enabled)
1076 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1078 * Set display0/1 priority up in the memory controller for
1079 * modes if the user specifies HIGH for displaypriority
1082 if ((rdev->disp_priority == 2) &&
1083 (rdev->family == CHIP_RV515)) {
1084 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1085 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1086 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1088 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1090 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1091 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1093 rv515_bandwidth_avivo_update(rdev);