2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
30 #include "radeon_drm.h"
31 #include "radeon_reg.h"
35 int radeon_debugfs_ib_init(struct radeon_device *rdev);
40 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
42 struct radeon_fence *fence;
43 struct radeon_ib *nib;
48 r = radeon_fence_create(rdev, &fence);
50 DRM_ERROR("failed to create fence for new IB\n");
53 mutex_lock(&rdev->ib_pool.mutex);
54 i = find_first_zero_bit(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
55 if (i < RADEON_IB_POOL_SIZE) {
56 set_bit(i, rdev->ib_pool.alloc_bm);
57 rdev->ib_pool.ibs[i].length_dw = 0;
58 *ib = &rdev->ib_pool.ibs[i];
61 if (list_empty(&rdev->ib_pool.scheduled_ibs)) {
62 /* we go do nothings here */
63 DRM_ERROR("all IB allocated none scheduled.\n");
67 /* get the first ib on the scheduled list */
68 nib = list_entry(rdev->ib_pool.scheduled_ibs.next,
69 struct radeon_ib, list);
70 if (nib->fence == NULL) {
71 /* we go do nothings here */
72 DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx);
76 r = radeon_fence_wait(nib->fence, false);
78 DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx,
79 (unsigned long)nib->gpu_addr, nib->length_dw);
80 DRM_ERROR("radeon: GPU lockup detected, fail to get a IB\n");
83 radeon_fence_unref(&nib->fence);
86 INIT_LIST_HEAD(&nib->list);
89 mutex_unlock(&rdev->ib_pool.mutex);
91 radeon_fence_unref(&fence);
98 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
100 struct radeon_ib *tmp = *ib;
106 mutex_lock(&rdev->ib_pool.mutex);
107 if (!list_empty(&tmp->list) && !radeon_fence_signaled(tmp->fence)) {
108 /* IB is scheduled & not signaled don't do anythings */
109 mutex_unlock(&rdev->ib_pool.mutex);
112 list_del(&tmp->list);
113 INIT_LIST_HEAD(&tmp->list);
115 radeon_fence_unref(&tmp->fence);
118 clear_bit(tmp->idx, rdev->ib_pool.alloc_bm);
119 mutex_unlock(&rdev->ib_pool.mutex);
122 static void radeon_ib_align(struct radeon_device *rdev, struct radeon_ib *ib)
124 while ((ib->length_dw & rdev->cp.align_mask)) {
125 ib->ptr[ib->length_dw++] = PACKET2(0);
129 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
133 mutex_lock(&rdev->ib_pool.mutex);
134 radeon_ib_align(rdev, ib);
135 if (!ib->length_dw || !rdev->cp.ready) {
136 /* TODO: Nothings in the ib we should report. */
137 mutex_unlock(&rdev->ib_pool.mutex);
138 DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx);
141 /* 64 dwords should be enough for fence too */
142 r = radeon_ring_lock(rdev, 64);
144 DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
145 mutex_unlock(&rdev->ib_pool.mutex);
148 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
149 radeon_ring_write(rdev, ib->gpu_addr);
150 radeon_ring_write(rdev, ib->length_dw);
151 radeon_fence_emit(rdev, ib->fence);
152 radeon_ring_unlock_commit(rdev);
153 list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs);
154 mutex_unlock(&rdev->ib_pool.mutex);
158 int radeon_ib_pool_init(struct radeon_device *rdev)
165 /* Allocate 1M object buffer */
166 INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs);
167 r = radeon_object_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
168 true, RADEON_GEM_DOMAIN_GTT,
169 false, &rdev->ib_pool.robj);
171 DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
174 r = radeon_object_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
176 DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
179 r = radeon_object_kmap(rdev->ib_pool.robj, &ptr);
181 DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);
184 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
187 offset = i * 64 * 1024;
188 rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
189 rdev->ib_pool.ibs[i].ptr = ptr + offset;
190 rdev->ib_pool.ibs[i].idx = i;
191 rdev->ib_pool.ibs[i].length_dw = 0;
192 INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].list);
194 bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
195 rdev->ib_pool.ready = true;
196 DRM_INFO("radeon: ib pool ready.\n");
197 if (radeon_debugfs_ib_init(rdev)) {
198 DRM_ERROR("Failed to register debugfs file for IB !\n");
203 void radeon_ib_pool_fini(struct radeon_device *rdev)
205 if (!rdev->ib_pool.ready) {
208 mutex_lock(&rdev->ib_pool.mutex);
209 bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
210 if (rdev->ib_pool.robj) {
211 radeon_object_kunmap(rdev->ib_pool.robj);
212 radeon_object_unref(&rdev->ib_pool.robj);
213 rdev->ib_pool.robj = NULL;
215 mutex_unlock(&rdev->ib_pool.mutex);
218 int radeon_ib_test(struct radeon_device *rdev)
220 struct radeon_ib *ib;
226 r = radeon_scratch_get(rdev, &scratch);
228 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
231 WREG32(scratch, 0xCAFEDEAD);
232 r = radeon_ib_get(rdev, &ib);
236 ib->ptr[0] = PACKET0(scratch, 0);
237 ib->ptr[1] = 0xDEADBEEF;
238 ib->ptr[2] = PACKET2(0);
239 ib->ptr[3] = PACKET2(0);
240 ib->ptr[4] = PACKET2(0);
241 ib->ptr[5] = PACKET2(0);
242 ib->ptr[6] = PACKET2(0);
243 ib->ptr[7] = PACKET2(0);
245 r = radeon_ib_schedule(rdev, ib);
247 radeon_scratch_free(rdev, scratch);
248 radeon_ib_free(rdev, &ib);
251 r = radeon_fence_wait(ib->fence, false);
255 for (i = 0; i < rdev->usec_timeout; i++) {
256 tmp = RREG32(scratch);
257 if (tmp == 0xDEADBEEF) {
262 if (i < rdev->usec_timeout) {
263 DRM_INFO("ib test succeeded in %u usecs\n", i);
265 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
269 radeon_scratch_free(rdev, scratch);
270 radeon_ib_free(rdev, &ib);
278 void radeon_ring_free_size(struct radeon_device *rdev)
280 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
281 /* This works because ring_size is a power of 2 */
282 rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
283 rdev->cp.ring_free_dw -= rdev->cp.wptr;
284 rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
285 if (!rdev->cp.ring_free_dw) {
286 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
290 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
294 /* Align requested size with padding so unlock_commit can
296 ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
297 mutex_lock(&rdev->cp.mutex);
298 while (ndw > (rdev->cp.ring_free_dw - 1)) {
299 radeon_ring_free_size(rdev);
300 if (ndw < rdev->cp.ring_free_dw) {
303 r = radeon_fence_wait_next(rdev);
305 mutex_unlock(&rdev->cp.mutex);
309 rdev->cp.count_dw = ndw;
310 rdev->cp.wptr_old = rdev->cp.wptr;
314 void radeon_ring_unlock_commit(struct radeon_device *rdev)
316 unsigned count_dw_pad;
319 /* We pad to match fetch size */
320 count_dw_pad = (rdev->cp.align_mask + 1) -
321 (rdev->cp.wptr & rdev->cp.align_mask);
322 for (i = 0; i < count_dw_pad; i++) {
323 radeon_ring_write(rdev, PACKET2(0));
326 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
327 (void)RREG32(RADEON_CP_RB_WPTR);
328 mutex_unlock(&rdev->cp.mutex);
331 void radeon_ring_unlock_undo(struct radeon_device *rdev)
333 rdev->cp.wptr = rdev->cp.wptr_old;
334 mutex_unlock(&rdev->cp.mutex);
337 int radeon_ring_test(struct radeon_device *rdev)
344 r = radeon_scratch_get(rdev, &scratch);
346 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
349 WREG32(scratch, 0xCAFEDEAD);
350 r = radeon_ring_lock(rdev, 2);
352 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
353 radeon_scratch_free(rdev, scratch);
356 radeon_ring_write(rdev, PACKET0(scratch, 0));
357 radeon_ring_write(rdev, 0xDEADBEEF);
358 radeon_ring_unlock_commit(rdev);
359 for (i = 0; i < rdev->usec_timeout; i++) {
360 tmp = RREG32(scratch);
361 if (tmp == 0xDEADBEEF) {
366 if (i < rdev->usec_timeout) {
367 DRM_INFO("ring test succeeded in %d usecs\n", i);
369 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
373 radeon_scratch_free(rdev, scratch);
377 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
381 rdev->cp.ring_size = ring_size;
382 /* Allocate ring buffer */
383 if (rdev->cp.ring_obj == NULL) {
384 r = radeon_object_create(rdev, NULL, rdev->cp.ring_size,
386 RADEON_GEM_DOMAIN_GTT,
390 DRM_ERROR("radeon: failed to create ring buffer (%d).\n", r);
391 mutex_unlock(&rdev->cp.mutex);
394 r = radeon_object_pin(rdev->cp.ring_obj,
395 RADEON_GEM_DOMAIN_GTT,
398 DRM_ERROR("radeon: failed to pin ring buffer (%d).\n", r);
399 mutex_unlock(&rdev->cp.mutex);
402 r = radeon_object_kmap(rdev->cp.ring_obj,
403 (void **)&rdev->cp.ring);
405 DRM_ERROR("radeon: failed to map ring buffer (%d).\n", r);
406 mutex_unlock(&rdev->cp.mutex);
410 rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
411 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
415 void radeon_ring_fini(struct radeon_device *rdev)
417 mutex_lock(&rdev->cp.mutex);
418 if (rdev->cp.ring_obj) {
419 radeon_object_kunmap(rdev->cp.ring_obj);
420 radeon_object_unpin(rdev->cp.ring_obj);
421 radeon_object_unref(&rdev->cp.ring_obj);
422 rdev->cp.ring = NULL;
423 rdev->cp.ring_obj = NULL;
425 mutex_unlock(&rdev->cp.mutex);
432 #if defined(CONFIG_DEBUG_FS)
433 static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
435 struct drm_info_node *node = (struct drm_info_node *) m->private;
436 struct radeon_ib *ib = node->info_ent->data;
442 seq_printf(m, "IB %04lu\n", ib->idx);
443 seq_printf(m, "IB fence %p\n", ib->fence);
444 seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
445 for (i = 0; i < ib->length_dw; i++) {
446 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
451 static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
452 static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
455 int radeon_debugfs_ib_init(struct radeon_device *rdev)
457 #if defined(CONFIG_DEBUG_FS)
460 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
461 sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
462 radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
463 radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
464 radeon_debugfs_ib_list[i].driver_features = 0;
465 radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
467 return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
468 RADEON_IB_POOL_SIZE);