2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include <drm/radeon_drm.h>
37 #include "radeon_trace.h"
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
49 void radeon_bo_clear_va(struct radeon_bo *bo)
51 struct radeon_bo_va *bo_va, *tmp;
53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
54 /* remove from all vm address space */
55 radeon_vm_bo_rmv(bo->rdev, bo_va);
59 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
63 bo = container_of(tbo, struct radeon_bo, tbo);
64 mutex_lock(&bo->rdev->gem.mutex);
65 list_del_init(&bo->list);
66 mutex_unlock(&bo->rdev->gem.mutex);
67 radeon_bo_clear_surface_reg(bo);
68 radeon_bo_clear_va(bo);
69 drm_gem_object_release(&bo->gem_base);
73 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
75 if (bo->destroy == &radeon_ttm_bo_destroy)
80 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
84 rbo->placement.fpfn = 0;
85 rbo->placement.lpfn = 0;
86 rbo->placement.placement = rbo->placements;
87 if (domain & RADEON_GEM_DOMAIN_VRAM)
88 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
90 if (domain & RADEON_GEM_DOMAIN_GTT) {
91 if (rbo->rdev->flags & RADEON_IS_AGP) {
92 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
94 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
97 if (domain & RADEON_GEM_DOMAIN_CPU) {
98 if (rbo->rdev->flags & RADEON_IS_AGP) {
99 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
101 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
105 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
106 rbo->placement.num_placement = c;
109 rbo->placement.busy_placement = rbo->busy_placements;
110 if (rbo->rdev->flags & RADEON_IS_AGP) {
111 rbo->busy_placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
113 rbo->busy_placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
115 rbo->placement.num_busy_placement = c;
118 int radeon_bo_create(struct radeon_device *rdev,
119 unsigned long size, int byte_align, bool kernel, u32 domain,
120 struct sg_table *sg, struct radeon_bo **bo_ptr)
122 struct radeon_bo *bo;
123 enum ttm_bo_type type;
124 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
128 size = ALIGN(size, PAGE_SIZE);
130 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
132 type = ttm_bo_type_kernel;
134 type = ttm_bo_type_sg;
136 type = ttm_bo_type_device;
140 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
141 sizeof(struct radeon_bo));
143 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
146 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
152 bo->gem_base.driver_private = NULL;
153 bo->surface_reg = -1;
154 INIT_LIST_HEAD(&bo->list);
155 INIT_LIST_HEAD(&bo->va);
156 radeon_ttm_placement_from_domain(bo, domain);
157 /* Kernel allocation are uninterruptible */
158 down_read(&rdev->pm.mclk_lock);
159 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
160 &bo->placement, page_align, !kernel, NULL,
161 acc_size, sg, &radeon_ttm_bo_destroy);
162 up_read(&rdev->pm.mclk_lock);
163 if (unlikely(r != 0)) {
168 trace_radeon_bo_create(bo);
173 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
184 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
188 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
192 radeon_bo_check_tiling(bo, 0, 0);
196 void radeon_bo_kunmap(struct radeon_bo *bo)
198 if (bo->kptr == NULL)
201 radeon_bo_check_tiling(bo, 0, 0);
202 ttm_bo_kunmap(&bo->kmap);
205 void radeon_bo_unref(struct radeon_bo **bo)
207 struct ttm_buffer_object *tbo;
208 struct radeon_device *rdev;
214 down_read(&rdev->pm.mclk_lock);
216 up_read(&rdev->pm.mclk_lock);
221 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
229 *gpu_addr = radeon_bo_gpu_offset(bo);
231 if (max_offset != 0) {
234 if (domain == RADEON_GEM_DOMAIN_VRAM)
235 domain_start = bo->rdev->mc.vram_start;
237 domain_start = bo->rdev->mc.gtt_start;
238 WARN_ON_ONCE(max_offset <
239 (radeon_bo_gpu_offset(bo) - domain_start));
244 radeon_ttm_placement_from_domain(bo, domain);
245 if (domain == RADEON_GEM_DOMAIN_VRAM) {
246 /* force to pin into visible video ram */
247 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
250 u64 lpfn = max_offset >> PAGE_SHIFT;
252 if (!bo->placement.lpfn)
253 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
255 if (lpfn < bo->placement.lpfn)
256 bo->placement.lpfn = lpfn;
258 for (i = 0; i < bo->placement.num_placement; i++)
259 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
260 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
261 if (likely(r == 0)) {
263 if (gpu_addr != NULL)
264 *gpu_addr = radeon_bo_gpu_offset(bo);
266 if (unlikely(r != 0))
267 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
271 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
273 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
276 int radeon_bo_unpin(struct radeon_bo *bo)
280 if (!bo->pin_count) {
281 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
287 for (i = 0; i < bo->placement.num_placement; i++)
288 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
289 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
290 if (unlikely(r != 0))
291 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
295 int radeon_bo_evict_vram(struct radeon_device *rdev)
297 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
298 if (0 && (rdev->flags & RADEON_IS_IGP)) {
299 if (rdev->mc.igp_sideport_enabled == false)
300 /* Useless to evict on IGP chips */
303 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
306 void radeon_bo_force_delete(struct radeon_device *rdev)
308 struct radeon_bo *bo, *n;
310 if (list_empty(&rdev->gem.objects)) {
313 dev_err(rdev->dev, "Userspace still has active objects !\n");
314 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
315 mutex_lock(&rdev->ddev->struct_mutex);
316 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
317 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
318 *((unsigned long *)&bo->gem_base.refcount));
319 mutex_lock(&bo->rdev->gem.mutex);
320 list_del_init(&bo->list);
321 mutex_unlock(&bo->rdev->gem.mutex);
322 /* this should unref the ttm bo */
323 drm_gem_object_unreference(&bo->gem_base);
324 mutex_unlock(&rdev->ddev->struct_mutex);
328 int radeon_bo_init(struct radeon_device *rdev)
330 /* Add an MTRR for the VRAM */
331 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
332 MTRR_TYPE_WRCOMB, 1);
333 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
334 rdev->mc.mc_vram_size >> 20,
335 (unsigned long long)rdev->mc.aper_size >> 20);
336 DRM_INFO("RAM width %dbits %cDR\n",
337 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
338 return radeon_ttm_init(rdev);
341 void radeon_bo_fini(struct radeon_device *rdev)
343 radeon_ttm_fini(rdev);
346 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
347 struct list_head *head)
350 list_add(&lobj->tv.head, head);
352 list_add_tail(&lobj->tv.head, head);
356 int radeon_bo_list_validate(struct list_head *head)
358 struct radeon_bo_list *lobj;
359 struct radeon_bo *bo;
362 r = ttm_eu_reserve_buffers(head);
363 if (unlikely(r != 0)) {
366 list_for_each_entry(lobj, head, tv.head) {
368 if (!bo->pin_count) {
369 r = ttm_bo_validate(&bo->tbo, &bo->placement,
375 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
376 lobj->tiling_flags = bo->tiling_flags;
381 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
382 struct vm_area_struct *vma)
384 return ttm_fbdev_mmap(vma, &bo->tbo);
387 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
389 struct radeon_device *rdev = bo->rdev;
390 struct radeon_surface_reg *reg;
391 struct radeon_bo *old_object;
395 BUG_ON(!radeon_bo_is_reserved(bo));
397 if (!bo->tiling_flags)
400 if (bo->surface_reg >= 0) {
401 reg = &rdev->surface_regs[bo->surface_reg];
407 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
409 reg = &rdev->surface_regs[i];
413 old_object = reg->bo;
414 if (old_object->pin_count == 0)
418 /* if we are all out */
419 if (i == RADEON_GEM_MAX_SURFACES) {
422 /* find someone with a surface reg and nuke their BO */
423 reg = &rdev->surface_regs[steal];
424 old_object = reg->bo;
425 /* blow away the mapping */
426 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
427 ttm_bo_unmap_virtual(&old_object->tbo);
428 old_object->surface_reg = -1;
436 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
437 bo->tbo.mem.start << PAGE_SHIFT,
438 bo->tbo.num_pages << PAGE_SHIFT);
442 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
444 struct radeon_device *rdev = bo->rdev;
445 struct radeon_surface_reg *reg;
447 if (bo->surface_reg == -1)
450 reg = &rdev->surface_regs[bo->surface_reg];
451 radeon_clear_surface_reg(rdev, bo->surface_reg);
454 bo->surface_reg = -1;
457 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
458 uint32_t tiling_flags, uint32_t pitch)
460 struct radeon_device *rdev = bo->rdev;
463 if (rdev->family >= CHIP_CEDAR) {
464 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
466 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
467 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
468 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
469 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
470 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
504 if (stilesplit > 6) {
508 r = radeon_bo_reserve(bo, false);
509 if (unlikely(r != 0))
511 bo->tiling_flags = tiling_flags;
513 radeon_bo_unreserve(bo);
517 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
518 uint32_t *tiling_flags,
521 BUG_ON(!radeon_bo_is_reserved(bo));
523 *tiling_flags = bo->tiling_flags;
528 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
531 BUG_ON(!radeon_bo_is_reserved(bo) && !force_drop);
533 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
537 radeon_bo_clear_surface_reg(bo);
541 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
545 if (bo->surface_reg >= 0)
546 radeon_bo_clear_surface_reg(bo);
550 if ((bo->surface_reg >= 0) && !has_moved)
553 return radeon_bo_get_surface_reg(bo);
556 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
557 struct ttm_mem_reg *mem)
559 struct radeon_bo *rbo;
560 if (!radeon_ttm_bo_is_radeon_bo(bo))
562 rbo = container_of(bo, struct radeon_bo, tbo);
563 radeon_bo_check_tiling(rbo, 0, 1);
564 radeon_vm_bo_invalidate(rbo->rdev, rbo);
567 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
569 struct radeon_device *rdev;
570 struct radeon_bo *rbo;
571 unsigned long offset, size;
574 if (!radeon_ttm_bo_is_radeon_bo(bo))
576 rbo = container_of(bo, struct radeon_bo, tbo);
577 radeon_bo_check_tiling(rbo, 0, 0);
579 if (bo->mem.mem_type == TTM_PL_VRAM) {
580 size = bo->mem.num_pages << PAGE_SHIFT;
581 offset = bo->mem.start << PAGE_SHIFT;
582 if ((offset + size) > rdev->mc.visible_vram_size) {
583 /* hurrah the memory is not visible ! */
584 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
585 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
586 r = ttm_bo_validate(bo, &rbo->placement, false, false);
587 if (unlikely(r != 0))
589 offset = bo->mem.start << PAGE_SHIFT;
590 /* this should not happen */
591 if ((offset + size) > rdev->mc.visible_vram_size)
598 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
602 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
603 if (unlikely(r != 0))
605 spin_lock(&bo->tbo.bdev->fence_lock);
607 *mem_type = bo->tbo.mem.mem_type;
608 if (bo->tbo.sync_obj)
609 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
610 spin_unlock(&bo->tbo.bdev->fence_lock);
611 ttm_bo_unreserve(&bo->tbo);
617 * radeon_bo_reserve - reserve bo
619 * @no_intr: don't return -ERESTARTSYS on pending signal
622 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
623 * a signal. Release all buffer reservations and return to user-space.
625 int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
629 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
630 if (unlikely(r != 0)) {
631 if (r != -ERESTARTSYS)
632 dev_err(bo->rdev->dev, "%p reserve failed\n", bo);