drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include "radeon_drm.h"
  36 #include "radeon.h"
  37 #include "radeon_trace.h"
  38
  39
  40 int radeon_ttm_init(struct radeon_device *rdev);
  41 void radeon_ttm_fini(struct radeon_device *rdev);
  42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  43
  44 /*
  45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  46  * function are calling it.
  47  */
  48
  49 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  50 {
  51         struct radeon_bo *bo;
  52
  53         bo = container_of(tbo, struct radeon_bo, tbo);
  54         mutex_lock(&bo->rdev->gem.mutex);
  55         list_del_init(&bo->list);
  56         mutex_unlock(&bo->rdev->gem.mutex);
  57         radeon_bo_clear_surface_reg(bo);
  58         kfree(bo);
  59 }
  60
  61 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  62 {
  63         if (bo->destroy == &radeon_ttm_bo_destroy)
  64                 return true;
  65         return false;
  66 }
  67
  68 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  69 {
  70         u32 c = 0;
  71
  72         rbo->placement.fpfn = 0;
  73         rbo->placement.lpfn = rbo->rdev->mc.active_vram_size >> PAGE_SHIFT;
  74         rbo->placement.placement = rbo->placements;
  75         rbo->placement.busy_placement = rbo->placements;
  76         if (domain & RADEON_GEM_DOMAIN_VRAM)
  77                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  78                                         TTM_PL_FLAG_VRAM;
  79         if (domain & RADEON_GEM_DOMAIN_GTT)
  80                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  81         if (domain & RADEON_GEM_DOMAIN_CPU)
  82                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  83         if (!c)
  84                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  85         rbo->placement.num_placement = c;
  86         rbo->placement.num_busy_placement = c;
  87 }
  88
  89 int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
  90                      unsigned long size, int byte_align, bool kernel, u32 domain,
  91                      struct radeon_bo **bo_ptr)
  92 {
  93         struct radeon_bo *bo;
  94         enum ttm_bo_type type;
  95         int page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
  96         int r;
  97
  98         if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
  99                 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
 100         }
 101         if (kernel) {
 102                 type = ttm_bo_type_kernel;
 103         } else {
 104                 type = ttm_bo_type_device;
 105         }
 106         *bo_ptr = NULL;
 107
 108 retry:
 109         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 110         if (bo == NULL)
 111                 return -ENOMEM;
 112         bo->rdev = rdev;
 113         bo->gobj = gobj;
 114         bo->surface_reg = -1;
 115         INIT_LIST_HEAD(&bo->list);
 116         radeon_ttm_placement_from_domain(bo, domain);
 117         /* Kernel allocation are uninterruptible */
 118         mutex_lock(&rdev->vram_mutex);
 119         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 120                         &bo->placement, page_align, 0, !kernel, NULL, size,
 121                         &radeon_ttm_bo_destroy);
 122         mutex_unlock(&rdev->vram_mutex);
 123         if (unlikely(r != 0)) {
 124                 if (r != -ERESTARTSYS) {
 125                         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 126                                 domain |= RADEON_GEM_DOMAIN_GTT;
 127                                 goto retry;
 128                         }
 129                         dev_err(rdev->dev,
 130                                 "object_init failed for (%lu, 0x%08X)\n",
 131                                 size, domain);
 132                 }
 133                 return r;
 134         }
 135         *bo_ptr = bo;
 136         if (gobj) {
 137                 mutex_lock(&bo->rdev->gem.mutex);
 138                 list_add_tail(&bo->list, &rdev->gem.objects);
 139                 mutex_unlock(&bo->rdev->gem.mutex);
 140         }
 141         trace_radeon_bo_create(bo);
 142         return 0;
 143 }
 144
 145 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 146 {
 147         bool is_iomem;
 148         int r;
 149
 150         if (bo->kptr) {
 151                 if (ptr) {
 152                         *ptr = bo->kptr;
 153                 }
 154                 return 0;
 155         }
 156         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 157         if (r) {
 158                 return r;
 159         }
 160         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 161         if (ptr) {
 162                 *ptr = bo->kptr;
 163         }
 164         radeon_bo_check_tiling(bo, 0, 0);
 165         return 0;
 166 }
 167
 168 void radeon_bo_kunmap(struct radeon_bo *bo)
 169 {
 170         if (bo->kptr == NULL)
 171                 return;
 172         bo->kptr = NULL;
 173         radeon_bo_check_tiling(bo, 0, 0);
 174         ttm_bo_kunmap(&bo->kmap);
 175 }
 176
 177 void radeon_bo_unref(struct radeon_bo **bo)
 178 {
 179         struct ttm_buffer_object *tbo;
 180         struct radeon_device *rdev;
 181
 182         if ((*bo) == NULL)
 183                 return;
 184         rdev = (*bo)->rdev;
 185         tbo = &((*bo)->tbo);
 186         mutex_lock(&rdev->vram_mutex);
 187         ttm_bo_unref(&tbo);
 188         mutex_unlock(&rdev->vram_mutex);
 189         if (tbo == NULL)
 190                 *bo = NULL;
 191 }
 192
 193 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 194 {
 195         int r, i;
 196
 197         if (bo->pin_count) {
 198                 bo->pin_count++;
 199                 if (gpu_addr)
 200                         *gpu_addr = radeon_bo_gpu_offset(bo);
 201                 return 0;
 202         }
 203         radeon_ttm_placement_from_domain(bo, domain);
 204         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 205                 /* force to pin into visible video ram */
 206                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 207         }
 208         for (i = 0; i < bo->placement.num_placement; i++)
 209                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
 210         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
 211         if (likely(r == 0)) {
 212                 bo->pin_count = 1;
 213                 if (gpu_addr != NULL)
 214                         *gpu_addr = radeon_bo_gpu_offset(bo);
 215         }
 216         if (unlikely(r != 0))
 217                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 218         return r;
 219 }
 220
 221 int radeon_bo_unpin(struct radeon_bo *bo)
 222 {
 223         int r, i;
 224
 225         if (!bo->pin_count) {
 226                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 227                 return 0;
 228         }
 229         bo->pin_count--;
 230         if (bo->pin_count)
 231                 return 0;
 232         for (i = 0; i < bo->placement.num_placement; i++)
 233                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
 234         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
 235         if (unlikely(r != 0))
 236                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 237         return r;
 238 }
 239
 240 int radeon_bo_evict_vram(struct radeon_device *rdev)
 241 {
 242         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 243         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 244                 if (rdev->mc.igp_sideport_enabled == false)
 245                         /* Useless to evict on IGP chips */
 246                         return 0;
 247         }
 248         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 249 }
 250
 251 void radeon_bo_force_delete(struct radeon_device *rdev)
 252 {
 253         struct radeon_bo *bo, *n;
 254         struct drm_gem_object *gobj;
 255
 256         if (list_empty(&rdev->gem.objects)) {
 257                 return;
 258         }
 259         dev_err(rdev->dev, "Userspace still has active objects !\n");
 260         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 261                 mutex_lock(&rdev->ddev->struct_mutex);
 262                 gobj = bo->gobj;
 263                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 264                         gobj, bo, (unsigned long)gobj->size,
 265                         *((unsigned long *)&gobj->refcount));
 266                 mutex_lock(&bo->rdev->gem.mutex);
 267                 list_del_init(&bo->list);
 268                 mutex_unlock(&bo->rdev->gem.mutex);
 269                 radeon_bo_unref(&bo);
 270                 gobj->driver_private = NULL;
 271                 drm_gem_object_unreference(gobj);
 272                 mutex_unlock(&rdev->ddev->struct_mutex);
 273         }
 274 }
 275
 276 int radeon_bo_init(struct radeon_device *rdev)
 277 {
 278         /* Add an MTRR for the VRAM */
 279         rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
 280                         MTRR_TYPE_WRCOMB, 1);
 281         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 282                 rdev->mc.mc_vram_size >> 20,
 283                 (unsigned long long)rdev->mc.aper_size >> 20);
 284         DRM_INFO("RAM width %dbits %cDR\n",
 285                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 286         return radeon_ttm_init(rdev);
 287 }
 288
 289 void radeon_bo_fini(struct radeon_device *rdev)
 290 {
 291         radeon_ttm_fini(rdev);
 292 }
 293
 294 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
 295                                 struct list_head *head)
 296 {
 297         if (lobj->wdomain) {
 298                 list_add(&lobj->tv.head, head);
 299         } else {
 300                 list_add_tail(&lobj->tv.head, head);
 301         }
 302 }
 303
 304 int radeon_bo_list_validate(struct list_head *head)
 305 {
 306         struct radeon_bo_list *lobj;
 307         struct radeon_bo *bo;
 308         u32 domain;
 309         int r;
 310
 311         r = ttm_eu_reserve_buffers(head);
 312         if (unlikely(r != 0)) {
 313                 return r;
 314         }
 315         list_for_each_entry(lobj, head, tv.head) {
 316                 bo = lobj->bo;
 317                 if (!bo->pin_count) {
 318                         domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
 319
 320                 retry:
 321                         radeon_ttm_placement_from_domain(bo, domain);
 322                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
 323                                                 true, false, false);
 324                         if (unlikely(r)) {
 325                                 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
 326                                         domain |= RADEON_GEM_DOMAIN_GTT;
 327                                         goto retry;
 328                                 }
 329                                 return r;
 330                         }
 331                 }
 332                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 333                 lobj->tiling_flags = bo->tiling_flags;
 334         }
 335         return 0;
 336 }
 337
 338 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 339                              struct vm_area_struct *vma)
 340 {
 341         return ttm_fbdev_mmap(vma, &bo->tbo);
 342 }
 343
 344 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 345 {
 346         struct radeon_device *rdev = bo->rdev;
 347         struct radeon_surface_reg *reg;
 348         struct radeon_bo *old_object;
 349         int steal;
 350         int i;
 351
 352         BUG_ON(!atomic_read(&bo->tbo.reserved));
 353
 354         if (!bo->tiling_flags)
 355                 return 0;
 356
 357         if (bo->surface_reg >= 0) {
 358                 reg = &rdev->surface_regs[bo->surface_reg];
 359                 i = bo->surface_reg;
 360                 goto out;
 361         }
 362
 363         steal = -1;
 364         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 365
 366                 reg = &rdev->surface_regs[i];
 367                 if (!reg->bo)
 368                         break;
 369
 370                 old_object = reg->bo;
 371                 if (old_object->pin_count == 0)
 372                         steal = i;
 373         }
 374
 375         /* if we are all out */
 376         if (i == RADEON_GEM_MAX_SURFACES) {
 377                 if (steal == -1)
 378                         return -ENOMEM;
 379                 /* find someone with a surface reg and nuke their BO */
 380                 reg = &rdev->surface_regs[steal];
 381                 old_object = reg->bo;
 382                 /* blow away the mapping */
 383                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 384                 ttm_bo_unmap_virtual(&old_object->tbo);
 385                 old_object->surface_reg = -1;
 386                 i = steal;
 387         }
 388
 389         bo->surface_reg = i;
 390         reg->bo = bo;
 391
 392 out:
 393         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 394                                bo->tbo.mem.start << PAGE_SHIFT,
 395                                bo->tbo.num_pages << PAGE_SHIFT);
 396         return 0;
 397 }
 398
 399 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 400 {
 401         struct radeon_device *rdev = bo->rdev;
 402         struct radeon_surface_reg *reg;
 403
 404         if (bo->surface_reg == -1)
 405                 return;
 406
 407         reg = &rdev->surface_regs[bo->surface_reg];
 408         radeon_clear_surface_reg(rdev, bo->surface_reg);
 409
 410         reg->bo = NULL;
 411         bo->surface_reg = -1;
 412 }
 413
 414 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 415                                 uint32_t tiling_flags, uint32_t pitch)
 416 {
 417         int r;
 418
 419         r = radeon_bo_reserve(bo, false);
 420         if (unlikely(r != 0))
 421                 return r;
 422         bo->tiling_flags = tiling_flags;
 423         bo->pitch = pitch;
 424         radeon_bo_unreserve(bo);
 425         return 0;
 426 }
 427
 428 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 429                                 uint32_t *tiling_flags,
 430                                 uint32_t *pitch)
 431 {
 432         BUG_ON(!atomic_read(&bo->tbo.reserved));
 433         if (tiling_flags)
 434                 *tiling_flags = bo->tiling_flags;
 435         if (pitch)
 436                 *pitch = bo->pitch;
 437 }
 438
 439 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 440                                 bool force_drop)
 441 {
 442         BUG_ON(!atomic_read(&bo->tbo.reserved));
 443
 444         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 445                 return 0;
 446
 447         if (force_drop) {
 448                 radeon_bo_clear_surface_reg(bo);
 449                 return 0;
 450         }
 451
 452         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 453                 if (!has_moved)
 454                         return 0;
 455
 456                 if (bo->surface_reg >= 0)
 457                         radeon_bo_clear_surface_reg(bo);
 458                 return 0;
 459         }
 460
 461         if ((bo->surface_reg >= 0) && !has_moved)
 462                 return 0;
 463
 464         return radeon_bo_get_surface_reg(bo);
 465 }
 466
 467 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 468                            struct ttm_mem_reg *mem)
 469 {
 470         struct radeon_bo *rbo;
 471         if (!radeon_ttm_bo_is_radeon_bo(bo))
 472                 return;
 473         rbo = container_of(bo, struct radeon_bo, tbo);
 474         radeon_bo_check_tiling(rbo, 0, 1);
 475 }
 476
 477 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 478 {
 479         struct radeon_device *rdev;
 480         struct radeon_bo *rbo;
 481         unsigned long offset, size;
 482         int r;
 483
 484         if (!radeon_ttm_bo_is_radeon_bo(bo))
 485                 return 0;
 486         rbo = container_of(bo, struct radeon_bo, tbo);
 487         radeon_bo_check_tiling(rbo, 0, 0);
 488         rdev = rbo->rdev;
 489         if (bo->mem.mem_type == TTM_PL_VRAM) {
 490                 size = bo->mem.num_pages << PAGE_SHIFT;
 491                 offset = bo->mem.start << PAGE_SHIFT;
 492                 if ((offset + size) > rdev->mc.visible_vram_size) {
 493                         /* hurrah the memory is not visible ! */
 494                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 495                         rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
 496                         r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
 497                         if (unlikely(r != 0))
 498                                 return r;
 499                         offset = bo->mem.start << PAGE_SHIFT;
 500                         /* this should not happen */
 501                         if ((offset + size) > rdev->mc.visible_vram_size)
 502                                 return -EINVAL;
 503                 }
 504         }
 505         return 0;
 506 }