drivers/gpu/drm/radeon/radeon_legacy_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
  33 {
  34         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  35         struct drm_encoder_helper_funcs *encoder_funcs;
  36
  37         encoder_funcs = encoder->helper_private;
  38         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  39         radeon_encoder->active_device = 0;
  40 }
  41
  42 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
  43 {
  44         struct drm_device *dev = encoder->dev;
  45         struct radeon_device *rdev = dev->dev_private;
  46         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  47         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
  48         int panel_pwr_delay = 2000;
  49         DRM_DEBUG("\n");
  50
  51         if (radeon_encoder->enc_priv) {
  52                 if (rdev->is_atom_bios) {
  53                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  54                         panel_pwr_delay = lvds->panel_pwr_delay;
  55                 } else {
  56                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  57                         panel_pwr_delay = lvds->panel_pwr_delay;
  58                 }
  59         }
  60
  61         switch (mode) {
  62         case DRM_MODE_DPMS_ON:
  63                 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
  64                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
  65                 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
  66                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  67                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
  68                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  69                 udelay(1000);
  70
  71                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  72                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
  73                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  74
  75                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  76                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
  77                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
  78                 udelay(panel_pwr_delay * 1000);
  79                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  80                 break;
  81         case DRM_MODE_DPMS_STANDBY:
  82         case DRM_MODE_DPMS_SUSPEND:
  83         case DRM_MODE_DPMS_OFF:
  84                 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  85                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
  86                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  87                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
  88                 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
  89                 udelay(panel_pwr_delay * 1000);
  90                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  91                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
  92                 break;
  93         }
  94
  95         if (rdev->is_atom_bios)
  96                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  97         else
  98                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  99 }
 100
 101 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 102 {
 103         struct radeon_device *rdev = encoder->dev->dev_private;
 104
 105         if (rdev->is_atom_bios)
 106                 radeon_atom_output_lock(encoder, true);
 107         else
 108                 radeon_combios_output_lock(encoder, true);
 109         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
 110 }
 111
 112 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
 113 {
 114         struct radeon_device *rdev = encoder->dev->dev_private;
 115
 116         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
 117         if (rdev->is_atom_bios)
 118                 radeon_atom_output_lock(encoder, false);
 119         else
 120                 radeon_combios_output_lock(encoder, false);
 121 }
 122
 123 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 124                                         struct drm_display_mode *mode,
 125                                         struct drm_display_mode *adjusted_mode)
 126 {
 127         struct drm_device *dev = encoder->dev;
 128         struct radeon_device *rdev = dev->dev_private;
 129         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 130         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 131         uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
 132
 133         DRM_DEBUG("\n");
 134
 135         lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
 136         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 137
 138         lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 139         if (rdev->is_atom_bios) {
 140                 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
 141                  * need to call that on resume to set up the reg properly.
 142                  */
 143                 radeon_encoder->pixel_clock = adjusted_mode->clock;
 144                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
 145                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 146         } else {
 147                 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 148                 if (lvds) {
 149                         DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
 150                         lvds_gen_cntl = lvds->lvds_gen_cntl;
 151                         lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 152                                               (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 153                         lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 154                                              (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 155                 } else
 156                         lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 157         }
 158         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 159         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
 160                            RADEON_LVDS_BLON |
 161                            RADEON_LVDS_EN |
 162                            RADEON_LVDS_RST_FM);
 163
 164         if (ASIC_IS_R300(rdev))
 165                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
 166
 167         if (radeon_crtc->crtc_id == 0) {
 168                 if (ASIC_IS_R300(rdev)) {
 169                         if (radeon_encoder->rmx_type != RMX_OFF)
 170                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
 171                 } else
 172                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
 173         } else {
 174                 if (ASIC_IS_R300(rdev))
 175                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
 176                 else
 177                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
 178         }
 179
 180         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 181         WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 182         WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
 183
 184         if (rdev->family == CHIP_RV410)
 185                 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
 186
 187         if (rdev->is_atom_bios)
 188                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 189         else
 190                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 191 }
 192
 193 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
 194                                      struct drm_display_mode *mode,
 195                                      struct drm_display_mode *adjusted_mode)
 196 {
 197         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 198
 199         /* set the active encoder to connector routing */
 200         radeon_encoder_set_active_device(encoder);
 201         drm_mode_set_crtcinfo(adjusted_mode, 0);
 202
 203         /* get the native mode for LVDS */
 204         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 205                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 206                 int mode_id = adjusted_mode->base.id;
 207                 *adjusted_mode = *native_mode;
 208                 adjusted_mode->hdisplay = mode->hdisplay;
 209                 adjusted_mode->vdisplay = mode->vdisplay;
 210                 adjusted_mode->crtc_hdisplay = mode->hdisplay;
 211                 adjusted_mode->crtc_vdisplay = mode->vdisplay;
 212                 adjusted_mode->base.id = mode_id;
 213         }
 214
 215         return true;
 216 }
 217
 218 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 219         .dpms = radeon_legacy_lvds_dpms,
 220         .mode_fixup = radeon_legacy_mode_fixup,
 221         .prepare = radeon_legacy_lvds_prepare,
 222         .mode_set = radeon_legacy_lvds_mode_set,
 223         .commit = radeon_legacy_lvds_commit,
 224         .disable = radeon_legacy_encoder_disable,
 225 };
 226
 227
 228 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
 229         .destroy = radeon_enc_destroy,
 230 };
 231
 232 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
 233 {
 234         struct drm_device *dev = encoder->dev;
 235         struct radeon_device *rdev = dev->dev_private;
 236         uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 237         uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
 238         uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 239
 240         DRM_DEBUG("\n");
 241
 242         switch (mode) {
 243         case DRM_MODE_DPMS_ON:
 244                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
 245                 dac_cntl &= ~RADEON_DAC_PDWN;
 246                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
 247                                     RADEON_DAC_PDWN_G |
 248                                     RADEON_DAC_PDWN_B);
 249                 break;
 250         case DRM_MODE_DPMS_STANDBY:
 251         case DRM_MODE_DPMS_SUSPEND:
 252         case DRM_MODE_DPMS_OFF:
 253                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
 254                 dac_cntl |= RADEON_DAC_PDWN;
 255                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
 256                                    RADEON_DAC_PDWN_G |
 257                                    RADEON_DAC_PDWN_B);
 258                 break;
 259         }
 260
 261         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 262         WREG32(RADEON_DAC_CNTL, dac_cntl);
 263         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 264
 265         if (rdev->is_atom_bios)
 266                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 267         else
 268                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 269 }
 270
 271 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 272 {
 273         struct radeon_device *rdev = encoder->dev->dev_private;
 274
 275         if (rdev->is_atom_bios)
 276                 radeon_atom_output_lock(encoder, true);
 277         else
 278                 radeon_combios_output_lock(encoder, true);
 279         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 280 }
 281
 282 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
 283 {
 284         struct radeon_device *rdev = encoder->dev->dev_private;
 285
 286         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 287
 288         if (rdev->is_atom_bios)
 289                 radeon_atom_output_lock(encoder, false);
 290         else
 291                 radeon_combios_output_lock(encoder, false);
 292 }
 293
 294 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
 295                                                struct drm_display_mode *mode,
 296                                                struct drm_display_mode *adjusted_mode)
 297 {
 298         struct drm_device *dev = encoder->dev;
 299         struct radeon_device *rdev = dev->dev_private;
 300         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 301         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 302         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
 303
 304         DRM_DEBUG("\n");
 305
 306         if (radeon_crtc->crtc_id == 0) {
 307                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 308                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 309                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 310                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 311                 } else {
 312                         dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
 313                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 314                 }
 315         } else {
 316                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 317                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 318                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 319                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
 320                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 321                 } else {
 322                         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
 323                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 324                 }
 325         }
 326
 327         dac_cntl = (RADEON_DAC_MASK_ALL |
 328                     RADEON_DAC_VGA_ADR_EN |
 329                     /* TODO 6-bits */
 330                     RADEON_DAC_8BIT_EN);
 331
 332         WREG32_P(RADEON_DAC_CNTL,
 333                        dac_cntl,
 334                        RADEON_DAC_RANGE_CNTL |
 335                        RADEON_DAC_BLANKING);
 336
 337         if (radeon_encoder->enc_priv) {
 338                 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
 339                 dac_macro_cntl = p_dac->ps2_pdac_adj;
 340         } else
 341                 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 342         dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
 343         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 344
 345         if (rdev->is_atom_bios)
 346                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 347         else
 348                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 349 }
 350
 351 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
 352                                                                   struct drm_connector *connector)
 353 {
 354         struct drm_device *dev = encoder->dev;
 355         struct radeon_device *rdev = dev->dev_private;
 356         uint32_t vclk_ecp_cntl, crtc_ext_cntl;
 357         uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
 358         enum drm_connector_status found = connector_status_disconnected;
 359         bool color = true;
 360
 361         /* save the regs we need */
 362         vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
 363         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 364         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
 365         dac_cntl = RREG32(RADEON_DAC_CNTL);
 366         dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 367
 368         tmp = vclk_ecp_cntl &
 369                 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
 370         WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
 371
 372         tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
 373         WREG32(RADEON_CRTC_EXT_CNTL, tmp);
 374
 375         tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
 376                 RADEON_DAC_FORCE_DATA_EN;
 377
 378         if (color)
 379                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
 380         else
 381                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
 382
 383         if (ASIC_IS_R300(rdev))
 384                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
 385         else
 386                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
 387
 388         WREG32(RADEON_DAC_EXT_CNTL, tmp);
 389
 390         tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
 391         tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
 392         WREG32(RADEON_DAC_CNTL, tmp);
 393
 394         tmp &= ~(RADEON_DAC_PDWN_R |
 395                  RADEON_DAC_PDWN_G |
 396                  RADEON_DAC_PDWN_B);
 397
 398         WREG32(RADEON_DAC_MACRO_CNTL, tmp);
 399
 400         udelay(2000);
 401
 402         if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
 403                 found = connector_status_connected;
 404
 405         /* restore the regs we used */
 406         WREG32(RADEON_DAC_CNTL, dac_cntl);
 407         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 408         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
 409         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 410         WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
 411
 412         return found;
 413 }
 414
 415 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
 416         .dpms = radeon_legacy_primary_dac_dpms,
 417         .mode_fixup = radeon_legacy_mode_fixup,
 418         .prepare = radeon_legacy_primary_dac_prepare,
 419         .mode_set = radeon_legacy_primary_dac_mode_set,
 420         .commit = radeon_legacy_primary_dac_commit,
 421         .detect = radeon_legacy_primary_dac_detect,
 422         .disable = radeon_legacy_encoder_disable,
 423 };
 424
 425
 426 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
 427         .destroy = radeon_enc_destroy,
 428 };
 429
 430 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
 431 {
 432         struct drm_device *dev = encoder->dev;
 433         struct radeon_device *rdev = dev->dev_private;
 434         uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
 435         DRM_DEBUG("\n");
 436
 437         switch (mode) {
 438         case DRM_MODE_DPMS_ON:
 439                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 440                 break;
 441         case DRM_MODE_DPMS_STANDBY:
 442         case DRM_MODE_DPMS_SUSPEND:
 443         case DRM_MODE_DPMS_OFF:
 444                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 445                 break;
 446         }
 447
 448         WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 449
 450         if (rdev->is_atom_bios)
 451                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 452         else
 453                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 454 }
 455
 456 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 457 {
 458         struct radeon_device *rdev = encoder->dev->dev_private;
 459
 460         if (rdev->is_atom_bios)
 461                 radeon_atom_output_lock(encoder, true);
 462         else
 463                 radeon_combios_output_lock(encoder, true);
 464         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
 465 }
 466
 467 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
 468 {
 469         struct radeon_device *rdev = encoder->dev->dev_private;
 470
 471         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
 472
 473         if (rdev->is_atom_bios)
 474                 radeon_atom_output_lock(encoder, true);
 475         else
 476                 radeon_combios_output_lock(encoder, true);
 477 }
 478
 479 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
 480                                             struct drm_display_mode *mode,
 481                                             struct drm_display_mode *adjusted_mode)
 482 {
 483         struct drm_device *dev = encoder->dev;
 484         struct radeon_device *rdev = dev->dev_private;
 485         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 486         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 487         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
 488         int i;
 489
 490         DRM_DEBUG("\n");
 491
 492         tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
 493         tmp &= 0xfffff;
 494         if (rdev->family == CHIP_RV280) {
 495                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 496                 tmp ^= (1 << 22);
 497                 tmds_pll_cntl ^= (1 << 22);
 498         }
 499
 500         if (radeon_encoder->enc_priv) {
 501                 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
 502
 503                 for (i = 0; i < 4; i++) {
 504                         if (tmds->tmds_pll[i].freq == 0)
 505                                 break;
 506                         if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
 507                                 tmp = tmds->tmds_pll[i].value ;
 508                                 break;
 509                         }
 510                 }
 511         }
 512
 513         if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
 514                 if (tmp & 0xfff00000)
 515                         tmds_pll_cntl = tmp;
 516                 else {
 517                         tmds_pll_cntl &= 0xfff00000;
 518                         tmds_pll_cntl |= tmp;
 519                 }
 520         } else
 521                 tmds_pll_cntl = tmp;
 522
 523         tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
 524                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
 525
 526     if (rdev->family == CHIP_R200 ||
 527         rdev->family == CHIP_R100 ||
 528         ASIC_IS_R300(rdev))
 529             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
 530     else /* RV chips got this bit reversed */
 531             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
 532
 533     fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
 534                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
 535                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
 536
 537     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 538
 539     fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
 540                      RADEON_FP_DFP_SYNC_SEL |
 541                      RADEON_FP_CRT_SYNC_SEL |
 542                      RADEON_FP_CRTC_LOCK_8DOT |
 543                      RADEON_FP_USE_SHADOW_EN |
 544                      RADEON_FP_CRTC_USE_SHADOW_VEND |
 545                      RADEON_FP_CRT_SYNC_ALT);
 546
 547     if (1) /*  FIXME rgbBits == 8 */
 548             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
 549     else
 550             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
 551
 552     if (radeon_crtc->crtc_id == 0) {
 553             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 554                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 555                     if (radeon_encoder->rmx_type != RMX_OFF)
 556                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 557                     else
 558                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 559             } else
 560                     fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
 561     } else {
 562             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 563                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 564                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
 565             } else
 566                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
 567     }
 568
 569     WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
 570     WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
 571     WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 572
 573         if (rdev->is_atom_bios)
 574                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 575         else
 576                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 577 }
 578
 579 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
 580         .dpms = radeon_legacy_tmds_int_dpms,
 581         .mode_fixup = radeon_legacy_mode_fixup,
 582         .prepare = radeon_legacy_tmds_int_prepare,
 583         .mode_set = radeon_legacy_tmds_int_mode_set,
 584         .commit = radeon_legacy_tmds_int_commit,
 585         .disable = radeon_legacy_encoder_disable,
 586 };
 587
 588
 589 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
 590         .destroy = radeon_enc_destroy,
 591 };
 592
 593 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
 594 {
 595         struct drm_device *dev = encoder->dev;
 596         struct radeon_device *rdev = dev->dev_private;
 597         uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 598         DRM_DEBUG("\n");
 599
 600         switch (mode) {
 601         case DRM_MODE_DPMS_ON:
 602                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
 603                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 604                 break;
 605         case DRM_MODE_DPMS_STANDBY:
 606         case DRM_MODE_DPMS_SUSPEND:
 607         case DRM_MODE_DPMS_OFF:
 608                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
 609                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 610                 break;
 611         }
 612
 613         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 614
 615         if (rdev->is_atom_bios)
 616                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 617         else
 618                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 619 }
 620
 621 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 622 {
 623         struct radeon_device *rdev = encoder->dev->dev_private;
 624
 625         if (rdev->is_atom_bios)
 626                 radeon_atom_output_lock(encoder, true);
 627         else
 628                 radeon_combios_output_lock(encoder, true);
 629         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
 630 }
 631
 632 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
 633 {
 634         struct radeon_device *rdev = encoder->dev->dev_private;
 635         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
 636
 637         if (rdev->is_atom_bios)
 638                 radeon_atom_output_lock(encoder, false);
 639         else
 640                 radeon_combios_output_lock(encoder, false);
 641 }
 642
 643 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
 644                                             struct drm_display_mode *mode,
 645                                             struct drm_display_mode *adjusted_mode)
 646 {
 647         struct drm_device *dev = encoder->dev;
 648         struct radeon_device *rdev = dev->dev_private;
 649         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 650         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 651         uint32_t fp2_gen_cntl;
 652
 653         DRM_DEBUG("\n");
 654
 655         if (rdev->is_atom_bios) {
 656                 radeon_encoder->pixel_clock = adjusted_mode->clock;
 657                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
 658                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 659         } else {
 660                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 661
 662                 if (1) /*  FIXME rgbBits == 8 */
 663                         fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
 664                 else
 665                         fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
 666
 667                 fp2_gen_cntl &= ~(RADEON_FP2_ON |
 668                                   RADEON_FP2_DVO_EN |
 669                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 670
 671                 /* XXX: these are oem specific */
 672                 if (ASIC_IS_R300(rdev)) {
 673                         if ((dev->pdev->device == 0x4850) &&
 674                             (dev->pdev->subsystem_vendor == 0x1028) &&
 675                             (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
 676                                 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
 677                         else
 678                                 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
 679
 680                         /*if (mode->clock > 165000)
 681                           fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
 682                 }
 683                 if (!radeon_combios_external_tmds_setup(encoder))
 684                         radeon_external_tmds_setup(encoder);
 685         }
 686
 687         if (radeon_crtc->crtc_id == 0) {
 688                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 689                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 690                         if (radeon_encoder->rmx_type != RMX_OFF)
 691                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
 692                         else
 693                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 694                 } else
 695                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 696         } else {
 697                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 698                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 699                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 700                 } else
 701                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
 702         }
 703
 704         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 705
 706         if (rdev->is_atom_bios)
 707                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 708         else
 709                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 710 }
 711
 712 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
 713 {
 714         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 715         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
 716         if (tmds) {
 717                 if (tmds->i2c_bus)
 718                         radeon_i2c_destroy(tmds->i2c_bus);
 719         }
 720         kfree(radeon_encoder->enc_priv);
 721         drm_encoder_cleanup(encoder);
 722         kfree(radeon_encoder);
 723 }
 724
 725 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
 726         .dpms = radeon_legacy_tmds_ext_dpms,
 727         .mode_fixup = radeon_legacy_mode_fixup,
 728         .prepare = radeon_legacy_tmds_ext_prepare,
 729         .mode_set = radeon_legacy_tmds_ext_mode_set,
 730         .commit = radeon_legacy_tmds_ext_commit,
 731         .disable = radeon_legacy_encoder_disable,
 732 };
 733
 734
 735 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
 736         .destroy = radeon_ext_tmds_enc_destroy,
 737 };
 738
 739 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 740 {
 741         struct drm_device *dev = encoder->dev;
 742         struct radeon_device *rdev = dev->dev_private;
 743         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 744         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
 745         uint32_t tv_master_cntl = 0;
 746         bool is_tv;
 747         DRM_DEBUG("\n");
 748
 749         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
 750
 751         if (rdev->family == CHIP_R200)
 752                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 753         else {
 754                 if (is_tv)
 755                         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
 756                 else
 757                         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 758                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 759         }
 760
 761         switch (mode) {
 762         case DRM_MODE_DPMS_ON:
 763                 if (rdev->family == CHIP_R200) {
 764                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 765                 } else {
 766                         if (is_tv)
 767                                 tv_master_cntl |= RADEON_TV_ON;
 768                         else
 769                                 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
 770
 771                         if (rdev->family == CHIP_R420 ||
 772                             rdev->family == CHIP_R423 ||
 773                             rdev->family == CHIP_RV410)
 774                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
 775                                                  R420_TV_DAC_GDACPD |
 776                                                  R420_TV_DAC_BDACPD |
 777                                                  RADEON_TV_DAC_BGSLEEP);
 778                         else
 779                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
 780                                                  RADEON_TV_DAC_GDACPD |
 781                                                  RADEON_TV_DAC_BDACPD |
 782                                                  RADEON_TV_DAC_BGSLEEP);
 783                 }
 784                 break;
 785         case DRM_MODE_DPMS_STANDBY:
 786         case DRM_MODE_DPMS_SUSPEND:
 787         case DRM_MODE_DPMS_OFF:
 788                 if (rdev->family == CHIP_R200)
 789                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 790                 else {
 791                         if (is_tv)
 792                                 tv_master_cntl &= ~RADEON_TV_ON;
 793                         else
 794                                 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
 795
 796                         if (rdev->family == CHIP_R420 ||
 797                                         rdev->family == CHIP_R423 ||
 798                                         rdev->family == CHIP_RV410)
 799                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
 800                                                 R420_TV_DAC_GDACPD |
 801                                                 R420_TV_DAC_BDACPD |
 802                                                 RADEON_TV_DAC_BGSLEEP);
 803                         else
 804                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
 805                                                 RADEON_TV_DAC_GDACPD |
 806                                                 RADEON_TV_DAC_BDACPD |
 807                                                 RADEON_TV_DAC_BGSLEEP);
 808                 }
 809                 break;
 810         }
 811
 812         if (rdev->family == CHIP_R200) {
 813                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 814         } else {
 815                 if (is_tv)
 816                         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
 817                 else
 818                         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 819                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 820         }
 821
 822         if (rdev->is_atom_bios)
 823                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 824         else
 825                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 826 }
 827
 828 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
 829 {
 830         struct radeon_device *rdev = encoder->dev->dev_private;
 831
 832         if (rdev->is_atom_bios)
 833                 radeon_atom_output_lock(encoder, true);
 834         else
 835                 radeon_combios_output_lock(encoder, true);
 836         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 837 }
 838
 839 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
 840 {
 841         struct radeon_device *rdev = encoder->dev->dev_private;
 842
 843         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 844
 845         if (rdev->is_atom_bios)
 846                 radeon_atom_output_lock(encoder, true);
 847         else
 848                 radeon_combios_output_lock(encoder, true);
 849 }
 850
 851 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
 852                 struct drm_display_mode *mode,
 853                 struct drm_display_mode *adjusted_mode)
 854 {
 855         struct drm_device *dev = encoder->dev;
 856         struct radeon_device *rdev = dev->dev_private;
 857         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 858         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 859         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
 860         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
 861         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
 862         bool is_tv = false;
 863
 864         DRM_DEBUG("\n");
 865
 866         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
 867
 868         if (rdev->family != CHIP_R200) {
 869                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 870                 if (rdev->family == CHIP_R420 ||
 871                                 rdev->family == CHIP_R423 ||
 872                                 rdev->family == CHIP_RV410) {
 873                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 874                                         RADEON_TV_DAC_BGADJ_MASK |
 875                                         R420_TV_DAC_DACADJ_MASK |
 876                                         R420_TV_DAC_RDACPD |
 877                                         R420_TV_DAC_GDACPD |
 878                                         R420_TV_DAC_BDACPD |
 879                                         R420_TV_DAC_TVENABLE);
 880                 } else {
 881                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 882                                         RADEON_TV_DAC_BGADJ_MASK |
 883                                         RADEON_TV_DAC_DACADJ_MASK |
 884                                         RADEON_TV_DAC_RDACPD |
 885                                         RADEON_TV_DAC_GDACPD |
 886                                         RADEON_TV_DAC_BDACPD);
 887                 }
 888
 889                 /*  FIXME TV */
 890                 if (tv_dac) {
 891                         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
 892                         tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
 893                                         RADEON_TV_DAC_NHOLD |
 894                                         RADEON_TV_DAC_STD_PS2 |
 895                                         tv_dac->ps2_tvdac_adj);
 896                 } else
 897                         tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
 898                                         RADEON_TV_DAC_NHOLD |
 899                                         RADEON_TV_DAC_STD_PS2);
 900
 901                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 902         }
 903
 904         if (ASIC_IS_R300(rdev)) {
 905                 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
 906                 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
 907         }
 908
 909         if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev))
 910                 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
 911         else
 912                 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
 913
 914         if (rdev->family == CHIP_R200)
 915                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 916
 917         if (is_tv) {
 918                 uint32_t dac_cntl;
 919
 920                 dac_cntl = RREG32(RADEON_DAC_CNTL);
 921                 dac_cntl &= ~RADEON_DAC_TVO_EN;
 922                 WREG32(RADEON_DAC_CNTL, dac_cntl);
 923
 924                 if (ASIC_IS_R300(rdev))
 925                         gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
 926
 927                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
 928                 if (radeon_crtc->crtc_id == 0) {
 929                         if (ASIC_IS_R300(rdev)) {
 930                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 931                                 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
 932                                                      RADEON_DISP_TV_SOURCE_CRTC);
 933                         }
 934                         if (rdev->family >= CHIP_R200) {
 935                                 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
 936                         } else {
 937                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 938                         }
 939                 } else {
 940                         if (ASIC_IS_R300(rdev)) {
 941                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 942                                 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
 943                         }
 944                         if (rdev->family >= CHIP_R200) {
 945                                 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
 946                         } else {
 947                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
 948                         }
 949                 }
 950                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 951         } else {
 952
 953                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
 954
 955                 if (radeon_crtc->crtc_id == 0) {
 956                         if (ASIC_IS_R300(rdev)) {
 957                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 958                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
 959                         } else if (rdev->family == CHIP_R200) {
 960                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 961                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 962                         } else
 963                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 964                 } else {
 965                         if (ASIC_IS_R300(rdev)) {
 966                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 967                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
 968                         } else if (rdev->family == CHIP_R200) {
 969                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 970                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 971                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 972                         } else
 973                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
 974                 }
 975                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 976         }
 977
 978         if (ASIC_IS_R300(rdev)) {
 979                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
 980                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 981         }
 982
 983         if (rdev->family >= CHIP_R200)
 984                 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
 985         else
 986                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 987
 988         if (rdev->family == CHIP_R200)
 989                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 990
 991         if (is_tv)
 992                 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
 993
 994         if (rdev->is_atom_bios)
 995                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 996         else
 997                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 998
 999 }
1000
1001 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1002                                   struct drm_connector *connector)
1003 {
1004         struct drm_device *dev = encoder->dev;
1005         struct radeon_device *rdev = dev->dev_private;
1006         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1007         uint32_t disp_output_cntl, gpiopad_a, tmp;
1008         bool found = false;
1009
1010         /* save regs needed */
1011         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1012         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1013         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1014         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1015         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1016         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1017
1018         WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1019
1020         WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1021
1022         WREG32(RADEON_CRTC2_GEN_CNTL,
1023                RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1024
1025         tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1026         tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1027         WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1028
1029         WREG32(RADEON_DAC_EXT_CNTL,
1030                RADEON_DAC2_FORCE_BLANK_OFF_EN |
1031                RADEON_DAC2_FORCE_DATA_EN |
1032                RADEON_DAC_FORCE_DATA_SEL_RGB |
1033                (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1034
1035         WREG32(RADEON_TV_DAC_CNTL,
1036                RADEON_TV_DAC_STD_NTSC |
1037                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1038                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1039
1040         RREG32(RADEON_TV_DAC_CNTL);
1041         mdelay(4);
1042
1043         WREG32(RADEON_TV_DAC_CNTL,
1044                RADEON_TV_DAC_NBLANK |
1045                RADEON_TV_DAC_NHOLD |
1046                RADEON_TV_MONITOR_DETECT_EN |
1047                RADEON_TV_DAC_STD_NTSC |
1048                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1049                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1050
1051         RREG32(RADEON_TV_DAC_CNTL);
1052         mdelay(6);
1053
1054         tmp = RREG32(RADEON_TV_DAC_CNTL);
1055         if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1056                 found = true;
1057                 DRM_DEBUG("S-video TV connection detected\n");
1058         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1059                 found = true;
1060                 DRM_DEBUG("Composite TV connection detected\n");
1061         }
1062
1063         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1064         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1065         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1066         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1067         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1068         WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1069         return found;
1070 }
1071
1072 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1073                                     struct drm_connector *connector)
1074 {
1075         struct drm_device *dev = encoder->dev;
1076         struct radeon_device *rdev = dev->dev_private;
1077         uint32_t tv_dac_cntl, dac_cntl2;
1078         uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1079         bool found = false;
1080
1081         if (ASIC_IS_R300(rdev))
1082                 return r300_legacy_tv_detect(encoder, connector);
1083
1084         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1085         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1086         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1087         config_cntl = RREG32(RADEON_CONFIG_CNTL);
1088         tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1089
1090         tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1091         WREG32(RADEON_DAC_CNTL2, tmp);
1092
1093         tmp = tv_master_cntl | RADEON_TV_ON;
1094         tmp &= ~(RADEON_TV_ASYNC_RST |
1095                  RADEON_RESTART_PHASE_FIX |
1096                  RADEON_CRT_FIFO_CE_EN |
1097                  RADEON_TV_FIFO_CE_EN |
1098                  RADEON_RE_SYNC_NOW_SEL_MASK);
1099         tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1100         WREG32(RADEON_TV_MASTER_CNTL, tmp);
1101
1102         tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1103                 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1104                 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1105
1106         if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1107                 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1108         else
1109                 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1110         WREG32(RADEON_TV_DAC_CNTL, tmp);
1111
1112         tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1113                 RADEON_RED_MX_FORCE_DAC_DATA |
1114                 RADEON_GRN_MX_FORCE_DAC_DATA |
1115                 RADEON_BLU_MX_FORCE_DAC_DATA |
1116                 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1117         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1118
1119         mdelay(3);
1120         tmp = RREG32(RADEON_TV_DAC_CNTL);
1121         if (tmp & RADEON_TV_DAC_GDACDET) {
1122                 found = true;
1123                 DRM_DEBUG("S-video TV connection detected\n");
1124         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1125                 found = true;
1126                 DRM_DEBUG("Composite TV connection detected\n");
1127         }
1128
1129         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1130         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1131         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1132         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1133         return found;
1134 }
1135
1136 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1137                                                              struct drm_connector *connector)
1138 {
1139         struct drm_device *dev = encoder->dev;
1140         struct radeon_device *rdev = dev->dev_private;
1141         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1142         uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1143         enum drm_connector_status found = connector_status_disconnected;
1144         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1145         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1146         bool color = true;
1147
1148         if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1149             connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1150             connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1151                 bool tv_detect;
1152
1153                 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1154                         return connector_status_disconnected;
1155
1156                 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1157                 if (tv_detect && tv_dac)
1158                         found = connector_status_connected;
1159                 return found;
1160         }
1161
1162         /* don't probe if the encoder is being used for something else not CRT related */
1163         if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1164                 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1165                 return connector_status_disconnected;
1166         }
1167
1168         /* save the regs we need */
1169         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1170         gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1171         disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1172         disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1173         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1174         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1175         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1176         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1177
1178         tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1179                                | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1180         WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1181
1182         if (ASIC_IS_R300(rdev))
1183                 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1184
1185         tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1186         tmp |= RADEON_CRTC2_CRT2_ON |
1187                 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1188
1189         WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1190
1191         if (ASIC_IS_R300(rdev)) {
1192                 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1193                 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1194                 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1195         } else {
1196                 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1197                 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1198         }
1199
1200         tmp = RADEON_TV_DAC_NBLANK |
1201                 RADEON_TV_DAC_NHOLD |
1202                 RADEON_TV_MONITOR_DETECT_EN |
1203                 RADEON_TV_DAC_STD_PS2;
1204
1205         WREG32(RADEON_TV_DAC_CNTL, tmp);
1206
1207         tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1208                 RADEON_DAC2_FORCE_DATA_EN;
1209
1210         if (color)
1211                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1212         else
1213                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1214
1215         if (ASIC_IS_R300(rdev))
1216                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1217         else
1218                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1219
1220         WREG32(RADEON_DAC_EXT_CNTL, tmp);
1221
1222         tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1223         WREG32(RADEON_DAC_CNTL2, tmp);
1224
1225         udelay(10000);
1226
1227         if (ASIC_IS_R300(rdev)) {
1228                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1229                         found = connector_status_connected;
1230         } else {
1231                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1232                         found = connector_status_connected;
1233         }
1234
1235         /* restore regs we used */
1236         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1237         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1238         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1239         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1240
1241         if (ASIC_IS_R300(rdev)) {
1242                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1243                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1244         } else {
1245                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1246         }
1247         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1248
1249         return found;
1250
1251 }
1252
1253 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1254         .dpms = radeon_legacy_tv_dac_dpms,
1255         .mode_fixup = radeon_legacy_mode_fixup,
1256         .prepare = radeon_legacy_tv_dac_prepare,
1257         .mode_set = radeon_legacy_tv_dac_mode_set,
1258         .commit = radeon_legacy_tv_dac_commit,
1259         .detect = radeon_legacy_tv_dac_detect,
1260         .disable = radeon_legacy_encoder_disable,
1261 };
1262
1263
1264 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1265         .destroy = radeon_enc_destroy,
1266 };
1267
1268
1269 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1270 {
1271         struct drm_device *dev = encoder->base.dev;
1272         struct radeon_device *rdev = dev->dev_private;
1273         struct radeon_encoder_int_tmds *tmds = NULL;
1274         bool ret;
1275
1276         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1277
1278         if (!tmds)
1279                 return NULL;
1280
1281         if (rdev->is_atom_bios)
1282                 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1283         else
1284                 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1285
1286         if (ret == false)
1287                 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1288
1289         return tmds;
1290 }
1291
1292 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1293 {
1294         struct drm_device *dev = encoder->base.dev;
1295         struct radeon_device *rdev = dev->dev_private;
1296         struct radeon_encoder_ext_tmds *tmds = NULL;
1297         bool ret;
1298
1299         if (rdev->is_atom_bios)
1300                 return NULL;
1301
1302         tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1303
1304         if (!tmds)
1305                 return NULL;
1306
1307         ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1308
1309         if (ret == false)
1310                 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1311
1312         return tmds;
1313 }
1314
1315 void
1316 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1317 {
1318         struct radeon_device *rdev = dev->dev_private;
1319         struct drm_encoder *encoder;
1320         struct radeon_encoder *radeon_encoder;
1321
1322         /* see if we already added it */
1323         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1324                 radeon_encoder = to_radeon_encoder(encoder);
1325                 if (radeon_encoder->encoder_id == encoder_id) {
1326                         radeon_encoder->devices |= supported_device;
1327                         return;
1328                 }
1329
1330         }
1331
1332         /* add a new one */
1333         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1334         if (!radeon_encoder)
1335                 return;
1336
1337         encoder = &radeon_encoder->base;
1338         if (rdev->flags & RADEON_SINGLE_CRTC)
1339                 encoder->possible_crtcs = 0x1;
1340         else
1341                 encoder->possible_crtcs = 0x3;
1342
1343         radeon_encoder->enc_priv = NULL;
1344
1345         radeon_encoder->encoder_id = encoder_id;
1346         radeon_encoder->devices = supported_device;
1347         radeon_encoder->rmx_type = RMX_OFF;
1348
1349         switch (radeon_encoder->encoder_id) {
1350         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1351                 encoder->possible_crtcs = 0x1;
1352                 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1353                 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1354                 if (rdev->is_atom_bios)
1355                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1356                 else
1357                         radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1358                 radeon_encoder->rmx_type = RMX_FULL;
1359                 break;
1360         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1361                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1362                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1363                 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1364                 break;
1365         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1366                 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1367                 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1368                 if (rdev->is_atom_bios)
1369                         radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1370                 else
1371                         radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1372                 break;
1373         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1374                 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1375                 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1376                 if (rdev->is_atom_bios)
1377                         radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1378                 else
1379                         radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1380                 break;
1381         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1382                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1383                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1384                 if (!rdev->is_atom_bios)
1385                         radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1386                 break;
1387         }
1388 }