drivers/gpu/drm/radeon/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 static void radeon_overscan_setup(struct drm_crtc *crtc,
  34                                   struct drm_display_mode *mode)
  35 {
  36         struct drm_device *dev = crtc->dev;
  37         struct radeon_device *rdev = dev->dev_private;
  38         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  39
  40         WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
  41         WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
  42         WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
  43 }
  44
  45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
  46                                        struct drm_display_mode *mode)
  47 {
  48         struct drm_device *dev = crtc->dev;
  49         struct radeon_device *rdev = dev->dev_private;
  50         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  51         int xres = mode->hdisplay;
  52         int yres = mode->vdisplay;
  53         bool hscale = true, vscale = true;
  54         int hsync_wid;
  55         int vsync_wid;
  56         int hsync_start;
  57         int blank_width;
  58         u32 scale, inc, crtc_more_cntl;
  59         u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
  60         u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
  61         u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
  62         struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
  63
  64         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
  65                 (RADEON_VERT_STRETCH_RESERVED |
  66                  RADEON_VERT_AUTO_RATIO_INC);
  67         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
  68                 (RADEON_HORZ_FP_LOOP_STRETCH |
  69                  RADEON_HORZ_AUTO_RATIO_INC);
  70
  71         crtc_more_cntl = 0;
  72         if ((rdev->family == CHIP_RS100) ||
  73             (rdev->family == CHIP_RS200)) {
  74                 /* This is to workaround the asic bug for RMX, some versions
  75                    of BIOS dosen't have this register initialized correctly. */
  76                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  77         }
  78
  79
  80         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  81                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  82
  83         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  84         if (!hsync_wid)
  85                 hsync_wid = 1;
  86         hsync_start = mode->crtc_hsync_start - 8;
  87
  88         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  89                               | ((hsync_wid & 0x3f) << 16)
  90                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  91                                  ? RADEON_CRTC_H_SYNC_POL
  92                                  : 0));
  93
  94         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  95                                 | ((mode->crtc_vdisplay - 1) << 16));
  96
  97         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  98         if (!vsync_wid)
  99                 vsync_wid = 1;
 100
 101         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 102                               | ((vsync_wid & 0x1f) << 16)
 103                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 104                                  ? RADEON_CRTC_V_SYNC_POL
 105                                  : 0));
 106
 107         fp_horz_vert_active = 0;
 108
 109         if (native_mode->hdisplay == 0 ||
 110             native_mode->vdisplay == 0) {
 111                 hscale = false;
 112                 vscale = false;
 113         } else {
 114                 if (xres > native_mode->hdisplay)
 115                         xres = native_mode->hdisplay;
 116                 if (yres > native_mode->vdisplay)
 117                         yres = native_mode->vdisplay;
 118
 119                 if (xres == native_mode->hdisplay)
 120                         hscale = false;
 121                 if (yres == native_mode->vdisplay)
 122                         vscale = false;
 123         }
 124
 125         switch (radeon_crtc->rmx_type) {
 126         case RMX_FULL:
 127         case RMX_ASPECT:
 128                 if (!hscale)
 129                         fp_horz_stretch |= ((xres/8-1) << 16);
 130                 else {
 131                         inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 132                         scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 133                                 / native_mode->hdisplay + 1;
 134                         fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 135                                         RADEON_HORZ_STRETCH_BLEND |
 136                                         RADEON_HORZ_STRETCH_ENABLE |
 137                                         ((native_mode->hdisplay/8-1) << 16));
 138                 }
 139
 140                 if (!vscale)
 141                         fp_vert_stretch |= ((yres-1) << 12);
 142                 else {
 143                         inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 144                         scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 145                                 / native_mode->vdisplay + 1;
 146                         fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 147                                         RADEON_VERT_STRETCH_ENABLE |
 148                                         RADEON_VERT_STRETCH_BLEND |
 149                                         ((native_mode->vdisplay-1) << 12));
 150                 }
 151                 break;
 152         case RMX_CENTER:
 153                 fp_horz_stretch |= ((xres/8-1) << 16);
 154                 fp_vert_stretch |= ((yres-1) << 12);
 155
 156                 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 157                                 RADEON_CRTC_AUTO_VERT_CENTER_EN);
 158
 159                 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 160                 if (blank_width > 110)
 161                         blank_width = 110;
 162
 163                 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 164                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 165
 166                 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 167                 if (!hsync_wid)
 168                         hsync_wid = 1;
 169
 170                 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 171                                 | ((hsync_wid & 0x3f) << 16)
 172                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 173                                         ? RADEON_CRTC_H_SYNC_POL
 174                                         : 0));
 175
 176                 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 177                                 | ((mode->crtc_vdisplay - 1) << 16));
 178
 179                 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 180                 if (!vsync_wid)
 181                         vsync_wid = 1;
 182
 183                 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 184                                         | ((vsync_wid & 0x1f) << 16)
 185                                         | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 186                                                 ? RADEON_CRTC_V_SYNC_POL
 187                                                 : 0)));
 188
 189                 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
 190                                 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
 191                 break;
 192         case RMX_OFF:
 193         default:
 194                 fp_horz_stretch |= ((xres/8-1) << 16);
 195                 fp_vert_stretch |= ((yres-1) << 12);
 196                 break;
 197         }
 198
 199         WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 200         WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 201         WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 202         WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 203         WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 204         WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 205         WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 206         WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 207 }
 208
 209 void radeon_restore_common_regs(struct drm_device *dev)
 210 {
 211         /* don't need this yet */
 212 }
 213
 214 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
 215 {
 216         struct radeon_device *rdev = dev->dev_private;
 217         int i = 0;
 218
 219         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 220            the cause yet, but this workaround will mask the problem for now.
 221            Other chips usually will pass at the very first test, so the
 222            workaround shouldn't have any effect on them. */
 223         for (i = 0;
 224              (i < 10000 &&
 225               RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 226              i++);
 227 }
 228
 229 static void radeon_pll_write_update(struct drm_device *dev)
 230 {
 231         struct radeon_device *rdev = dev->dev_private;
 232
 233         while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 234
 235         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 236                            RADEON_PPLL_ATOMIC_UPDATE_W,
 237                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
 238 }
 239
 240 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
 241 {
 242         struct radeon_device *rdev = dev->dev_private;
 243         int i = 0;
 244
 245
 246         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 247            the cause yet, but this workaround will mask the problem for now.
 248            Other chips usually will pass at the very first test, so the
 249            workaround shouldn't have any effect on them. */
 250         for (i = 0;
 251              (i < 10000 &&
 252               RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 253              i++);
 254 }
 255
 256 static void radeon_pll2_write_update(struct drm_device *dev)
 257 {
 258         struct radeon_device *rdev = dev->dev_private;
 259
 260         while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 261
 262         WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 263                            RADEON_P2PLL_ATOMIC_UPDATE_W,
 264                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
 265 }
 266
 267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
 268                                        uint16_t fb_div)
 269 {
 270         unsigned int vcoFreq;
 271
 272         if (!ref_div)
 273                 return 1;
 274
 275         vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
 276
 277         /*
 278          * This is horribly crude: the VCO frequency range is divided into
 279          * 3 parts, each part having a fixed PLL gain value.
 280          */
 281         if (vcoFreq >= 30000)
 282                 /*
 283                  * [300..max] MHz : 7
 284                  */
 285                 return 7;
 286         else if (vcoFreq >= 18000)
 287                 /*
 288                  * [180..300) MHz : 4
 289                  */
 290                 return 4;
 291         else
 292                 /*
 293                  * [0..180) MHz : 1
 294                  */
 295                 return 1;
 296 }
 297
 298 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 299 {
 300         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 301         struct drm_device *dev = crtc->dev;
 302         struct radeon_device *rdev = dev->dev_private;
 303         uint32_t mask;
 304
 305         if (radeon_crtc->crtc_id)
 306                 mask = (RADEON_CRTC2_DISP_DIS |
 307                         RADEON_CRTC2_VSYNC_DIS |
 308                         RADEON_CRTC2_HSYNC_DIS |
 309                         RADEON_CRTC2_DISP_REQ_EN_B);
 310         else
 311                 mask = (RADEON_CRTC_DISPLAY_DIS |
 312                         RADEON_CRTC_VSYNC_DIS |
 313                         RADEON_CRTC_HSYNC_DIS);
 314
 315         switch (mode) {
 316         case DRM_MODE_DPMS_ON:
 317                 radeon_crtc->enabled = true;
 318                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 319                 radeon_pm_compute_clocks(rdev);
 320                 if (radeon_crtc->crtc_id)
 321                         WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
 322                 else {
 323                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 324                                                                          RADEON_CRTC_DISP_REQ_EN_B));
 325                         WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 326                 }
 327                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 328                 radeon_crtc_load_lut(crtc);
 329                 break;
 330         case DRM_MODE_DPMS_STANDBY:
 331         case DRM_MODE_DPMS_SUSPEND:
 332         case DRM_MODE_DPMS_OFF:
 333                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 334                 if (radeon_crtc->crtc_id)
 335                         WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
 336                 else {
 337                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 338                                                                                     RADEON_CRTC_DISP_REQ_EN_B));
 339                         WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
 340                 }
 341                 radeon_crtc->enabled = false;
 342                 /* adjust pm to dpms changes AFTER disabling crtcs */
 343                 radeon_pm_compute_clocks(rdev);
 344                 break;
 345         }
 346 }
 347
 348 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 349                          struct drm_framebuffer *old_fb)
 350 {
 351         return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
 352 }
 353
 354 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
 355                                 struct drm_framebuffer *fb,
 356                                 int x, int y, enum mode_set_atomic state)
 357 {
 358         return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
 359 }
 360
 361 int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 362                          struct drm_framebuffer *fb,
 363                          int x, int y, int atomic)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         struct radeon_device *rdev = dev->dev_private;
 367         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 368         struct radeon_framebuffer *radeon_fb;
 369         struct drm_framebuffer *target_fb;
 370         struct drm_gem_object *obj;
 371         struct radeon_bo *rbo;
 372         uint64_t base;
 373         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 374         uint32_t crtc_pitch, pitch_pixels;
 375         uint32_t tiling_flags;
 376         int format;
 377         uint32_t gen_cntl_reg, gen_cntl_val;
 378         int r;
 379
 380         DRM_DEBUG_KMS("\n");
 381         /* no fb bound */
 382         if (!atomic && !crtc->fb) {
 383                 DRM_DEBUG_KMS("No FB bound\n");
 384                 return 0;
 385         }
 386
 387         if (atomic) {
 388                 radeon_fb = to_radeon_framebuffer(fb);
 389                 target_fb = fb;
 390         }
 391         else {
 392                 radeon_fb = to_radeon_framebuffer(crtc->fb);
 393                 target_fb = crtc->fb;
 394         }
 395
 396         switch (target_fb->bits_per_pixel) {
 397         case 8:
 398                 format = 2;
 399                 break;
 400         case 15:      /*  555 */
 401                 format = 3;
 402                 break;
 403         case 16:      /*  565 */
 404                 format = 4;
 405                 break;
 406         case 24:      /*  RGB */
 407                 format = 5;
 408                 break;
 409         case 32:      /* xRGB */
 410                 format = 6;
 411                 break;
 412         default:
 413                 return false;
 414         }
 415
 416         /* Pin framebuffer & get tilling informations */
 417         obj = radeon_fb->obj;
 418         rbo = gem_to_radeon_bo(obj);
 419 retry:
 420         r = radeon_bo_reserve(rbo, false);
 421         if (unlikely(r != 0))
 422                 return r;
 423         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
 424         if (unlikely(r != 0)) {
 425                 radeon_bo_unreserve(rbo);
 426
 427                 /* On old GPU like RN50 with little vram pining can fails because
 428                  * current fb is taking all space needed. So instead of unpining
 429                  * the old buffer after pining the new one, first unpin old one
 430                  * and then retry pining new one.
 431                  *
 432                  * As only master can set mode only master can pin and it is
 433                  * unlikely the master client will race with itself especialy
 434                  * on those old gpu with single crtc.
 435                  *
 436                  * We don't shutdown the display controller because new buffer
 437                  * will end up in same spot.
 438                  */
 439                 if (!atomic && fb && fb != crtc->fb) {
 440                         struct radeon_bo *old_rbo;
 441                         unsigned long nsize, osize;
 442
 443                         old_rbo = gem_to_radeon_bo(to_radeon_framebuffer(fb)->obj);
 444                         osize = radeon_bo_size(old_rbo);
 445                         nsize = radeon_bo_size(rbo);
 446                         if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) {
 447                                 radeon_bo_unpin(old_rbo);
 448                                 radeon_bo_unreserve(old_rbo);
 449                                 fb = NULL;
 450                                 goto retry;
 451                         }
 452                 }
 453                 return -EINVAL;
 454         }
 455         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 456         radeon_bo_unreserve(rbo);
 457         if (tiling_flags & RADEON_TILING_MICRO)
 458                 DRM_ERROR("trying to scanout microtiled buffer\n");
 459
 460         /* if scanout was in GTT this really wouldn't work */
 461         /* crtc offset is from display base addr not FB location */
 462         radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
 463
 464         base -= radeon_crtc->legacy_display_base_addr;
 465
 466         crtc_offset_cntl = 0;
 467
 468         pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
 469         crtc_pitch  = (((pitch_pixels * target_fb->bits_per_pixel) +
 470                         ((target_fb->bits_per_pixel * 8) - 1)) /
 471                        (target_fb->bits_per_pixel * 8));
 472         crtc_pitch |= crtc_pitch << 16;
 473
 474         crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
 475         if (tiling_flags & RADEON_TILING_MACRO) {
 476                 if (ASIC_IS_R300(rdev))
 477                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 478                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 479                                              R300_CRTC_MACRO_TILE_EN);
 480                 else
 481                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 482         } else {
 483                 if (ASIC_IS_R300(rdev))
 484                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 485                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 486                                               R300_CRTC_MACRO_TILE_EN);
 487                 else
 488                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 489         }
 490
 491         if (tiling_flags & RADEON_TILING_MACRO) {
 492                 if (ASIC_IS_R300(rdev)) {
 493                         crtc_tile_x0_y0 = x | (y << 16);
 494                         base &= ~0x7ff;
 495                 } else {
 496                         int byteshift = target_fb->bits_per_pixel >> 4;
 497                         int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
 498                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 499                         crtc_offset_cntl |= (y % 16);
 500                 }
 501         } else {
 502                 int offset = y * pitch_pixels + x;
 503                 switch (target_fb->bits_per_pixel) {
 504                 case 8:
 505                         offset *= 1;
 506                         break;
 507                 case 15:
 508                 case 16:
 509                         offset *= 2;
 510                         break;
 511                 case 24:
 512                         offset *= 3;
 513                         break;
 514                 case 32:
 515                         offset *= 4;
 516                         break;
 517                 default:
 518                         return false;
 519                 }
 520                 base += offset;
 521         }
 522
 523         base &= ~7;
 524
 525         if (radeon_crtc->crtc_id == 1)
 526                 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
 527         else
 528                 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 529
 530         gen_cntl_val = RREG32(gen_cntl_reg);
 531         gen_cntl_val &= ~(0xf << 8);
 532         gen_cntl_val |= (format << 8);
 533         gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
 534         WREG32(gen_cntl_reg, gen_cntl_val);
 535
 536         crtc_offset = (u32)base;
 537
 538         WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 539
 540         if (ASIC_IS_R300(rdev)) {
 541                 if (radeon_crtc->crtc_id)
 542                         WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
 543                 else
 544                         WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 545         }
 546         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
 547         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
 548         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 549
 550         if (!atomic && fb && fb != crtc->fb) {
 551                 radeon_fb = to_radeon_framebuffer(fb);
 552                 rbo = gem_to_radeon_bo(radeon_fb->obj);
 553                 r = radeon_bo_reserve(rbo, false);
 554                 if (unlikely(r != 0))
 555                         return r;
 556                 radeon_bo_unpin(rbo);
 557                 radeon_bo_unreserve(rbo);
 558         }
 559
 560         /* Bytes per pixel may have changed */
 561         radeon_bandwidth_update(rdev);
 562
 563         return 0;
 564 }
 565
 566 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 567 {
 568         struct drm_device *dev = crtc->dev;
 569         struct radeon_device *rdev = dev->dev_private;
 570         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 571         struct drm_encoder *encoder;
 572         int format;
 573         int hsync_start;
 574         int hsync_wid;
 575         int vsync_wid;
 576         uint32_t crtc_h_total_disp;
 577         uint32_t crtc_h_sync_strt_wid;
 578         uint32_t crtc_v_total_disp;
 579         uint32_t crtc_v_sync_strt_wid;
 580         bool is_tv = false;
 581
 582         DRM_DEBUG_KMS("\n");
 583         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 584                 if (encoder->crtc == crtc) {
 585                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 586                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 587                                 is_tv = true;
 588                                 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
 589                                 break;
 590                         }
 591                 }
 592         }
 593
 594         switch (crtc->fb->bits_per_pixel) {
 595         case 8:
 596                 format = 2;
 597                 break;
 598         case 15:      /*  555 */
 599                 format = 3;
 600                 break;
 601         case 16:      /*  565 */
 602                 format = 4;
 603                 break;
 604         case 24:      /*  RGB */
 605                 format = 5;
 606                 break;
 607         case 32:      /* xRGB */
 608                 format = 6;
 609                 break;
 610         default:
 611                 return false;
 612         }
 613
 614         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 615                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 616
 617         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 618         if (!hsync_wid)
 619                 hsync_wid = 1;
 620         hsync_start = mode->crtc_hsync_start - 8;
 621
 622         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 623                                 | ((hsync_wid & 0x3f) << 16)
 624                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 625                                    ? RADEON_CRTC_H_SYNC_POL
 626                                    : 0));
 627
 628         /* This works for double scan mode. */
 629         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 630                              | ((mode->crtc_vdisplay - 1) << 16));
 631
 632         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 633         if (!vsync_wid)
 634                 vsync_wid = 1;
 635
 636         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 637                                 | ((vsync_wid & 0x1f) << 16)
 638                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 639                                    ? RADEON_CRTC_V_SYNC_POL
 640                                    : 0));
 641
 642         if (radeon_crtc->crtc_id) {
 643                 uint32_t crtc2_gen_cntl;
 644                 uint32_t disp2_merge_cntl;
 645
 646                 /* if TV DAC is enabled for another crtc and keep it enabled */
 647                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
 648                 crtc2_gen_cntl |= ((format << 8)
 649                                    | RADEON_CRTC2_VSYNC_DIS
 650                                    | RADEON_CRTC2_HSYNC_DIS
 651                                    | RADEON_CRTC2_DISP_DIS
 652                                    | RADEON_CRTC2_DISP_REQ_EN_B
 653                                    | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 654                                       ? RADEON_CRTC2_DBL_SCAN_EN
 655                                       : 0)
 656                                    | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 657                                       ? RADEON_CRTC2_CSYNC_EN
 658                                       : 0)
 659                                    | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 660                                       ? RADEON_CRTC2_INTERLACE_EN
 661                                       : 0));
 662
 663                 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 664                 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 665                         crtc2_gen_cntl |= RADEON_CRTC2_EN;
 666
 667                 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 668                 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 669
 670                 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
 671                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 672
 673                 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 674                 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 675         } else {
 676                 uint32_t crtc_gen_cntl;
 677                 uint32_t crtc_ext_cntl;
 678                 uint32_t disp_merge_cntl;
 679
 680                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
 681                 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
 682                                  | (format << 8)
 683                                  | RADEON_CRTC_DISP_REQ_EN_B
 684                                  | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 685                                     ? RADEON_CRTC_DBL_SCAN_EN
 686                                     : 0)
 687                                  | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 688                                     ? RADEON_CRTC_CSYNC_EN
 689                                     : 0)
 690                                  | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 691                                     ? RADEON_CRTC_INTERLACE_EN
 692                                     : 0));
 693
 694                 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 695                 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 696                         crtc_gen_cntl |= RADEON_CRTC_EN;
 697
 698                 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 699                 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 700                                   RADEON_CRTC_VSYNC_DIS |
 701                                   RADEON_CRTC_HSYNC_DIS |
 702                                   RADEON_CRTC_DISPLAY_DIS);
 703
 704                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 705                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 706
 707                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 708                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 709                 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 710         }
 711
 712         if (is_tv)
 713                 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
 714                                                  &crtc_h_sync_strt_wid, &crtc_v_total_disp,
 715                                                  &crtc_v_sync_strt_wid);
 716
 717         WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
 718         WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
 719         WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
 720         WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 721
 722         return true;
 723 }
 724
 725 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 726 {
 727         struct drm_device *dev = crtc->dev;
 728         struct radeon_device *rdev = dev->dev_private;
 729         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 730         struct drm_encoder *encoder;
 731         uint32_t feedback_div = 0;
 732         uint32_t frac_fb_div = 0;
 733         uint32_t reference_div = 0;
 734         uint32_t post_divider = 0;
 735         uint32_t freq = 0;
 736         uint8_t pll_gain;
 737         bool use_bios_divs = false;
 738         /* PLL registers */
 739         uint32_t pll_ref_div = 0;
 740         uint32_t pll_fb_post_div = 0;
 741         uint32_t htotal_cntl = 0;
 742         bool is_tv = false;
 743         struct radeon_pll *pll;
 744
 745         struct {
 746                 int divider;
 747                 int bitvalue;
 748         } *post_div, post_divs[]   = {
 749                 /* From RAGE 128 VR/RAGE 128 GL Register
 750                  * Reference Manual (Technical Reference
 751                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 752                  * 3-17 (PLL_DIV_[3:0]).
 753                  */
 754                 {  1, 0 },              /* VCLK_SRC                 */
 755                 {  2, 1 },              /* VCLK_SRC/2               */
 756                 {  4, 2 },              /* VCLK_SRC/4               */
 757                 {  8, 3 },              /* VCLK_SRC/8               */
 758                 {  3, 4 },              /* VCLK_SRC/3               */
 759                 { 16, 5 },              /* VCLK_SRC/16              */
 760                 {  6, 6 },              /* VCLK_SRC/6               */
 761                 { 12, 7 },              /* VCLK_SRC/12              */
 762                 {  0, 0 }
 763         };
 764
 765         if (radeon_crtc->crtc_id)
 766                 pll = &rdev->clock.p2pll;
 767         else
 768                 pll = &rdev->clock.p1pll;
 769
 770         pll->flags = RADEON_PLL_LEGACY;
 771
 772         if (mode->clock > 200000) /* range limits??? */
 773                 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 774         else
 775                 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 776
 777         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 778                 if (encoder->crtc == crtc) {
 779                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 780
 781                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 782                                 is_tv = true;
 783                                 break;
 784                         }
 785
 786                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 787                                 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 788                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 789                                 if (!rdev->is_atom_bios) {
 790                                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 791                                         struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 792                                         if (lvds) {
 793                                                 if (lvds->use_bios_dividers) {
 794                                                         pll_ref_div = lvds->panel_ref_divider;
 795                                                         pll_fb_post_div   = (lvds->panel_fb_divider |
 796                                                                              (lvds->panel_post_divider << 16));
 797                                                         htotal_cntl  = 0;
 798                                                         use_bios_divs = true;
 799                                                 }
 800                                         }
 801                                 }
 802                                 pll->flags |= RADEON_PLL_USE_REF_DIV;
 803                         }
 804                 }
 805         }
 806
 807         DRM_DEBUG_KMS("\n");
 808
 809         if (!use_bios_divs) {
 810                 radeon_compute_pll_legacy(pll, mode->clock,
 811                                           &freq, &feedback_div, &frac_fb_div,
 812                                           &reference_div, &post_divider);
 813
 814                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 815                         if (post_div->divider == post_divider)
 816                                 break;
 817                 }
 818
 819                 if (!post_div->divider)
 820                         post_div = &post_divs[0];
 821
 822                 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
 823                           (unsigned)freq,
 824                           feedback_div,
 825                           reference_div,
 826                           post_divider);
 827
 828                 pll_ref_div   = reference_div;
 829 #if defined(__powerpc__) && (0) /* TODO */
 830                 /* apparently programming this otherwise causes a hang??? */
 831                 if (info->MacModel == RADEON_MAC_IBOOK)
 832                         pll_fb_post_div = 0x000600ad;
 833                 else
 834 #endif
 835                         pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 836
 837                 htotal_cntl    = mode->htotal & 0x7;
 838
 839         }
 840
 841         pll_gain = radeon_compute_pll_gain(pll->reference_freq,
 842                                            pll_ref_div & 0x3ff,
 843                                            pll_fb_post_div & 0x7ff);
 844
 845         if (radeon_crtc->crtc_id) {
 846                 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
 847                                           ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 848                                          RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 849
 850                 if (is_tv) {
 851                         radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
 852                                                      &pll_ref_div, &pll_fb_post_div,
 853                                                      &pixclks_cntl);
 854                 }
 855
 856                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 857                              RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 858                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 859
 860                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 861                              RADEON_P2PLL_RESET
 862                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 863                              | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 864                              ~(RADEON_P2PLL_RESET
 865                                | RADEON_P2PLL_ATOMIC_UPDATE_EN
 866                                | RADEON_P2PLL_PVG_MASK));
 867
 868                 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 869                              pll_ref_div,
 870                              ~RADEON_P2PLL_REF_DIV_MASK);
 871
 872                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 873                              pll_fb_post_div,
 874                              ~RADEON_P2PLL_FB0_DIV_MASK);
 875
 876                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 877                              pll_fb_post_div,
 878                              ~RADEON_P2PLL_POST0_DIV_MASK);
 879
 880                 radeon_pll2_write_update(dev);
 881                 radeon_pll2_wait_for_read_update_complete(dev);
 882
 883                 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 884
 885                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 886                              0,
 887                              ~(RADEON_P2PLL_RESET
 888                                | RADEON_P2PLL_SLEEP
 889                                | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 890
 891                 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 892                           (unsigned)pll_ref_div,
 893                           (unsigned)pll_fb_post_div,
 894                           (unsigned)htotal_cntl,
 895                           RREG32_PLL(RADEON_P2PLL_CNTL));
 896                 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
 897                           (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 898                           (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
 899                           (unsigned)((pll_fb_post_div &
 900                                       RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 901
 902                 mdelay(50); /* Let the clock to lock */
 903
 904                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 905                              RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 906                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 907
 908                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 909         } else {
 910                 uint32_t pixclks_cntl;
 911
 912
 913                 if (is_tv) {
 914                         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 915                         radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
 916                                                      &pll_fb_post_div, &pixclks_cntl);
 917                 }
 918
 919                 if (rdev->flags & RADEON_IS_MOBILITY) {
 920                         /* A temporal workaround for the occasional blanking on certain laptop panels.
 921                            This appears to related to the PLL divider registers (fail to lock?).
 922                            It occurs even when all dividers are the same with their old settings.
 923                            In this case we really don't need to fiddle with PLL registers.
 924                            By doing this we can avoid the blanking problem with some panels.
 925                         */
 926                         if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 927                             (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
 928                                                  (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 929                                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 930                                          RADEON_PLL_DIV_SEL,
 931                                          ~(RADEON_PLL_DIV_SEL));
 932                                 r100_pll_errata_after_index(rdev);
 933                                 return;
 934                         }
 935                 }
 936
 937                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 938                              RADEON_VCLK_SRC_SEL_CPUCLK,
 939                              ~(RADEON_VCLK_SRC_SEL_MASK));
 940                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 941                              RADEON_PPLL_RESET
 942                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 943                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 944                              | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 945                              ~(RADEON_PPLL_RESET
 946                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 947                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 948                                | RADEON_PPLL_PVG_MASK));
 949
 950                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 951                          RADEON_PLL_DIV_SEL,
 952                          ~(RADEON_PLL_DIV_SEL));
 953                 r100_pll_errata_after_index(rdev);
 954
 955                 if (ASIC_IS_R300(rdev) ||
 956                     (rdev->family == CHIP_RS300) ||
 957                     (rdev->family == CHIP_RS400) ||
 958                     (rdev->family == CHIP_RS480)) {
 959                         if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 960                                 /* When restoring console mode, use saved PPLL_REF_DIV
 961                                  * setting.
 962                                  */
 963                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 964                                              pll_ref_div,
 965                                              0);
 966                         } else {
 967                                 /* R300 uses ref_div_acc field as real ref divider */
 968                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 969                                              (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 970                                              ~R300_PPLL_REF_DIV_ACC_MASK);
 971                         }
 972                 } else
 973                         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 974                                      pll_ref_div,
 975                                      ~RADEON_PPLL_REF_DIV_MASK);
 976
 977                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 978                              pll_fb_post_div,
 979                              ~RADEON_PPLL_FB3_DIV_MASK);
 980
 981                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 982                              pll_fb_post_div,
 983                              ~RADEON_PPLL_POST3_DIV_MASK);
 984
 985                 radeon_pll_write_update(dev);
 986                 radeon_pll_wait_for_read_update_complete(dev);
 987
 988                 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
 989
 990                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 991                              0,
 992                              ~(RADEON_PPLL_RESET
 993                                | RADEON_PPLL_SLEEP
 994                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 995                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 996
 997                 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 998                           pll_ref_div,
 999                           pll_fb_post_div,
1000                           (unsigned)htotal_cntl,
1001                           RREG32_PLL(RADEON_PPLL_CNTL));
1002                 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
1003                           pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
1004                           pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
1005                           (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
1006
1007                 mdelay(50); /* Let the clock to lock */
1008
1009                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1010                              RADEON_VCLK_SRC_SEL_PPLLCLK,
1011                              ~(RADEON_VCLK_SRC_SEL_MASK));
1012
1013                 if (is_tv)
1014                         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1015         }
1016 }
1017
1018 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1019                                    struct drm_display_mode *mode,
1020                                    struct drm_display_mode *adjusted_mode)
1021 {
1022         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1023                 return false;
1024         return true;
1025 }
1026
1027 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1028                                  struct drm_display_mode *mode,
1029                                  struct drm_display_mode *adjusted_mode,
1030                                  int x, int y, struct drm_framebuffer *old_fb)
1031 {
1032         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1033
1034         /* TODO TV */
1035         radeon_crtc_set_base(crtc, x, y, old_fb);
1036         radeon_set_crtc_timing(crtc, adjusted_mode);
1037         radeon_set_pll(crtc, adjusted_mode);
1038         radeon_overscan_setup(crtc, adjusted_mode);
1039         if (radeon_crtc->crtc_id == 0) {
1040                 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1041         } else {
1042                 if (radeon_crtc->rmx_type != RMX_OFF) {
1043                         /* FIXME: only first crtc has rmx what should we
1044                          * do ?
1045                          */
1046                         DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1047                 }
1048         }
1049         return 0;
1050 }
1051
1052 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1053 {
1054         struct drm_device *dev = crtc->dev;
1055         struct drm_crtc *crtci;
1056
1057         /*
1058         * The hardware wedges sometimes if you reconfigure one CRTC
1059         * whilst another is running (see fdo bug #24611).
1060         */
1061         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1062                 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1063 }
1064
1065 static void radeon_crtc_commit(struct drm_crtc *crtc)
1066 {
1067         struct drm_device *dev = crtc->dev;
1068         struct drm_crtc *crtci;
1069
1070         /*
1071         * Reenable the CRTCs that should be running.
1072         */
1073         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1074                 if (crtci->enabled)
1075                         radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1076         }
1077 }
1078
1079 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1080         .dpms = radeon_crtc_dpms,
1081         .mode_fixup = radeon_crtc_mode_fixup,
1082         .mode_set = radeon_crtc_mode_set,
1083         .mode_set_base = radeon_crtc_set_base,
1084         .mode_set_base_atomic = radeon_crtc_set_base_atomic,
1085         .prepare = radeon_crtc_prepare,
1086         .commit = radeon_crtc_commit,
1087         .load_lut = radeon_crtc_load_lut,
1088 };
1089
1090
1091 void radeon_legacy_init_crtc(struct drm_device *dev,
1092                                struct radeon_crtc *radeon_crtc)
1093 {
1094         if (radeon_crtc->crtc_id == 1)
1095                 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1096         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1097 }