2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon_fixed.h"
32 void radeon_restore_common_regs(struct drm_device *dev)
34 /* don't need this yet */
37 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
39 struct radeon_device *rdev = dev->dev_private;
42 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
43 the cause yet, but this workaround will mask the problem for now.
44 Other chips usually will pass at the very first test, so the
45 workaround shouldn't have any effect on them. */
48 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
52 static void radeon_pll_write_update(struct drm_device *dev)
54 struct radeon_device *rdev = dev->dev_private;
56 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
58 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
59 RADEON_PPLL_ATOMIC_UPDATE_W,
60 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
63 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
65 struct radeon_device *rdev = dev->dev_private;
69 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
70 the cause yet, but this workaround will mask the problem for now.
71 Other chips usually will pass at the very first test, so the
72 workaround shouldn't have any effect on them. */
75 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
79 static void radeon_pll2_write_update(struct drm_device *dev)
81 struct radeon_device *rdev = dev->dev_private;
83 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
85 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
86 RADEON_P2PLL_ATOMIC_UPDATE_W,
87 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
90 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
98 vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
101 * This is horribly crude: the VCO frequency range is divided into
102 * 3 parts, each part having a fixed PLL gain value.
104 if (vcoFreq >= 30000)
109 else if (vcoFreq >= 18000)
121 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
123 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
124 struct drm_device *dev = crtc->dev;
125 struct radeon_device *rdev = dev->dev_private;
128 if (radeon_crtc->crtc_id)
129 mask = (RADEON_CRTC2_EN |
130 RADEON_CRTC2_DISP_DIS |
131 RADEON_CRTC2_VSYNC_DIS |
132 RADEON_CRTC2_HSYNC_DIS |
133 RADEON_CRTC2_DISP_REQ_EN_B);
135 mask = (RADEON_CRTC_DISPLAY_DIS |
136 RADEON_CRTC_VSYNC_DIS |
137 RADEON_CRTC_HSYNC_DIS);
140 case DRM_MODE_DPMS_ON:
141 if (radeon_crtc->crtc_id)
142 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);
144 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
145 RADEON_CRTC_DISP_REQ_EN_B));
146 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
149 case DRM_MODE_DPMS_STANDBY:
150 case DRM_MODE_DPMS_SUSPEND:
151 case DRM_MODE_DPMS_OFF:
152 if (radeon_crtc->crtc_id)
153 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
155 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
156 RADEON_CRTC_DISP_REQ_EN_B));
157 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
162 if (mode != DRM_MODE_DPMS_OFF) {
163 radeon_crtc_load_lut(crtc);
167 /* properly set crtc bpp when using atombios */
168 void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
170 struct drm_device *dev = crtc->dev;
171 struct radeon_device *rdev = dev->dev_private;
172 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
174 uint32_t crtc_gen_cntl;
175 uint32_t disp_merge_cntl;
178 switch (crtc->fb->bits_per_pixel) {
195 crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
196 ((crtc->fb->bits_per_pixel * 8) - 1)) /
197 (crtc->fb->bits_per_pixel * 8));
198 crtc_pitch |= crtc_pitch << 16;
200 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
202 switch (radeon_crtc->crtc_id) {
204 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
205 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
206 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
208 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
209 crtc_gen_cntl |= (format << 8);
210 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
211 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
214 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
215 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
216 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
218 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
219 crtc_gen_cntl |= (format << 8);
220 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
221 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
222 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
227 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
228 struct drm_framebuffer *old_fb)
230 struct drm_device *dev = crtc->dev;
231 struct radeon_device *rdev = dev->dev_private;
232 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
233 struct radeon_framebuffer *radeon_fb;
234 struct drm_gem_object *obj;
236 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
237 uint32_t crtc_pitch, pitch_pixels;
241 radeon_fb = to_radeon_framebuffer(crtc->fb);
243 obj = radeon_fb->obj;
244 if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
247 /* if scanout was in GTT this really wouldn't work */
248 /* crtc offset is from display base addr not FB location */
249 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
251 base -= radeon_crtc->legacy_display_base_addr;
253 crtc_offset_cntl = 0;
255 pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
256 crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +
257 ((crtc->fb->bits_per_pixel * 8) - 1)) /
258 (crtc->fb->bits_per_pixel * 8));
259 crtc_pitch |= crtc_pitch << 16;
263 if (ASIC_IS_R300(rdev))
264 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
265 R300_CRTC_MICRO_TILE_BUFFER_DIS |
266 R300_CRTC_MACRO_TILE_EN);
268 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
270 if (ASIC_IS_R300(rdev))
271 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
272 R300_CRTC_MICRO_TILE_BUFFER_DIS |
273 R300_CRTC_MACRO_TILE_EN);
275 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
279 /* TODO more tiling */
281 if (ASIC_IS_R300(rdev)) {
282 crtc_tile_x0_y0 = x | (y << 16);
285 int byteshift = crtc->fb->bits_per_pixel >> 4;
286 int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
287 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
288 crtc_offset_cntl |= (y % 16);
291 int offset = y * pitch_pixels + x;
292 switch (crtc->fb->bits_per_pixel) {
311 crtc_offset = (u32)base;
313 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
315 if (ASIC_IS_R300(rdev)) {
316 if (radeon_crtc->crtc_id)
317 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
319 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
321 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
322 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
323 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
325 if (old_fb && old_fb != crtc->fb) {
326 radeon_fb = to_radeon_framebuffer(old_fb);
327 radeon_gem_object_unpin(radeon_fb->obj);
332 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
334 struct drm_device *dev = crtc->dev;
335 struct radeon_device *rdev = dev->dev_private;
336 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
341 uint32_t crtc_h_total_disp;
342 uint32_t crtc_h_sync_strt_wid;
343 uint32_t crtc_v_total_disp;
344 uint32_t crtc_v_sync_strt_wid;
348 switch (crtc->fb->bits_per_pixel) {
365 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
366 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
368 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
371 hsync_start = mode->crtc_hsync_start - 8;
373 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
374 | ((hsync_wid & 0x3f) << 16)
375 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
376 ? RADEON_CRTC_H_SYNC_POL
379 /* This works for double scan mode. */
380 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
381 | ((mode->crtc_vdisplay - 1) << 16));
383 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
387 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
388 | ((vsync_wid & 0x1f) << 16)
389 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
390 ? RADEON_CRTC_V_SYNC_POL
393 /* TODO -> Dell Server */
395 uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
396 uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
397 uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
398 uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
400 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
401 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
403 /* For CRT on DAC2, don't turn it on if BIOS didn't
404 enable it, even it's detected.
406 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
407 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
408 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
410 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
411 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
412 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
413 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
416 if (radeon_crtc->crtc_id) {
417 uint32_t crtc2_gen_cntl;
418 uint32_t disp2_merge_cntl;
420 /* check to see if TV DAC is enabled for another crtc and keep it enabled */
421 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
422 crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
426 crtc2_gen_cntl |= ((format << 8)
427 | RADEON_CRTC2_VSYNC_DIS
428 | RADEON_CRTC2_HSYNC_DIS
429 | RADEON_CRTC2_DISP_DIS
430 | RADEON_CRTC2_DISP_REQ_EN_B
431 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
432 ? RADEON_CRTC2_DBL_SCAN_EN
434 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
435 ? RADEON_CRTC2_CSYNC_EN
437 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
438 ? RADEON_CRTC2_INTERLACE_EN
441 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
442 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
444 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
445 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
447 uint32_t crtc_gen_cntl;
448 uint32_t crtc_ext_cntl;
449 uint32_t disp_merge_cntl;
451 crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
453 | RADEON_CRTC_DISP_REQ_EN_B
454 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
455 ? RADEON_CRTC_DBL_SCAN_EN
457 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
458 ? RADEON_CRTC_CSYNC_EN
460 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
461 ? RADEON_CRTC_INTERLACE_EN
464 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
465 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
466 RADEON_CRTC_VSYNC_DIS |
467 RADEON_CRTC_HSYNC_DIS |
468 RADEON_CRTC_DISPLAY_DIS);
470 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
471 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
473 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
474 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
475 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
478 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
479 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
480 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
481 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
486 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
488 struct drm_device *dev = crtc->dev;
489 struct radeon_device *rdev = dev->dev_private;
490 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
491 struct drm_encoder *encoder;
492 uint32_t feedback_div = 0;
493 uint32_t frac_fb_div = 0;
494 uint32_t reference_div = 0;
495 uint32_t post_divider = 0;
498 int pll_flags = RADEON_PLL_LEGACY;
499 bool use_bios_divs = false;
501 uint32_t pll_ref_div = 0;
502 uint32_t pll_fb_post_div = 0;
503 uint32_t htotal_cntl = 0;
505 struct radeon_pll *pll;
510 } *post_div, post_divs[] = {
511 /* From RAGE 128 VR/RAGE 128 GL Register
512 * Reference Manual (Technical Reference
513 * Manual P/N RRG-G04100-C Rev. 0.04), page
514 * 3-17 (PLL_DIV_[3:0]).
516 { 1, 0 }, /* VCLK_SRC */
517 { 2, 1 }, /* VCLK_SRC/2 */
518 { 4, 2 }, /* VCLK_SRC/4 */
519 { 8, 3 }, /* VCLK_SRC/8 */
520 { 3, 4 }, /* VCLK_SRC/3 */
521 { 16, 5 }, /* VCLK_SRC/16 */
522 { 6, 6 }, /* VCLK_SRC/6 */
523 { 12, 7 }, /* VCLK_SRC/12 */
527 if (radeon_crtc->crtc_id)
528 pll = &rdev->clock.p2pll;
530 pll = &rdev->clock.p1pll;
532 if (mode->clock > 200000) /* range limits??? */
533 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
535 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
537 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
538 if (encoder->crtc == crtc) {
539 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
540 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
541 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
542 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
543 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
545 if (lvds->use_bios_dividers) {
546 pll_ref_div = lvds->panel_ref_divider;
547 pll_fb_post_div = (lvds->panel_fb_divider |
548 (lvds->panel_post_divider << 16));
550 use_bios_divs = true;
553 pll_flags |= RADEON_PLL_USE_REF_DIV;
560 if (!use_bios_divs) {
561 radeon_compute_pll(pll, mode->clock,
562 &freq, &feedback_div, &frac_fb_div,
563 &reference_div, &post_divider,
566 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
567 if (post_div->divider == post_divider)
571 if (!post_div->divider)
572 post_div = &post_divs[0];
574 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
580 pll_ref_div = reference_div;
581 #if defined(__powerpc__) && (0) /* TODO */
582 /* apparently programming this otherwise causes a hang??? */
583 if (info->MacModel == RADEON_MAC_IBOOK)
584 pll_fb_post_div = 0x000600ad;
587 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
589 htotal_cntl = mode->htotal & 0x7;
593 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
595 pll_fb_post_div & 0x7ff);
597 if (radeon_crtc->crtc_id) {
598 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
599 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
600 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
602 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
603 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
604 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
606 WREG32_PLL_P(RADEON_P2PLL_CNTL,
608 | RADEON_P2PLL_ATOMIC_UPDATE_EN
609 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
611 | RADEON_P2PLL_ATOMIC_UPDATE_EN
612 | RADEON_P2PLL_PVG_MASK));
614 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
616 ~RADEON_P2PLL_REF_DIV_MASK);
618 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
620 ~RADEON_P2PLL_FB0_DIV_MASK);
622 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
624 ~RADEON_P2PLL_POST0_DIV_MASK);
626 radeon_pll2_write_update(dev);
627 radeon_pll2_wait_for_read_update_complete(dev);
629 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
631 WREG32_PLL_P(RADEON_P2PLL_CNTL,
635 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
637 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
638 (unsigned)pll_ref_div,
639 (unsigned)pll_fb_post_div,
640 (unsigned)htotal_cntl,
641 RREG32_PLL(RADEON_P2PLL_CNTL));
642 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
643 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
644 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
645 (unsigned)((pll_fb_post_div &
646 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
648 mdelay(50); /* Let the clock to lock */
650 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
651 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
652 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
654 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
656 if (rdev->flags & RADEON_IS_MOBILITY) {
657 /* A temporal workaround for the occational blanking on certain laptop panels.
658 This appears to related to the PLL divider registers (fail to lock?).
659 It occurs even when all dividers are the same with their old settings.
660 In this case we really don't need to fiddle with PLL registers.
661 By doing this we can avoid the blanking problem with some panels.
663 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
664 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
665 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
666 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
668 ~(RADEON_PLL_DIV_SEL));
669 r100_pll_errata_after_index(rdev);
674 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
675 RADEON_VCLK_SRC_SEL_CPUCLK,
676 ~(RADEON_VCLK_SRC_SEL_MASK));
677 WREG32_PLL_P(RADEON_PPLL_CNTL,
679 | RADEON_PPLL_ATOMIC_UPDATE_EN
680 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
681 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
683 | RADEON_PPLL_ATOMIC_UPDATE_EN
684 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
685 | RADEON_PPLL_PVG_MASK));
687 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
689 ~(RADEON_PLL_DIV_SEL));
690 r100_pll_errata_after_index(rdev);
692 if (ASIC_IS_R300(rdev) ||
693 (rdev->family == CHIP_RS300) ||
694 (rdev->family == CHIP_RS400) ||
695 (rdev->family == CHIP_RS480)) {
696 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
697 /* When restoring console mode, use saved PPLL_REF_DIV
700 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
704 /* R300 uses ref_div_acc field as real ref divider */
705 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
706 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
707 ~R300_PPLL_REF_DIV_ACC_MASK);
710 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
712 ~RADEON_PPLL_REF_DIV_MASK);
714 WREG32_PLL_P(RADEON_PPLL_DIV_3,
716 ~RADEON_PPLL_FB3_DIV_MASK);
718 WREG32_PLL_P(RADEON_PPLL_DIV_3,
720 ~RADEON_PPLL_POST3_DIV_MASK);
722 radeon_pll_write_update(dev);
723 radeon_pll_wait_for_read_update_complete(dev);
725 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
727 WREG32_PLL_P(RADEON_PPLL_CNTL,
731 | RADEON_PPLL_ATOMIC_UPDATE_EN
732 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
734 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
737 (unsigned)htotal_cntl,
738 RREG32_PLL(RADEON_PPLL_CNTL));
739 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
740 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
741 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
742 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
744 mdelay(50); /* Let the clock to lock */
746 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
747 RADEON_VCLK_SRC_SEL_PPLLCLK,
748 ~(RADEON_VCLK_SRC_SEL_MASK));
753 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
754 struct drm_display_mode *mode,
755 struct drm_display_mode *adjusted_mode)
760 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
761 struct drm_display_mode *mode,
762 struct drm_display_mode *adjusted_mode,
763 int x, int y, struct drm_framebuffer *old_fb)
770 radeon_crtc_set_base(crtc, x, y, old_fb);
771 radeon_set_crtc_timing(crtc, adjusted_mode);
772 radeon_set_pll(crtc, adjusted_mode);
773 radeon_init_disp_bandwidth(crtc->dev);
778 static void radeon_crtc_prepare(struct drm_crtc *crtc)
780 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
783 static void radeon_crtc_commit(struct drm_crtc *crtc)
785 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
788 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
789 .dpms = radeon_crtc_dpms,
790 .mode_fixup = radeon_crtc_mode_fixup,
791 .mode_set = radeon_crtc_mode_set,
792 .mode_set_base = radeon_crtc_set_base,
793 .prepare = radeon_crtc_prepare,
794 .commit = radeon_crtc_commit,
798 void radeon_legacy_init_crtc(struct drm_device *dev,
799 struct radeon_crtc *radeon_crtc)
801 if (radeon_crtc->crtc_id == 1)
802 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
803 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
806 void radeon_init_disp_bw_legacy(struct drm_device *dev,
807 struct drm_display_mode *mode1,
808 uint32_t pixel_bytes1,
809 struct drm_display_mode *mode2,
810 uint32_t pixel_bytes2)
812 struct radeon_device *rdev = dev->dev_private;
813 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
814 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
815 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
816 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
817 fixed20_12 memtcas_ff[8] = {
826 fixed20_12 memtcas_rs480_ff[8] = {
836 fixed20_12 memtcas2_ff[8] = {
846 fixed20_12 memtrbs[8] = {
856 fixed20_12 memtrbs_r4xx[8] = {
866 fixed20_12 min_mem_eff;
867 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
868 fixed20_12 cur_latency_mclk, cur_latency_sclk;
869 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
870 disp_drain_rate2, read_return_rate;
871 fixed20_12 time_disp1_drop_priority;
873 int cur_size = 16; /* in octawords */
874 int critical_point = 0, critical_point2;
875 /* uint32_t read_return_rate, time_disp1_drop_priority; */
876 int stop_req, max_stop_req;
878 min_mem_eff.full = rfixed_const_8(0);
880 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
881 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
882 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
883 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
884 /* check crtc enables */
886 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
888 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
889 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
893 * determine is there is enough bw for current mode
895 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
896 temp_ff.full = rfixed_const(100);
897 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
898 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
899 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
901 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
902 temp_ff.full = rfixed_const(temp);
903 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
907 peak_disp_bw.full = 0;
909 temp_ff.full = rfixed_const(1000);
910 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
911 pix_clk.full = rfixed_div(pix_clk, temp_ff);
912 temp_ff.full = rfixed_const(pixel_bytes1);
913 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
916 temp_ff.full = rfixed_const(1000);
917 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
918 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
919 temp_ff.full = rfixed_const(pixel_bytes2);
920 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
923 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
924 if (peak_disp_bw.full >= mem_bw.full) {
925 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
926 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
929 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
930 temp = RREG32(RADEON_MEM_TIMING_CNTL);
931 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
932 mem_trcd = ((temp >> 2) & 0x3) + 1;
933 mem_trp = ((temp & 0x3)) + 1;
934 mem_tras = ((temp & 0x70) >> 4) + 1;
935 } else if (rdev->family == CHIP_R300 ||
936 rdev->family == CHIP_R350) { /* r300, r350 */
937 mem_trcd = (temp & 0x7) + 1;
938 mem_trp = ((temp >> 8) & 0x7) + 1;
939 mem_tras = ((temp >> 11) & 0xf) + 4;
940 } else if (rdev->family == CHIP_RV350 ||
941 rdev->family <= CHIP_RV380) {
943 mem_trcd = (temp & 0x7) + 3;
944 mem_trp = ((temp >> 8) & 0x7) + 3;
945 mem_tras = ((temp >> 11) & 0xf) + 6;
946 } else if (rdev->family == CHIP_R420 ||
947 rdev->family == CHIP_R423 ||
948 rdev->family == CHIP_RV410) {
950 mem_trcd = (temp & 0xf) + 3;
953 mem_trp = ((temp >> 8) & 0xf) + 3;
956 mem_tras = ((temp >> 12) & 0x1f) + 6;
959 } else { /* RV200, R200 */
960 mem_trcd = (temp & 0x7) + 1;
961 mem_trp = ((temp >> 8) & 0x7) + 1;
962 mem_tras = ((temp >> 12) & 0xf) + 4;
965 trcd_ff.full = rfixed_const(mem_trcd);
966 trp_ff.full = rfixed_const(mem_trp);
967 tras_ff.full = rfixed_const(mem_tras);
969 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
970 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
971 data = (temp & (7 << 20)) >> 20;
972 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
973 if (rdev->family == CHIP_RS480) /* don't think rs400 */
974 tcas_ff = memtcas_rs480_ff[data];
976 tcas_ff = memtcas_ff[data];
978 tcas_ff = memtcas2_ff[data];
980 if (rdev->family == CHIP_RS400 ||
981 rdev->family == CHIP_RS480) {
982 /* extra cas latency stored in bits 23-25 0-4 clocks */
983 data = (temp >> 23) & 0x7;
985 tcas_ff.full += rfixed_const(data);
988 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
989 /* on the R300, Tcas is included in Trbs.
991 temp = RREG32(RADEON_MEM_CNTL);
992 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
994 if (R300_MEM_USE_CD_CH_ONLY & temp) {
995 temp = RREG32(R300_MC_IND_INDEX);
996 temp &= ~R300_MC_IND_ADDR_MASK;
997 temp |= R300_MC_READ_CNTL_CD_mcind;
998 WREG32(R300_MC_IND_INDEX, temp);
999 temp = RREG32(R300_MC_IND_DATA);
1000 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
1002 temp = RREG32(R300_MC_READ_CNTL_AB);
1003 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
1006 temp = RREG32(R300_MC_READ_CNTL_AB);
1007 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
1009 if (rdev->family == CHIP_RV410 ||
1010 rdev->family == CHIP_R420 ||
1011 rdev->family == CHIP_R423)
1012 trbs_ff = memtrbs_r4xx[data];
1014 trbs_ff = memtrbs[data];
1015 tcas_ff.full += trbs_ff.full;
1018 sclk_eff_ff.full = sclk_ff.full;
1020 if (rdev->flags & RADEON_IS_AGP) {
1021 fixed20_12 agpmode_ff;
1022 agpmode_ff.full = rfixed_const(radeon_agpmode);
1023 temp_ff.full = rfixed_const_666(16);
1024 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
1026 /* TODO PCIE lanes may affect this - agpmode == 16?? */
1028 if (ASIC_IS_R300(rdev)) {
1029 sclk_delay_ff.full = rfixed_const(250);
1031 if ((rdev->family == CHIP_RV100) ||
1032 rdev->flags & RADEON_IS_IGP) {
1033 if (rdev->mc.vram_is_ddr)
1034 sclk_delay_ff.full = rfixed_const(41);
1036 sclk_delay_ff.full = rfixed_const(33);
1038 if (rdev->mc.vram_width == 128)
1039 sclk_delay_ff.full = rfixed_const(57);
1041 sclk_delay_ff.full = rfixed_const(41);
1045 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
1047 if (rdev->mc.vram_is_ddr) {
1048 if (rdev->mc.vram_width == 32) {
1049 k1.full = rfixed_const(40);
1052 k1.full = rfixed_const(20);
1056 k1.full = rfixed_const(40);
1060 temp_ff.full = rfixed_const(2);
1061 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
1062 temp_ff.full = rfixed_const(c);
1063 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
1064 temp_ff.full = rfixed_const(4);
1065 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
1066 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
1067 mc_latency_mclk.full += k1.full;
1069 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
1070 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
1073 HW cursor time assuming worst case of full size colour cursor.
1075 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
1076 temp_ff.full += trcd_ff.full;
1077 if (temp_ff.full < tras_ff.full)
1078 temp_ff.full = tras_ff.full;
1079 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
1081 temp_ff.full = rfixed_const(cur_size);
1082 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
1084 Find the total latency for the display data.
1086 disp_latency_overhead.full = rfixed_const(80);
1087 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
1088 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
1089 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
1091 if (mc_latency_mclk.full > mc_latency_sclk.full)
1092 disp_latency.full = mc_latency_mclk.full;
1094 disp_latency.full = mc_latency_sclk.full;
1096 /* setup Max GRPH_STOP_REQ default value */
1097 if (ASIC_IS_RV100(rdev))
1098 max_stop_req = 0x5c;
1100 max_stop_req = 0x7c;
1104 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
1105 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
1107 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
1109 if (stop_req > max_stop_req)
1110 stop_req = max_stop_req;
1113 Find the drain rate of the display buffer.
1115 temp_ff.full = rfixed_const((16/pixel_bytes1));
1116 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
1119 Find the critical point of the display buffer.
1121 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
1122 crit_point_ff.full += rfixed_const_half(0);
1124 critical_point = rfixed_trunc(crit_point_ff);
1126 if (rdev->disp_priority == 2) {
1131 The critical point should never be above max_stop_req-4. Setting
1132 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
1134 if (max_stop_req - critical_point < 4)
1137 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
1138 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
1139 critical_point = 0x10;
1142 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
1143 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
1144 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
1145 temp &= ~(RADEON_GRPH_START_REQ_MASK);
1146 if ((rdev->family == CHIP_R350) &&
1147 (stop_req > 0x15)) {
1150 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
1151 temp |= RADEON_GRPH_BUFFER_SIZE;
1152 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
1153 RADEON_GRPH_CRITICAL_AT_SOF |
1154 RADEON_GRPH_STOP_CNTL);
1156 Write the result into the register.
1158 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
1159 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
1162 if ((rdev->family == CHIP_RS400) ||
1163 (rdev->family == CHIP_RS480)) {
1164 /* attempt to program RS400 disp regs correctly ??? */
1165 temp = RREG32(RS400_DISP1_REG_CNTL);
1166 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
1167 RS400_DISP1_STOP_REQ_LEVEL_MASK);
1168 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
1169 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
1170 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
1171 temp = RREG32(RS400_DMIF_MEM_CNTL1);
1172 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
1173 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
1174 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
1175 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
1176 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
1180 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
1181 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
1182 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
1187 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
1189 if (stop_req > max_stop_req)
1190 stop_req = max_stop_req;
1193 Find the drain rate of the display buffer.
1195 temp_ff.full = rfixed_const((16/pixel_bytes2));
1196 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
1198 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
1199 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
1200 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
1201 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
1202 if ((rdev->family == CHIP_R350) &&
1203 (stop_req > 0x15)) {
1206 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
1207 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
1208 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
1209 RADEON_GRPH_CRITICAL_AT_SOF |
1210 RADEON_GRPH_STOP_CNTL);
1212 if ((rdev->family == CHIP_RS100) ||
1213 (rdev->family == CHIP_RS200))
1214 critical_point2 = 0;
1216 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
1217 temp_ff.full = rfixed_const(temp);
1218 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
1219 if (sclk_ff.full < temp_ff.full)
1220 temp_ff.full = sclk_ff.full;
1222 read_return_rate.full = temp_ff.full;
1225 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
1226 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
1228 time_disp1_drop_priority.full = 0;
1230 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
1231 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
1232 crit_point_ff.full += rfixed_const_half(0);
1234 critical_point2 = rfixed_trunc(crit_point_ff);
1236 if (rdev->disp_priority == 2) {
1237 critical_point2 = 0;
1240 if (max_stop_req - critical_point2 < 4)
1241 critical_point2 = 0;
1245 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
1246 /* some R300 cards have problem with this set to 0 */
1247 critical_point2 = 0x10;
1250 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
1251 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
1253 if ((rdev->family == CHIP_RS400) ||
1254 (rdev->family == CHIP_RS480)) {
1256 /* attempt to program RS400 disp2 regs correctly ??? */
1257 temp = RREG32(RS400_DISP2_REQ_CNTL1);
1258 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
1259 RS400_DISP2_STOP_REQ_LEVEL_MASK);
1260 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
1261 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
1262 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
1263 temp = RREG32(RS400_DISP2_REQ_CNTL2);
1264 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
1265 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
1266 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
1267 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
1268 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
1270 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
1271 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
1272 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
1273 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
1276 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
1277 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));