2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
62 if (clone_encoder == encoder)
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
69 index_mask |= (1 << count);
74 void radeon_setup_encoder_clones(struct drm_device *dev)
76 struct drm_encoder *encoder;
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
86 struct radeon_device *rdev = dev->dev_private;
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
180 radeon_link_encoder_connector(struct drm_device *dev)
182 struct drm_connector *connector;
183 struct radeon_connector *radeon_connector;
184 struct drm_encoder *encoder;
185 struct radeon_encoder *radeon_encoder;
187 /* walk the list and link encoders to connectors */
188 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
189 radeon_connector = to_radeon_connector(connector);
190 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
191 radeon_encoder = to_radeon_encoder(encoder);
192 if (radeon_encoder->devices & radeon_connector->devices)
193 drm_mode_connector_attach_encoder(connector, encoder);
198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 struct drm_device *dev = encoder->dev;
201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
202 struct drm_connector *connector;
204 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
205 if (connector->encoder == encoder) {
206 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
207 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
208 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
209 radeon_encoder->active_device, radeon_encoder->devices,
210 radeon_connector->devices, encoder->encoder_type);
215 struct drm_connector *
216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 struct drm_device *dev = encoder->dev;
219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220 struct drm_connector *connector;
221 struct radeon_connector *radeon_connector;
223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
224 radeon_connector = to_radeon_connector(connector);
225 if (radeon_encoder->active_device & radeon_connector->devices)
231 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
232 struct drm_display_mode *adjusted_mode)
234 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
235 struct drm_device *dev = encoder->dev;
236 struct radeon_device *rdev = dev->dev_private;
237 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
238 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
239 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
240 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
241 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
242 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
243 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
245 adjusted_mode->clock = native_mode->clock;
246 adjusted_mode->flags = native_mode->flags;
248 if (ASIC_IS_AVIVO(rdev)) {
249 adjusted_mode->hdisplay = native_mode->hdisplay;
250 adjusted_mode->vdisplay = native_mode->vdisplay;
253 adjusted_mode->htotal = native_mode->hdisplay + hblank;
254 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
255 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
257 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
258 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
259 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
261 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
263 if (ASIC_IS_AVIVO(rdev)) {
264 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
265 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
268 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
269 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
270 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
272 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
273 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
274 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
278 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
279 struct drm_display_mode *mode,
280 struct drm_display_mode *adjusted_mode)
282 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
283 struct drm_device *dev = encoder->dev;
284 struct radeon_device *rdev = dev->dev_private;
286 /* set the active encoder to connector routing */
287 radeon_encoder_set_active_device(encoder);
288 drm_mode_set_crtcinfo(adjusted_mode, 0);
291 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
292 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
293 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
295 /* get the native mode for LVDS */
296 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
297 radeon_panel_mode_fixup(encoder, adjusted_mode);
299 /* get the native mode for TV */
300 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
301 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
303 if (tv_dac->tv_std == TV_STD_NTSC ||
304 tv_dac->tv_std == TV_STD_NTSC_J ||
305 tv_dac->tv_std == TV_STD_PAL_M)
306 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
308 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
312 if (ASIC_IS_DCE3(rdev) &&
313 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
314 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
315 radeon_dp_set_link_config(connector, mode);
322 atombios_dac_setup(struct drm_encoder *encoder, int action)
324 struct drm_device *dev = encoder->dev;
325 struct radeon_device *rdev = dev->dev_private;
326 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
327 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
329 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
331 memset(&args, 0, sizeof(args));
333 switch (radeon_encoder->encoder_id) {
334 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
335 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
336 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
338 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
339 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
340 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
344 args.ucAction = action;
346 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
347 args.ucDacStandard = ATOM_DAC1_PS2;
348 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
349 args.ucDacStandard = ATOM_DAC1_CV;
351 switch (dac_info->tv_std) {
354 case TV_STD_SCART_PAL:
357 args.ucDacStandard = ATOM_DAC1_PAL;
363 args.ucDacStandard = ATOM_DAC1_NTSC;
367 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
369 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
374 atombios_tv_setup(struct drm_encoder *encoder, int action)
376 struct drm_device *dev = encoder->dev;
377 struct radeon_device *rdev = dev->dev_private;
378 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
379 TV_ENCODER_CONTROL_PS_ALLOCATION args;
381 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
383 memset(&args, 0, sizeof(args));
385 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
387 args.sTVEncoder.ucAction = action;
389 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
390 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
392 switch (dac_info->tv_std) {
394 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
397 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
400 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
403 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
406 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
408 case TV_STD_SCART_PAL:
409 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
412 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
415 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
418 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
423 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
425 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
430 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
432 struct drm_device *dev = encoder->dev;
433 struct radeon_device *rdev = dev->dev_private;
434 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
435 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
438 memset(&args, 0, sizeof(args));
440 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
442 args.sXTmdsEncoder.ucEnable = action;
444 if (radeon_encoder->pixel_clock > 165000)
445 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
447 /*if (pScrn->rgbBits == 8)*/
448 args.sXTmdsEncoder.ucMisc |= (1 << 1);
450 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
455 atombios_ddia_setup(struct drm_encoder *encoder, int action)
457 struct drm_device *dev = encoder->dev;
458 struct radeon_device *rdev = dev->dev_private;
459 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
460 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
463 memset(&args, 0, sizeof(args));
465 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
467 args.sDVOEncoder.ucAction = action;
468 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
470 if (radeon_encoder->pixel_clock > 165000)
471 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
473 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
477 union lvds_encoder_control {
478 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
479 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
483 atombios_digital_setup(struct drm_encoder *encoder, int action)
485 struct drm_device *dev = encoder->dev;
486 struct radeon_device *rdev = dev->dev_private;
487 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
488 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
489 union lvds_encoder_control args;
491 int hdmi_detected = 0;
497 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
500 memset(&args, 0, sizeof(args));
502 switch (radeon_encoder->encoder_id) {
503 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
504 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
506 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
507 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
508 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
510 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
511 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
512 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
514 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
518 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
527 args.v1.ucAction = action;
529 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
530 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
531 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
532 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
533 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
534 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
535 args.v1.ucMisc |= (1 << 1);
538 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
539 if (radeon_encoder->pixel_clock > 165000)
540 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
541 /*if (pScrn->rgbBits == 8) */
542 args.v1.ucMisc |= (1 << 1);
548 args.v2.ucAction = action;
550 if (dig->coherent_mode)
551 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
554 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
555 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
556 args.v2.ucTruncate = 0;
557 args.v2.ucSpatial = 0;
558 args.v2.ucTemporal = 0;
560 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
561 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
562 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
563 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
564 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
565 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
566 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
568 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
569 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
570 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
571 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
572 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
573 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
577 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
578 if (radeon_encoder->pixel_clock > 165000)
579 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
583 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
588 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
592 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
596 atombios_get_encoder_mode(struct drm_encoder *encoder)
598 struct drm_connector *connector;
599 struct radeon_connector *radeon_connector;
600 struct radeon_connector_atom_dig *dig_connector;
602 connector = radeon_get_connector_for_encoder(encoder);
606 radeon_connector = to_radeon_connector(connector);
608 switch (connector->connector_type) {
609 case DRM_MODE_CONNECTOR_DVII:
610 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
611 if (drm_detect_hdmi_monitor(radeon_connector->edid))
612 return ATOM_ENCODER_MODE_HDMI;
613 else if (radeon_connector->use_digital)
614 return ATOM_ENCODER_MODE_DVI;
616 return ATOM_ENCODER_MODE_CRT;
618 case DRM_MODE_CONNECTOR_DVID:
619 case DRM_MODE_CONNECTOR_HDMIA:
621 if (drm_detect_hdmi_monitor(radeon_connector->edid))
622 return ATOM_ENCODER_MODE_HDMI;
624 return ATOM_ENCODER_MODE_DVI;
626 case DRM_MODE_CONNECTOR_LVDS:
627 return ATOM_ENCODER_MODE_LVDS;
629 case DRM_MODE_CONNECTOR_DisplayPort:
630 case DRM_MODE_CONNECTOR_eDP:
631 dig_connector = radeon_connector->con_priv;
632 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
633 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
634 return ATOM_ENCODER_MODE_DP;
635 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
636 return ATOM_ENCODER_MODE_HDMI;
638 return ATOM_ENCODER_MODE_DVI;
640 case DRM_MODE_CONNECTOR_DVIA:
641 case DRM_MODE_CONNECTOR_VGA:
642 return ATOM_ENCODER_MODE_CRT;
644 case DRM_MODE_CONNECTOR_Composite:
645 case DRM_MODE_CONNECTOR_SVIDEO:
646 case DRM_MODE_CONNECTOR_9PinDIN:
648 return ATOM_ENCODER_MODE_TV;
649 /*return ATOM_ENCODER_MODE_CV;*/
655 * DIG Encoder/Transmitter Setup
658 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
659 * Supports up to 3 digital outputs
660 * - 2 DIG encoder blocks.
661 * DIG1 can drive UNIPHY link A or link B
662 * DIG2 can drive UNIPHY link B or LVTMA
665 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
666 * Supports up to 5 digital outputs
667 * - 2 DIG encoder blocks.
668 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
671 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
672 * Supports up to 6 digital outputs
673 * - 6 DIG encoder blocks.
674 * - DIG to PHY mapping is hardcoded
675 * DIG1 drives UNIPHY0 link A, A+B
676 * DIG2 drives UNIPHY0 link B
677 * DIG3 drives UNIPHY1 link A, A+B
678 * DIG4 drives UNIPHY1 link B
679 * DIG5 drives UNIPHY2 link A, A+B
680 * DIG6 drives UNIPHY2 link B
683 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
685 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
686 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
687 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
688 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
691 union dig_encoder_control {
692 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
693 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
694 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
698 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
700 struct drm_device *dev = encoder->dev;
701 struct radeon_device *rdev = dev->dev_private;
702 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
703 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
704 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
705 union dig_encoder_control args;
709 int dp_lane_count = 0;
712 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
713 struct radeon_connector_atom_dig *dig_connector =
714 radeon_connector->con_priv;
716 dp_clock = dig_connector->dp_clock;
717 dp_lane_count = dig_connector->dp_lane_count;
720 /* no dig encoder assigned */
721 if (dig->dig_encoder == -1)
724 memset(&args, 0, sizeof(args));
726 if (ASIC_IS_DCE4(rdev))
727 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
729 if (dig->dig_encoder)
730 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
732 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
735 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
738 args.v1.ucAction = action;
739 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
740 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
742 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
743 if (dp_clock == 270000)
744 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
745 args.v1.ucLaneNum = dp_lane_count;
746 } else if (radeon_encoder->pixel_clock > 165000)
747 args.v1.ucLaneNum = 8;
749 args.v1.ucLaneNum = 4;
751 if (ASIC_IS_DCE4(rdev)) {
752 args.v3.acConfig.ucDigSel = dig->dig_encoder;
753 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
755 switch (radeon_encoder->encoder_id) {
756 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
757 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
759 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
760 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
761 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
763 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
764 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
768 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
770 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
773 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
777 union dig_transmitter_control {
778 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
779 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
780 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
784 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
786 struct drm_device *dev = encoder->dev;
787 struct radeon_device *rdev = dev->dev_private;
788 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
789 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
790 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
791 union dig_transmitter_control args;
797 int dp_lane_count = 0;
798 int connector_object_id = 0;
799 int igp_lane_info = 0;
802 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
803 struct radeon_connector_atom_dig *dig_connector =
804 radeon_connector->con_priv;
806 dp_clock = dig_connector->dp_clock;
807 dp_lane_count = dig_connector->dp_lane_count;
808 connector_object_id =
809 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
810 igp_lane_info = dig_connector->igp_lane_info;
813 /* no dig encoder assigned */
814 if (dig->dig_encoder == -1)
817 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
820 memset(&args, 0, sizeof(args));
822 switch (radeon_encoder->encoder_id) {
823 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
824 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
825 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
826 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
828 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
829 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
833 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
836 args.v1.ucAction = action;
837 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
838 args.v1.usInitInfo = connector_object_id;
839 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
840 args.v1.asMode.ucLaneSel = lane_num;
841 args.v1.asMode.ucLaneSet = lane_set;
844 args.v1.usPixelClock =
845 cpu_to_le16(dp_clock / 10);
846 else if (radeon_encoder->pixel_clock > 165000)
847 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
849 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
851 if (ASIC_IS_DCE4(rdev)) {
853 args.v3.ucLaneNum = dp_lane_count;
854 else if (radeon_encoder->pixel_clock > 165000)
855 args.v3.ucLaneNum = 8;
857 args.v3.ucLaneNum = 4;
860 args.v3.acConfig.ucLinkSel = 1;
861 args.v3.acConfig.ucEncoderSel = 1;
864 /* Select the PLL for the PHY
865 * DP PHY should be clocked from external src if there is
869 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
870 pll_id = radeon_crtc->pll_id;
872 if (is_dp && rdev->clock.dp_extclk)
873 args.v3.acConfig.ucRefClkSource = 2; /* external src */
875 args.v3.acConfig.ucRefClkSource = pll_id;
877 switch (radeon_encoder->encoder_id) {
878 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
879 args.v3.acConfig.ucTransmitterSel = 0;
881 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
882 args.v3.acConfig.ucTransmitterSel = 1;
884 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
885 args.v3.acConfig.ucTransmitterSel = 2;
890 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
891 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
892 if (dig->coherent_mode)
893 args.v3.acConfig.fCoherentMode = 1;
894 if (radeon_encoder->pixel_clock > 165000)
895 args.v3.acConfig.fDualLinkConnector = 1;
897 } else if (ASIC_IS_DCE32(rdev)) {
898 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
900 args.v2.acConfig.ucLinkSel = 1;
902 switch (radeon_encoder->encoder_id) {
903 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
904 args.v2.acConfig.ucTransmitterSel = 0;
906 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
907 args.v2.acConfig.ucTransmitterSel = 1;
909 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
910 args.v2.acConfig.ucTransmitterSel = 2;
915 args.v2.acConfig.fCoherentMode = 1;
916 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
917 if (dig->coherent_mode)
918 args.v2.acConfig.fCoherentMode = 1;
919 if (radeon_encoder->pixel_clock > 165000)
920 args.v2.acConfig.fDualLinkConnector = 1;
923 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
925 if (dig->dig_encoder)
926 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
928 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
930 if ((rdev->flags & RADEON_IS_IGP) &&
931 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
932 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
933 if (igp_lane_info & 0x1)
934 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
935 else if (igp_lane_info & 0x2)
936 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
937 else if (igp_lane_info & 0x4)
938 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
939 else if (igp_lane_info & 0x8)
940 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
942 if (igp_lane_info & 0x3)
943 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
944 else if (igp_lane_info & 0xc)
945 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
950 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
952 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
955 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
956 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
957 if (dig->coherent_mode)
958 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
959 if (radeon_encoder->pixel_clock > 165000)
960 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
964 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
968 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
970 struct drm_device *dev = encoder->dev;
971 struct radeon_device *rdev = dev->dev_private;
972 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
973 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
974 ENABLE_YUV_PS_ALLOCATION args;
975 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
978 memset(&args, 0, sizeof(args));
980 if (rdev->family >= CHIP_R600)
981 reg = R600_BIOS_3_SCRATCH;
983 reg = RADEON_BIOS_3_SCRATCH;
985 /* XXX: fix up scratch reg handling */
987 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
988 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
989 (radeon_crtc->crtc_id << 18)));
990 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
991 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
996 args.ucEnable = ATOM_ENABLE;
997 args.ucCRTC = radeon_crtc->crtc_id;
999 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1005 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1007 struct drm_device *dev = encoder->dev;
1008 struct radeon_device *rdev = dev->dev_private;
1009 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1010 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1012 bool is_dig = false;
1014 memset(&args, 0, sizeof(args));
1016 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1017 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1018 radeon_encoder->active_device);
1019 switch (radeon_encoder->encoder_id) {
1020 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1021 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1022 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1024 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1025 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1026 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1027 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1030 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1031 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1032 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1033 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1035 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1036 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1038 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1039 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1040 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1042 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1044 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1045 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1046 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1047 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1048 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1049 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1051 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1053 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1054 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1055 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1056 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1057 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1058 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1060 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1066 case DRM_MODE_DPMS_ON:
1067 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1068 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1069 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1071 dp_link_train(encoder, connector);
1072 if (ASIC_IS_DCE4(rdev))
1073 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1076 case DRM_MODE_DPMS_STANDBY:
1077 case DRM_MODE_DPMS_SUSPEND:
1078 case DRM_MODE_DPMS_OFF:
1079 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1080 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1081 if (ASIC_IS_DCE4(rdev))
1082 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1088 case DRM_MODE_DPMS_ON:
1089 args.ucAction = ATOM_ENABLE;
1091 case DRM_MODE_DPMS_STANDBY:
1092 case DRM_MODE_DPMS_SUSPEND:
1093 case DRM_MODE_DPMS_OFF:
1094 args.ucAction = ATOM_DISABLE;
1097 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1099 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1103 union crtc_source_param {
1104 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1105 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1109 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1111 struct drm_device *dev = encoder->dev;
1112 struct radeon_device *rdev = dev->dev_private;
1113 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1114 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1115 union crtc_source_param args;
1116 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1118 struct radeon_encoder_atom_dig *dig;
1120 memset(&args, 0, sizeof(args));
1122 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1130 if (ASIC_IS_AVIVO(rdev))
1131 args.v1.ucCRTC = radeon_crtc->crtc_id;
1133 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1134 args.v1.ucCRTC = radeon_crtc->crtc_id;
1136 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1139 switch (radeon_encoder->encoder_id) {
1140 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1141 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1142 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1144 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1145 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1146 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1147 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1149 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1151 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1152 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1153 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1154 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1156 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1157 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1158 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1159 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1160 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1161 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1163 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1165 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1166 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1167 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1168 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1169 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1170 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1172 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1177 args.v2.ucCRTC = radeon_crtc->crtc_id;
1178 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1179 switch (radeon_encoder->encoder_id) {
1180 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1181 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1182 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1183 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1184 dig = radeon_encoder->enc_priv;
1185 switch (dig->dig_encoder) {
1187 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1190 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1193 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1196 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1199 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1202 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1206 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1207 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1209 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1210 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1211 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1212 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1213 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1215 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1217 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1218 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1219 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1220 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1221 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1223 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1230 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1234 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1236 /* update scratch regs with new routing */
1237 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1241 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1242 struct drm_display_mode *mode)
1244 struct drm_device *dev = encoder->dev;
1245 struct radeon_device *rdev = dev->dev_private;
1246 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1247 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1249 /* Funky macbooks */
1250 if ((dev->pdev->device == 0x71C5) &&
1251 (dev->pdev->subsystem_vendor == 0x106b) &&
1252 (dev->pdev->subsystem_device == 0x0080)) {
1253 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1254 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1256 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1257 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1259 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1263 /* set scaler clears this on some chips */
1264 /* XXX check DCE4 */
1265 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1266 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1267 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1268 AVIVO_D1MODE_INTERLEAVE_EN);
1272 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1274 struct drm_device *dev = encoder->dev;
1275 struct radeon_device *rdev = dev->dev_private;
1276 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1277 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1278 struct drm_encoder *test_encoder;
1279 struct radeon_encoder_atom_dig *dig;
1280 uint32_t dig_enc_in_use = 0;
1282 if (ASIC_IS_DCE4(rdev)) {
1283 dig = radeon_encoder->enc_priv;
1284 switch (radeon_encoder->encoder_id) {
1285 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1291 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1306 /* on DCE32 and encoder can driver any block so just crtc id */
1307 if (ASIC_IS_DCE32(rdev)) {
1308 return radeon_crtc->crtc_id;
1311 /* on DCE3 - LVTMA can only be driven by DIGB */
1312 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1313 struct radeon_encoder *radeon_test_encoder;
1315 if (encoder == test_encoder)
1318 if (!radeon_encoder_is_digital(test_encoder))
1321 radeon_test_encoder = to_radeon_encoder(test_encoder);
1322 dig = radeon_test_encoder->enc_priv;
1324 if (dig->dig_encoder >= 0)
1325 dig_enc_in_use |= (1 << dig->dig_encoder);
1328 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1329 if (dig_enc_in_use & 0x2)
1330 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1333 if (!(dig_enc_in_use & 1))
1339 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1340 struct drm_display_mode *mode,
1341 struct drm_display_mode *adjusted_mode)
1343 struct drm_device *dev = encoder->dev;
1344 struct radeon_device *rdev = dev->dev_private;
1345 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1347 radeon_encoder->pixel_clock = adjusted_mode->clock;
1349 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1350 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1351 atombios_yuv_setup(encoder, true);
1353 atombios_yuv_setup(encoder, false);
1356 switch (radeon_encoder->encoder_id) {
1357 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1358 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1359 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1360 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1361 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1363 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1364 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1365 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1366 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1367 if (ASIC_IS_DCE4(rdev)) {
1368 /* disable the transmitter */
1369 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1370 /* setup and enable the encoder */
1371 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1373 /* init and enable the transmitter */
1374 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1375 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1377 /* disable the encoder and transmitter */
1378 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1379 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1381 /* setup and enable the encoder and transmitter */
1382 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1383 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1384 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1385 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1388 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1389 atombios_ddia_setup(encoder, ATOM_ENABLE);
1391 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1392 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1393 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1395 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1396 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1397 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1398 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1399 atombios_dac_setup(encoder, ATOM_ENABLE);
1400 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1401 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1402 atombios_tv_setup(encoder, ATOM_ENABLE);
1404 atombios_tv_setup(encoder, ATOM_DISABLE);
1408 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1410 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1411 r600_hdmi_enable(encoder);
1412 r600_hdmi_setmode(encoder, adjusted_mode);
1417 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1419 struct drm_device *dev = encoder->dev;
1420 struct radeon_device *rdev = dev->dev_private;
1421 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1422 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1424 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1425 ATOM_DEVICE_CV_SUPPORT |
1426 ATOM_DEVICE_CRT_SUPPORT)) {
1427 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1428 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1431 memset(&args, 0, sizeof(args));
1433 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1436 args.sDacload.ucMisc = 0;
1438 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1439 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1440 args.sDacload.ucDacType = ATOM_DAC_A;
1442 args.sDacload.ucDacType = ATOM_DAC_B;
1444 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1445 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1446 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1447 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1448 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1449 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1451 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1452 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1453 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1455 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1458 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1465 static enum drm_connector_status
1466 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1468 struct drm_device *dev = encoder->dev;
1469 struct radeon_device *rdev = dev->dev_private;
1470 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1471 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1472 uint32_t bios_0_scratch;
1474 if (!atombios_dac_load_detect(encoder, connector)) {
1475 DRM_DEBUG_KMS("detect returned false \n");
1476 return connector_status_unknown;
1479 if (rdev->family >= CHIP_R600)
1480 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1482 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1484 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1485 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1486 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1487 return connector_status_connected;
1489 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1490 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1491 return connector_status_connected;
1493 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1494 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1495 return connector_status_connected;
1497 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1498 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1499 return connector_status_connected; /* CTV */
1500 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1501 return connector_status_connected; /* STV */
1503 return connector_status_disconnected;
1506 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1508 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1510 if (radeon_encoder->active_device &
1511 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1512 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1514 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1517 radeon_atom_output_lock(encoder, true);
1518 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1520 /* this is needed for the pll/ss setup to work correctly in some cases */
1521 atombios_set_encoder_crtc_source(encoder);
1524 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1526 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1527 radeon_atom_output_lock(encoder, false);
1530 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1532 struct drm_device *dev = encoder->dev;
1533 struct radeon_device *rdev = dev->dev_private;
1534 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1535 struct radeon_encoder_atom_dig *dig;
1536 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1538 switch (radeon_encoder->encoder_id) {
1539 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1540 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1541 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1542 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1543 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1545 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1546 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1547 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1548 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1549 if (ASIC_IS_DCE4(rdev))
1550 /* disable the transmitter */
1551 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1553 /* disable the encoder and transmitter */
1554 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1555 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1558 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1559 atombios_ddia_setup(encoder, ATOM_DISABLE);
1561 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1563 atombios_external_tmds_setup(encoder, ATOM_DISABLE);
1565 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1566 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1567 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1568 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1569 atombios_dac_setup(encoder, ATOM_DISABLE);
1570 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1571 atombios_tv_setup(encoder, ATOM_DISABLE);
1575 if (radeon_encoder_is_digital(encoder)) {
1576 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1577 r600_hdmi_disable(encoder);
1578 dig = radeon_encoder->enc_priv;
1579 dig->dig_encoder = -1;
1581 radeon_encoder->active_device = 0;
1584 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1585 .dpms = radeon_atom_encoder_dpms,
1586 .mode_fixup = radeon_atom_mode_fixup,
1587 .prepare = radeon_atom_encoder_prepare,
1588 .mode_set = radeon_atom_encoder_mode_set,
1589 .commit = radeon_atom_encoder_commit,
1590 .disable = radeon_atom_encoder_disable,
1591 /* no detect for TMDS/LVDS yet */
1594 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1595 .dpms = radeon_atom_encoder_dpms,
1596 .mode_fixup = radeon_atom_mode_fixup,
1597 .prepare = radeon_atom_encoder_prepare,
1598 .mode_set = radeon_atom_encoder_mode_set,
1599 .commit = radeon_atom_encoder_commit,
1600 .detect = radeon_atom_dac_detect,
1603 void radeon_enc_destroy(struct drm_encoder *encoder)
1605 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1606 kfree(radeon_encoder->enc_priv);
1607 drm_encoder_cleanup(encoder);
1608 kfree(radeon_encoder);
1611 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1612 .destroy = radeon_enc_destroy,
1615 struct radeon_encoder_atom_dac *
1616 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1618 struct drm_device *dev = radeon_encoder->base.dev;
1619 struct radeon_device *rdev = dev->dev_private;
1620 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1625 dac->tv_std = radeon_atombios_get_tv_info(rdev);
1629 struct radeon_encoder_atom_dig *
1630 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1632 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1633 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1638 /* coherent mode by default */
1639 dig->coherent_mode = true;
1640 dig->dig_encoder = -1;
1642 if (encoder_enum == 2)
1651 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1653 struct radeon_device *rdev = dev->dev_private;
1654 struct drm_encoder *encoder;
1655 struct radeon_encoder *radeon_encoder;
1657 /* see if we already added it */
1658 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1659 radeon_encoder = to_radeon_encoder(encoder);
1660 if (radeon_encoder->encoder_enum == encoder_enum) {
1661 radeon_encoder->devices |= supported_device;
1668 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1669 if (!radeon_encoder)
1672 encoder = &radeon_encoder->base;
1673 switch (rdev->num_crtc) {
1675 encoder->possible_crtcs = 0x1;
1679 encoder->possible_crtcs = 0x3;
1682 encoder->possible_crtcs = 0x3f;
1686 radeon_encoder->enc_priv = NULL;
1688 radeon_encoder->encoder_enum = encoder_enum;
1689 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1690 radeon_encoder->devices = supported_device;
1691 radeon_encoder->rmx_type = RMX_OFF;
1692 radeon_encoder->underscan_type = UNDERSCAN_OFF;
1694 switch (radeon_encoder->encoder_id) {
1695 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1696 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1697 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1698 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1699 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1700 radeon_encoder->rmx_type = RMX_FULL;
1701 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1702 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1704 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1705 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1706 if (ASIC_IS_AVIVO(rdev))
1707 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1709 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1711 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1712 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1713 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1714 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1716 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1717 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1718 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1719 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1720 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1721 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1723 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1724 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1725 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1726 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1727 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1728 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1729 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1730 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1731 radeon_encoder->rmx_type = RMX_FULL;
1732 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1733 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1735 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1736 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1737 if (ASIC_IS_AVIVO(rdev))
1738 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1740 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);