2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
62 if (clone_encoder == encoder)
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
69 index_mask |= (1 << count);
74 void radeon_setup_encoder_clones(struct drm_device *dev)
76 struct drm_encoder *encoder;
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
86 struct radeon_device *rdev = dev->dev_private;
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
181 radeon_link_encoder_connector(struct drm_device *dev)
183 struct drm_connector *connector;
184 struct radeon_connector *radeon_connector;
185 struct drm_encoder *encoder;
186 struct radeon_encoder *radeon_encoder;
188 /* walk the list and link encoders to connectors */
189 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
190 radeon_connector = to_radeon_connector(connector);
191 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
192 radeon_encoder = to_radeon_encoder(encoder);
193 if (radeon_encoder->devices & radeon_connector->devices)
194 drm_mode_connector_attach_encoder(connector, encoder);
199 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
201 struct drm_device *dev = encoder->dev;
202 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
203 struct drm_connector *connector;
205 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
206 if (connector->encoder == encoder) {
207 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
208 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
209 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
210 radeon_encoder->active_device, radeon_encoder->devices,
211 radeon_connector->devices, encoder->encoder_type);
216 struct drm_connector *
217 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
219 struct drm_device *dev = encoder->dev;
220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
221 struct drm_connector *connector;
222 struct radeon_connector *radeon_connector;
224 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
225 radeon_connector = to_radeon_connector(connector);
226 if (radeon_encoder->active_device & radeon_connector->devices)
232 static struct drm_connector *
233 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
235 struct drm_device *dev = encoder->dev;
236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
237 struct drm_connector *connector;
238 struct radeon_connector *radeon_connector;
240 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
241 radeon_connector = to_radeon_connector(connector);
242 if (radeon_encoder->devices & radeon_connector->devices)
248 struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
250 struct drm_device *dev = encoder->dev;
251 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
252 struct drm_encoder *other_encoder;
253 struct radeon_encoder *other_radeon_encoder;
255 if (radeon_encoder->is_ext_encoder)
258 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
259 if (other_encoder == encoder)
261 other_radeon_encoder = to_radeon_encoder(other_encoder);
262 if (other_radeon_encoder->is_ext_encoder &&
263 (radeon_encoder->devices & other_radeon_encoder->devices))
264 return other_encoder;
269 bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder)
271 struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder);
274 struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
276 switch (radeon_encoder->encoder_id) {
277 case ENCODER_OBJECT_ID_TRAVIS:
278 case ENCODER_OBJECT_ID_NUTMEG:
288 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
289 struct drm_display_mode *adjusted_mode)
291 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
292 struct drm_device *dev = encoder->dev;
293 struct radeon_device *rdev = dev->dev_private;
294 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
295 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
296 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
297 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
298 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
299 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
300 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
302 adjusted_mode->clock = native_mode->clock;
303 adjusted_mode->flags = native_mode->flags;
305 if (ASIC_IS_AVIVO(rdev)) {
306 adjusted_mode->hdisplay = native_mode->hdisplay;
307 adjusted_mode->vdisplay = native_mode->vdisplay;
310 adjusted_mode->htotal = native_mode->hdisplay + hblank;
311 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
312 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
314 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
315 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
316 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
318 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
320 if (ASIC_IS_AVIVO(rdev)) {
321 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
322 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
325 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
326 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
327 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
329 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
330 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
331 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
335 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
336 struct drm_display_mode *mode,
337 struct drm_display_mode *adjusted_mode)
339 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
340 struct drm_device *dev = encoder->dev;
341 struct radeon_device *rdev = dev->dev_private;
343 /* set the active encoder to connector routing */
344 radeon_encoder_set_active_device(encoder);
345 drm_mode_set_crtcinfo(adjusted_mode, 0);
348 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
349 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
350 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
352 /* get the native mode for LVDS */
353 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
354 radeon_panel_mode_fixup(encoder, adjusted_mode);
356 /* get the native mode for TV */
357 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
358 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
360 if (tv_dac->tv_std == TV_STD_NTSC ||
361 tv_dac->tv_std == TV_STD_NTSC_J ||
362 tv_dac->tv_std == TV_STD_PAL_M)
363 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
365 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
369 if (ASIC_IS_DCE3(rdev) &&
370 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
371 radeon_encoder_is_dp_bridge(encoder))) {
372 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
373 radeon_dp_set_link_config(connector, mode);
380 atombios_dac_setup(struct drm_encoder *encoder, int action)
382 struct drm_device *dev = encoder->dev;
383 struct radeon_device *rdev = dev->dev_private;
384 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
385 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
387 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
389 memset(&args, 0, sizeof(args));
391 switch (radeon_encoder->encoder_id) {
392 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
393 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
394 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
396 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
397 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
398 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
402 args.ucAction = action;
404 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
405 args.ucDacStandard = ATOM_DAC1_PS2;
406 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
407 args.ucDacStandard = ATOM_DAC1_CV;
409 switch (dac_info->tv_std) {
412 case TV_STD_SCART_PAL:
415 args.ucDacStandard = ATOM_DAC1_PAL;
421 args.ucDacStandard = ATOM_DAC1_NTSC;
425 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
427 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
432 atombios_tv_setup(struct drm_encoder *encoder, int action)
434 struct drm_device *dev = encoder->dev;
435 struct radeon_device *rdev = dev->dev_private;
436 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
437 TV_ENCODER_CONTROL_PS_ALLOCATION args;
439 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
441 memset(&args, 0, sizeof(args));
443 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
445 args.sTVEncoder.ucAction = action;
447 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
448 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
450 switch (dac_info->tv_std) {
452 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
455 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
458 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
461 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
464 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
466 case TV_STD_SCART_PAL:
467 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
470 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
473 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
476 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
481 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
483 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
487 union dvo_encoder_control {
488 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
489 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
490 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
494 atombios_dvo_setup(struct drm_encoder *encoder, int action)
496 struct drm_device *dev = encoder->dev;
497 struct radeon_device *rdev = dev->dev_private;
498 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
499 union dvo_encoder_control args;
500 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
502 memset(&args, 0, sizeof(args));
504 if (ASIC_IS_DCE3(rdev)) {
506 args.dvo_v3.ucAction = action;
507 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
508 args.dvo_v3.ucDVOConfig = 0; /* XXX */
509 } else if (ASIC_IS_DCE2(rdev)) {
510 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
511 args.dvo.sDVOEncoder.ucAction = action;
512 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
513 /* DFP1, CRT1, TV1 depending on the type of port */
514 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
516 if (radeon_encoder->pixel_clock > 165000)
517 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
520 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
522 if (radeon_encoder->pixel_clock > 165000)
523 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
525 /*if (pScrn->rgbBits == 8)*/
526 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
529 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
532 union lvds_encoder_control {
533 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
534 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
538 atombios_digital_setup(struct drm_encoder *encoder, int action)
540 struct drm_device *dev = encoder->dev;
541 struct radeon_device *rdev = dev->dev_private;
542 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
543 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
544 union lvds_encoder_control args;
546 int hdmi_detected = 0;
552 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
555 memset(&args, 0, sizeof(args));
557 switch (radeon_encoder->encoder_id) {
558 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
559 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
561 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
563 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
565 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
566 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
567 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
569 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
573 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
582 args.v1.ucAction = action;
584 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
585 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
586 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
587 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
588 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
589 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
590 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
593 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
594 if (radeon_encoder->pixel_clock > 165000)
595 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
596 /*if (pScrn->rgbBits == 8) */
597 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
603 args.v2.ucAction = action;
605 if (dig->coherent_mode)
606 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
609 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
610 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
611 args.v2.ucTruncate = 0;
612 args.v2.ucSpatial = 0;
613 args.v2.ucTemporal = 0;
615 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
616 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
617 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
618 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
619 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
620 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
621 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
623 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
624 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
625 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
626 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
627 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
628 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
632 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
633 if (radeon_encoder->pixel_clock > 165000)
634 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
638 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
643 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
647 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
651 atombios_get_encoder_mode(struct drm_encoder *encoder)
653 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
654 struct drm_device *dev = encoder->dev;
655 struct radeon_device *rdev = dev->dev_private;
656 struct drm_connector *connector;
657 struct radeon_connector *radeon_connector;
658 struct radeon_connector_atom_dig *dig_connector;
660 /* dp bridges are always DP */
661 if (radeon_encoder_is_dp_bridge(encoder))
662 return ATOM_ENCODER_MODE_DP;
664 /* DVO is always DVO */
665 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
666 return ATOM_ENCODER_MODE_DVO;
668 connector = radeon_get_connector_for_encoder(encoder);
669 /* if we don't have an active device yet, just use one of
670 * the connectors tied to the encoder.
673 connector = radeon_get_connector_for_encoder_init(encoder);
674 radeon_connector = to_radeon_connector(connector);
676 switch (connector->connector_type) {
677 case DRM_MODE_CONNECTOR_DVII:
678 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
679 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
681 if (ASIC_IS_DCE4(rdev))
682 return ATOM_ENCODER_MODE_DVI;
684 return ATOM_ENCODER_MODE_HDMI;
685 } else if (radeon_connector->use_digital)
686 return ATOM_ENCODER_MODE_DVI;
688 return ATOM_ENCODER_MODE_CRT;
690 case DRM_MODE_CONNECTOR_DVID:
691 case DRM_MODE_CONNECTOR_HDMIA:
693 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
695 if (ASIC_IS_DCE4(rdev))
696 return ATOM_ENCODER_MODE_DVI;
698 return ATOM_ENCODER_MODE_HDMI;
700 return ATOM_ENCODER_MODE_DVI;
702 case DRM_MODE_CONNECTOR_LVDS:
703 return ATOM_ENCODER_MODE_LVDS;
705 case DRM_MODE_CONNECTOR_DisplayPort:
706 dig_connector = radeon_connector->con_priv;
707 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
708 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
709 return ATOM_ENCODER_MODE_DP;
710 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
712 if (ASIC_IS_DCE4(rdev))
713 return ATOM_ENCODER_MODE_DVI;
715 return ATOM_ENCODER_MODE_HDMI;
717 return ATOM_ENCODER_MODE_DVI;
719 case DRM_MODE_CONNECTOR_eDP:
720 return ATOM_ENCODER_MODE_DP;
721 case DRM_MODE_CONNECTOR_DVIA:
722 case DRM_MODE_CONNECTOR_VGA:
723 return ATOM_ENCODER_MODE_CRT;
725 case DRM_MODE_CONNECTOR_Composite:
726 case DRM_MODE_CONNECTOR_SVIDEO:
727 case DRM_MODE_CONNECTOR_9PinDIN:
729 return ATOM_ENCODER_MODE_TV;
730 /*return ATOM_ENCODER_MODE_CV;*/
736 * DIG Encoder/Transmitter Setup
739 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
740 * Supports up to 3 digital outputs
741 * - 2 DIG encoder blocks.
742 * DIG1 can drive UNIPHY link A or link B
743 * DIG2 can drive UNIPHY link B or LVTMA
746 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
747 * Supports up to 5 digital outputs
748 * - 2 DIG encoder blocks.
749 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
752 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
753 * Supports up to 6 digital outputs
754 * - 6 DIG encoder blocks.
755 * - DIG to PHY mapping is hardcoded
756 * DIG1 drives UNIPHY0 link A, A+B
757 * DIG2 drives UNIPHY0 link B
758 * DIG3 drives UNIPHY1 link A, A+B
759 * DIG4 drives UNIPHY1 link B
760 * DIG5 drives UNIPHY2 link A, A+B
761 * DIG6 drives UNIPHY2 link B
764 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
765 * Supports up to 6 digital outputs
766 * - 2 DIG encoder blocks.
767 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
770 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
772 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
773 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
774 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
775 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
778 union dig_encoder_control {
779 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
780 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
781 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
782 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
786 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
788 struct drm_device *dev = encoder->dev;
789 struct radeon_device *rdev = dev->dev_private;
790 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
791 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
792 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
793 union dig_encoder_control args;
797 int dp_lane_count = 0;
798 int hpd_id = RADEON_HPD_NONE;
802 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
803 struct radeon_connector_atom_dig *dig_connector =
804 radeon_connector->con_priv;
806 dp_clock = dig_connector->dp_clock;
807 dp_lane_count = dig_connector->dp_lane_count;
808 hpd_id = radeon_connector->hpd.hpd;
809 bpc = connector->display_info.bpc;
812 /* no dig encoder assigned */
813 if (dig->dig_encoder == -1)
816 memset(&args, 0, sizeof(args));
818 if (ASIC_IS_DCE4(rdev))
819 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
821 if (dig->dig_encoder)
822 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
824 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
827 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
830 args.v1.ucAction = action;
831 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
832 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
833 args.v3.ucPanelMode = panel_mode;
835 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
837 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
838 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
839 args.v1.ucLaneNum = dp_lane_count;
840 else if (radeon_encoder->pixel_clock > 165000)
841 args.v1.ucLaneNum = 8;
843 args.v1.ucLaneNum = 4;
845 if (ASIC_IS_DCE5(rdev)) {
846 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
847 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
848 if (dp_clock == 270000)
849 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
850 else if (dp_clock == 540000)
851 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
853 args.v4.acConfig.ucDigSel = dig->dig_encoder;
856 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
859 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
863 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
866 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
869 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
872 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
875 if (hpd_id == RADEON_HPD_NONE)
876 args.v4.ucHPD_ID = 0;
878 args.v4.ucHPD_ID = hpd_id + 1;
879 } else if (ASIC_IS_DCE4(rdev)) {
880 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
881 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
882 args.v3.acConfig.ucDigSel = dig->dig_encoder;
885 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
888 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
892 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
895 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
898 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
901 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
905 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
906 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
907 switch (radeon_encoder->encoder_id) {
908 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
909 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
911 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
912 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
913 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
915 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
916 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
920 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
922 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
925 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
929 union dig_transmitter_control {
930 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
931 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
932 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
933 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
937 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
939 struct drm_device *dev = encoder->dev;
940 struct radeon_device *rdev = dev->dev_private;
941 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
942 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
943 struct drm_connector *connector;
944 union dig_transmitter_control args;
950 int dp_lane_count = 0;
951 int connector_object_id = 0;
952 int igp_lane_info = 0;
953 int dig_encoder = dig->dig_encoder;
955 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
956 connector = radeon_get_connector_for_encoder_init(encoder);
957 /* just needed to avoid bailing in the encoder check. the encoder
958 * isn't used for init
962 connector = radeon_get_connector_for_encoder(encoder);
965 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
966 struct radeon_connector_atom_dig *dig_connector =
967 radeon_connector->con_priv;
969 dp_clock = dig_connector->dp_clock;
970 dp_lane_count = dig_connector->dp_lane_count;
971 connector_object_id =
972 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
973 igp_lane_info = dig_connector->igp_lane_info;
976 /* no dig encoder assigned */
977 if (dig_encoder == -1)
980 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
983 memset(&args, 0, sizeof(args));
985 switch (radeon_encoder->encoder_id) {
986 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
987 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
989 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
990 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
991 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
992 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
994 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
995 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
999 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1002 args.v1.ucAction = action;
1003 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1004 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1005 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1006 args.v1.asMode.ucLaneSel = lane_num;
1007 args.v1.asMode.ucLaneSet = lane_set;
1010 args.v1.usPixelClock =
1011 cpu_to_le16(dp_clock / 10);
1012 else if (radeon_encoder->pixel_clock > 165000)
1013 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1015 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1017 if (ASIC_IS_DCE4(rdev)) {
1019 args.v3.ucLaneNum = dp_lane_count;
1020 else if (radeon_encoder->pixel_clock > 165000)
1021 args.v3.ucLaneNum = 8;
1023 args.v3.ucLaneNum = 4;
1026 args.v3.acConfig.ucLinkSel = 1;
1027 if (dig_encoder & 1)
1028 args.v3.acConfig.ucEncoderSel = 1;
1030 /* Select the PLL for the PHY
1031 * DP PHY should be clocked from external src if there is
1034 if (encoder->crtc) {
1035 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1036 pll_id = radeon_crtc->pll_id;
1039 if (ASIC_IS_DCE5(rdev)) {
1040 /* On DCE5 DCPLL usually generates the DP ref clock */
1042 if (rdev->clock.dp_extclk)
1043 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1045 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1047 args.v4.acConfig.ucRefClkSource = pll_id;
1049 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1050 if (is_dp && rdev->clock.dp_extclk)
1051 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1053 args.v3.acConfig.ucRefClkSource = pll_id;
1056 switch (radeon_encoder->encoder_id) {
1057 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1058 args.v3.acConfig.ucTransmitterSel = 0;
1060 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1061 args.v3.acConfig.ucTransmitterSel = 1;
1063 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1064 args.v3.acConfig.ucTransmitterSel = 2;
1069 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1070 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1071 if (dig->coherent_mode)
1072 args.v3.acConfig.fCoherentMode = 1;
1073 if (radeon_encoder->pixel_clock > 165000)
1074 args.v3.acConfig.fDualLinkConnector = 1;
1076 } else if (ASIC_IS_DCE32(rdev)) {
1077 args.v2.acConfig.ucEncoderSel = dig_encoder;
1079 args.v2.acConfig.ucLinkSel = 1;
1081 switch (radeon_encoder->encoder_id) {
1082 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1083 args.v2.acConfig.ucTransmitterSel = 0;
1085 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1086 args.v2.acConfig.ucTransmitterSel = 1;
1088 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1089 args.v2.acConfig.ucTransmitterSel = 2;
1094 args.v2.acConfig.fCoherentMode = 1;
1095 args.v2.acConfig.fDPConnector = 1;
1096 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1097 if (dig->coherent_mode)
1098 args.v2.acConfig.fCoherentMode = 1;
1099 if (radeon_encoder->pixel_clock > 165000)
1100 args.v2.acConfig.fDualLinkConnector = 1;
1103 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1108 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1110 if ((rdev->flags & RADEON_IS_IGP) &&
1111 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1112 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
1113 if (igp_lane_info & 0x1)
1114 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1115 else if (igp_lane_info & 0x2)
1116 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1117 else if (igp_lane_info & 0x4)
1118 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1119 else if (igp_lane_info & 0x8)
1120 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1122 if (igp_lane_info & 0x3)
1123 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1124 else if (igp_lane_info & 0xc)
1125 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1130 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1132 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1135 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1136 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1137 if (dig->coherent_mode)
1138 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1139 if (radeon_encoder->pixel_clock > 165000)
1140 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1144 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1148 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1150 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1151 struct drm_device *dev = radeon_connector->base.dev;
1152 struct radeon_device *rdev = dev->dev_private;
1153 union dig_transmitter_control args;
1154 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1157 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1160 if (!ASIC_IS_DCE4(rdev))
1163 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1164 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1167 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1170 memset(&args, 0, sizeof(args));
1172 args.v1.ucAction = action;
1174 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1176 /* wait for the panel to power up */
1177 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1180 for (i = 0; i < 300; i++) {
1181 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1191 union external_encoder_control {
1192 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1193 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1197 atombios_external_encoder_setup(struct drm_encoder *encoder,
1198 struct drm_encoder *ext_encoder,
1201 struct drm_device *dev = encoder->dev;
1202 struct radeon_device *rdev = dev->dev_private;
1203 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1204 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1205 union external_encoder_control args;
1206 struct drm_connector *connector;
1207 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1210 int dp_lane_count = 0;
1211 int connector_object_id = 0;
1212 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1215 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1216 connector = radeon_get_connector_for_encoder_init(encoder);
1218 connector = radeon_get_connector_for_encoder(encoder);
1221 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1222 struct radeon_connector_atom_dig *dig_connector =
1223 radeon_connector->con_priv;
1225 dp_clock = dig_connector->dp_clock;
1226 dp_lane_count = dig_connector->dp_lane_count;
1227 connector_object_id =
1228 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1229 bpc = connector->display_info.bpc;
1232 memset(&args, 0, sizeof(args));
1234 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1239 /* no params on frev 1 */
1245 args.v1.sDigEncoder.ucAction = action;
1246 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1247 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1249 if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1250 if (dp_clock == 270000)
1251 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1252 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1253 } else if (radeon_encoder->pixel_clock > 165000)
1254 args.v1.sDigEncoder.ucLaneNum = 8;
1256 args.v1.sDigEncoder.ucLaneNum = 4;
1259 args.v3.sExtEncoder.ucAction = action;
1260 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1261 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1263 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1264 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1266 if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1267 if (dp_clock == 270000)
1268 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1269 else if (dp_clock == 540000)
1270 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1271 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1272 } else if (radeon_encoder->pixel_clock > 165000)
1273 args.v3.sExtEncoder.ucLaneNum = 8;
1275 args.v3.sExtEncoder.ucLaneNum = 4;
1277 case GRAPH_OBJECT_ENUM_ID1:
1278 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1280 case GRAPH_OBJECT_ENUM_ID2:
1281 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1283 case GRAPH_OBJECT_ENUM_ID3:
1284 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1289 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1292 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1296 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1299 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1302 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1305 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1310 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1315 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1318 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1322 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1324 struct drm_device *dev = encoder->dev;
1325 struct radeon_device *rdev = dev->dev_private;
1326 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1327 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1328 ENABLE_YUV_PS_ALLOCATION args;
1329 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1332 memset(&args, 0, sizeof(args));
1334 if (rdev->family >= CHIP_R600)
1335 reg = R600_BIOS_3_SCRATCH;
1337 reg = RADEON_BIOS_3_SCRATCH;
1339 /* XXX: fix up scratch reg handling */
1341 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1342 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1343 (radeon_crtc->crtc_id << 18)));
1344 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1345 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1350 args.ucEnable = ATOM_ENABLE;
1351 args.ucCRTC = radeon_crtc->crtc_id;
1353 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1359 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1361 struct drm_device *dev = encoder->dev;
1362 struct radeon_device *rdev = dev->dev_private;
1363 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1364 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1365 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1367 bool is_dig = false;
1368 bool is_dce5_dac = false;
1369 bool is_dce5_dvo = false;
1371 memset(&args, 0, sizeof(args));
1373 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1374 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1375 radeon_encoder->active_device);
1376 switch (radeon_encoder->encoder_id) {
1377 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1378 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1379 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1381 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1382 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1383 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1384 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1387 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1388 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1389 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1391 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1392 if (ASIC_IS_DCE5(rdev))
1394 else if (ASIC_IS_DCE3(rdev))
1397 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1399 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1400 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1402 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1403 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1404 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1406 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1408 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1409 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1410 if (ASIC_IS_DCE5(rdev))
1413 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1414 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1415 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1416 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1418 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1421 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1422 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1423 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1424 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1425 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1426 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1428 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1434 case DRM_MODE_DPMS_ON:
1435 /* some early dce3.2 boards have a bug in their transmitter control table */
1436 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1437 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1439 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1440 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1441 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1444 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1445 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1446 struct radeon_connector_atom_dig *radeon_dig_connector =
1447 radeon_connector->con_priv;
1448 atombios_set_edp_panel_power(connector,
1449 ATOM_TRANSMITTER_ACTION_POWER_ON);
1450 radeon_dig_connector->edp_on = true;
1452 if (ASIC_IS_DCE4(rdev))
1453 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1454 radeon_dp_link_train(encoder, connector);
1455 if (ASIC_IS_DCE4(rdev))
1456 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1458 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1459 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1461 case DRM_MODE_DPMS_STANDBY:
1462 case DRM_MODE_DPMS_SUSPEND:
1463 case DRM_MODE_DPMS_OFF:
1464 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1465 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1466 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1468 if (ASIC_IS_DCE4(rdev))
1469 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1471 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1472 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1473 struct radeon_connector_atom_dig *radeon_dig_connector =
1474 radeon_connector->con_priv;
1475 atombios_set_edp_panel_power(connector,
1476 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1477 radeon_dig_connector->edp_on = false;
1480 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1481 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1484 } else if (is_dce5_dac) {
1486 case DRM_MODE_DPMS_ON:
1487 atombios_dac_setup(encoder, ATOM_ENABLE);
1489 case DRM_MODE_DPMS_STANDBY:
1490 case DRM_MODE_DPMS_SUSPEND:
1491 case DRM_MODE_DPMS_OFF:
1492 atombios_dac_setup(encoder, ATOM_DISABLE);
1495 } else if (is_dce5_dvo) {
1497 case DRM_MODE_DPMS_ON:
1498 atombios_dvo_setup(encoder, ATOM_ENABLE);
1500 case DRM_MODE_DPMS_STANDBY:
1501 case DRM_MODE_DPMS_SUSPEND:
1502 case DRM_MODE_DPMS_OFF:
1503 atombios_dvo_setup(encoder, ATOM_DISABLE);
1508 case DRM_MODE_DPMS_ON:
1509 args.ucAction = ATOM_ENABLE;
1510 /* workaround for DVOOutputControl on some RS690 systems */
1511 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1512 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1513 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1514 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1515 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1517 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1518 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1519 args.ucAction = ATOM_LCD_BLON;
1520 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1523 case DRM_MODE_DPMS_STANDBY:
1524 case DRM_MODE_DPMS_SUSPEND:
1525 case DRM_MODE_DPMS_OFF:
1526 args.ucAction = ATOM_DISABLE;
1527 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1528 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1529 args.ucAction = ATOM_LCD_BLOFF;
1530 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1538 case DRM_MODE_DPMS_ON:
1540 if (ASIC_IS_DCE41(rdev)) {
1541 atombios_external_encoder_setup(encoder, ext_encoder,
1542 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1543 atombios_external_encoder_setup(encoder, ext_encoder,
1544 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1546 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1548 case DRM_MODE_DPMS_STANDBY:
1549 case DRM_MODE_DPMS_SUSPEND:
1550 case DRM_MODE_DPMS_OFF:
1551 if (ASIC_IS_DCE41(rdev)) {
1552 atombios_external_encoder_setup(encoder, ext_encoder,
1553 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1554 atombios_external_encoder_setup(encoder, ext_encoder,
1555 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1557 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1562 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1566 union crtc_source_param {
1567 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1568 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1572 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1574 struct drm_device *dev = encoder->dev;
1575 struct radeon_device *rdev = dev->dev_private;
1576 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1577 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1578 union crtc_source_param args;
1579 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1581 struct radeon_encoder_atom_dig *dig;
1583 memset(&args, 0, sizeof(args));
1585 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1593 if (ASIC_IS_AVIVO(rdev))
1594 args.v1.ucCRTC = radeon_crtc->crtc_id;
1596 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1597 args.v1.ucCRTC = radeon_crtc->crtc_id;
1599 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1602 switch (radeon_encoder->encoder_id) {
1603 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1604 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1605 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1607 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1608 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1609 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1610 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1612 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1614 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1615 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1616 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1617 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1619 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1620 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1621 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1622 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1623 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1624 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1626 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1628 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1629 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1630 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1631 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1632 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1633 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1635 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1640 args.v2.ucCRTC = radeon_crtc->crtc_id;
1641 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1642 switch (radeon_encoder->encoder_id) {
1643 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1644 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1645 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1646 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1647 dig = radeon_encoder->enc_priv;
1648 switch (dig->dig_encoder) {
1650 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1653 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1656 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1659 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1662 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1665 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1669 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1670 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1672 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1673 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1674 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1675 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1676 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1678 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1680 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1681 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1682 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1683 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1684 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1686 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1693 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1697 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1699 /* update scratch regs with new routing */
1700 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1704 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1705 struct drm_display_mode *mode)
1707 struct drm_device *dev = encoder->dev;
1708 struct radeon_device *rdev = dev->dev_private;
1709 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1710 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1712 /* Funky macbooks */
1713 if ((dev->pdev->device == 0x71C5) &&
1714 (dev->pdev->subsystem_vendor == 0x106b) &&
1715 (dev->pdev->subsystem_device == 0x0080)) {
1716 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1717 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1719 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1720 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1722 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1726 /* set scaler clears this on some chips */
1727 if (ASIC_IS_AVIVO(rdev) &&
1728 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1729 if (ASIC_IS_DCE4(rdev)) {
1730 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1731 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1732 EVERGREEN_INTERLEAVE_EN);
1734 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1736 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1737 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1738 AVIVO_D1MODE_INTERLEAVE_EN);
1740 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1745 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1747 struct drm_device *dev = encoder->dev;
1748 struct radeon_device *rdev = dev->dev_private;
1749 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1750 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1751 struct drm_encoder *test_encoder;
1752 struct radeon_encoder_atom_dig *dig;
1753 uint32_t dig_enc_in_use = 0;
1756 if (ASIC_IS_DCE4(rdev)) {
1757 dig = radeon_encoder->enc_priv;
1758 if (ASIC_IS_DCE41(rdev))
1759 return radeon_crtc->crtc_id;
1761 switch (radeon_encoder->encoder_id) {
1762 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1768 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1774 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1784 /* on DCE32 and encoder can driver any block so just crtc id */
1785 if (ASIC_IS_DCE32(rdev)) {
1786 return radeon_crtc->crtc_id;
1789 /* on DCE3 - LVTMA can only be driven by DIGB */
1790 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1791 struct radeon_encoder *radeon_test_encoder;
1793 if (encoder == test_encoder)
1796 if (!radeon_encoder_is_digital(test_encoder))
1799 radeon_test_encoder = to_radeon_encoder(test_encoder);
1800 dig = radeon_test_encoder->enc_priv;
1802 if (dig->dig_encoder >= 0)
1803 dig_enc_in_use |= (1 << dig->dig_encoder);
1806 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1807 if (dig_enc_in_use & 0x2)
1808 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1811 if (!(dig_enc_in_use & 1))
1816 /* This only needs to be called once at startup */
1818 radeon_atom_encoder_init(struct radeon_device *rdev)
1820 struct drm_device *dev = rdev->ddev;
1821 struct drm_encoder *encoder;
1823 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1824 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1825 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1827 switch (radeon_encoder->encoder_id) {
1828 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1829 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1830 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1831 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1832 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1838 if (ext_encoder && ASIC_IS_DCE41(rdev))
1839 atombios_external_encoder_setup(encoder, ext_encoder,
1840 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1845 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1846 struct drm_display_mode *mode,
1847 struct drm_display_mode *adjusted_mode)
1849 struct drm_device *dev = encoder->dev;
1850 struct radeon_device *rdev = dev->dev_private;
1851 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1852 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1854 radeon_encoder->pixel_clock = adjusted_mode->clock;
1856 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1857 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1858 atombios_yuv_setup(encoder, true);
1860 atombios_yuv_setup(encoder, false);
1863 switch (radeon_encoder->encoder_id) {
1864 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1865 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1866 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1867 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1868 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1870 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1871 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1872 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1873 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1874 if (ASIC_IS_DCE4(rdev)) {
1875 /* disable the transmitter */
1876 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1877 /* setup and enable the encoder */
1878 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1880 /* enable the transmitter */
1881 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1883 /* disable the encoder and transmitter */
1884 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1885 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1887 /* setup and enable the encoder and transmitter */
1888 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1889 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1890 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1893 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1894 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1895 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1896 atombios_dvo_setup(encoder, ATOM_ENABLE);
1898 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1899 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1900 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1901 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1902 atombios_dac_setup(encoder, ATOM_ENABLE);
1903 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1904 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1905 atombios_tv_setup(encoder, ATOM_ENABLE);
1907 atombios_tv_setup(encoder, ATOM_DISABLE);
1913 if (ASIC_IS_DCE41(rdev))
1914 atombios_external_encoder_setup(encoder, ext_encoder,
1915 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1917 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1920 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1922 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1923 r600_hdmi_enable(encoder);
1924 r600_hdmi_setmode(encoder, adjusted_mode);
1929 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1931 struct drm_device *dev = encoder->dev;
1932 struct radeon_device *rdev = dev->dev_private;
1933 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1934 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1936 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1937 ATOM_DEVICE_CV_SUPPORT |
1938 ATOM_DEVICE_CRT_SUPPORT)) {
1939 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1940 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1943 memset(&args, 0, sizeof(args));
1945 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1948 args.sDacload.ucMisc = 0;
1950 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1951 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1952 args.sDacload.ucDacType = ATOM_DAC_A;
1954 args.sDacload.ucDacType = ATOM_DAC_B;
1956 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1957 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1958 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1959 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1960 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1961 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1963 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1964 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1965 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1967 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1970 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1977 static enum drm_connector_status
1978 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1980 struct drm_device *dev = encoder->dev;
1981 struct radeon_device *rdev = dev->dev_private;
1982 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1983 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1984 uint32_t bios_0_scratch;
1986 if (!atombios_dac_load_detect(encoder, connector)) {
1987 DRM_DEBUG_KMS("detect returned false \n");
1988 return connector_status_unknown;
1991 if (rdev->family >= CHIP_R600)
1992 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1994 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1996 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1997 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1998 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1999 return connector_status_connected;
2001 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2002 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2003 return connector_status_connected;
2005 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2006 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2007 return connector_status_connected;
2009 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2010 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2011 return connector_status_connected; /* CTV */
2012 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2013 return connector_status_connected; /* STV */
2015 return connector_status_disconnected;
2018 static enum drm_connector_status
2019 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2021 struct drm_device *dev = encoder->dev;
2022 struct radeon_device *rdev = dev->dev_private;
2023 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2024 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2025 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2028 if (!ASIC_IS_DCE4(rdev))
2029 return connector_status_unknown;
2032 return connector_status_unknown;
2034 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2035 return connector_status_unknown;
2037 /* load detect on the dp bridge */
2038 atombios_external_encoder_setup(encoder, ext_encoder,
2039 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2041 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2043 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2044 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2045 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2046 return connector_status_connected;
2048 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2049 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2050 return connector_status_connected;
2052 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2053 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2054 return connector_status_connected;
2056 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2057 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2058 return connector_status_connected; /* CTV */
2059 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2060 return connector_status_connected; /* STV */
2062 return connector_status_disconnected;
2066 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2068 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2071 /* ddc_setup on the dp bridge */
2072 atombios_external_encoder_setup(encoder, ext_encoder,
2073 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2077 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2079 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2080 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2082 if ((radeon_encoder->active_device &
2083 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2084 radeon_encoder_is_dp_bridge(encoder)) {
2085 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2087 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2090 radeon_atom_output_lock(encoder, true);
2091 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2094 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2096 /* select the clock/data port if it uses a router */
2097 if (radeon_connector->router.cd_valid)
2098 radeon_router_select_cd_port(radeon_connector);
2100 /* turn eDP panel on for mode set */
2101 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2102 atombios_set_edp_panel_power(connector,
2103 ATOM_TRANSMITTER_ACTION_POWER_ON);
2106 /* this is needed for the pll/ss setup to work correctly in some cases */
2107 atombios_set_encoder_crtc_source(encoder);
2110 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2112 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2113 radeon_atom_output_lock(encoder, false);
2116 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2118 struct drm_device *dev = encoder->dev;
2119 struct radeon_device *rdev = dev->dev_private;
2120 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2121 struct radeon_encoder_atom_dig *dig;
2123 /* check for pre-DCE3 cards with shared encoders;
2124 * can't really use the links individually, so don't disable
2125 * the encoder if it's in use by another connector
2127 if (!ASIC_IS_DCE3(rdev)) {
2128 struct drm_encoder *other_encoder;
2129 struct radeon_encoder *other_radeon_encoder;
2131 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2132 other_radeon_encoder = to_radeon_encoder(other_encoder);
2133 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2134 drm_helper_encoder_in_use(other_encoder))
2139 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2141 switch (radeon_encoder->encoder_id) {
2142 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2143 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2144 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2145 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2146 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2148 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2149 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2150 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2151 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2152 if (ASIC_IS_DCE4(rdev))
2153 /* disable the transmitter */
2154 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2156 /* disable the encoder and transmitter */
2157 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2158 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2161 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2162 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2163 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2164 atombios_dvo_setup(encoder, ATOM_DISABLE);
2166 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2167 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2168 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2169 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2170 atombios_dac_setup(encoder, ATOM_DISABLE);
2171 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2172 atombios_tv_setup(encoder, ATOM_DISABLE);
2177 if (radeon_encoder_is_digital(encoder)) {
2178 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2179 r600_hdmi_disable(encoder);
2180 dig = radeon_encoder->enc_priv;
2181 dig->dig_encoder = -1;
2183 radeon_encoder->active_device = 0;
2186 /* these are handled by the primary encoders */
2187 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2192 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2198 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2199 struct drm_display_mode *mode,
2200 struct drm_display_mode *adjusted_mode)
2205 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2211 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2216 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2217 struct drm_display_mode *mode,
2218 struct drm_display_mode *adjusted_mode)
2223 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2224 .dpms = radeon_atom_ext_dpms,
2225 .mode_fixup = radeon_atom_ext_mode_fixup,
2226 .prepare = radeon_atom_ext_prepare,
2227 .mode_set = radeon_atom_ext_mode_set,
2228 .commit = radeon_atom_ext_commit,
2229 .disable = radeon_atom_ext_disable,
2230 /* no detect for TMDS/LVDS yet */
2233 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2234 .dpms = radeon_atom_encoder_dpms,
2235 .mode_fixup = radeon_atom_mode_fixup,
2236 .prepare = radeon_atom_encoder_prepare,
2237 .mode_set = radeon_atom_encoder_mode_set,
2238 .commit = radeon_atom_encoder_commit,
2239 .disable = radeon_atom_encoder_disable,
2240 .detect = radeon_atom_dig_detect,
2243 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2244 .dpms = radeon_atom_encoder_dpms,
2245 .mode_fixup = radeon_atom_mode_fixup,
2246 .prepare = radeon_atom_encoder_prepare,
2247 .mode_set = radeon_atom_encoder_mode_set,
2248 .commit = radeon_atom_encoder_commit,
2249 .detect = radeon_atom_dac_detect,
2252 void radeon_enc_destroy(struct drm_encoder *encoder)
2254 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2255 kfree(radeon_encoder->enc_priv);
2256 drm_encoder_cleanup(encoder);
2257 kfree(radeon_encoder);
2260 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2261 .destroy = radeon_enc_destroy,
2264 struct radeon_encoder_atom_dac *
2265 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2267 struct drm_device *dev = radeon_encoder->base.dev;
2268 struct radeon_device *rdev = dev->dev_private;
2269 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2274 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2278 struct radeon_encoder_atom_dig *
2279 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2281 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2282 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2287 /* coherent mode by default */
2288 dig->coherent_mode = true;
2289 dig->dig_encoder = -1;
2291 if (encoder_enum == 2)
2300 radeon_add_atom_encoder(struct drm_device *dev,
2301 uint32_t encoder_enum,
2302 uint32_t supported_device,
2305 struct radeon_device *rdev = dev->dev_private;
2306 struct drm_encoder *encoder;
2307 struct radeon_encoder *radeon_encoder;
2309 /* see if we already added it */
2310 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2311 radeon_encoder = to_radeon_encoder(encoder);
2312 if (radeon_encoder->encoder_enum == encoder_enum) {
2313 radeon_encoder->devices |= supported_device;
2320 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2321 if (!radeon_encoder)
2324 encoder = &radeon_encoder->base;
2325 switch (rdev->num_crtc) {
2327 encoder->possible_crtcs = 0x1;
2331 encoder->possible_crtcs = 0x3;
2334 encoder->possible_crtcs = 0xf;
2337 encoder->possible_crtcs = 0x3f;
2341 radeon_encoder->enc_priv = NULL;
2343 radeon_encoder->encoder_enum = encoder_enum;
2344 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2345 radeon_encoder->devices = supported_device;
2346 radeon_encoder->rmx_type = RMX_OFF;
2347 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2348 radeon_encoder->is_ext_encoder = false;
2349 radeon_encoder->caps = caps;
2351 switch (radeon_encoder->encoder_id) {
2352 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2353 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2354 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2355 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2356 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2357 radeon_encoder->rmx_type = RMX_FULL;
2358 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2359 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2361 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2362 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2364 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2366 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2367 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2368 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2369 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2371 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2372 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2373 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2374 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2375 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2376 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2378 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2379 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2380 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2381 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2382 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2383 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2384 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2385 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2386 radeon_encoder->rmx_type = RMX_FULL;
2387 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2388 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2389 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2390 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2391 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2393 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2394 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2396 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2398 case ENCODER_OBJECT_ID_SI170B:
2399 case ENCODER_OBJECT_ID_CH7303:
2400 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2401 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2402 case ENCODER_OBJECT_ID_TITFP513:
2403 case ENCODER_OBJECT_ID_VT1623:
2404 case ENCODER_OBJECT_ID_HDMI_SI1930:
2405 case ENCODER_OBJECT_ID_TRAVIS:
2406 case ENCODER_OBJECT_ID_NUTMEG:
2407 /* these are handled by the primary encoders */
2408 radeon_encoder->is_ext_encoder = true;
2409 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2410 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2411 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2412 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2414 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2415 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);