2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include <asm/div64.h>
33 #include "drm_crtc_helper.h"
36 static int radeon_ddc_dump(struct drm_connector *connector);
38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
45 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
71 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
78 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
93 for (i = 0; i < 256; i++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
95 (radeon_crtc->lut_r[i] << 20) |
96 (radeon_crtc->lut_g[i] << 10) |
97 (radeon_crtc->lut_b[i] << 0));
101 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct radeon_device *rdev = dev->dev_private;
108 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
110 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
111 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
112 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
113 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
114 NI_GRPH_PRESCALE_BYPASS);
115 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
116 NI_OVL_PRESCALE_BYPASS);
117 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
118 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
119 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
121 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
131 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
132 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
134 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
135 for (i = 0; i < 256; i++) {
136 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
137 (radeon_crtc->lut_r[i] << 20) |
138 (radeon_crtc->lut_g[i] << 10) |
139 (radeon_crtc->lut_b[i] << 0));
142 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
143 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
144 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
145 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
147 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
148 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
149 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
150 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
151 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
152 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
153 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
154 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
155 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
156 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
157 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
161 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
163 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
164 struct drm_device *dev = crtc->dev;
165 struct radeon_device *rdev = dev->dev_private;
169 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
170 if (radeon_crtc->crtc_id == 0)
171 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
173 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
174 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
176 WREG8(RADEON_PALETTE_INDEX, 0);
177 for (i = 0; i < 256; i++) {
178 WREG32(RADEON_PALETTE_30_DATA,
179 (radeon_crtc->lut_r[i] << 20) |
180 (radeon_crtc->lut_g[i] << 10) |
181 (radeon_crtc->lut_b[i] << 0));
185 void radeon_crtc_load_lut(struct drm_crtc *crtc)
187 struct drm_device *dev = crtc->dev;
188 struct radeon_device *rdev = dev->dev_private;
193 if (ASIC_IS_DCE5(rdev))
194 dce5_crtc_load_lut(crtc);
195 else if (ASIC_IS_DCE4(rdev))
196 dce4_crtc_load_lut(crtc);
197 else if (ASIC_IS_AVIVO(rdev))
198 avivo_crtc_load_lut(crtc);
200 legacy_crtc_load_lut(crtc);
203 /** Sets the color ramps on behalf of fbcon */
204 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
207 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
209 radeon_crtc->lut_r[regno] = red >> 6;
210 radeon_crtc->lut_g[regno] = green >> 6;
211 radeon_crtc->lut_b[regno] = blue >> 6;
214 /** Gets the color ramps on behalf of fbcon */
215 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
216 u16 *blue, int regno)
218 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
220 *red = radeon_crtc->lut_r[regno] << 6;
221 *green = radeon_crtc->lut_g[regno] << 6;
222 *blue = radeon_crtc->lut_b[regno] << 6;
225 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
226 u16 *blue, uint32_t start, uint32_t size)
228 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
229 int end = (start + size > 256) ? 256 : start + size, i;
231 /* userspace palettes are always correct as is */
232 for (i = start; i < end; i++) {
233 radeon_crtc->lut_r[i] = red[i] >> 6;
234 radeon_crtc->lut_g[i] = green[i] >> 6;
235 radeon_crtc->lut_b[i] = blue[i] >> 6;
237 radeon_crtc_load_lut(crtc);
240 static void radeon_crtc_destroy(struct drm_crtc *crtc)
242 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
244 drm_crtc_cleanup(crtc);
249 * Handle unpin events outside the interrupt handler proper.
251 static void radeon_unpin_work_func(struct work_struct *__work)
253 struct radeon_unpin_work *work =
254 container_of(__work, struct radeon_unpin_work, work);
257 /* unpin of the old buffer */
258 r = radeon_bo_reserve(work->old_rbo, false);
259 if (likely(r == 0)) {
260 r = radeon_bo_unpin(work->old_rbo);
261 if (unlikely(r != 0)) {
262 DRM_ERROR("failed to unpin buffer after flip\n");
264 radeon_bo_unreserve(work->old_rbo);
266 DRM_ERROR("failed to reserve buffer after flip\n");
268 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
272 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
274 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
275 struct radeon_unpin_work *work;
276 struct drm_pending_vblank_event *e;
282 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
283 work = radeon_crtc->unpin_work;
285 (work->fence && !radeon_fence_signaled(work->fence))) {
286 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
289 /* New pageflip, or just completion of a previous one? */
290 if (!radeon_crtc->deferred_flip_completion) {
291 /* do the flip (mmio) */
292 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
294 /* This is just a completion of a flip queued in crtc
295 * at last invocation. Make sure we go directly to
296 * completion routine.
299 radeon_crtc->deferred_flip_completion = 0;
302 /* Has the pageflip already completed in crtc, or is it certain
303 * to complete in this vblank?
305 if (update_pending &&
306 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
309 (vpos < (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100)) {
310 /* crtc didn't flip in this target vblank interval,
311 * but flip is pending in crtc. It will complete it
312 * in next vblank interval, so complete the flip at
315 radeon_crtc->deferred_flip_completion = 1;
316 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
320 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
321 radeon_crtc->unpin_work = NULL;
323 /* wakeup userspace */
326 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
327 e->event.tv_sec = now.tv_sec;
328 e->event.tv_usec = now.tv_usec;
329 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
330 wake_up_interruptible(&e->base.file_priv->event_wait);
332 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
334 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
335 radeon_fence_unref(&work->fence);
336 radeon_post_page_flip(work->rdev, work->crtc_id);
337 schedule_work(&work->work);
340 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
341 struct drm_framebuffer *fb,
342 struct drm_pending_vblank_event *event)
344 struct drm_device *dev = crtc->dev;
345 struct radeon_device *rdev = dev->dev_private;
346 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
347 struct radeon_framebuffer *old_radeon_fb;
348 struct radeon_framebuffer *new_radeon_fb;
349 struct drm_gem_object *obj;
350 struct radeon_bo *rbo;
351 struct radeon_unpin_work *work;
353 u32 tiling_flags, pitch_pixels;
357 work = kzalloc(sizeof *work, GFP_KERNEL);
363 work->crtc_id = radeon_crtc->crtc_id;
364 old_radeon_fb = to_radeon_framebuffer(crtc->fb);
365 new_radeon_fb = to_radeon_framebuffer(fb);
366 /* schedule unpin of the old buffer */
367 obj = old_radeon_fb->obj;
368 /* take a reference to the old object */
369 drm_gem_object_reference(obj);
370 rbo = gem_to_radeon_bo(obj);
372 obj = new_radeon_fb->obj;
373 rbo = gem_to_radeon_bo(obj);
374 if (rbo->tbo.sync_obj)
375 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
376 INIT_WORK(&work->work, radeon_unpin_work_func);
378 /* We borrow the event spin lock for protecting unpin_work */
379 spin_lock_irqsave(&dev->event_lock, flags);
380 if (radeon_crtc->unpin_work) {
381 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
385 radeon_crtc->unpin_work = work;
386 radeon_crtc->deferred_flip_completion = 0;
387 spin_unlock_irqrestore(&dev->event_lock, flags);
389 /* pin the new buffer */
390 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
393 r = radeon_bo_reserve(rbo, false);
394 if (unlikely(r != 0)) {
395 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
398 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
399 if (unlikely(r != 0)) {
400 radeon_bo_unreserve(rbo);
402 DRM_ERROR("failed to pin new rbo buffer before flip\n");
405 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
406 radeon_bo_unreserve(rbo);
408 if (!ASIC_IS_AVIVO(rdev)) {
409 /* crtc offset is from display base addr not FB location */
410 base -= radeon_crtc->legacy_display_base_addr;
411 pitch_pixels = fb->pitch / (fb->bits_per_pixel / 8);
413 if (tiling_flags & RADEON_TILING_MACRO) {
414 if (ASIC_IS_R300(rdev)) {
417 int byteshift = fb->bits_per_pixel >> 4;
418 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
419 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
422 int offset = crtc->y * pitch_pixels + crtc->x;
423 switch (fb->bits_per_pixel) {
444 spin_lock_irqsave(&dev->event_lock, flags);
445 work->new_crtc_base = base;
446 spin_unlock_irqrestore(&dev->event_lock, flags);
451 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
453 DRM_ERROR("failed to get vblank before flip\n");
457 /* set the proper interrupt */
458 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
463 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
464 DRM_ERROR("failed to reserve new rbo in error path\n");
467 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
468 DRM_ERROR("failed to unpin new rbo in error path\n");
470 radeon_bo_unreserve(rbo);
473 spin_lock_irqsave(&dev->event_lock, flags);
474 radeon_crtc->unpin_work = NULL;
476 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
477 spin_unlock_irqrestore(&dev->event_lock, flags);
478 radeon_fence_unref(&work->fence);
484 static const struct drm_crtc_funcs radeon_crtc_funcs = {
485 .cursor_set = radeon_crtc_cursor_set,
486 .cursor_move = radeon_crtc_cursor_move,
487 .gamma_set = radeon_crtc_gamma_set,
488 .set_config = drm_crtc_helper_set_config,
489 .destroy = radeon_crtc_destroy,
490 .page_flip = radeon_crtc_page_flip,
493 static void radeon_crtc_init(struct drm_device *dev, int index)
495 struct radeon_device *rdev = dev->dev_private;
496 struct radeon_crtc *radeon_crtc;
499 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
500 if (radeon_crtc == NULL)
503 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
505 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
506 radeon_crtc->crtc_id = index;
507 rdev->mode_info.crtcs[index] = radeon_crtc;
510 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
511 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
512 radeon_crtc->mode_set.num_connectors = 0;
515 for (i = 0; i < 256; i++) {
516 radeon_crtc->lut_r[i] = i << 2;
517 radeon_crtc->lut_g[i] = i << 2;
518 radeon_crtc->lut_b[i] = i << 2;
521 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
522 radeon_atombios_init_crtc(dev, radeon_crtc);
524 radeon_legacy_init_crtc(dev, radeon_crtc);
527 static const char *encoder_names[36] = {
547 "INTERNAL_KLDSCP_TMDS1",
548 "INTERNAL_KLDSCP_DVO1",
549 "INTERNAL_KLDSCP_DAC1",
550 "INTERNAL_KLDSCP_DAC2",
559 "INTERNAL_KLDSCP_LVTMA",
566 static const char *connector_names[15] = {
584 static const char *hpd_names[6] = {
593 static void radeon_print_display_setup(struct drm_device *dev)
595 struct drm_connector *connector;
596 struct radeon_connector *radeon_connector;
597 struct drm_encoder *encoder;
598 struct radeon_encoder *radeon_encoder;
602 DRM_INFO("Radeon Display Connectors\n");
603 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
604 radeon_connector = to_radeon_connector(connector);
605 DRM_INFO("Connector %d:\n", i);
606 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
607 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
608 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
609 if (radeon_connector->ddc_bus) {
610 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
611 radeon_connector->ddc_bus->rec.mask_clk_reg,
612 radeon_connector->ddc_bus->rec.mask_data_reg,
613 radeon_connector->ddc_bus->rec.a_clk_reg,
614 radeon_connector->ddc_bus->rec.a_data_reg,
615 radeon_connector->ddc_bus->rec.en_clk_reg,
616 radeon_connector->ddc_bus->rec.en_data_reg,
617 radeon_connector->ddc_bus->rec.y_clk_reg,
618 radeon_connector->ddc_bus->rec.y_data_reg);
619 if (radeon_connector->router.ddc_valid)
620 DRM_INFO(" DDC Router 0x%x/0x%x\n",
621 radeon_connector->router.ddc_mux_control_pin,
622 radeon_connector->router.ddc_mux_state);
623 if (radeon_connector->router.cd_valid)
624 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
625 radeon_connector->router.cd_mux_control_pin,
626 radeon_connector->router.cd_mux_state);
628 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
629 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
630 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
631 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
632 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
633 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
634 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
636 DRM_INFO(" Encoders:\n");
637 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
638 radeon_encoder = to_radeon_encoder(encoder);
639 devices = radeon_encoder->devices & radeon_connector->devices;
641 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
642 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
643 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
644 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
645 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
646 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
647 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
648 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
649 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
650 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
651 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
652 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
653 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
654 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
655 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
656 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
657 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
658 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
659 if (devices & ATOM_DEVICE_TV1_SUPPORT)
660 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
661 if (devices & ATOM_DEVICE_CV_SUPPORT)
662 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
669 static bool radeon_setup_enc_conn(struct drm_device *dev)
671 struct radeon_device *rdev = dev->dev_private;
672 struct drm_connector *drm_connector;
676 if (rdev->is_atom_bios) {
677 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
679 ret = radeon_get_atom_connector_info_from_object_table(dev);
681 ret = radeon_get_legacy_connector_info_from_bios(dev);
683 ret = radeon_get_legacy_connector_info_from_table(dev);
686 if (!ASIC_IS_AVIVO(rdev))
687 ret = radeon_get_legacy_connector_info_from_table(dev);
690 radeon_setup_encoder_clones(dev);
691 radeon_print_display_setup(dev);
692 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
693 radeon_ddc_dump(drm_connector);
699 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
701 struct drm_device *dev = radeon_connector->base.dev;
702 struct radeon_device *rdev = dev->dev_private;
705 /* on hw with routers, select right port */
706 if (radeon_connector->router.ddc_valid)
707 radeon_router_select_ddc_port(radeon_connector);
709 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
710 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
711 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
712 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
713 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
714 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
716 if (!radeon_connector->ddc_bus)
718 if (!radeon_connector->edid) {
719 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
722 if (!radeon_connector->edid) {
723 if (rdev->is_atom_bios) {
724 /* some laptops provide a hardcoded edid in rom for LCDs */
725 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
726 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
727 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
729 /* some servers provide a hardcoded edid in rom for KVMs */
730 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
732 if (radeon_connector->edid) {
733 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
734 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
737 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
741 static int radeon_ddc_dump(struct drm_connector *connector)
744 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
747 /* on hw with routers, select right port */
748 if (radeon_connector->router.ddc_valid)
749 radeon_router_select_ddc_port(radeon_connector);
751 if (!radeon_connector->ddc_bus)
753 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
761 static void avivo_get_fb_div(struct radeon_pll *pll,
768 u32 tmp = post_div * ref_div;
771 *fb_div = tmp / pll->reference_freq;
772 *frac_fb_div = tmp % pll->reference_freq;
774 if (*fb_div > pll->max_feedback_div)
775 *fb_div = pll->max_feedback_div;
776 else if (*fb_div < pll->min_feedback_div)
777 *fb_div = pll->min_feedback_div;
780 static u32 avivo_get_post_div(struct radeon_pll *pll,
783 u32 vco, post_div, tmp;
785 if (pll->flags & RADEON_PLL_USE_POST_DIV)
786 return pll->post_div;
788 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
789 if (pll->flags & RADEON_PLL_IS_LCD)
790 vco = pll->lcd_pll_out_min;
792 vco = pll->pll_out_min;
794 if (pll->flags & RADEON_PLL_IS_LCD)
795 vco = pll->lcd_pll_out_max;
797 vco = pll->pll_out_max;
800 post_div = vco / target_clock;
801 tmp = vco % target_clock;
803 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
811 if (post_div > pll->max_post_div)
812 post_div = pll->max_post_div;
813 else if (post_div < pll->min_post_div)
814 post_div = pll->min_post_div;
819 #define MAX_TOLERANCE 10
821 void radeon_compute_pll_avivo(struct radeon_pll *pll,
829 u32 target_clock = freq / 10;
830 u32 post_div = avivo_get_post_div(pll, target_clock);
831 u32 ref_div = pll->min_ref_div;
832 u32 fb_div = 0, frac_fb_div = 0, tmp;
834 if (pll->flags & RADEON_PLL_USE_REF_DIV)
835 ref_div = pll->reference_div;
837 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
838 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
839 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
840 if (frac_fb_div >= 5) {
842 frac_fb_div = frac_fb_div / 10;
845 if (frac_fb_div >= 10) {
850 while (ref_div <= pll->max_ref_div) {
851 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
852 &fb_div, &frac_fb_div);
853 if (frac_fb_div >= (pll->reference_freq / 2))
856 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
857 tmp = (tmp * 10000) / target_clock;
859 if (tmp > (10000 + MAX_TOLERANCE))
861 else if (tmp >= (10000 - MAX_TOLERANCE))
868 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
869 (ref_div * post_div * 10);
871 *frac_fb_div_p = frac_fb_div;
872 *ref_div_p = ref_div;
873 *post_div_p = post_div;
874 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
875 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
879 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
889 void radeon_compute_pll_legacy(struct radeon_pll *pll,
891 uint32_t *dot_clock_p,
893 uint32_t *frac_fb_div_p,
895 uint32_t *post_div_p)
897 uint32_t min_ref_div = pll->min_ref_div;
898 uint32_t max_ref_div = pll->max_ref_div;
899 uint32_t min_post_div = pll->min_post_div;
900 uint32_t max_post_div = pll->max_post_div;
901 uint32_t min_fractional_feed_div = 0;
902 uint32_t max_fractional_feed_div = 0;
903 uint32_t best_vco = pll->best_vco;
904 uint32_t best_post_div = 1;
905 uint32_t best_ref_div = 1;
906 uint32_t best_feedback_div = 1;
907 uint32_t best_frac_feedback_div = 0;
908 uint32_t best_freq = -1;
909 uint32_t best_error = 0xffffffff;
910 uint32_t best_vco_diff = 1;
912 u32 pll_out_min, pll_out_max;
914 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
917 if (pll->flags & RADEON_PLL_IS_LCD) {
918 pll_out_min = pll->lcd_pll_out_min;
919 pll_out_max = pll->lcd_pll_out_max;
921 pll_out_min = pll->pll_out_min;
922 pll_out_max = pll->pll_out_max;
925 if (pll_out_min > 64800)
928 if (pll->flags & RADEON_PLL_USE_REF_DIV)
929 min_ref_div = max_ref_div = pll->reference_div;
931 while (min_ref_div < max_ref_div-1) {
932 uint32_t mid = (min_ref_div + max_ref_div) / 2;
933 uint32_t pll_in = pll->reference_freq / mid;
934 if (pll_in < pll->pll_in_min)
936 else if (pll_in > pll->pll_in_max)
943 if (pll->flags & RADEON_PLL_USE_POST_DIV)
944 min_post_div = max_post_div = pll->post_div;
946 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
947 min_fractional_feed_div = pll->min_frac_feedback_div;
948 max_fractional_feed_div = pll->max_frac_feedback_div;
951 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
954 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
957 /* legacy radeons only have a few post_divs */
958 if (pll->flags & RADEON_PLL_LEGACY) {
959 if ((post_div == 5) ||
970 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
971 uint32_t feedback_div, current_freq = 0, error, vco_diff;
972 uint32_t pll_in = pll->reference_freq / ref_div;
973 uint32_t min_feed_div = pll->min_feedback_div;
974 uint32_t max_feed_div = pll->max_feedback_div + 1;
976 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
979 while (min_feed_div < max_feed_div) {
981 uint32_t min_frac_feed_div = min_fractional_feed_div;
982 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
983 uint32_t frac_feedback_div;
986 feedback_div = (min_feed_div + max_feed_div) / 2;
988 tmp = (uint64_t)pll->reference_freq * feedback_div;
989 vco = radeon_div(tmp, ref_div);
991 if (vco < pll_out_min) {
992 min_feed_div = feedback_div + 1;
994 } else if (vco > pll_out_max) {
995 max_feed_div = feedback_div;
999 while (min_frac_feed_div < max_frac_feed_div) {
1000 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1001 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1002 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1003 current_freq = radeon_div(tmp, ref_div * post_div);
1005 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1006 if (freq < current_freq)
1009 error = freq - current_freq;
1011 error = abs(current_freq - freq);
1012 vco_diff = abs(vco - best_vco);
1014 if ((best_vco == 0 && error < best_error) ||
1016 ((best_error > 100 && error < best_error - 100) ||
1017 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1018 best_post_div = post_div;
1019 best_ref_div = ref_div;
1020 best_feedback_div = feedback_div;
1021 best_frac_feedback_div = frac_feedback_div;
1022 best_freq = current_freq;
1024 best_vco_diff = vco_diff;
1025 } else if (current_freq == freq) {
1026 if (best_freq == -1) {
1027 best_post_div = post_div;
1028 best_ref_div = ref_div;
1029 best_feedback_div = feedback_div;
1030 best_frac_feedback_div = frac_feedback_div;
1031 best_freq = current_freq;
1033 best_vco_diff = vco_diff;
1034 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1035 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1036 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1037 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1038 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1039 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1040 best_post_div = post_div;
1041 best_ref_div = ref_div;
1042 best_feedback_div = feedback_div;
1043 best_frac_feedback_div = frac_feedback_div;
1044 best_freq = current_freq;
1046 best_vco_diff = vco_diff;
1049 if (current_freq < freq)
1050 min_frac_feed_div = frac_feedback_div + 1;
1052 max_frac_feed_div = frac_feedback_div;
1054 if (current_freq < freq)
1055 min_feed_div = feedback_div + 1;
1057 max_feed_div = feedback_div;
1062 *dot_clock_p = best_freq / 10000;
1063 *fb_div_p = best_feedback_div;
1064 *frac_fb_div_p = best_frac_feedback_div;
1065 *ref_div_p = best_ref_div;
1066 *post_div_p = best_post_div;
1067 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1069 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1070 best_ref_div, best_post_div);
1074 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1076 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1078 if (radeon_fb->obj) {
1079 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1081 drm_framebuffer_cleanup(fb);
1085 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1086 struct drm_file *file_priv,
1087 unsigned int *handle)
1089 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1091 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1094 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1095 .destroy = radeon_user_framebuffer_destroy,
1096 .create_handle = radeon_user_framebuffer_create_handle,
1100 radeon_framebuffer_init(struct drm_device *dev,
1101 struct radeon_framebuffer *rfb,
1102 struct drm_mode_fb_cmd *mode_cmd,
1103 struct drm_gem_object *obj)
1106 drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1107 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1110 static struct drm_framebuffer *
1111 radeon_user_framebuffer_create(struct drm_device *dev,
1112 struct drm_file *file_priv,
1113 struct drm_mode_fb_cmd *mode_cmd)
1115 struct drm_gem_object *obj;
1116 struct radeon_framebuffer *radeon_fb;
1118 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
1120 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1121 "can't create framebuffer\n", mode_cmd->handle);
1122 return ERR_PTR(-ENOENT);
1125 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1126 if (radeon_fb == NULL)
1127 return ERR_PTR(-ENOMEM);
1129 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1131 return &radeon_fb->base;
1134 static void radeon_output_poll_changed(struct drm_device *dev)
1136 struct radeon_device *rdev = dev->dev_private;
1137 radeon_fb_output_poll_changed(rdev);
1140 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1141 .fb_create = radeon_user_framebuffer_create,
1142 .output_poll_changed = radeon_output_poll_changed
1145 struct drm_prop_enum_list {
1150 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1155 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1156 { { TV_STD_NTSC, "ntsc" },
1157 { TV_STD_PAL, "pal" },
1158 { TV_STD_PAL_M, "pal-m" },
1159 { TV_STD_PAL_60, "pal-60" },
1160 { TV_STD_NTSC_J, "ntsc-j" },
1161 { TV_STD_SCART_PAL, "scart-pal" },
1162 { TV_STD_PAL_CN, "pal-cn" },
1163 { TV_STD_SECAM, "secam" },
1166 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1167 { { UNDERSCAN_OFF, "off" },
1168 { UNDERSCAN_ON, "on" },
1169 { UNDERSCAN_AUTO, "auto" },
1172 static int radeon_modeset_create_props(struct radeon_device *rdev)
1176 if (rdev->is_atom_bios) {
1177 rdev->mode_info.coherent_mode_property =
1178 drm_property_create(rdev->ddev,
1179 DRM_MODE_PROP_RANGE,
1181 if (!rdev->mode_info.coherent_mode_property)
1184 rdev->mode_info.coherent_mode_property->values[0] = 0;
1185 rdev->mode_info.coherent_mode_property->values[1] = 1;
1188 if (!ASIC_IS_AVIVO(rdev)) {
1189 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1190 rdev->mode_info.tmds_pll_property =
1191 drm_property_create(rdev->ddev,
1194 for (i = 0; i < sz; i++) {
1195 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
1197 radeon_tmds_pll_enum_list[i].type,
1198 radeon_tmds_pll_enum_list[i].name);
1202 rdev->mode_info.load_detect_property =
1203 drm_property_create(rdev->ddev,
1204 DRM_MODE_PROP_RANGE,
1205 "load detection", 2);
1206 if (!rdev->mode_info.load_detect_property)
1208 rdev->mode_info.load_detect_property->values[0] = 0;
1209 rdev->mode_info.load_detect_property->values[1] = 1;
1211 drm_mode_create_scaling_mode_property(rdev->ddev);
1213 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1214 rdev->mode_info.tv_std_property =
1215 drm_property_create(rdev->ddev,
1218 for (i = 0; i < sz; i++) {
1219 drm_property_add_enum(rdev->mode_info.tv_std_property,
1221 radeon_tv_std_enum_list[i].type,
1222 radeon_tv_std_enum_list[i].name);
1225 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1226 rdev->mode_info.underscan_property =
1227 drm_property_create(rdev->ddev,
1230 for (i = 0; i < sz; i++) {
1231 drm_property_add_enum(rdev->mode_info.underscan_property,
1233 radeon_underscan_enum_list[i].type,
1234 radeon_underscan_enum_list[i].name);
1237 rdev->mode_info.underscan_hborder_property =
1238 drm_property_create(rdev->ddev,
1239 DRM_MODE_PROP_RANGE,
1240 "underscan hborder", 2);
1241 if (!rdev->mode_info.underscan_hborder_property)
1243 rdev->mode_info.underscan_hborder_property->values[0] = 0;
1244 rdev->mode_info.underscan_hborder_property->values[1] = 128;
1246 rdev->mode_info.underscan_vborder_property =
1247 drm_property_create(rdev->ddev,
1248 DRM_MODE_PROP_RANGE,
1249 "underscan vborder", 2);
1250 if (!rdev->mode_info.underscan_vborder_property)
1252 rdev->mode_info.underscan_vborder_property->values[0] = 0;
1253 rdev->mode_info.underscan_vborder_property->values[1] = 128;
1258 void radeon_update_display_priority(struct radeon_device *rdev)
1260 /* adjustment options for the display watermarks */
1261 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1262 /* set display priority to high for r3xx, rv515 chips
1263 * this avoids flickering due to underflow to the
1264 * display controllers during heavy acceleration.
1265 * Don't force high on rs4xx igp chips as it seems to
1266 * affect the sound card. See kernel bug 15982.
1268 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1269 !(rdev->flags & RADEON_IS_IGP))
1270 rdev->disp_priority = 2;
1272 rdev->disp_priority = 0;
1274 rdev->disp_priority = radeon_disp_priority;
1278 int radeon_modeset_init(struct radeon_device *rdev)
1283 drm_mode_config_init(rdev->ddev);
1284 rdev->mode_info.mode_config_initialized = true;
1286 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1288 if (ASIC_IS_DCE5(rdev)) {
1289 rdev->ddev->mode_config.max_width = 16384;
1290 rdev->ddev->mode_config.max_height = 16384;
1291 } else if (ASIC_IS_AVIVO(rdev)) {
1292 rdev->ddev->mode_config.max_width = 8192;
1293 rdev->ddev->mode_config.max_height = 8192;
1295 rdev->ddev->mode_config.max_width = 4096;
1296 rdev->ddev->mode_config.max_height = 4096;
1299 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1301 ret = radeon_modeset_create_props(rdev);
1306 /* init i2c buses */
1307 radeon_i2c_init(rdev);
1309 /* check combios for a valid hardcoded EDID - Sun servers */
1310 if (!rdev->is_atom_bios) {
1311 /* check for hardcoded EDID in BIOS */
1312 radeon_combios_check_hardcoded_edid(rdev);
1315 /* allocate crtcs */
1316 for (i = 0; i < rdev->num_crtc; i++) {
1317 radeon_crtc_init(rdev->ddev, i);
1320 /* okay we should have all the bios connectors */
1321 ret = radeon_setup_enc_conn(rdev->ddev);
1327 if (rdev->is_atom_bios)
1328 radeon_atom_encoder_init(rdev);
1330 /* initialize hpd */
1331 radeon_hpd_init(rdev);
1333 /* Initialize power management */
1334 radeon_pm_init(rdev);
1336 radeon_fbdev_init(rdev);
1337 drm_kms_helper_poll_init(rdev->ddev);
1342 void radeon_modeset_fini(struct radeon_device *rdev)
1344 radeon_fbdev_fini(rdev);
1345 kfree(rdev->mode_info.bios_hardcoded_edid);
1346 radeon_pm_fini(rdev);
1348 if (rdev->mode_info.mode_config_initialized) {
1349 drm_kms_helper_poll_fini(rdev->ddev);
1350 radeon_hpd_fini(rdev);
1351 drm_mode_config_cleanup(rdev->ddev);
1352 rdev->mode_info.mode_config_initialized = false;
1354 /* free i2c buses */
1355 radeon_i2c_fini(rdev);
1358 static bool is_hdtv_mode(struct drm_display_mode *mode)
1360 /* try and guess if this is a tv or a monitor */
1361 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1362 (mode->vdisplay == 576) || /* 576p */
1363 (mode->vdisplay == 720) || /* 720p */
1364 (mode->vdisplay == 1080)) /* 1080p */
1370 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1371 struct drm_display_mode *mode,
1372 struct drm_display_mode *adjusted_mode)
1374 struct drm_device *dev = crtc->dev;
1375 struct radeon_device *rdev = dev->dev_private;
1376 struct drm_encoder *encoder;
1377 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1378 struct radeon_encoder *radeon_encoder;
1379 struct drm_connector *connector;
1380 struct radeon_connector *radeon_connector;
1382 u32 src_v = 1, dst_v = 1;
1383 u32 src_h = 1, dst_h = 1;
1385 radeon_crtc->h_border = 0;
1386 radeon_crtc->v_border = 0;
1388 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1389 if (encoder->crtc != crtc)
1391 radeon_encoder = to_radeon_encoder(encoder);
1392 connector = radeon_get_connector_for_encoder(encoder);
1393 radeon_connector = to_radeon_connector(connector);
1397 if (radeon_encoder->rmx_type == RMX_OFF)
1398 radeon_crtc->rmx_type = RMX_OFF;
1399 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1400 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1401 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1403 radeon_crtc->rmx_type = RMX_OFF;
1404 /* copy native mode */
1405 memcpy(&radeon_crtc->native_mode,
1406 &radeon_encoder->native_mode,
1407 sizeof(struct drm_display_mode));
1408 src_v = crtc->mode.vdisplay;
1409 dst_v = radeon_crtc->native_mode.vdisplay;
1410 src_h = crtc->mode.hdisplay;
1411 dst_h = radeon_crtc->native_mode.hdisplay;
1413 /* fix up for overscan on hdmi */
1414 if (ASIC_IS_AVIVO(rdev) &&
1415 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1416 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1417 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1418 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1419 is_hdtv_mode(mode)))) {
1420 if (radeon_encoder->underscan_hborder != 0)
1421 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1423 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1424 if (radeon_encoder->underscan_vborder != 0)
1425 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1427 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1428 radeon_crtc->rmx_type = RMX_FULL;
1429 src_v = crtc->mode.vdisplay;
1430 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1431 src_h = crtc->mode.hdisplay;
1432 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1436 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1437 /* WARNING: Right now this can't happen but
1438 * in the future we need to check that scaling
1439 * are consistent across different encoder
1440 * (ie all encoder can work with the same
1443 DRM_ERROR("Scaling not consistent across encoder.\n");
1448 if (radeon_crtc->rmx_type != RMX_OFF) {
1450 a.full = dfixed_const(src_v);
1451 b.full = dfixed_const(dst_v);
1452 radeon_crtc->vsc.full = dfixed_div(a, b);
1453 a.full = dfixed_const(src_h);
1454 b.full = dfixed_const(dst_h);
1455 radeon_crtc->hsc.full = dfixed_div(a, b);
1457 radeon_crtc->vsc.full = dfixed_const(1);
1458 radeon_crtc->hsc.full = dfixed_const(1);
1464 * Retrieve current video scanout position of crtc on a given gpu.
1466 * \param dev Device to query.
1467 * \param crtc Crtc to query.
1468 * \param *vpos Location where vertical scanout position should be stored.
1469 * \param *hpos Location where horizontal scanout position should go.
1471 * Returns vpos as a positive number while in active scanout area.
1472 * Returns vpos as a negative number inside vblank, counting the number
1473 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1474 * until start of active scanout / end of vblank."
1476 * \return Flags, or'ed together as follows:
1478 * DRM_SCANOUTPOS_VALID = Query successful.
1479 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1480 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1481 * this flag means that returned position may be offset by a constant but
1482 * unknown small number of scanlines wrt. real scanout position.
1485 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1487 u32 stat_crtc = 0, vbl = 0, position = 0;
1488 int vbl_start, vbl_end, vtotal, ret = 0;
1491 struct radeon_device *rdev = dev->dev_private;
1493 if (ASIC_IS_DCE4(rdev)) {
1495 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1496 EVERGREEN_CRTC0_REGISTER_OFFSET);
1497 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1498 EVERGREEN_CRTC0_REGISTER_OFFSET);
1499 ret |= DRM_SCANOUTPOS_VALID;
1502 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1503 EVERGREEN_CRTC1_REGISTER_OFFSET);
1504 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1505 EVERGREEN_CRTC1_REGISTER_OFFSET);
1506 ret |= DRM_SCANOUTPOS_VALID;
1509 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1510 EVERGREEN_CRTC2_REGISTER_OFFSET);
1511 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1512 EVERGREEN_CRTC2_REGISTER_OFFSET);
1513 ret |= DRM_SCANOUTPOS_VALID;
1516 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1517 EVERGREEN_CRTC3_REGISTER_OFFSET);
1518 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1519 EVERGREEN_CRTC3_REGISTER_OFFSET);
1520 ret |= DRM_SCANOUTPOS_VALID;
1523 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1524 EVERGREEN_CRTC4_REGISTER_OFFSET);
1525 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1526 EVERGREEN_CRTC4_REGISTER_OFFSET);
1527 ret |= DRM_SCANOUTPOS_VALID;
1530 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1531 EVERGREEN_CRTC5_REGISTER_OFFSET);
1532 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1533 EVERGREEN_CRTC5_REGISTER_OFFSET);
1534 ret |= DRM_SCANOUTPOS_VALID;
1536 } else if (ASIC_IS_AVIVO(rdev)) {
1538 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1539 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1540 ret |= DRM_SCANOUTPOS_VALID;
1543 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1544 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1545 ret |= DRM_SCANOUTPOS_VALID;
1548 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1550 /* Assume vbl_end == 0, get vbl_start from
1553 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1554 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1555 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1556 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1557 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1558 if (!(stat_crtc & 1))
1561 ret |= DRM_SCANOUTPOS_VALID;
1564 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1565 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1566 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1567 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1568 if (!(stat_crtc & 1))
1571 ret |= DRM_SCANOUTPOS_VALID;
1575 /* Decode into vertical and horizontal scanout position. */
1576 *vpos = position & 0x1fff;
1577 *hpos = (position >> 16) & 0x1fff;
1579 /* Valid vblank area boundaries from gpu retrieved? */
1582 ret |= DRM_SCANOUTPOS_ACCURATE;
1583 vbl_start = vbl & 0x1fff;
1584 vbl_end = (vbl >> 16) & 0x1fff;
1587 /* No: Fake something reasonable which gives at least ok results. */
1588 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1592 /* Test scanout position against vblank region. */
1593 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1596 /* Check if inside vblank area and apply corrective offsets:
1597 * vpos will then be >=0 in video scanout area, but negative
1598 * within vblank area, counting down the number of lines until
1602 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1603 if (in_vbl && (*vpos >= vbl_start)) {
1604 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1605 *vpos = *vpos - vtotal;
1608 /* Correct for shifted end of vbl at vbl_end. */
1609 *vpos = *vpos - vbl_end;
1613 ret |= DRM_SCANOUTPOS_INVBL;