drivers/gpu/drm/radeon/radeon_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <linux/efi.h>
  36 #include "radeon_reg.h"
  37 #include "radeon.h"
  38 #include "atom.h"
  39
  40 static const char radeon_family_name[][16] = {
  41         "R100",
  42         "RV100",
  43         "RS100",
  44         "RV200",
  45         "RS200",
  46         "R200",
  47         "RV250",
  48         "RS300",
  49         "RV280",
  50         "R300",
  51         "R350",
  52         "RV350",
  53         "RV380",
  54         "R420",
  55         "R423",
  56         "RV410",
  57         "RS400",
  58         "RS480",
  59         "RS600",
  60         "RS690",
  61         "RS740",
  62         "RV515",
  63         "R520",
  64         "RV530",
  65         "RV560",
  66         "RV570",
  67         "R580",
  68         "R600",
  69         "RV610",
  70         "RV630",
  71         "RV670",
  72         "RV620",
  73         "RV635",
  74         "RS780",
  75         "RS880",
  76         "RV770",
  77         "RV730",
  78         "RV710",
  79         "RV740",
  80         "CEDAR",
  81         "REDWOOD",
  82         "JUNIPER",
  83         "CYPRESS",
  84         "HEMLOCK",
  85         "PALM",
  86         "SUMO",
  87         "SUMO2",
  88         "BARTS",
  89         "TURKS",
  90         "CAICOS",
  91         "CAYMAN",
  92         "LAST",
  93 };
  94
  95 /*
  96  * Clear GPU surface registers.
  97  */
  98 void radeon_surface_init(struct radeon_device *rdev)
  99 {
 100         /* FIXME: check this out */
 101         if (rdev->family < CHIP_R600) {
 102                 int i;
 103
 104                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 105                         if (rdev->surface_regs[i].bo)
 106                                 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
 107                         else
 108                                 radeon_clear_surface_reg(rdev, i);
 109                 }
 110                 /* enable surfaces */
 111                 WREG32(RADEON_SURFACE_CNTL, 0);
 112         }
 113 }
 114
 115 /*
 116  * GPU scratch registers helpers function.
 117  */
 118 void radeon_scratch_init(struct radeon_device *rdev)
 119 {
 120         int i;
 121
 122         /* FIXME: check this out */
 123         if (rdev->family < CHIP_R300) {
 124                 rdev->scratch.num_reg = 5;
 125         } else {
 126                 rdev->scratch.num_reg = 7;
 127         }
 128         rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
 129         for (i = 0; i < rdev->scratch.num_reg; i++) {
 130                 rdev->scratch.free[i] = true;
 131                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
 132         }
 133 }
 134
 135 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
 136 {
 137         int i;
 138
 139         for (i = 0; i < rdev->scratch.num_reg; i++) {
 140                 if (rdev->scratch.free[i]) {
 141                         rdev->scratch.free[i] = false;
 142                         *reg = rdev->scratch.reg[i];
 143                         return 0;
 144                 }
 145         }
 146         return -EINVAL;
 147 }
 148
 149 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
 150 {
 151         int i;
 152
 153         for (i = 0; i < rdev->scratch.num_reg; i++) {
 154                 if (rdev->scratch.reg[i] == reg) {
 155                         rdev->scratch.free[i] = true;
 156                         return;
 157                 }
 158         }
 159 }
 160
 161 void radeon_wb_disable(struct radeon_device *rdev)
 162 {
 163         int r;
 164
 165         if (rdev->wb.wb_obj) {
 166                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 167                 if (unlikely(r != 0))
 168                         return;
 169                 radeon_bo_kunmap(rdev->wb.wb_obj);
 170                 radeon_bo_unpin(rdev->wb.wb_obj);
 171                 radeon_bo_unreserve(rdev->wb.wb_obj);
 172         }
 173         rdev->wb.enabled = false;
 174 }
 175
 176 void radeon_wb_fini(struct radeon_device *rdev)
 177 {
 178         radeon_wb_disable(rdev);
 179         if (rdev->wb.wb_obj) {
 180                 radeon_bo_unref(&rdev->wb.wb_obj);
 181                 rdev->wb.wb = NULL;
 182                 rdev->wb.wb_obj = NULL;
 183         }
 184 }
 185
 186 int radeon_wb_init(struct radeon_device *rdev)
 187 {
 188         int r;
 189
 190         if (rdev->wb.wb_obj == NULL) {
 191                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
 192                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
 193                 if (r) {
 194                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
 195                         return r;
 196                 }
 197         }
 198         r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 199         if (unlikely(r != 0)) {
 200                 radeon_wb_fini(rdev);
 201                 return r;
 202         }
 203         r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 204                           &rdev->wb.gpu_addr);
 205         if (r) {
 206                 radeon_bo_unreserve(rdev->wb.wb_obj);
 207                 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
 208                 radeon_wb_fini(rdev);
 209                 return r;
 210         }
 211         r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 212         radeon_bo_unreserve(rdev->wb.wb_obj);
 213         if (r) {
 214                 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
 215                 radeon_wb_fini(rdev);
 216                 return r;
 217         }
 218
 219         /* clear wb memory */
 220         memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
 221         /* disable event_write fences */
 222         rdev->wb.use_event = false;
 223         /* disabled via module param */
 224         if (radeon_no_wb == 1)
 225                 rdev->wb.enabled = false;
 226         else {
 227                 /* often unreliable on AGP */
 228                 if (rdev->flags & RADEON_IS_AGP) {
 229                         rdev->wb.enabled = false;
 230                 } else {
 231                         rdev->wb.enabled = true;
 232                         /* event_write fences are only available on r600+ */
 233                         if (rdev->family >= CHIP_R600)
 234                                 rdev->wb.use_event = true;
 235                 }
 236         }
 237         /* always use writeback/events on NI */
 238         if (ASIC_IS_DCE5(rdev)) {
 239                 rdev->wb.enabled = true;
 240                 rdev->wb.use_event = true;
 241         }
 242
 243         dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
 244
 245         return 0;
 246 }
 247
 248 /**
 249  * radeon_vram_location - try to find VRAM location
 250  * @rdev: radeon device structure holding all necessary informations
 251  * @mc: memory controller structure holding memory informations
 252  * @base: base address at which to put VRAM
 253  *
 254  * Function will place try to place VRAM at base address provided
 255  * as parameter (which is so far either PCI aperture address or
 256  * for IGP TOM base address).
 257  *
 258  * If there is not enough space to fit the unvisible VRAM in the 32bits
 259  * address space then we limit the VRAM size to the aperture.
 260  *
 261  * If we are using AGP and if the AGP aperture doesn't allow us to have
 262  * room for all the VRAM than we restrict the VRAM to the PCI aperture
 263  * size and print a warning.
 264  *
 265  * This function will never fails, worst case are limiting VRAM.
 266  *
 267  * Note: GTT start, end, size should be initialized before calling this
 268  * function on AGP platform.
 269  *
 270  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 271  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 272  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 273  * not IGP.
 274  *
 275  * Note: we use mc_vram_size as on some board we need to program the mc to
 276  * cover the whole aperture even if VRAM size is inferior to aperture size
 277  * Novell bug 204882 + along with lots of ubuntu ones
 278  *
 279  * Note: when limiting vram it's safe to overwritte real_vram_size because
 280  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 281  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 282  * ones)
 283  *
 284  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 285  * explicitly check for that thought.
 286  *
 287  * FIXME: when reducing VRAM size align new size on power of 2.
 288  */
 289 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
 290 {
 291         mc->vram_start = base;
 292         if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
 293                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 294                 mc->real_vram_size = mc->aper_size;
 295                 mc->mc_vram_size = mc->aper_size;
 296         }
 297         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 298         if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
 299                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 300                 mc->real_vram_size = mc->aper_size;
 301                 mc->mc_vram_size = mc->aper_size;
 302         }
 303         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 304         dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 305                         mc->mc_vram_size >> 20, mc->vram_start,
 306                         mc->vram_end, mc->real_vram_size >> 20);
 307 }
 308
 309 /**
 310  * radeon_gtt_location - try to find GTT location
 311  * @rdev: radeon device structure holding all necessary informations
 312  * @mc: memory controller structure holding memory informations
 313  *
 314  * Function will place try to place GTT before or after VRAM.
 315  *
 316  * If GTT size is bigger than space left then we ajust GTT size.
 317  * Thus function will never fails.
 318  *
 319  * FIXME: when reducing GTT size align new size on power of 2.
 320  */
 321 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 322 {
 323         u64 size_af, size_bf;
 324
 325         size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 326         size_bf = mc->vram_start & ~mc->gtt_base_align;
 327         if (size_bf > size_af) {
 328                 if (mc->gtt_size > size_bf) {
 329                         dev_warn(rdev->dev, "limiting GTT\n");
 330                         mc->gtt_size = size_bf;
 331                 }
 332                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 333         } else {
 334                 if (mc->gtt_size > size_af) {
 335                         dev_warn(rdev->dev, "limiting GTT\n");
 336                         mc->gtt_size = size_af;
 337                 }
 338                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 339         }
 340         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 341         dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 342                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 343 }
 344
 345 /*
 346  * GPU helpers function.
 347  */
 348 bool radeon_card_posted(struct radeon_device *rdev)
 349 {
 350         uint32_t reg;
 351
 352         if (efi_enabled && rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)
 353                 return false;
 354
 355         /* first check CRTCs */
 356         if (ASIC_IS_DCE41(rdev)) {
 357                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 358                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 359                 if (reg & EVERGREEN_CRTC_MASTER_EN)
 360                         return true;
 361         } else if (ASIC_IS_DCE4(rdev)) {
 362                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 363                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
 364                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
 365                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
 366                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
 367                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 368                 if (reg & EVERGREEN_CRTC_MASTER_EN)
 369                         return true;
 370         } else if (ASIC_IS_AVIVO(rdev)) {
 371                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 372                       RREG32(AVIVO_D2CRTC_CONTROL);
 373                 if (reg & AVIVO_CRTC_EN) {
 374                         return true;
 375                 }
 376         } else {
 377                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 378                       RREG32(RADEON_CRTC2_GEN_CNTL);
 379                 if (reg & RADEON_CRTC_EN) {
 380                         return true;
 381                 }
 382         }
 383
 384         /* then check MEM_SIZE, in case the crtcs are off */
 385         if (rdev->family >= CHIP_R600)
 386                 reg = RREG32(R600_CONFIG_MEMSIZE);
 387         else
 388                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
 389
 390         if (reg)
 391                 return true;
 392
 393         return false;
 394
 395 }
 396
 397 void radeon_update_bandwidth_info(struct radeon_device *rdev)
 398 {
 399         fixed20_12 a;
 400         u32 sclk = rdev->pm.current_sclk;
 401         u32 mclk = rdev->pm.current_mclk;
 402
 403         /* sclk/mclk in Mhz */
 404         a.full = dfixed_const(100);
 405         rdev->pm.sclk.full = dfixed_const(sclk);
 406         rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
 407         rdev->pm.mclk.full = dfixed_const(mclk);
 408         rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 409
 410         if (rdev->flags & RADEON_IS_IGP) {
 411                 a.full = dfixed_const(16);
 412                 /* core_bandwidth = sclk(Mhz) * 16 */
 413                 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
 414         }
 415 }
 416
 417 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 418 {
 419         if (radeon_card_posted(rdev))
 420                 return true;
 421
 422         if (rdev->bios) {
 423                 DRM_INFO("GPU not posted. posting now...\n");
 424                 if (rdev->is_atom_bios)
 425                         atom_asic_init(rdev->mode_info.atom_context);
 426                 else
 427                         radeon_combios_asic_init(rdev->ddev);
 428                 return true;
 429         } else {
 430                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 431                 return false;
 432         }
 433 }
 434
 435 int radeon_dummy_page_init(struct radeon_device *rdev)
 436 {
 437         if (rdev->dummy_page.page)
 438                 return 0;
 439         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 440         if (rdev->dummy_page.page == NULL)
 441                 return -ENOMEM;
 442         rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 443                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 444         if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
 445                 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 446                 __free_page(rdev->dummy_page.page);
 447                 rdev->dummy_page.page = NULL;
 448                 return -ENOMEM;
 449         }
 450         return 0;
 451 }
 452
 453 void radeon_dummy_page_fini(struct radeon_device *rdev)
 454 {
 455         if (rdev->dummy_page.page == NULL)
 456                 return;
 457         pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 458                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 459         __free_page(rdev->dummy_page.page);
 460         rdev->dummy_page.page = NULL;
 461 }
 462
 463
 464 /* ATOM accessor methods */
 465 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 466 {
 467         struct radeon_device *rdev = info->dev->dev_private;
 468         uint32_t r;
 469
 470         r = rdev->pll_rreg(rdev, reg);
 471         return r;
 472 }
 473
 474 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 475 {
 476         struct radeon_device *rdev = info->dev->dev_private;
 477
 478         rdev->pll_wreg(rdev, reg, val);
 479 }
 480
 481 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 482 {
 483         struct radeon_device *rdev = info->dev->dev_private;
 484         uint32_t r;
 485
 486         r = rdev->mc_rreg(rdev, reg);
 487         return r;
 488 }
 489
 490 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 491 {
 492         struct radeon_device *rdev = info->dev->dev_private;
 493
 494         rdev->mc_wreg(rdev, reg, val);
 495 }
 496
 497 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 498 {
 499         struct radeon_device *rdev = info->dev->dev_private;
 500
 501         WREG32(reg*4, val);
 502 }
 503
 504 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 505 {
 506         struct radeon_device *rdev = info->dev->dev_private;
 507         uint32_t r;
 508
 509         r = RREG32(reg*4);
 510         return r;
 511 }
 512
 513 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 514 {
 515         struct radeon_device *rdev = info->dev->dev_private;
 516
 517         WREG32_IO(reg*4, val);
 518 }
 519
 520 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 521 {
 522         struct radeon_device *rdev = info->dev->dev_private;
 523         uint32_t r;
 524
 525         r = RREG32_IO(reg*4);
 526         return r;
 527 }
 528
 529 int radeon_atombios_init(struct radeon_device *rdev)
 530 {
 531         struct card_info *atom_card_info =
 532             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 533
 534         if (!atom_card_info)
 535                 return -ENOMEM;
 536
 537         rdev->mode_info.atom_card_info = atom_card_info;
 538         atom_card_info->dev = rdev->ddev;
 539         atom_card_info->reg_read = cail_reg_read;
 540         atom_card_info->reg_write = cail_reg_write;
 541         /* needed for iio ops */
 542         if (rdev->rio_mem) {
 543                 atom_card_info->ioreg_read = cail_ioreg_read;
 544                 atom_card_info->ioreg_write = cail_ioreg_write;
 545         } else {
 546                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 547                 atom_card_info->ioreg_read = cail_reg_read;
 548                 atom_card_info->ioreg_write = cail_reg_write;
 549         }
 550         atom_card_info->mc_read = cail_mc_read;
 551         atom_card_info->mc_write = cail_mc_write;
 552         atom_card_info->pll_read = cail_pll_read;
 553         atom_card_info->pll_write = cail_pll_write;
 554
 555         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 556         mutex_init(&rdev->mode_info.atom_context->mutex);
 557         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 558         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
 559         return 0;
 560 }
 561
 562 void radeon_atombios_fini(struct radeon_device *rdev)
 563 {
 564         if (rdev->mode_info.atom_context) {
 565                 kfree(rdev->mode_info.atom_context->scratch);
 566                 kfree(rdev->mode_info.atom_context);
 567         }
 568         kfree(rdev->mode_info.atom_card_info);
 569 }
 570
 571 int radeon_combios_init(struct radeon_device *rdev)
 572 {
 573         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
 574         return 0;
 575 }
 576
 577 void radeon_combios_fini(struct radeon_device *rdev)
 578 {
 579 }
 580
 581 /* if we get transitioned to only one device, tak VGA back */
 582 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
 583 {
 584         struct radeon_device *rdev = cookie;
 585         radeon_vga_set_state(rdev, state);
 586         if (state)
 587                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 588                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 589         else
 590                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 591 }
 592
 593 void radeon_check_arguments(struct radeon_device *rdev)
 594 {
 595         /* vramlimit must be a power of two */
 596         switch (radeon_vram_limit) {
 597         case 0:
 598         case 4:
 599         case 8:
 600         case 16:
 601         case 32:
 602         case 64:
 603         case 128:
 604         case 256:
 605         case 512:
 606         case 1024:
 607         case 2048:
 608         case 4096:
 609                 break;
 610         default:
 611                 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
 612                                 radeon_vram_limit);
 613                 radeon_vram_limit = 0;
 614                 break;
 615         }
 616         radeon_vram_limit = radeon_vram_limit << 20;
 617         /* gtt size must be power of two and greater or equal to 32M */
 618         switch (radeon_gart_size) {
 619         case 4:
 620         case 8:
 621         case 16:
 622                 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
 623                                 radeon_gart_size);
 624                 radeon_gart_size = 512;
 625                 break;
 626         case 32:
 627         case 64:
 628         case 128:
 629         case 256:
 630         case 512:
 631         case 1024:
 632         case 2048:
 633         case 4096:
 634                 break;
 635         default:
 636                 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
 637                                 radeon_gart_size);
 638                 radeon_gart_size = 512;
 639                 break;
 640         }
 641         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 642         /* AGP mode can only be -1, 1, 2, 4, 8 */
 643         switch (radeon_agpmode) {
 644         case -1:
 645         case 0:
 646         case 1:
 647         case 2:
 648         case 4:
 649         case 8:
 650                 break;
 651         default:
 652                 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
 653                                 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
 654                 radeon_agpmode = 0;
 655                 break;
 656         }
 657 }
 658
 659 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 660 {
 661         struct drm_device *dev = pci_get_drvdata(pdev);
 662         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 663         if (state == VGA_SWITCHEROO_ON) {
 664                 printk(KERN_INFO "radeon: switched on\n");
 665                 /* don't suspend or resume card normally */
 666                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 667                 radeon_resume_kms(dev);
 668                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 669                 drm_kms_helper_poll_enable(dev);
 670         } else {
 671                 printk(KERN_INFO "radeon: switched off\n");
 672                 drm_kms_helper_poll_disable(dev);
 673                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 674                 radeon_suspend_kms(dev, pmm);
 675                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 676         }
 677 }
 678
 679 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
 680 {
 681         struct drm_device *dev = pci_get_drvdata(pdev);
 682         bool can_switch;
 683
 684         spin_lock(&dev->count_lock);
 685         can_switch = (dev->open_count == 0);
 686         spin_unlock(&dev->count_lock);
 687         return can_switch;
 688 }
 689
 690
 691 int radeon_device_init(struct radeon_device *rdev,
 692                        struct drm_device *ddev,
 693                        struct pci_dev *pdev,
 694                        uint32_t flags)
 695 {
 696         int r, i;
 697         int dma_bits;
 698
 699         rdev->shutdown = false;
 700         rdev->dev = &pdev->dev;
 701         rdev->ddev = ddev;
 702         rdev->pdev = pdev;
 703         rdev->flags = flags;
 704         rdev->family = flags & RADEON_FAMILY_MASK;
 705         rdev->is_atom_bios = false;
 706         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
 707         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 708         rdev->gpu_lockup = false;
 709         rdev->accel_working = false;
 710
 711         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
 712                 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
 713                 pdev->subsystem_vendor, pdev->subsystem_device);
 714
 715         /* mutex initialization are all done here so we
 716          * can recall function without having locking issues */
 717         mutex_init(&rdev->cs_mutex);
 718         mutex_init(&rdev->ib_pool.mutex);
 719         mutex_init(&rdev->cp.mutex);
 720         mutex_init(&rdev->dc_hw_i2c_mutex);
 721         if (rdev->family >= CHIP_R600)
 722                 spin_lock_init(&rdev->ih.lock);
 723         mutex_init(&rdev->gem.mutex);
 724         mutex_init(&rdev->pm.mutex);
 725         mutex_init(&rdev->vram_mutex);
 726         rwlock_init(&rdev->fence_drv.lock);
 727         INIT_LIST_HEAD(&rdev->gem.objects);
 728         init_waitqueue_head(&rdev->irq.vblank_queue);
 729         init_waitqueue_head(&rdev->irq.idle_queue);
 730
 731         /* Set asic functions */
 732         r = radeon_asic_init(rdev);
 733         if (r)
 734                 return r;
 735         radeon_check_arguments(rdev);
 736
 737         /* all of the newer IGP chips have an internal gart
 738          * However some rs4xx report as AGP, so remove that here.
 739          */
 740         if ((rdev->family >= CHIP_RS400) &&
 741             (rdev->flags & RADEON_IS_IGP)) {
 742                 rdev->flags &= ~RADEON_IS_AGP;
 743         }
 744
 745         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
 746                 radeon_agp_disable(rdev);
 747         }
 748
 749         /* set DMA mask + need_dma32 flags.
 750          * PCIE - can handle 40-bits.
 751          * IGP - can handle 40-bits (in theory)
 752          * AGP - generally dma32 is safest
 753          * PCI - only dma32
 754          */
 755         rdev->need_dma32 = false;
 756         if (rdev->flags & RADEON_IS_AGP)
 757                 rdev->need_dma32 = true;
 758         if (rdev->flags & RADEON_IS_PCI)
 759                 rdev->need_dma32 = true;
 760
 761         dma_bits = rdev->need_dma32 ? 32 : 40;
 762         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 763         if (r) {
 764                 rdev->need_dma32 = true;
 765                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
 766         }
 767
 768         /* Registers mapping */
 769         /* TODO: block userspace mapping of io register */
 770         rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
 771         rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
 772         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
 773         if (rdev->rmmio == NULL) {
 774                 return -ENOMEM;
 775         }
 776         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
 777         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 778
 779         /* io port mapping */
 780         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 781                 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
 782                         rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
 783                         rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
 784                         break;
 785                 }
 786         }
 787         if (rdev->rio_mem == NULL)
 788                 DRM_ERROR("Unable to find PCI I/O BAR\n");
 789
 790         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
 791         /* this will fail for cards that aren't VGA class devices, just
 792          * ignore it */
 793         vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
 794         vga_switcheroo_register_client(rdev->pdev,
 795                                        radeon_switcheroo_set_state,
 796                                        NULL,
 797                                        radeon_switcheroo_can_switch);
 798
 799         r = radeon_init(rdev);
 800         if (r)
 801                 return r;
 802
 803         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
 804                 /* Acceleration not working on AGP card try again
 805                  * with fallback to PCI or PCIE GART
 806                  */
 807                 radeon_asic_reset(rdev);
 808                 radeon_fini(rdev);
 809                 radeon_agp_disable(rdev);
 810                 r = radeon_init(rdev);
 811                 if (r)
 812                         return r;
 813         }
 814         if (radeon_testing) {
 815                 radeon_test_moves(rdev);
 816         }
 817         if (radeon_benchmarking) {
 818                 radeon_benchmark(rdev);
 819         }
 820         return 0;
 821 }
 822
 823 void radeon_device_fini(struct radeon_device *rdev)
 824 {
 825         DRM_INFO("radeon: finishing device.\n");
 826         rdev->shutdown = true;
 827         /* evict vram memory */
 828         radeon_bo_evict_vram(rdev);
 829         radeon_fini(rdev);
 830         vga_switcheroo_unregister_client(rdev->pdev);
 831         vga_client_register(rdev->pdev, NULL, NULL, NULL);
 832         if (rdev->rio_mem)
 833                 pci_iounmap(rdev->pdev, rdev->rio_mem);
 834         rdev->rio_mem = NULL;
 835         iounmap(rdev->rmmio);
 836         rdev->rmmio = NULL;
 837 }
 838
 839
 840 /*
 841  * Suspend & resume.
 842  */
 843 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 844 {
 845         struct radeon_device *rdev;
 846         struct drm_crtc *crtc;
 847         struct drm_connector *connector;
 848         int r;
 849
 850         if (dev == NULL || dev->dev_private == NULL) {
 851                 return -ENODEV;
 852         }
 853         if (state.event == PM_EVENT_PRETHAW) {
 854                 return 0;
 855         }
 856         rdev = dev->dev_private;
 857
 858         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 859                 return 0;
 860
 861         /* turn off display hw */
 862         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 863                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
 864         }
 865
 866         /* unpin the front buffers */
 867         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 868                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
 869                 struct radeon_bo *robj;
 870
 871                 if (rfb == NULL || rfb->obj == NULL) {
 872                         continue;
 873                 }
 874                 robj = gem_to_radeon_bo(rfb->obj);
 875                 /* don't unpin kernel fb objects */
 876                 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
 877                         r = radeon_bo_reserve(robj, false);
 878                         if (r == 0) {
 879                                 radeon_bo_unpin(robj);
 880                                 radeon_bo_unreserve(robj);
 881                         }
 882                 }
 883         }
 884         /* evict vram memory */
 885         radeon_bo_evict_vram(rdev);
 886         /* wait for gpu to finish processing current batch */
 887         radeon_fence_wait_last(rdev);
 888
 889         radeon_save_bios_scratch_regs(rdev);
 890
 891         radeon_pm_suspend(rdev);
 892         radeon_suspend(rdev);
 893         radeon_hpd_fini(rdev);
 894         /* evict remaining vram memory */
 895         radeon_bo_evict_vram(rdev);
 896
 897         radeon_agp_suspend(rdev);
 898
 899         pci_save_state(dev->pdev);
 900         if (state.event == PM_EVENT_SUSPEND) {
 901                 /* Shut down the device */
 902                 pci_disable_device(dev->pdev);
 903                 pci_set_power_state(dev->pdev, PCI_D3hot);
 904         }
 905         console_lock();
 906         radeon_fbdev_set_suspend(rdev, 1);
 907         console_unlock();
 908         return 0;
 909 }
 910
 911 int radeon_resume_kms(struct drm_device *dev)
 912 {
 913         struct drm_connector *connector;
 914         struct radeon_device *rdev = dev->dev_private;
 915
 916         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 917                 return 0;
 918
 919         console_lock();
 920         pci_set_power_state(dev->pdev, PCI_D0);
 921         pci_restore_state(dev->pdev);
 922         if (pci_enable_device(dev->pdev)) {
 923                 console_unlock();
 924                 return -1;
 925         }
 926         pci_set_master(dev->pdev);
 927         /* resume AGP if in use */
 928         radeon_agp_resume(rdev);
 929         radeon_resume(rdev);
 930         radeon_pm_resume(rdev);
 931         radeon_restore_bios_scratch_regs(rdev);
 932
 933         radeon_fbdev_set_suspend(rdev, 0);
 934         console_unlock();
 935
 936         /* init dig PHYs */
 937         if (rdev->is_atom_bios)
 938                 radeon_atom_encoder_init(rdev);
 939         /* reset hpd state */
 940         radeon_hpd_init(rdev);
 941         /* blat the mode back in */
 942         drm_helper_resume_force_mode(dev);
 943         /* turn on display hw */
 944         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 945                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
 946         }
 947         return 0;
 948 }
 949
 950 int radeon_gpu_reset(struct radeon_device *rdev)
 951 {
 952         int r;
 953         int resched;
 954
 955         radeon_save_bios_scratch_regs(rdev);
 956         /* block TTM */
 957         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 958         radeon_suspend(rdev);
 959
 960         r = radeon_asic_reset(rdev);
 961         if (!r) {
 962                 dev_info(rdev->dev, "GPU reset succeed\n");
 963                 radeon_resume(rdev);
 964                 radeon_restore_bios_scratch_regs(rdev);
 965                 drm_helper_resume_force_mode(rdev->ddev);
 966                 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 967                 return 0;
 968         }
 969         /* bad news, how to tell it to userspace ? */
 970         dev_info(rdev->dev, "GPU reset failed\n");
 971         return r;
 972 }
 973
 974
 975 /*
 976  * Debugfs
 977  */
 978 struct radeon_debugfs {
 979         struct drm_info_list    *files;
 980         unsigned                num_files;
 981 };
 982 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
 983 static unsigned _radeon_debugfs_count = 0;
 984
 985 int radeon_debugfs_add_files(struct radeon_device *rdev,
 986                              struct drm_info_list *files,
 987                              unsigned nfiles)
 988 {
 989         unsigned i;
 990
 991         for (i = 0; i < _radeon_debugfs_count; i++) {
 992                 if (_radeon_debugfs[i].files == files) {
 993                         /* Already registered */
 994                         return 0;
 995                 }
 996         }
 997         if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
 998                 DRM_ERROR("Reached maximum number of debugfs files.\n");
 999                 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
1000                 return -EINVAL;
1001         }
1002         _radeon_debugfs[_radeon_debugfs_count].files = files;
1003         _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
1004         _radeon_debugfs_count++;
1005 #if defined(CONFIG_DEBUG_FS)
1006         drm_debugfs_create_files(files, nfiles,
1007                                  rdev->ddev->control->debugfs_root,
1008                                  rdev->ddev->control);
1009         drm_debugfs_create_files(files, nfiles,
1010                                  rdev->ddev->primary->debugfs_root,
1011                                  rdev->ddev->primary);
1012 #endif
1013         return 0;
1014 }
1015
1016 #if defined(CONFIG_DEBUG_FS)
1017 int radeon_debugfs_init(struct drm_minor *minor)
1018 {
1019         return 0;
1020 }
1021
1022 void radeon_debugfs_cleanup(struct drm_minor *minor)
1023 {
1024         unsigned i;
1025
1026         for (i = 0; i < _radeon_debugfs_count; i++) {
1027                 drm_debugfs_remove_files(_radeon_debugfs[i].files,
1028                                          _radeon_debugfs[i].num_files, minor);
1029         }
1030 }
1031 #endif