2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include "radeon_drm.h"
29 #include "radeon_reg.h"
32 void r100_cs_dump_packet(struct radeon_cs_parser *p,
33 struct radeon_cs_packet *pkt);
35 int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
37 struct drm_device *ddev = p->rdev->ddev;
38 struct radeon_cs_chunk *chunk;
42 if (p->chunk_relocs_idx == -1) {
45 chunk = &p->chunks[p->chunk_relocs_idx];
46 /* FIXME: we assume that each relocs use 4 dwords */
47 p->nrelocs = chunk->length_dw / 4;
48 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
49 if (p->relocs_ptr == NULL) {
52 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
53 if (p->relocs == NULL) {
56 for (i = 0; i < p->nrelocs; i++) {
57 struct drm_radeon_cs_reloc *r;
60 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
61 for (j = 0; j < i; j++) {
62 if (r->handle == p->relocs[j].handle) {
63 p->relocs_ptr[i] = &p->relocs[j];
69 p->relocs[i].gobj = drm_gem_object_lookup(ddev,
72 if (p->relocs[i].gobj == NULL) {
73 DRM_ERROR("gem object lookup failed 0x%x\n",
77 p->relocs_ptr[i] = &p->relocs[i];
78 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
79 p->relocs[i].lobj.bo = p->relocs[i].robj;
80 p->relocs[i].lobj.wdomain = r->write_domain;
81 p->relocs[i].lobj.rdomain = r->read_domains;
82 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
83 p->relocs[i].handle = r->handle;
84 p->relocs[i].flags = r->flags;
85 radeon_bo_list_add_object(&p->relocs[i].lobj,
89 p->relocs[i].handle = 0;
91 return radeon_bo_list_validate(&p->validated);
94 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
96 p->priority = priority;
100 DRM_ERROR("unknown ring id: %d\n", ring);
102 case RADEON_CS_RING_GFX:
103 p->ring = RADEON_RING_TYPE_GFX_INDEX;
105 case RADEON_CS_RING_COMPUTE:
107 p->ring = RADEON_RING_TYPE_GFX_INDEX;
113 static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
115 bool sync_to_ring[RADEON_NUM_RINGS] = { };
118 for (i = 0; i < p->nrelocs; i++) {
119 if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
122 if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) {
123 struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
124 if (!radeon_fence_signaled(fence)) {
125 sync_to_ring[fence->ring] = true;
130 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
131 /* no need to sync to our own or unused rings */
132 if (i == p->ring || !sync_to_ring[i] || !p->rdev->ring[i].ready)
135 if (!p->ib->fence->semaphore) {
136 r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
141 r = radeon_ring_lock(p->rdev, &p->rdev->ring[i], 3);
144 radeon_semaphore_emit_signal(p->rdev, i, p->ib->fence->semaphore);
145 radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[i]);
147 r = radeon_ring_lock(p->rdev, &p->rdev->ring[p->ring], 3);
150 radeon_semaphore_emit_wait(p->rdev, p->ring, p->ib->fence->semaphore);
151 radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[p->ring]);
156 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
158 struct drm_radeon_cs *cs = data;
159 uint64_t *chunk_array_ptr;
161 u32 ring = RADEON_CS_RING_GFX;
164 if (!cs->num_chunks) {
168 INIT_LIST_HEAD(&p->validated);
170 p->chunk_ib_idx = -1;
171 p->chunk_relocs_idx = -1;
172 p->chunk_flags_idx = -1;
173 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
174 if (p->chunks_array == NULL) {
177 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
178 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
179 sizeof(uint64_t)*cs->num_chunks)) {
183 p->nchunks = cs->num_chunks;
184 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
185 if (p->chunks == NULL) {
188 for (i = 0; i < p->nchunks; i++) {
189 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
190 struct drm_radeon_cs_chunk user_chunk;
191 uint32_t __user *cdata;
193 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
194 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
195 sizeof(struct drm_radeon_cs_chunk))) {
198 p->chunks[i].length_dw = user_chunk.length_dw;
199 p->chunks[i].kdata = NULL;
200 p->chunks[i].chunk_id = user_chunk.chunk_id;
202 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
203 p->chunk_relocs_idx = i;
205 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
207 /* zero length IB isn't useful */
208 if (p->chunks[i].length_dw == 0)
211 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
212 p->chunk_flags_idx = i;
213 /* zero length flags aren't useful */
214 if (p->chunks[i].length_dw == 0)
218 p->chunks[i].length_dw = user_chunk.length_dw;
219 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
221 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
222 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
223 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
224 size = p->chunks[i].length_dw * sizeof(uint32_t);
225 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
226 if (p->chunks[i].kdata == NULL) {
229 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
230 p->chunks[i].user_ptr, size)) {
233 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
234 p->cs_flags = p->chunks[i].kdata[0];
235 if (p->chunks[i].length_dw > 1)
236 ring = p->chunks[i].kdata[1];
237 if (p->chunks[i].length_dw > 2)
238 priority = (s32)p->chunks[i].kdata[2];
243 if ((p->cs_flags & RADEON_CS_USE_VM) &&
244 !p->rdev->vm_manager.enabled) {
245 DRM_ERROR("VM not active on asic!\n");
246 if (p->chunk_relocs_idx != -1)
247 kfree(p->chunks[p->chunk_relocs_idx].kdata);
248 if (p->chunk_flags_idx != -1)
249 kfree(p->chunks[p->chunk_flags_idx].kdata);
253 if (radeon_cs_get_ring(p, ring, priority)) {
254 if (p->chunk_relocs_idx != -1)
255 kfree(p->chunks[p->chunk_relocs_idx].kdata);
256 if (p->chunk_flags_idx != -1)
257 kfree(p->chunks[p->chunk_flags_idx].kdata);
262 /* deal with non-vm */
263 if ((p->chunk_ib_idx != -1) &&
264 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
265 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
266 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
267 DRM_ERROR("cs IB too big: %d\n",
268 p->chunks[p->chunk_ib_idx].length_dw);
271 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
272 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
273 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
274 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
275 kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
276 kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
279 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
280 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
281 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
282 p->chunks[p->chunk_ib_idx].last_page_index =
283 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
290 * cs_parser_fini() - clean parser states
291 * @parser: parser structure holding parsing context.
292 * @error: error number
294 * If error is set than unvalidate buffer, otherwise just free memory
295 * used by parsing context.
297 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
302 if (!error && parser->ib)
303 ttm_eu_fence_buffer_objects(&parser->validated,
306 ttm_eu_backoff_reservation(&parser->validated);
308 if (parser->relocs != NULL) {
309 for (i = 0; i < parser->nrelocs; i++) {
310 if (parser->relocs[i].gobj)
311 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
314 kfree(parser->track);
315 kfree(parser->relocs);
316 kfree(parser->relocs_ptr);
317 for (i = 0; i < parser->nchunks; i++) {
318 kfree(parser->chunks[i].kdata);
319 kfree(parser->chunks[i].kpage[0]);
320 kfree(parser->chunks[i].kpage[1]);
322 kfree(parser->chunks);
323 kfree(parser->chunks_array);
324 radeon_ib_free(parser->rdev, &parser->ib);
327 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
328 struct radeon_cs_parser *parser)
330 struct radeon_cs_chunk *ib_chunk;
333 if (parser->chunk_ib_idx == -1)
336 if (parser->cs_flags & RADEON_CS_USE_VM)
339 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
340 /* Copy the packet into the IB, the parser will read from the
341 * input memory (cached) and write to the IB (which can be
344 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
345 ib_chunk->length_dw * 4);
347 DRM_ERROR("Failed to get ib !\n");
350 parser->ib->length_dw = ib_chunk->length_dw;
351 r = radeon_cs_parse(rdev, parser->ring, parser);
352 if (r || parser->parser_error) {
353 DRM_ERROR("Invalid command stream !\n");
356 r = radeon_cs_finish_pages(parser);
358 DRM_ERROR("Invalid command stream !\n");
361 r = radeon_cs_sync_rings(parser);
363 DRM_ERROR("Failed to synchronize rings !\n");
365 parser->ib->vm_id = 0;
366 r = radeon_ib_schedule(rdev, parser->ib);
368 DRM_ERROR("Failed to schedule IB !\n");
373 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
374 struct radeon_vm *vm)
376 struct radeon_bo_list *lobj;
377 struct radeon_bo *bo;
380 list_for_each_entry(lobj, &parser->validated, tv.head) {
382 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
390 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
391 struct radeon_cs_parser *parser)
393 struct radeon_cs_chunk *ib_chunk;
394 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
395 struct radeon_vm *vm = &fpriv->vm;
398 if (parser->chunk_ib_idx == -1)
401 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
404 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
405 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
406 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
409 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
410 ib_chunk->length_dw * 4);
412 DRM_ERROR("Failed to get ib !\n");
415 parser->ib->length_dw = ib_chunk->length_dw;
416 /* Copy the packet into the IB */
417 if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
418 ib_chunk->length_dw * 4)) {
421 r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
426 mutex_lock(&vm->mutex);
427 r = radeon_vm_bind(rdev, vm);
431 r = radeon_bo_vm_update_pte(parser, vm);
435 r = radeon_cs_sync_rings(parser);
437 DRM_ERROR("Failed to synchronize rings !\n");
439 parser->ib->vm_id = vm->id;
440 /* ib pool is bind at 0 in virtual address space to gpu_addr is the
441 * offset inside the pool bo
443 parser->ib->gpu_addr = parser->ib->sa_bo.offset;
444 r = radeon_ib_schedule(rdev, parser->ib);
448 radeon_fence_unref(&vm->fence);
450 vm->fence = radeon_fence_ref(parser->ib->fence);
452 mutex_unlock(&fpriv->vm.mutex);
456 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
458 struct radeon_device *rdev = dev->dev_private;
459 struct radeon_cs_parser parser;
462 radeon_mutex_lock(&rdev->cs_mutex);
463 if (!rdev->accel_working) {
464 radeon_mutex_unlock(&rdev->cs_mutex);
467 /* initialize parser */
468 memset(&parser, 0, sizeof(struct radeon_cs_parser));
471 parser.dev = rdev->dev;
472 parser.family = rdev->family;
473 r = radeon_cs_parser_init(&parser, data);
475 DRM_ERROR("Failed to initialize parser !\n");
476 radeon_cs_parser_fini(&parser, r);
477 radeon_mutex_unlock(&rdev->cs_mutex);
480 r = radeon_cs_parser_relocs(&parser);
482 if (r != -ERESTARTSYS)
483 DRM_ERROR("Failed to parse relocation %d!\n", r);
484 radeon_cs_parser_fini(&parser, r);
485 radeon_mutex_unlock(&rdev->cs_mutex);
488 r = radeon_cs_ib_chunk(rdev, &parser);
492 r = radeon_cs_ib_vm_chunk(rdev, &parser);
497 radeon_cs_parser_fini(&parser, r);
498 radeon_mutex_unlock(&rdev->cs_mutex);
502 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
504 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
506 int size = PAGE_SIZE;
508 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
509 if (i == ibc->last_page_index) {
510 size = (ibc->length_dw * 4) % PAGE_SIZE;
515 if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
516 ibc->user_ptr + (i * PAGE_SIZE),
523 int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
526 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
528 int size = PAGE_SIZE;
530 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
531 if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
532 ibc->user_ptr + (i * PAGE_SIZE),
534 p->parser_error = -EFAULT;
539 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
541 if (pg_idx == ibc->last_page_index) {
542 size = (ibc->length_dw * 4) % PAGE_SIZE;
547 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
548 ibc->user_ptr + (pg_idx * PAGE_SIZE),
550 p->parser_error = -EFAULT;
554 /* copy to IB here */
555 memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
557 ibc->last_copied_page = pg_idx;
558 ibc->kpage_idx[new_page] = pg_idx;