2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include "radeon_drm.h"
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
56 /* from radeon_legacy_encoder.c */
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
59 uint32_t supported_device);
61 /* old legacy ATI BIOS routines */
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
114 enum radeon_combios_ddc {
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
149 struct radeon_device *rdev = dev->dev_private;
151 uint16_t offset = 0, check_offset;
154 /* absolute offset tables */
155 case COMBIOS_ASIC_INIT_1_TABLE:
156 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
158 offset = check_offset;
160 case COMBIOS_BIOS_SUPPORT_TABLE:
161 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
163 offset = check_offset;
165 case COMBIOS_DAC_PROGRAMMING_TABLE:
166 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
168 offset = check_offset;
170 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
171 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
173 offset = check_offset;
175 case COMBIOS_CRTC_INFO_TABLE:
176 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
178 offset = check_offset;
180 case COMBIOS_PLL_INFO_TABLE:
181 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
183 offset = check_offset;
185 case COMBIOS_TV_INFO_TABLE:
186 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
188 offset = check_offset;
190 case COMBIOS_DFP_INFO_TABLE:
191 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
193 offset = check_offset;
195 case COMBIOS_HW_CONFIG_INFO_TABLE:
196 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
198 offset = check_offset;
200 case COMBIOS_MULTIMEDIA_INFO_TABLE:
201 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
203 offset = check_offset;
205 case COMBIOS_TV_STD_PATCH_TABLE:
206 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
208 offset = check_offset;
210 case COMBIOS_LCD_INFO_TABLE:
211 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
213 offset = check_offset;
215 case COMBIOS_MOBILE_INFO_TABLE:
216 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
218 offset = check_offset;
220 case COMBIOS_PLL_INIT_TABLE:
221 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
223 offset = check_offset;
225 case COMBIOS_MEM_CONFIG_TABLE:
226 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
228 offset = check_offset;
230 case COMBIOS_SAVE_MASK_TABLE:
231 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
233 offset = check_offset;
235 case COMBIOS_HARDCODED_EDID_TABLE:
236 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
238 offset = check_offset;
240 case COMBIOS_ASIC_INIT_2_TABLE:
241 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
243 offset = check_offset;
245 case COMBIOS_CONNECTOR_INFO_TABLE:
246 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
248 offset = check_offset;
250 case COMBIOS_DYN_CLK_1_TABLE:
251 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
253 offset = check_offset;
255 case COMBIOS_RESERVED_MEM_TABLE:
256 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
258 offset = check_offset;
260 case COMBIOS_EXT_TMDS_INFO_TABLE:
261 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
263 offset = check_offset;
265 case COMBIOS_MEM_CLK_INFO_TABLE:
266 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
268 offset = check_offset;
270 case COMBIOS_EXT_DAC_INFO_TABLE:
271 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
273 offset = check_offset;
275 case COMBIOS_MISC_INFO_TABLE:
276 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
278 offset = check_offset;
280 case COMBIOS_CRT_INFO_TABLE:
281 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
283 offset = check_offset;
285 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
286 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
288 offset = check_offset;
290 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
291 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
293 offset = check_offset;
295 case COMBIOS_FAN_SPEED_INFO_TABLE:
296 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
298 offset = check_offset;
300 case COMBIOS_OVERDRIVE_INFO_TABLE:
301 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
303 offset = check_offset;
305 case COMBIOS_OEM_INFO_TABLE:
306 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
308 offset = check_offset;
310 case COMBIOS_DYN_CLK_2_TABLE:
311 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
313 offset = check_offset;
315 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
316 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
318 offset = check_offset;
320 case COMBIOS_I2C_INFO_TABLE:
321 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
323 offset = check_offset;
325 /* relative offset tables */
326 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
328 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
330 rev = RBIOS8(check_offset);
332 check_offset = RBIOS16(check_offset + 0x3);
334 offset = check_offset;
338 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
340 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
342 rev = RBIOS8(check_offset);
344 check_offset = RBIOS16(check_offset + 0x5);
346 offset = check_offset;
350 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
352 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
354 rev = RBIOS8(check_offset);
356 check_offset = RBIOS16(check_offset + 0x7);
358 offset = check_offset;
362 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
364 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
366 rev = RBIOS8(check_offset);
368 check_offset = RBIOS16(check_offset + 0x9);
370 offset = check_offset;
374 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
376 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
378 while (RBIOS8(check_offset++));
381 offset = check_offset;
384 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
386 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
388 check_offset = RBIOS16(check_offset + 0x11);
390 offset = check_offset;
393 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
395 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
397 check_offset = RBIOS16(check_offset + 0x13);
399 offset = check_offset;
402 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
404 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
406 check_offset = RBIOS16(check_offset + 0x15);
408 offset = check_offset;
411 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
413 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
415 check_offset = RBIOS16(check_offset + 0x17);
417 offset = check_offset;
420 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
422 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
424 check_offset = RBIOS16(check_offset + 0x2);
426 offset = check_offset;
429 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
431 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
433 check_offset = RBIOS16(check_offset + 0x4);
435 offset = check_offset;
446 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
449 struct radeon_i2c_bus_rec i2c;
451 if (ddc_line == RADEON_GPIOPAD_MASK) {
452 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
453 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
454 i2c.a_clk_reg = RADEON_GPIOPAD_A;
455 i2c.a_data_reg = RADEON_GPIOPAD_A;
456 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
457 i2c.en_data_reg = RADEON_GPIOPAD_EN;
458 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
459 i2c.y_data_reg = RADEON_GPIOPAD_Y;
460 } else if (ddc_line == RADEON_MDGPIO_MASK) {
461 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
462 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
463 i2c.a_clk_reg = RADEON_MDGPIO_A;
464 i2c.a_data_reg = RADEON_MDGPIO_A;
465 i2c.en_clk_reg = RADEON_MDGPIO_EN;
466 i2c.en_data_reg = RADEON_MDGPIO_EN;
467 i2c.y_clk_reg = RADEON_MDGPIO_Y;
468 i2c.y_data_reg = RADEON_MDGPIO_Y;
470 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
471 i2c.mask_data_mask = RADEON_GPIO_EN_0;
472 i2c.a_clk_mask = RADEON_GPIO_A_1;
473 i2c.a_data_mask = RADEON_GPIO_A_0;
474 i2c.en_clk_mask = RADEON_GPIO_EN_1;
475 i2c.en_data_mask = RADEON_GPIO_EN_0;
476 i2c.y_clk_mask = RADEON_GPIO_Y_1;
477 i2c.y_data_mask = RADEON_GPIO_Y_0;
479 i2c.mask_clk_reg = ddc_line;
480 i2c.mask_data_reg = ddc_line;
481 i2c.a_clk_reg = ddc_line;
482 i2c.a_data_reg = ddc_line;
483 i2c.en_clk_reg = ddc_line;
484 i2c.en_data_reg = ddc_line;
485 i2c.y_clk_reg = ddc_line;
486 i2c.y_data_reg = ddc_line;
489 if (rdev->family < CHIP_R200)
490 i2c.hw_capable = false;
493 case RADEON_GPIO_VGA_DDC:
494 case RADEON_GPIO_DVI_DDC:
495 i2c.hw_capable = true;
497 case RADEON_GPIO_MONID:
498 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
499 * reliably on some pre-r4xx hardware; not sure why.
501 i2c.hw_capable = false;
504 i2c.hw_capable = false;
519 bool radeon_combios_get_clock_info(struct drm_device *dev)
521 struct radeon_device *rdev = dev->dev_private;
523 struct radeon_pll *p1pll = &rdev->clock.p1pll;
524 struct radeon_pll *p2pll = &rdev->clock.p2pll;
525 struct radeon_pll *spll = &rdev->clock.spll;
526 struct radeon_pll *mpll = &rdev->clock.mpll;
530 if (rdev->bios == NULL)
533 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
535 rev = RBIOS8(pll_info);
538 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
539 p1pll->reference_div = RBIOS16(pll_info + 0x10);
540 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
541 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
544 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
545 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
547 p1pll->pll_in_min = 40;
548 p1pll->pll_in_max = 500;
553 spll->reference_freq = RBIOS16(pll_info + 0x1a);
554 spll->reference_div = RBIOS16(pll_info + 0x1c);
555 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
556 spll->pll_out_max = RBIOS32(pll_info + 0x22);
559 spll->pll_in_min = RBIOS32(pll_info + 0x48);
560 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
563 spll->pll_in_min = 40;
564 spll->pll_in_max = 500;
568 mpll->reference_freq = RBIOS16(pll_info + 0x26);
569 mpll->reference_div = RBIOS16(pll_info + 0x28);
570 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
571 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
574 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
575 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
578 mpll->pll_in_min = 40;
579 mpll->pll_in_max = 500;
582 /* default sclk/mclk */
583 sclk = RBIOS16(pll_info + 0xa);
584 mclk = RBIOS16(pll_info + 0x8);
590 rdev->clock.default_sclk = sclk;
591 rdev->clock.default_mclk = mclk;
598 bool radeon_combios_sideport_present(struct radeon_device *rdev)
600 struct drm_device *dev = rdev->ddev;
603 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
606 if (RBIOS16(igp_info + 0x4))
612 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
613 0x00000808, /* r100 */
614 0x00000808, /* rv100 */
615 0x00000808, /* rs100 */
616 0x00000808, /* rv200 */
617 0x00000808, /* rs200 */
618 0x00000808, /* r200 */
619 0x00000808, /* rv250 */
620 0x00000000, /* rs300 */
621 0x00000808, /* rv280 */
622 0x00000808, /* r300 */
623 0x00000808, /* r350 */
624 0x00000808, /* rv350 */
625 0x00000808, /* rv380 */
626 0x00000808, /* r420 */
627 0x00000808, /* r423 */
628 0x00000808, /* rv410 */
629 0x00000000, /* rs400 */
630 0x00000000, /* rs480 */
633 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
634 struct radeon_encoder_primary_dac *p_dac)
636 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
640 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
644 struct drm_device *dev = encoder->base.dev;
645 struct radeon_device *rdev = dev->dev_private;
647 uint8_t rev, bg, dac;
648 struct radeon_encoder_primary_dac *p_dac = NULL;
651 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
657 if (rdev->bios == NULL)
660 /* check CRT table */
661 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
663 rev = RBIOS8(dac_info) & 0x3;
665 bg = RBIOS8(dac_info + 0x2) & 0xf;
666 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
667 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
669 bg = RBIOS8(dac_info + 0x2) & 0xf;
670 dac = RBIOS8(dac_info + 0x3) & 0xf;
671 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
677 if (!found) /* fallback to defaults */
678 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
684 radeon_combios_get_tv_info(struct radeon_device *rdev)
686 struct drm_device *dev = rdev->ddev;
688 enum radeon_tv_std tv_std = TV_STD_NTSC;
690 if (rdev->bios == NULL)
693 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
695 if (RBIOS8(tv_info + 6) == 'T') {
696 switch (RBIOS8(tv_info + 7) & 0xf) {
698 tv_std = TV_STD_NTSC;
699 DRM_INFO("Default TV standard: NTSC\n");
703 DRM_INFO("Default TV standard: PAL\n");
706 tv_std = TV_STD_PAL_M;
707 DRM_INFO("Default TV standard: PAL-M\n");
710 tv_std = TV_STD_PAL_60;
711 DRM_INFO("Default TV standard: PAL-60\n");
714 tv_std = TV_STD_NTSC_J;
715 DRM_INFO("Default TV standard: NTSC-J\n");
718 tv_std = TV_STD_SCART_PAL;
719 DRM_INFO("Default TV standard: SCART-PAL\n");
722 tv_std = TV_STD_NTSC;
724 ("Unknown TV standard; defaulting to NTSC\n");
728 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
730 DRM_INFO("29.498928713 MHz TV ref clk\n");
733 DRM_INFO("28.636360000 MHz TV ref clk\n");
736 DRM_INFO("14.318180000 MHz TV ref clk\n");
739 DRM_INFO("27.000000000 MHz TV ref clk\n");
749 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
750 0x00000000, /* r100 */
751 0x00280000, /* rv100 */
752 0x00000000, /* rs100 */
753 0x00880000, /* rv200 */
754 0x00000000, /* rs200 */
755 0x00000000, /* r200 */
756 0x00770000, /* rv250 */
757 0x00290000, /* rs300 */
758 0x00560000, /* rv280 */
759 0x00780000, /* r300 */
760 0x00770000, /* r350 */
761 0x00780000, /* rv350 */
762 0x00780000, /* rv380 */
763 0x01080000, /* r420 */
764 0x01080000, /* r423 */
765 0x01080000, /* rv410 */
766 0x00780000, /* rs400 */
767 0x00780000, /* rs480 */
770 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
771 struct radeon_encoder_tv_dac *tv_dac)
773 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
774 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
775 tv_dac->ps2_tvdac_adj = 0x00880000;
776 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
777 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
781 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
785 struct drm_device *dev = encoder->base.dev;
786 struct radeon_device *rdev = dev->dev_private;
788 uint8_t rev, bg, dac;
789 struct radeon_encoder_tv_dac *tv_dac = NULL;
792 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
796 if (rdev->bios == NULL)
799 /* first check TV table */
800 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
802 rev = RBIOS8(dac_info + 0x3);
804 bg = RBIOS8(dac_info + 0xc) & 0xf;
805 dac = RBIOS8(dac_info + 0xd) & 0xf;
806 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
808 bg = RBIOS8(dac_info + 0xe) & 0xf;
809 dac = RBIOS8(dac_info + 0xf) & 0xf;
810 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
812 bg = RBIOS8(dac_info + 0x10) & 0xf;
813 dac = RBIOS8(dac_info + 0x11) & 0xf;
814 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
816 } else if (rev > 1) {
817 bg = RBIOS8(dac_info + 0xc) & 0xf;
818 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
819 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
821 bg = RBIOS8(dac_info + 0xd) & 0xf;
822 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
823 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
825 bg = RBIOS8(dac_info + 0xe) & 0xf;
826 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
827 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
830 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
833 /* then check CRT table */
835 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
837 rev = RBIOS8(dac_info) & 0x3;
839 bg = RBIOS8(dac_info + 0x3) & 0xf;
840 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
841 tv_dac->ps2_tvdac_adj =
842 (bg << 16) | (dac << 20);
843 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
844 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
847 bg = RBIOS8(dac_info + 0x4) & 0xf;
848 dac = RBIOS8(dac_info + 0x5) & 0xf;
849 tv_dac->ps2_tvdac_adj =
850 (bg << 16) | (dac << 20);
851 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
852 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
856 DRM_INFO("No TV DAC info found in BIOS\n");
861 if (!found) /* fallback to defaults */
862 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
867 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
871 struct radeon_encoder_lvds *lvds = NULL;
872 uint32_t fp_vert_stretch, fp_horz_stretch;
873 uint32_t ppll_div_sel, ppll_val;
874 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
876 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
881 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
882 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
884 /* These should be fail-safe defaults, fingers crossed */
885 lvds->panel_pwr_delay = 200;
886 lvds->panel_vcc_delay = 2000;
888 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
889 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
890 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
892 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
893 lvds->native_mode.vdisplay =
894 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
895 RADEON_VERT_PANEL_SHIFT) + 1;
897 lvds->native_mode.vdisplay =
898 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
900 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
901 lvds->native_mode.hdisplay =
902 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
903 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
905 lvds->native_mode.hdisplay =
906 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
908 if ((lvds->native_mode.hdisplay < 640) ||
909 (lvds->native_mode.vdisplay < 480)) {
910 lvds->native_mode.hdisplay = 640;
911 lvds->native_mode.vdisplay = 480;
914 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
915 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
916 if ((ppll_val & 0x000707ff) == 0x1bb)
917 lvds->use_bios_dividers = false;
919 lvds->panel_ref_divider =
920 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
921 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
922 lvds->panel_fb_divider = ppll_val & 0x7ff;
924 if ((lvds->panel_ref_divider != 0) &&
925 (lvds->panel_fb_divider > 3))
926 lvds->use_bios_dividers = true;
928 lvds->panel_vcc_delay = 200;
930 DRM_INFO("Panel info derived from registers\n");
931 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
932 lvds->native_mode.vdisplay);
937 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
940 struct drm_device *dev = encoder->base.dev;
941 struct radeon_device *rdev = dev->dev_private;
943 uint32_t panel_setup;
946 struct radeon_encoder_lvds *lvds = NULL;
948 if (rdev->bios == NULL) {
949 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
953 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
956 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
961 for (i = 0; i < 24; i++)
962 stmp[i] = RBIOS8(lcd_info + i + 1);
965 DRM_INFO("Panel ID String: %s\n", stmp);
967 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
968 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
970 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
971 lvds->native_mode.vdisplay);
973 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
974 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
976 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
977 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
978 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
980 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
981 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
982 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
983 if ((lvds->panel_ref_divider != 0) &&
984 (lvds->panel_fb_divider > 3))
985 lvds->use_bios_dividers = true;
987 panel_setup = RBIOS32(lcd_info + 0x39);
988 lvds->lvds_gen_cntl = 0xff00;
989 if (panel_setup & 0x1)
990 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
992 if ((panel_setup >> 4) & 0x1)
993 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
995 switch ((panel_setup >> 8) & 0x7) {
997 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1000 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1003 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1009 if ((panel_setup >> 16) & 0x1)
1010 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1012 if ((panel_setup >> 17) & 0x1)
1013 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1015 if ((panel_setup >> 18) & 0x1)
1016 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1018 if ((panel_setup >> 23) & 0x1)
1019 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1021 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1023 for (i = 0; i < 32; i++) {
1024 tmp = RBIOS16(lcd_info + 64 + i * 2);
1028 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1029 (RBIOS16(tmp + 2) ==
1030 lvds->native_mode.vdisplay)) {
1031 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
1032 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
1033 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
1034 RBIOS16(tmp + 21)) * 8;
1036 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
1037 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
1038 lvds->native_mode.vsync_end =
1039 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
1040 (RBIOS16(tmp + 28) & 0x7ff);
1042 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1043 lvds->native_mode.flags = 0;
1044 /* set crtc values */
1045 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1050 DRM_INFO("No panel info found in BIOS\n");
1051 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1055 encoder->native_mode = lvds->native_mode;
1059 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1060 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1061 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1062 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1063 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1064 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1065 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1066 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1067 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1068 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1069 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1070 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1071 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1072 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1073 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1074 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1075 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1076 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1077 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1080 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1081 struct radeon_encoder_int_tmds *tmds)
1083 struct drm_device *dev = encoder->base.dev;
1084 struct radeon_device *rdev = dev->dev_private;
1087 for (i = 0; i < 4; i++) {
1088 tmds->tmds_pll[i].value =
1089 default_tmds_pll[rdev->family][i].value;
1090 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1096 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1097 struct radeon_encoder_int_tmds *tmds)
1099 struct drm_device *dev = encoder->base.dev;
1100 struct radeon_device *rdev = dev->dev_private;
1105 if (rdev->bios == NULL)
1108 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1111 ver = RBIOS8(tmds_info);
1112 DRM_INFO("DFP table revision: %d\n", ver);
1114 n = RBIOS8(tmds_info + 5) + 1;
1117 for (i = 0; i < n; i++) {
1118 tmds->tmds_pll[i].value =
1119 RBIOS32(tmds_info + i * 10 + 0x08);
1120 tmds->tmds_pll[i].freq =
1121 RBIOS16(tmds_info + i * 10 + 0x10);
1122 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1123 tmds->tmds_pll[i].freq,
1124 tmds->tmds_pll[i].value);
1126 } else if (ver == 4) {
1128 n = RBIOS8(tmds_info + 5) + 1;
1131 for (i = 0; i < n; i++) {
1132 tmds->tmds_pll[i].value =
1133 RBIOS32(tmds_info + stride + 0x08);
1134 tmds->tmds_pll[i].freq =
1135 RBIOS16(tmds_info + stride + 0x10);
1140 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1141 tmds->tmds_pll[i].freq,
1142 tmds->tmds_pll[i].value);
1146 DRM_INFO("No TMDS info found in BIOS\n");
1152 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1153 struct radeon_encoder_ext_tmds *tmds)
1155 struct drm_device *dev = encoder->base.dev;
1156 struct radeon_device *rdev = dev->dev_private;
1157 struct radeon_i2c_bus_rec i2c_bus;
1159 /* default for macs */
1160 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1161 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1163 /* XXX some macs have duallink chips */
1164 switch (rdev->mode_info.connector_table) {
1165 case CT_POWERBOOK_EXTERNAL:
1166 case CT_MINI_EXTERNAL:
1168 tmds->dvo_chip = DVO_SIL164;
1169 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1176 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1177 struct radeon_encoder_ext_tmds *tmds)
1179 struct drm_device *dev = encoder->base.dev;
1180 struct radeon_device *rdev = dev->dev_private;
1182 uint8_t ver, id, blocks, clk, data;
1184 enum radeon_combios_ddc gpio;
1185 struct radeon_i2c_bus_rec i2c_bus;
1187 if (rdev->bios == NULL)
1190 tmds->i2c_bus = NULL;
1191 if (rdev->flags & RADEON_IS_IGP) {
1192 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1194 ver = RBIOS8(offset);
1195 DRM_INFO("GPIO Table revision: %d\n", ver);
1196 blocks = RBIOS8(offset + 2);
1197 for (i = 0; i < blocks; i++) {
1198 id = RBIOS8(offset + 3 + (i * 5) + 0);
1200 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1201 data = RBIOS8(offset + 3 + (i * 5) + 4);
1202 i2c_bus.valid = true;
1203 i2c_bus.mask_clk_mask = (1 << clk);
1204 i2c_bus.mask_data_mask = (1 << data);
1205 i2c_bus.a_clk_mask = (1 << clk);
1206 i2c_bus.a_data_mask = (1 << data);
1207 i2c_bus.en_clk_mask = (1 << clk);
1208 i2c_bus.en_data_mask = (1 << data);
1209 i2c_bus.y_clk_mask = (1 << clk);
1210 i2c_bus.y_data_mask = (1 << data);
1211 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1212 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1213 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1214 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1215 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1216 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1217 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1218 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1219 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1220 tmds->dvo_chip = DVO_SIL164;
1221 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1227 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1229 ver = RBIOS8(offset);
1230 DRM_INFO("External TMDS Table revision: %d\n", ver);
1231 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1232 tmds->slave_addr >>= 1; /* 7 bit addressing */
1233 gpio = RBIOS8(offset + 4 + 3);
1236 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1237 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1240 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1241 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1244 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1245 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1248 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1249 if (rdev->family >= CHIP_R300)
1250 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1252 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1253 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1255 case DDC_LCD: /* MM i2c */
1256 DRM_ERROR("MM i2c requires hw i2c engine\n");
1259 DRM_ERROR("Unsupported gpio %d\n", gpio);
1265 if (!tmds->i2c_bus) {
1266 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1273 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1275 struct radeon_device *rdev = dev->dev_private;
1276 struct radeon_i2c_bus_rec ddc_i2c;
1277 struct radeon_hpd hpd;
1279 rdev->mode_info.connector_table = radeon_connector_table;
1280 if (rdev->mode_info.connector_table == CT_NONE) {
1281 #ifdef CONFIG_PPC_PMAC
1282 if (machine_is_compatible("PowerBook3,3")) {
1283 /* powerbook with VGA */
1284 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1285 } else if (machine_is_compatible("PowerBook3,4") ||
1286 machine_is_compatible("PowerBook3,5")) {
1287 /* powerbook with internal tmds */
1288 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1289 } else if (machine_is_compatible("PowerBook5,1") ||
1290 machine_is_compatible("PowerBook5,2") ||
1291 machine_is_compatible("PowerBook5,3") ||
1292 machine_is_compatible("PowerBook5,4") ||
1293 machine_is_compatible("PowerBook5,5")) {
1294 /* powerbook with external single link tmds (sil164) */
1295 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1296 } else if (machine_is_compatible("PowerBook5,6")) {
1297 /* powerbook with external dual or single link tmds */
1298 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1299 } else if (machine_is_compatible("PowerBook5,7") ||
1300 machine_is_compatible("PowerBook5,8") ||
1301 machine_is_compatible("PowerBook5,9")) {
1302 /* PowerBook6,2 ? */
1303 /* powerbook with external dual link tmds (sil1178?) */
1304 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1305 } else if (machine_is_compatible("PowerBook4,1") ||
1306 machine_is_compatible("PowerBook4,2") ||
1307 machine_is_compatible("PowerBook4,3") ||
1308 machine_is_compatible("PowerBook6,3") ||
1309 machine_is_compatible("PowerBook6,5") ||
1310 machine_is_compatible("PowerBook6,7")) {
1312 rdev->mode_info.connector_table = CT_IBOOK;
1313 } else if (machine_is_compatible("PowerMac4,4")) {
1315 rdev->mode_info.connector_table = CT_EMAC;
1316 } else if (machine_is_compatible("PowerMac10,1")) {
1317 /* mini with internal tmds */
1318 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1319 } else if (machine_is_compatible("PowerMac10,2")) {
1320 /* mini with external tmds */
1321 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1322 } else if (machine_is_compatible("PowerMac12,1")) {
1324 /* imac g5 isight */
1325 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1327 #endif /* CONFIG_PPC_PMAC */
1328 rdev->mode_info.connector_table = CT_GENERIC;
1331 switch (rdev->mode_info.connector_table) {
1333 DRM_INFO("Connector Table: %d (generic)\n",
1334 rdev->mode_info.connector_table);
1335 /* these are the most common settings */
1336 if (rdev->flags & RADEON_SINGLE_CRTC) {
1337 /* VGA - primary dac */
1338 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1339 hpd.hpd = RADEON_HPD_NONE;
1340 radeon_add_legacy_encoder(dev,
1341 radeon_get_encoder_id(dev,
1342 ATOM_DEVICE_CRT1_SUPPORT,
1344 ATOM_DEVICE_CRT1_SUPPORT);
1345 radeon_add_legacy_connector(dev, 0,
1346 ATOM_DEVICE_CRT1_SUPPORT,
1347 DRM_MODE_CONNECTOR_VGA,
1349 CONNECTOR_OBJECT_ID_VGA,
1351 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1353 ddc_i2c = combios_setup_i2c_bus(rdev, 0);
1354 hpd.hpd = RADEON_HPD_NONE;
1355 radeon_add_legacy_encoder(dev,
1356 radeon_get_encoder_id(dev,
1357 ATOM_DEVICE_LCD1_SUPPORT,
1359 ATOM_DEVICE_LCD1_SUPPORT);
1360 radeon_add_legacy_connector(dev, 0,
1361 ATOM_DEVICE_LCD1_SUPPORT,
1362 DRM_MODE_CONNECTOR_LVDS,
1364 CONNECTOR_OBJECT_ID_LVDS,
1367 /* VGA - primary dac */
1368 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1369 hpd.hpd = RADEON_HPD_NONE;
1370 radeon_add_legacy_encoder(dev,
1371 radeon_get_encoder_id(dev,
1372 ATOM_DEVICE_CRT1_SUPPORT,
1374 ATOM_DEVICE_CRT1_SUPPORT);
1375 radeon_add_legacy_connector(dev, 1,
1376 ATOM_DEVICE_CRT1_SUPPORT,
1377 DRM_MODE_CONNECTOR_VGA,
1379 CONNECTOR_OBJECT_ID_VGA,
1382 /* DVI-I - tv dac, int tmds */
1383 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1384 hpd.hpd = RADEON_HPD_1;
1385 radeon_add_legacy_encoder(dev,
1386 radeon_get_encoder_id(dev,
1387 ATOM_DEVICE_DFP1_SUPPORT,
1389 ATOM_DEVICE_DFP1_SUPPORT);
1390 radeon_add_legacy_encoder(dev,
1391 radeon_get_encoder_id(dev,
1392 ATOM_DEVICE_CRT2_SUPPORT,
1394 ATOM_DEVICE_CRT2_SUPPORT);
1395 radeon_add_legacy_connector(dev, 0,
1396 ATOM_DEVICE_DFP1_SUPPORT |
1397 ATOM_DEVICE_CRT2_SUPPORT,
1398 DRM_MODE_CONNECTOR_DVII,
1400 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1403 /* VGA - primary dac */
1404 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1405 hpd.hpd = RADEON_HPD_NONE;
1406 radeon_add_legacy_encoder(dev,
1407 radeon_get_encoder_id(dev,
1408 ATOM_DEVICE_CRT1_SUPPORT,
1410 ATOM_DEVICE_CRT1_SUPPORT);
1411 radeon_add_legacy_connector(dev, 1,
1412 ATOM_DEVICE_CRT1_SUPPORT,
1413 DRM_MODE_CONNECTOR_VGA,
1415 CONNECTOR_OBJECT_ID_VGA,
1419 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1421 ddc_i2c.valid = false;
1422 hpd.hpd = RADEON_HPD_NONE;
1423 radeon_add_legacy_encoder(dev,
1424 radeon_get_encoder_id(dev,
1425 ATOM_DEVICE_TV1_SUPPORT,
1427 ATOM_DEVICE_TV1_SUPPORT);
1428 radeon_add_legacy_connector(dev, 2,
1429 ATOM_DEVICE_TV1_SUPPORT,
1430 DRM_MODE_CONNECTOR_SVIDEO,
1432 CONNECTOR_OBJECT_ID_SVIDEO,
1437 DRM_INFO("Connector Table: %d (ibook)\n",
1438 rdev->mode_info.connector_table);
1440 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1441 hpd.hpd = RADEON_HPD_NONE;
1442 radeon_add_legacy_encoder(dev,
1443 radeon_get_encoder_id(dev,
1444 ATOM_DEVICE_LCD1_SUPPORT,
1446 ATOM_DEVICE_LCD1_SUPPORT);
1447 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1448 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1449 CONNECTOR_OBJECT_ID_LVDS,
1452 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1453 hpd.hpd = RADEON_HPD_NONE;
1454 radeon_add_legacy_encoder(dev,
1455 radeon_get_encoder_id(dev,
1456 ATOM_DEVICE_CRT2_SUPPORT,
1458 ATOM_DEVICE_CRT2_SUPPORT);
1459 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1460 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1461 CONNECTOR_OBJECT_ID_VGA,
1464 ddc_i2c.valid = false;
1465 hpd.hpd = RADEON_HPD_NONE;
1466 radeon_add_legacy_encoder(dev,
1467 radeon_get_encoder_id(dev,
1468 ATOM_DEVICE_TV1_SUPPORT,
1470 ATOM_DEVICE_TV1_SUPPORT);
1471 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1472 DRM_MODE_CONNECTOR_SVIDEO,
1474 CONNECTOR_OBJECT_ID_SVIDEO,
1477 case CT_POWERBOOK_EXTERNAL:
1478 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1479 rdev->mode_info.connector_table);
1481 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1482 hpd.hpd = RADEON_HPD_NONE;
1483 radeon_add_legacy_encoder(dev,
1484 radeon_get_encoder_id(dev,
1485 ATOM_DEVICE_LCD1_SUPPORT,
1487 ATOM_DEVICE_LCD1_SUPPORT);
1488 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1489 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1490 CONNECTOR_OBJECT_ID_LVDS,
1492 /* DVI-I - primary dac, ext tmds */
1493 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1494 hpd.hpd = RADEON_HPD_2; /* ??? */
1495 radeon_add_legacy_encoder(dev,
1496 radeon_get_encoder_id(dev,
1497 ATOM_DEVICE_DFP2_SUPPORT,
1499 ATOM_DEVICE_DFP2_SUPPORT);
1500 radeon_add_legacy_encoder(dev,
1501 radeon_get_encoder_id(dev,
1502 ATOM_DEVICE_CRT1_SUPPORT,
1504 ATOM_DEVICE_CRT1_SUPPORT);
1505 /* XXX some are SL */
1506 radeon_add_legacy_connector(dev, 1,
1507 ATOM_DEVICE_DFP2_SUPPORT |
1508 ATOM_DEVICE_CRT1_SUPPORT,
1509 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1510 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1513 ddc_i2c.valid = false;
1514 hpd.hpd = RADEON_HPD_NONE;
1515 radeon_add_legacy_encoder(dev,
1516 radeon_get_encoder_id(dev,
1517 ATOM_DEVICE_TV1_SUPPORT,
1519 ATOM_DEVICE_TV1_SUPPORT);
1520 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1521 DRM_MODE_CONNECTOR_SVIDEO,
1523 CONNECTOR_OBJECT_ID_SVIDEO,
1526 case CT_POWERBOOK_INTERNAL:
1527 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1528 rdev->mode_info.connector_table);
1530 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1531 hpd.hpd = RADEON_HPD_NONE;
1532 radeon_add_legacy_encoder(dev,
1533 radeon_get_encoder_id(dev,
1534 ATOM_DEVICE_LCD1_SUPPORT,
1536 ATOM_DEVICE_LCD1_SUPPORT);
1537 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1538 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1539 CONNECTOR_OBJECT_ID_LVDS,
1541 /* DVI-I - primary dac, int tmds */
1542 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1543 hpd.hpd = RADEON_HPD_1; /* ??? */
1544 radeon_add_legacy_encoder(dev,
1545 radeon_get_encoder_id(dev,
1546 ATOM_DEVICE_DFP1_SUPPORT,
1548 ATOM_DEVICE_DFP1_SUPPORT);
1549 radeon_add_legacy_encoder(dev,
1550 radeon_get_encoder_id(dev,
1551 ATOM_DEVICE_CRT1_SUPPORT,
1553 ATOM_DEVICE_CRT1_SUPPORT);
1554 radeon_add_legacy_connector(dev, 1,
1555 ATOM_DEVICE_DFP1_SUPPORT |
1556 ATOM_DEVICE_CRT1_SUPPORT,
1557 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1558 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1561 ddc_i2c.valid = false;
1562 hpd.hpd = RADEON_HPD_NONE;
1563 radeon_add_legacy_encoder(dev,
1564 radeon_get_encoder_id(dev,
1565 ATOM_DEVICE_TV1_SUPPORT,
1567 ATOM_DEVICE_TV1_SUPPORT);
1568 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1569 DRM_MODE_CONNECTOR_SVIDEO,
1571 CONNECTOR_OBJECT_ID_SVIDEO,
1574 case CT_POWERBOOK_VGA:
1575 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1576 rdev->mode_info.connector_table);
1578 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1579 hpd.hpd = RADEON_HPD_NONE;
1580 radeon_add_legacy_encoder(dev,
1581 radeon_get_encoder_id(dev,
1582 ATOM_DEVICE_LCD1_SUPPORT,
1584 ATOM_DEVICE_LCD1_SUPPORT);
1585 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1586 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1587 CONNECTOR_OBJECT_ID_LVDS,
1589 /* VGA - primary dac */
1590 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1591 hpd.hpd = RADEON_HPD_NONE;
1592 radeon_add_legacy_encoder(dev,
1593 radeon_get_encoder_id(dev,
1594 ATOM_DEVICE_CRT1_SUPPORT,
1596 ATOM_DEVICE_CRT1_SUPPORT);
1597 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1598 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1599 CONNECTOR_OBJECT_ID_VGA,
1602 ddc_i2c.valid = false;
1603 hpd.hpd = RADEON_HPD_NONE;
1604 radeon_add_legacy_encoder(dev,
1605 radeon_get_encoder_id(dev,
1606 ATOM_DEVICE_TV1_SUPPORT,
1608 ATOM_DEVICE_TV1_SUPPORT);
1609 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1610 DRM_MODE_CONNECTOR_SVIDEO,
1612 CONNECTOR_OBJECT_ID_SVIDEO,
1615 case CT_MINI_EXTERNAL:
1616 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1617 rdev->mode_info.connector_table);
1618 /* DVI-I - tv dac, ext tmds */
1619 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1620 hpd.hpd = RADEON_HPD_2; /* ??? */
1621 radeon_add_legacy_encoder(dev,
1622 radeon_get_encoder_id(dev,
1623 ATOM_DEVICE_DFP2_SUPPORT,
1625 ATOM_DEVICE_DFP2_SUPPORT);
1626 radeon_add_legacy_encoder(dev,
1627 radeon_get_encoder_id(dev,
1628 ATOM_DEVICE_CRT2_SUPPORT,
1630 ATOM_DEVICE_CRT2_SUPPORT);
1631 /* XXX are any DL? */
1632 radeon_add_legacy_connector(dev, 0,
1633 ATOM_DEVICE_DFP2_SUPPORT |
1634 ATOM_DEVICE_CRT2_SUPPORT,
1635 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1636 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1639 ddc_i2c.valid = false;
1640 hpd.hpd = RADEON_HPD_NONE;
1641 radeon_add_legacy_encoder(dev,
1642 radeon_get_encoder_id(dev,
1643 ATOM_DEVICE_TV1_SUPPORT,
1645 ATOM_DEVICE_TV1_SUPPORT);
1646 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1647 DRM_MODE_CONNECTOR_SVIDEO,
1649 CONNECTOR_OBJECT_ID_SVIDEO,
1652 case CT_MINI_INTERNAL:
1653 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1654 rdev->mode_info.connector_table);
1655 /* DVI-I - tv dac, int tmds */
1656 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1657 hpd.hpd = RADEON_HPD_1; /* ??? */
1658 radeon_add_legacy_encoder(dev,
1659 radeon_get_encoder_id(dev,
1660 ATOM_DEVICE_DFP1_SUPPORT,
1662 ATOM_DEVICE_DFP1_SUPPORT);
1663 radeon_add_legacy_encoder(dev,
1664 radeon_get_encoder_id(dev,
1665 ATOM_DEVICE_CRT2_SUPPORT,
1667 ATOM_DEVICE_CRT2_SUPPORT);
1668 radeon_add_legacy_connector(dev, 0,
1669 ATOM_DEVICE_DFP1_SUPPORT |
1670 ATOM_DEVICE_CRT2_SUPPORT,
1671 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1672 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1675 ddc_i2c.valid = false;
1676 hpd.hpd = RADEON_HPD_NONE;
1677 radeon_add_legacy_encoder(dev,
1678 radeon_get_encoder_id(dev,
1679 ATOM_DEVICE_TV1_SUPPORT,
1681 ATOM_DEVICE_TV1_SUPPORT);
1682 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1683 DRM_MODE_CONNECTOR_SVIDEO,
1685 CONNECTOR_OBJECT_ID_SVIDEO,
1688 case CT_IMAC_G5_ISIGHT:
1689 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1690 rdev->mode_info.connector_table);
1691 /* DVI-D - int tmds */
1692 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1693 hpd.hpd = RADEON_HPD_1; /* ??? */
1694 radeon_add_legacy_encoder(dev,
1695 radeon_get_encoder_id(dev,
1696 ATOM_DEVICE_DFP1_SUPPORT,
1698 ATOM_DEVICE_DFP1_SUPPORT);
1699 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1700 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1701 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1704 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1705 hpd.hpd = RADEON_HPD_NONE;
1706 radeon_add_legacy_encoder(dev,
1707 radeon_get_encoder_id(dev,
1708 ATOM_DEVICE_CRT2_SUPPORT,
1710 ATOM_DEVICE_CRT2_SUPPORT);
1711 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1712 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1713 CONNECTOR_OBJECT_ID_VGA,
1716 ddc_i2c.valid = false;
1717 hpd.hpd = RADEON_HPD_NONE;
1718 radeon_add_legacy_encoder(dev,
1719 radeon_get_encoder_id(dev,
1720 ATOM_DEVICE_TV1_SUPPORT,
1722 ATOM_DEVICE_TV1_SUPPORT);
1723 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1724 DRM_MODE_CONNECTOR_SVIDEO,
1726 CONNECTOR_OBJECT_ID_SVIDEO,
1730 DRM_INFO("Connector Table: %d (emac)\n",
1731 rdev->mode_info.connector_table);
1732 /* VGA - primary dac */
1733 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1734 hpd.hpd = RADEON_HPD_NONE;
1735 radeon_add_legacy_encoder(dev,
1736 radeon_get_encoder_id(dev,
1737 ATOM_DEVICE_CRT1_SUPPORT,
1739 ATOM_DEVICE_CRT1_SUPPORT);
1740 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1741 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1742 CONNECTOR_OBJECT_ID_VGA,
1745 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1746 hpd.hpd = RADEON_HPD_NONE;
1747 radeon_add_legacy_encoder(dev,
1748 radeon_get_encoder_id(dev,
1749 ATOM_DEVICE_CRT2_SUPPORT,
1751 ATOM_DEVICE_CRT2_SUPPORT);
1752 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1753 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1754 CONNECTOR_OBJECT_ID_VGA,
1757 ddc_i2c.valid = false;
1758 hpd.hpd = RADEON_HPD_NONE;
1759 radeon_add_legacy_encoder(dev,
1760 radeon_get_encoder_id(dev,
1761 ATOM_DEVICE_TV1_SUPPORT,
1763 ATOM_DEVICE_TV1_SUPPORT);
1764 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1765 DRM_MODE_CONNECTOR_SVIDEO,
1767 CONNECTOR_OBJECT_ID_SVIDEO,
1771 DRM_INFO("Connector table: %d (invalid)\n",
1772 rdev->mode_info.connector_table);
1776 radeon_link_encoder_connector(dev);
1781 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1783 enum radeon_combios_connector
1785 struct radeon_i2c_bus_rec *ddc_i2c,
1786 struct radeon_hpd *hpd)
1788 struct radeon_device *rdev = dev->dev_private;
1790 /* XPRESS DDC quirks */
1791 if ((rdev->family == CHIP_RS400 ||
1792 rdev->family == CHIP_RS480) &&
1793 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1794 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1795 else if ((rdev->family == CHIP_RS400 ||
1796 rdev->family == CHIP_RS480) &&
1797 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1798 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1799 ddc_i2c->mask_clk_mask = (0x20 << 8);
1800 ddc_i2c->mask_data_mask = 0x80;
1801 ddc_i2c->a_clk_mask = (0x20 << 8);
1802 ddc_i2c->a_data_mask = 0x80;
1803 ddc_i2c->en_clk_mask = (0x20 << 8);
1804 ddc_i2c->en_data_mask = 0x80;
1805 ddc_i2c->y_clk_mask = (0x20 << 8);
1806 ddc_i2c->y_data_mask = 0x80;
1809 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1810 if ((rdev->family >= CHIP_R300) &&
1811 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1812 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1814 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1815 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1816 if (dev->pdev->device == 0x515e &&
1817 dev->pdev->subsystem_vendor == 0x1014) {
1818 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1819 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1823 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1824 if (dev->pdev->device == 0x5159 &&
1825 dev->pdev->subsystem_vendor == 0x1002 &&
1826 dev->pdev->subsystem_device == 0x013a) {
1827 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1828 *legacy_connector = CONNECTOR_CRT_LEGACY;
1832 /* X300 card with extra non-existent DVI port */
1833 if (dev->pdev->device == 0x5B60 &&
1834 dev->pdev->subsystem_vendor == 0x17af &&
1835 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1836 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1843 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1845 /* Acer 5102 has non-existent TV port */
1846 if (dev->pdev->device == 0x5975 &&
1847 dev->pdev->subsystem_vendor == 0x1025 &&
1848 dev->pdev->subsystem_device == 0x009f)
1851 /* HP dc5750 has non-existent TV port */
1852 if (dev->pdev->device == 0x5974 &&
1853 dev->pdev->subsystem_vendor == 0x103c &&
1854 dev->pdev->subsystem_device == 0x280a)
1857 /* MSI S270 has non-existent TV port */
1858 if (dev->pdev->device == 0x5955 &&
1859 dev->pdev->subsystem_vendor == 0x1462 &&
1860 dev->pdev->subsystem_device == 0x0131)
1866 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1868 struct radeon_device *rdev = dev->dev_private;
1869 uint32_t ext_tmds_info;
1871 if (rdev->flags & RADEON_IS_IGP) {
1873 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1875 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1877 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1878 if (ext_tmds_info) {
1879 uint8_t rev = RBIOS8(ext_tmds_info);
1880 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1883 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1885 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1889 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1891 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1896 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1898 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1901 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1903 struct radeon_device *rdev = dev->dev_private;
1904 uint32_t conn_info, entry, devices;
1905 uint16_t tmp, connector_object_id;
1906 enum radeon_combios_ddc ddc_type;
1907 enum radeon_combios_connector connector;
1909 struct radeon_i2c_bus_rec ddc_i2c;
1910 struct radeon_hpd hpd;
1912 if (rdev->bios == NULL)
1915 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1917 for (i = 0; i < 4; i++) {
1918 entry = conn_info + 2 + i * 2;
1920 if (!RBIOS16(entry))
1923 tmp = RBIOS16(entry);
1925 connector = (tmp >> 12) & 0xf;
1927 ddc_type = (tmp >> 8) & 0xf;
1931 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1935 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1939 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1943 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1949 switch (connector) {
1950 case CONNECTOR_PROPRIETARY_LEGACY:
1951 case CONNECTOR_DVI_I_LEGACY:
1952 case CONNECTOR_DVI_D_LEGACY:
1953 if ((tmp >> 4) & 0x1)
1954 hpd.hpd = RADEON_HPD_2;
1956 hpd.hpd = RADEON_HPD_1;
1959 hpd.hpd = RADEON_HPD_NONE;
1963 if (!radeon_apply_legacy_quirks(dev, i, &connector,
1967 switch (connector) {
1968 case CONNECTOR_PROPRIETARY_LEGACY:
1969 if ((tmp >> 4) & 0x1)
1970 devices = ATOM_DEVICE_DFP2_SUPPORT;
1972 devices = ATOM_DEVICE_DFP1_SUPPORT;
1973 radeon_add_legacy_encoder(dev,
1974 radeon_get_encoder_id
1977 radeon_add_legacy_connector(dev, i, devices,
1978 legacy_connector_convert
1981 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1984 case CONNECTOR_CRT_LEGACY:
1986 devices = ATOM_DEVICE_CRT2_SUPPORT;
1987 radeon_add_legacy_encoder(dev,
1988 radeon_get_encoder_id
1990 ATOM_DEVICE_CRT2_SUPPORT,
1992 ATOM_DEVICE_CRT2_SUPPORT);
1994 devices = ATOM_DEVICE_CRT1_SUPPORT;
1995 radeon_add_legacy_encoder(dev,
1996 radeon_get_encoder_id
1998 ATOM_DEVICE_CRT1_SUPPORT,
2000 ATOM_DEVICE_CRT1_SUPPORT);
2002 radeon_add_legacy_connector(dev,
2005 legacy_connector_convert
2008 CONNECTOR_OBJECT_ID_VGA,
2011 case CONNECTOR_DVI_I_LEGACY:
2014 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2015 radeon_add_legacy_encoder(dev,
2016 radeon_get_encoder_id
2018 ATOM_DEVICE_CRT2_SUPPORT,
2020 ATOM_DEVICE_CRT2_SUPPORT);
2022 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2023 radeon_add_legacy_encoder(dev,
2024 radeon_get_encoder_id
2026 ATOM_DEVICE_CRT1_SUPPORT,
2028 ATOM_DEVICE_CRT1_SUPPORT);
2030 if ((tmp >> 4) & 0x1) {
2031 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2032 radeon_add_legacy_encoder(dev,
2033 radeon_get_encoder_id
2035 ATOM_DEVICE_DFP2_SUPPORT,
2037 ATOM_DEVICE_DFP2_SUPPORT);
2038 connector_object_id = combios_check_dl_dvi(dev, 0);
2040 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2041 radeon_add_legacy_encoder(dev,
2042 radeon_get_encoder_id
2044 ATOM_DEVICE_DFP1_SUPPORT,
2046 ATOM_DEVICE_DFP1_SUPPORT);
2047 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2049 radeon_add_legacy_connector(dev,
2052 legacy_connector_convert
2055 connector_object_id,
2058 case CONNECTOR_DVI_D_LEGACY:
2059 if ((tmp >> 4) & 0x1) {
2060 devices = ATOM_DEVICE_DFP2_SUPPORT;
2061 connector_object_id = combios_check_dl_dvi(dev, 1);
2063 devices = ATOM_DEVICE_DFP1_SUPPORT;
2064 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2066 radeon_add_legacy_encoder(dev,
2067 radeon_get_encoder_id
2070 radeon_add_legacy_connector(dev, i, devices,
2071 legacy_connector_convert
2074 connector_object_id,
2077 case CONNECTOR_CTV_LEGACY:
2078 case CONNECTOR_STV_LEGACY:
2079 radeon_add_legacy_encoder(dev,
2080 radeon_get_encoder_id
2082 ATOM_DEVICE_TV1_SUPPORT,
2084 ATOM_DEVICE_TV1_SUPPORT);
2085 radeon_add_legacy_connector(dev, i,
2086 ATOM_DEVICE_TV1_SUPPORT,
2087 legacy_connector_convert
2090 CONNECTOR_OBJECT_ID_SVIDEO,
2094 DRM_ERROR("Unknown connector type: %d\n",
2101 uint16_t tmds_info =
2102 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2104 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2106 radeon_add_legacy_encoder(dev,
2107 radeon_get_encoder_id(dev,
2108 ATOM_DEVICE_CRT1_SUPPORT,
2110 ATOM_DEVICE_CRT1_SUPPORT);
2111 radeon_add_legacy_encoder(dev,
2112 radeon_get_encoder_id(dev,
2113 ATOM_DEVICE_DFP1_SUPPORT,
2115 ATOM_DEVICE_DFP1_SUPPORT);
2117 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2118 hpd.hpd = RADEON_HPD_NONE;
2119 radeon_add_legacy_connector(dev,
2121 ATOM_DEVICE_CRT1_SUPPORT |
2122 ATOM_DEVICE_DFP1_SUPPORT,
2123 DRM_MODE_CONNECTOR_DVII,
2125 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2129 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2130 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2132 radeon_add_legacy_encoder(dev,
2133 radeon_get_encoder_id(dev,
2134 ATOM_DEVICE_CRT1_SUPPORT,
2136 ATOM_DEVICE_CRT1_SUPPORT);
2137 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2138 hpd.hpd = RADEON_HPD_NONE;
2139 radeon_add_legacy_connector(dev,
2141 ATOM_DEVICE_CRT1_SUPPORT,
2142 DRM_MODE_CONNECTOR_VGA,
2144 CONNECTOR_OBJECT_ID_VGA,
2147 DRM_DEBUG("No connector info found\n");
2153 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2155 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2157 uint16_t lcd_ddc_info =
2158 combios_get_table_offset(dev,
2159 COMBIOS_LCD_DDC_INFO_TABLE);
2161 radeon_add_legacy_encoder(dev,
2162 radeon_get_encoder_id(dev,
2163 ATOM_DEVICE_LCD1_SUPPORT,
2165 ATOM_DEVICE_LCD1_SUPPORT);
2168 ddc_type = RBIOS8(lcd_ddc_info + 2);
2172 combios_setup_i2c_bus
2173 (rdev, RADEON_GPIO_MONID);
2177 combios_setup_i2c_bus
2178 (rdev, RADEON_GPIO_DVI_DDC);
2182 combios_setup_i2c_bus
2183 (rdev, RADEON_GPIO_VGA_DDC);
2187 combios_setup_i2c_bus
2188 (rdev, RADEON_GPIO_CRT2_DDC);
2192 combios_setup_i2c_bus
2193 (rdev, RADEON_GPIOPAD_MASK);
2194 ddc_i2c.mask_clk_mask =
2195 RBIOS32(lcd_ddc_info + 3);
2196 ddc_i2c.mask_data_mask =
2197 RBIOS32(lcd_ddc_info + 7);
2198 ddc_i2c.a_clk_mask =
2199 RBIOS32(lcd_ddc_info + 3);
2200 ddc_i2c.a_data_mask =
2201 RBIOS32(lcd_ddc_info + 7);
2202 ddc_i2c.en_clk_mask =
2203 RBIOS32(lcd_ddc_info + 3);
2204 ddc_i2c.en_data_mask =
2205 RBIOS32(lcd_ddc_info + 7);
2206 ddc_i2c.y_clk_mask =
2207 RBIOS32(lcd_ddc_info + 3);
2208 ddc_i2c.y_data_mask =
2209 RBIOS32(lcd_ddc_info + 7);
2213 combios_setup_i2c_bus
2214 (rdev, RADEON_MDGPIO_MASK);
2215 ddc_i2c.mask_clk_mask =
2216 RBIOS32(lcd_ddc_info + 3);
2217 ddc_i2c.mask_data_mask =
2218 RBIOS32(lcd_ddc_info + 7);
2219 ddc_i2c.a_clk_mask =
2220 RBIOS32(lcd_ddc_info + 3);
2221 ddc_i2c.a_data_mask =
2222 RBIOS32(lcd_ddc_info + 7);
2223 ddc_i2c.en_clk_mask =
2224 RBIOS32(lcd_ddc_info + 3);
2225 ddc_i2c.en_data_mask =
2226 RBIOS32(lcd_ddc_info + 7);
2227 ddc_i2c.y_clk_mask =
2228 RBIOS32(lcd_ddc_info + 3);
2229 ddc_i2c.y_data_mask =
2230 RBIOS32(lcd_ddc_info + 7);
2233 ddc_i2c.valid = false;
2236 DRM_DEBUG("LCD DDC Info Table found!\n");
2238 ddc_i2c.valid = false;
2240 hpd.hpd = RADEON_HPD_NONE;
2241 radeon_add_legacy_connector(dev,
2243 ATOM_DEVICE_LCD1_SUPPORT,
2244 DRM_MODE_CONNECTOR_LVDS,
2246 CONNECTOR_OBJECT_ID_LVDS,
2251 /* check TV table */
2252 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2254 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2256 if (RBIOS8(tv_info + 6) == 'T') {
2257 if (radeon_apply_legacy_tv_quirks(dev)) {
2258 hpd.hpd = RADEON_HPD_NONE;
2259 radeon_add_legacy_encoder(dev,
2260 radeon_get_encoder_id
2262 ATOM_DEVICE_TV1_SUPPORT,
2264 ATOM_DEVICE_TV1_SUPPORT);
2265 radeon_add_legacy_connector(dev, 6,
2266 ATOM_DEVICE_TV1_SUPPORT,
2267 DRM_MODE_CONNECTOR_SVIDEO,
2269 CONNECTOR_OBJECT_ID_SVIDEO,
2276 radeon_link_encoder_connector(dev);
2281 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2283 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2284 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2289 switch (tmds->dvo_chip) {
2292 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2293 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2296 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2299 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2302 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2305 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2308 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2311 /* sil 1178 - untested */
2330 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2332 struct drm_device *dev = encoder->dev;
2333 struct radeon_device *rdev = dev->dev_private;
2334 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2336 uint8_t blocks, slave_addr, rev;
2338 uint32_t reg, val, and_mask, or_mask;
2339 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2341 if (rdev->bios == NULL)
2347 if (rdev->flags & RADEON_IS_IGP) {
2348 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2349 rev = RBIOS8(offset);
2351 rev = RBIOS8(offset);
2353 blocks = RBIOS8(offset + 3);
2355 while (blocks > 0) {
2356 id = RBIOS16(index);
2360 reg = (id & 0x1fff) * 4;
2361 val = RBIOS32(index);
2366 reg = (id & 0x1fff) * 4;
2367 and_mask = RBIOS32(index);
2369 or_mask = RBIOS32(index);
2372 val = (val & and_mask) | or_mask;
2376 val = RBIOS16(index);
2381 val = RBIOS16(index);
2386 slave_addr = id & 0xff;
2387 slave_addr >>= 1; /* 7 bit addressing */
2389 reg = RBIOS8(index);
2391 val = RBIOS8(index);
2393 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2394 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2397 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2400 DRM_ERROR("Unknown id %d\n", id >> 13);
2409 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2411 index = offset + 10;
2412 id = RBIOS16(index);
2413 while (id != 0xffff) {
2417 reg = (id & 0x1fff) * 4;
2418 val = RBIOS32(index);
2422 reg = (id & 0x1fff) * 4;
2423 and_mask = RBIOS32(index);
2425 or_mask = RBIOS32(index);
2428 val = (val & and_mask) | or_mask;
2432 val = RBIOS16(index);
2438 and_mask = RBIOS32(index);
2440 or_mask = RBIOS32(index);
2442 val = RREG32_PLL(reg);
2443 val = (val & and_mask) | or_mask;
2444 WREG32_PLL(reg, val);
2448 val = RBIOS8(index);
2450 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2451 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2454 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2457 DRM_ERROR("Unknown id %d\n", id >> 13);
2460 id = RBIOS16(index);
2468 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2470 struct radeon_device *rdev = dev->dev_private;
2473 while (RBIOS16(offset)) {
2474 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2475 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2476 uint32_t val, and_mask, or_mask;
2482 val = RBIOS32(offset);
2487 val = RBIOS32(offset);
2492 and_mask = RBIOS32(offset);
2494 or_mask = RBIOS32(offset);
2502 and_mask = RBIOS32(offset);
2504 or_mask = RBIOS32(offset);
2512 val = RBIOS16(offset);
2517 val = RBIOS16(offset);
2524 (RADEON_CLK_PWRMGT_CNTL) &
2531 if ((RREG32(RADEON_MC_STATUS) &
2547 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2549 struct radeon_device *rdev = dev->dev_private;
2552 while (RBIOS8(offset)) {
2553 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2554 uint8_t addr = (RBIOS8(offset) & 0x3f);
2555 uint32_t val, shift, tmp;
2556 uint32_t and_mask, or_mask;
2561 val = RBIOS32(offset);
2563 WREG32_PLL(addr, val);
2566 shift = RBIOS8(offset) * 8;
2568 and_mask = RBIOS8(offset) << shift;
2569 and_mask |= ~(0xff << shift);
2571 or_mask = RBIOS8(offset) << shift;
2573 tmp = RREG32_PLL(addr);
2576 WREG32_PLL(addr, tmp);
2592 (RADEON_CLK_PWRMGT_CNTL) &
2600 (RADEON_CLK_PWRMGT_CNTL) &
2607 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2608 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2610 uint32_t mclk_cntl =
2613 mclk_cntl &= 0xffff0000;
2614 /*mclk_cntl |= 0x00001111;*//* ??? */
2615 WREG32_PLL(RADEON_MCLK_CNTL,
2620 (RADEON_CLK_PWRMGT_CNTL,
2622 ~RADEON_CG_NO1_DEBUG_0);
2637 static void combios_parse_ram_reset_table(struct drm_device *dev,
2640 struct radeon_device *rdev = dev->dev_private;
2644 uint8_t val = RBIOS8(offset);
2645 while (val != 0xff) {
2649 uint32_t channel_complete_mask;
2651 if (ASIC_IS_R300(rdev))
2652 channel_complete_mask =
2653 R300_MEM_PWRUP_COMPLETE;
2655 channel_complete_mask =
2656 RADEON_MEM_PWRUP_COMPLETE;
2659 if ((RREG32(RADEON_MEM_STR_CNTL) &
2660 channel_complete_mask) ==
2661 channel_complete_mask)
2665 uint32_t or_mask = RBIOS16(offset);
2668 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2669 tmp &= RADEON_SDRAM_MODE_MASK;
2671 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2673 or_mask = val << 24;
2674 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2675 tmp &= RADEON_B3MEM_RESET_MASK;
2677 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2679 val = RBIOS8(offset);
2684 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2685 int mem_addr_mapping)
2687 struct radeon_device *rdev = dev->dev_private;
2692 mem_cntl = RREG32(RADEON_MEM_CNTL);
2693 if (mem_cntl & RV100_HALF_MODE)
2696 mem_cntl &= ~(0xff << 8);
2697 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2698 WREG32(RADEON_MEM_CNTL, mem_cntl);
2699 RREG32(RADEON_MEM_CNTL);
2703 /* something like this???? */
2705 addr = ram * 1024 * 1024;
2706 /* write to each page */
2707 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2708 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2709 /* read back and verify */
2710 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2711 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2718 static void combios_write_ram_size(struct drm_device *dev)
2720 struct radeon_device *rdev = dev->dev_private;
2723 uint32_t mem_size = 0;
2724 uint32_t mem_cntl = 0;
2726 /* should do something smarter here I guess... */
2727 if (rdev->flags & RADEON_IS_IGP)
2730 /* first check detected mem table */
2731 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2733 rev = RBIOS8(offset);
2735 mem_cntl = RBIOS32(offset + 1);
2736 mem_size = RBIOS16(offset + 5);
2737 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2738 ((dev->pdev->device != 0x515e)
2739 && (dev->pdev->device != 0x5969)))
2740 WREG32(RADEON_MEM_CNTL, mem_cntl);
2746 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2748 rev = RBIOS8(offset - 1);
2750 if (((rdev->flags & RADEON_FAMILY_MASK) <
2752 && ((dev->pdev->device != 0x515e)
2753 && (dev->pdev->device != 0x5969))) {
2755 int mem_addr_mapping = 0;
2757 while (RBIOS8(offset)) {
2758 ram = RBIOS8(offset);
2761 if (mem_addr_mapping != 0x25)
2764 combios_detect_ram(dev, ram,
2771 mem_size = RBIOS8(offset);
2773 mem_size = RBIOS8(offset);
2774 mem_size *= 2; /* convert to MB */
2779 mem_size *= (1024 * 1024); /* convert to bytes */
2780 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2783 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2785 uint16_t dyn_clk_info =
2786 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2789 combios_parse_pll_table(dev, dyn_clk_info);
2792 void radeon_combios_asic_init(struct drm_device *dev)
2794 struct radeon_device *rdev = dev->dev_private;
2797 /* port hardcoded mac stuff from radeonfb */
2798 if (rdev->bios == NULL)
2802 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2804 combios_parse_mmio_table(dev, table);
2807 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2809 combios_parse_pll_table(dev, table);
2812 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2814 combios_parse_mmio_table(dev, table);
2816 if (!(rdev->flags & RADEON_IS_IGP)) {
2819 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2821 combios_parse_mmio_table(dev, table);
2824 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2826 combios_parse_ram_reset_table(dev, table);
2830 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2832 combios_parse_mmio_table(dev, table);
2834 /* write CONFIG_MEMSIZE */
2835 combios_write_ram_size(dev);
2839 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2841 combios_parse_pll_table(dev, table);
2845 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2847 struct radeon_device *rdev = dev->dev_private;
2848 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2850 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2851 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2852 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2854 /* let the bios control the backlight */
2855 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2857 /* tell the bios not to handle mode switching */
2858 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2859 RADEON_ACC_MODE_CHANGE);
2861 /* tell the bios a driver is loaded */
2862 bios_7_scratch |= RADEON_DRV_LOADED;
2864 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2865 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2866 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2869 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2871 struct drm_device *dev = encoder->dev;
2872 struct radeon_device *rdev = dev->dev_private;
2873 uint32_t bios_6_scratch;
2875 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2878 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2880 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2882 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2886 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2887 struct drm_encoder *encoder,
2890 struct drm_device *dev = connector->dev;
2891 struct radeon_device *rdev = dev->dev_private;
2892 struct radeon_connector *radeon_connector =
2893 to_radeon_connector(connector);
2894 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2895 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2896 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2898 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2899 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2901 DRM_DEBUG("TV1 connected\n");
2903 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2904 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2905 bios_5_scratch |= RADEON_TV1_ON;
2906 bios_5_scratch |= RADEON_ACC_REQ_TV1;
2908 DRM_DEBUG("TV1 disconnected\n");
2909 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2910 bios_5_scratch &= ~RADEON_TV1_ON;
2911 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2914 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2915 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2917 DRM_DEBUG("LCD1 connected\n");
2918 bios_4_scratch |= RADEON_LCD1_ATTACHED;
2919 bios_5_scratch |= RADEON_LCD1_ON;
2920 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2922 DRM_DEBUG("LCD1 disconnected\n");
2923 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2924 bios_5_scratch &= ~RADEON_LCD1_ON;
2925 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2928 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2929 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2931 DRM_DEBUG("CRT1 connected\n");
2932 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2933 bios_5_scratch |= RADEON_CRT1_ON;
2934 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2936 DRM_DEBUG("CRT1 disconnected\n");
2937 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2938 bios_5_scratch &= ~RADEON_CRT1_ON;
2939 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2942 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2943 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2945 DRM_DEBUG("CRT2 connected\n");
2946 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2947 bios_5_scratch |= RADEON_CRT2_ON;
2948 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2950 DRM_DEBUG("CRT2 disconnected\n");
2951 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2952 bios_5_scratch &= ~RADEON_CRT2_ON;
2953 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2956 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2957 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2959 DRM_DEBUG("DFP1 connected\n");
2960 bios_4_scratch |= RADEON_DFP1_ATTACHED;
2961 bios_5_scratch |= RADEON_DFP1_ON;
2962 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2964 DRM_DEBUG("DFP1 disconnected\n");
2965 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2966 bios_5_scratch &= ~RADEON_DFP1_ON;
2967 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2970 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2971 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2973 DRM_DEBUG("DFP2 connected\n");
2974 bios_4_scratch |= RADEON_DFP2_ATTACHED;
2975 bios_5_scratch |= RADEON_DFP2_ON;
2976 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2978 DRM_DEBUG("DFP2 disconnected\n");
2979 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2980 bios_5_scratch &= ~RADEON_DFP2_ON;
2981 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2984 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2985 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2989 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2991 struct drm_device *dev = encoder->dev;
2992 struct radeon_device *rdev = dev->dev_private;
2993 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2994 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2996 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2997 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2998 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3000 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3001 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3002 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3004 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3005 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3006 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3008 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3009 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3010 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3012 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3013 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3014 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3016 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3017 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3018 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3020 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3024 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3026 struct drm_device *dev = encoder->dev;
3027 struct radeon_device *rdev = dev->dev_private;
3028 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3029 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3031 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3033 bios_6_scratch |= RADEON_TV_DPMS_ON;
3035 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3037 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3039 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3041 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3043 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3045 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3047 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3049 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3051 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3053 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3055 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);