drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  43                       uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  57                           uint32_t supported_device);
  58
  59 /* old legacy ATI BIOS routines */
  60
  61 /* COMBIOS table offsets */
  62 enum radeon_combios_table_offset {
  63         /* absolute offset tables */
  64         COMBIOS_ASIC_INIT_1_TABLE,
  65         COMBIOS_BIOS_SUPPORT_TABLE,
  66         COMBIOS_DAC_PROGRAMMING_TABLE,
  67         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  68         COMBIOS_CRTC_INFO_TABLE,
  69         COMBIOS_PLL_INFO_TABLE,
  70         COMBIOS_TV_INFO_TABLE,
  71         COMBIOS_DFP_INFO_TABLE,
  72         COMBIOS_HW_CONFIG_INFO_TABLE,
  73         COMBIOS_MULTIMEDIA_INFO_TABLE,
  74         COMBIOS_TV_STD_PATCH_TABLE,
  75         COMBIOS_LCD_INFO_TABLE,
  76         COMBIOS_MOBILE_INFO_TABLE,
  77         COMBIOS_PLL_INIT_TABLE,
  78         COMBIOS_MEM_CONFIG_TABLE,
  79         COMBIOS_SAVE_MASK_TABLE,
  80         COMBIOS_HARDCODED_EDID_TABLE,
  81         COMBIOS_ASIC_INIT_2_TABLE,
  82         COMBIOS_CONNECTOR_INFO_TABLE,
  83         COMBIOS_DYN_CLK_1_TABLE,
  84         COMBIOS_RESERVED_MEM_TABLE,
  85         COMBIOS_EXT_TMDS_INFO_TABLE,
  86         COMBIOS_MEM_CLK_INFO_TABLE,
  87         COMBIOS_EXT_DAC_INFO_TABLE,
  88         COMBIOS_MISC_INFO_TABLE,
  89         COMBIOS_CRT_INFO_TABLE,
  90         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  91         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  92         COMBIOS_FAN_SPEED_INFO_TABLE,
  93         COMBIOS_OVERDRIVE_INFO_TABLE,
  94         COMBIOS_OEM_INFO_TABLE,
  95         COMBIOS_DYN_CLK_2_TABLE,
  96         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  97         COMBIOS_I2C_INFO_TABLE,
  98         /* relative offset tables */
  99         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 100         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 101         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 102         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 103         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 104         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 105         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 106         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 107         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 108         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 109         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 110 };
 111
 112 enum radeon_combios_ddc {
 113         DDC_NONE_DETECTED,
 114         DDC_MONID,
 115         DDC_DVI,
 116         DDC_VGA,
 117         DDC_CRT2,
 118         DDC_LCD,
 119         DDC_GPIO,
 120 };
 121
 122 enum radeon_combios_connector {
 123         CONNECTOR_NONE_LEGACY,
 124         CONNECTOR_PROPRIETARY_LEGACY,
 125         CONNECTOR_CRT_LEGACY,
 126         CONNECTOR_DVI_I_LEGACY,
 127         CONNECTOR_DVI_D_LEGACY,
 128         CONNECTOR_CTV_LEGACY,
 129         CONNECTOR_STV_LEGACY,
 130         CONNECTOR_UNSUPPORTED_LEGACY
 131 };
 132
 133 const int legacy_connector_convert[] = {
 134         DRM_MODE_CONNECTOR_Unknown,
 135         DRM_MODE_CONNECTOR_DVID,
 136         DRM_MODE_CONNECTOR_VGA,
 137         DRM_MODE_CONNECTOR_DVII,
 138         DRM_MODE_CONNECTOR_DVID,
 139         DRM_MODE_CONNECTOR_Composite,
 140         DRM_MODE_CONNECTOR_SVIDEO,
 141         DRM_MODE_CONNECTOR_Unknown,
 142 };
 143
 144 static uint16_t combios_get_table_offset(struct drm_device *dev,
 145                                          enum radeon_combios_table_offset table)
 146 {
 147         struct radeon_device *rdev = dev->dev_private;
 148         int rev;
 149         uint16_t offset = 0, check_offset;
 150
 151         switch (table) {
 152                 /* absolute offset tables */
 153         case COMBIOS_ASIC_INIT_1_TABLE:
 154                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 155                 if (check_offset)
 156                         offset = check_offset;
 157                 break;
 158         case COMBIOS_BIOS_SUPPORT_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_DAC_PROGRAMMING_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_CRTC_INFO_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_PLL_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_TV_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_DFP_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_HW_CONFIG_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_TV_STD_PATCH_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_LCD_INFO_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_MOBILE_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_PLL_INIT_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_MEM_CONFIG_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_SAVE_MASK_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_HARDCODED_EDID_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_ASIC_INIT_2_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_CONNECTOR_INFO_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_DYN_CLK_1_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_RESERVED_MEM_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_EXT_TMDS_INFO_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_MEM_CLK_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_EXT_DAC_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_MISC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_CRT_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_FAN_SPEED_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_OVERDRIVE_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OEM_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_DYN_CLK_2_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_I2C_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323                 /* relative offset tables */
 324         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 325                 check_offset =
 326                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 327                 if (check_offset) {
 328                         rev = RBIOS8(check_offset);
 329                         if (rev > 0) {
 330                                 check_offset = RBIOS16(check_offset + 0x3);
 331                                 if (check_offset)
 332                                         offset = check_offset;
 333                         }
 334                 }
 335                 break;
 336         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 337                 check_offset =
 338                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 339                 if (check_offset) {
 340                         rev = RBIOS8(check_offset);
 341                         if (rev > 0) {
 342                                 check_offset = RBIOS16(check_offset + 0x5);
 343                                 if (check_offset)
 344                                         offset = check_offset;
 345                         }
 346                 }
 347                 break;
 348         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 349                 check_offset =
 350                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 351                 if (check_offset) {
 352                         rev = RBIOS8(check_offset);
 353                         if (rev > 0) {
 354                                 check_offset = RBIOS16(check_offset + 0x7);
 355                                 if (check_offset)
 356                                         offset = check_offset;
 357                         }
 358                 }
 359                 break;
 360         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 361                 check_offset =
 362                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 363                 if (check_offset) {
 364                         rev = RBIOS8(check_offset);
 365                         if (rev == 2) {
 366                                 check_offset = RBIOS16(check_offset + 0x9);
 367                                 if (check_offset)
 368                                         offset = check_offset;
 369                         }
 370                 }
 371                 break;
 372         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 373                 check_offset =
 374                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 375                 if (check_offset) {
 376                         while (RBIOS8(check_offset++));
 377                         check_offset += 2;
 378                         if (check_offset)
 379                                 offset = check_offset;
 380                 }
 381                 break;
 382         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 383                 check_offset =
 384                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 385                 if (check_offset) {
 386                         check_offset = RBIOS16(check_offset + 0x11);
 387                         if (check_offset)
 388                                 offset = check_offset;
 389                 }
 390                 break;
 391         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 392                 check_offset =
 393                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 394                 if (check_offset) {
 395                         check_offset = RBIOS16(check_offset + 0x13);
 396                         if (check_offset)
 397                                 offset = check_offset;
 398                 }
 399                 break;
 400         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 401                 check_offset =
 402                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 403                 if (check_offset) {
 404                         check_offset = RBIOS16(check_offset + 0x15);
 405                         if (check_offset)
 406                                 offset = check_offset;
 407                 }
 408                 break;
 409         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 410                 check_offset =
 411                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 412                 if (check_offset) {
 413                         check_offset = RBIOS16(check_offset + 0x17);
 414                         if (check_offset)
 415                                 offset = check_offset;
 416                 }
 417                 break;
 418         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 419                 check_offset =
 420                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 421                 if (check_offset) {
 422                         check_offset = RBIOS16(check_offset + 0x2);
 423                         if (check_offset)
 424                                 offset = check_offset;
 425                 }
 426                 break;
 427         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 428                 check_offset =
 429                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 430                 if (check_offset) {
 431                         check_offset = RBIOS16(check_offset + 0x4);
 432                         if (check_offset)
 433                                 offset = check_offset;
 434                 }
 435                 break;
 436         default:
 437                 break;
 438         }
 439
 440         return offset;
 441
 442 }
 443
 444 struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
 445 {
 446         struct radeon_i2c_bus_rec i2c;
 447
 448         i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 449         i2c.mask_data_mask = RADEON_GPIO_EN_0;
 450         i2c.a_clk_mask = RADEON_GPIO_A_1;
 451         i2c.a_data_mask = RADEON_GPIO_A_0;
 452         i2c.put_clk_mask = RADEON_GPIO_EN_1;
 453         i2c.put_data_mask = RADEON_GPIO_EN_0;
 454         i2c.get_clk_mask = RADEON_GPIO_Y_1;
 455         i2c.get_data_mask = RADEON_GPIO_Y_0;
 456         if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
 457             (ddc_line == RADEON_MDGPIO_EN_REG)) {
 458                 i2c.mask_clk_reg = ddc_line;
 459                 i2c.mask_data_reg = ddc_line;
 460                 i2c.a_clk_reg = ddc_line;
 461                 i2c.a_data_reg = ddc_line;
 462                 i2c.put_clk_reg = ddc_line;
 463                 i2c.put_data_reg = ddc_line;
 464                 i2c.get_clk_reg = ddc_line + 4;
 465                 i2c.get_data_reg = ddc_line + 4;
 466         } else {
 467                 i2c.mask_clk_reg = ddc_line;
 468                 i2c.mask_data_reg = ddc_line;
 469                 i2c.a_clk_reg = ddc_line;
 470                 i2c.a_data_reg = ddc_line;
 471                 i2c.put_clk_reg = ddc_line;
 472                 i2c.put_data_reg = ddc_line;
 473                 i2c.get_clk_reg = ddc_line;
 474                 i2c.get_data_reg = ddc_line;
 475         }
 476
 477         if (ddc_line)
 478                 i2c.valid = true;
 479         else
 480                 i2c.valid = false;
 481
 482         return i2c;
 483 }
 484
 485 bool radeon_combios_get_clock_info(struct drm_device *dev)
 486 {
 487         struct radeon_device *rdev = dev->dev_private;
 488         uint16_t pll_info;
 489         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 490         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 491         struct radeon_pll *spll = &rdev->clock.spll;
 492         struct radeon_pll *mpll = &rdev->clock.mpll;
 493         int8_t rev;
 494         uint16_t sclk, mclk;
 495
 496         if (rdev->bios == NULL)
 497                 return NULL;
 498
 499         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 500         if (pll_info) {
 501                 rev = RBIOS8(pll_info);
 502
 503                 /* pixel clocks */
 504                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 505                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 506                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 507                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 508
 509                 if (rev > 9) {
 510                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 511                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 512                 } else {
 513                         p1pll->pll_in_min = 40;
 514                         p1pll->pll_in_max = 500;
 515                 }
 516                 *p2pll = *p1pll;
 517
 518                 /* system clock */
 519                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 520                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 521                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 522                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 523
 524                 if (rev > 10) {
 525                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 526                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 527                 } else {
 528                         /* ??? */
 529                         spll->pll_in_min = 40;
 530                         spll->pll_in_max = 500;
 531                 }
 532
 533                 /* memory clock */
 534                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 535                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 536                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 537                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 538
 539                 if (rev > 10) {
 540                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 541                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 542                 } else {
 543                         /* ??? */
 544                         mpll->pll_in_min = 40;
 545                         mpll->pll_in_max = 500;
 546                 }
 547
 548                 /* default sclk/mclk */
 549                 sclk = RBIOS16(pll_info + 0xa);
 550                 mclk = RBIOS16(pll_info + 0x8);
 551                 if (sclk == 0)
 552                         sclk = 200 * 100;
 553                 if (mclk == 0)
 554                         mclk = 200 * 100;
 555
 556                 rdev->clock.default_sclk = sclk;
 557                 rdev->clock.default_mclk = mclk;
 558
 559                 return true;
 560         }
 561         return false;
 562 }
 563
 564 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 565                                                                        radeon_encoder
 566                                                                        *encoder)
 567 {
 568         struct drm_device *dev = encoder->base.dev;
 569         struct radeon_device *rdev = dev->dev_private;
 570         uint16_t dac_info;
 571         uint8_t rev, bg, dac;
 572         struct radeon_encoder_primary_dac *p_dac = NULL;
 573
 574         if (rdev->bios == NULL)
 575                 return NULL;
 576
 577         /* check CRT table */
 578         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 579         if (dac_info) {
 580                 p_dac =
 581                     kzalloc(sizeof(struct radeon_encoder_primary_dac),
 582                             GFP_KERNEL);
 583
 584                 if (!p_dac)
 585                         return NULL;
 586
 587                 rev = RBIOS8(dac_info) & 0x3;
 588                 if (rev < 2) {
 589                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 590                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 591                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 592                 } else {
 593                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 594                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 595                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 596                 }
 597
 598         }
 599
 600         return p_dac;
 601 }
 602
 603 static enum radeon_tv_std
 604 radeon_combios_get_tv_info(struct radeon_encoder *encoder)
 605 {
 606         struct drm_device *dev = encoder->base.dev;
 607         struct radeon_device *rdev = dev->dev_private;
 608         uint16_t tv_info;
 609         enum radeon_tv_std tv_std = TV_STD_NTSC;
 610
 611         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 612         if (tv_info) {
 613                 if (RBIOS8(tv_info + 6) == 'T') {
 614                         switch (RBIOS8(tv_info + 7) & 0xf) {
 615                         case 1:
 616                                 tv_std = TV_STD_NTSC;
 617                                 DRM_INFO("Default TV standard: NTSC\n");
 618                                 break;
 619                         case 2:
 620                                 tv_std = TV_STD_PAL;
 621                                 DRM_INFO("Default TV standard: PAL\n");
 622                                 break;
 623                         case 3:
 624                                 tv_std = TV_STD_PAL_M;
 625                                 DRM_INFO("Default TV standard: PAL-M\n");
 626                                 break;
 627                         case 4:
 628                                 tv_std = TV_STD_PAL_60;
 629                                 DRM_INFO("Default TV standard: PAL-60\n");
 630                                 break;
 631                         case 5:
 632                                 tv_std = TV_STD_NTSC_J;
 633                                 DRM_INFO("Default TV standard: NTSC-J\n");
 634                                 break;
 635                         case 6:
 636                                 tv_std = TV_STD_SCART_PAL;
 637                                 DRM_INFO("Default TV standard: SCART-PAL\n");
 638                                 break;
 639                         default:
 640                                 tv_std = TV_STD_NTSC;
 641                                 DRM_INFO
 642                                     ("Unknown TV standard; defaulting to NTSC\n");
 643                                 break;
 644                         }
 645
 646                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 647                         case 0:
 648                                 DRM_INFO("29.498928713 MHz TV ref clk\n");
 649                                 break;
 650                         case 1:
 651                                 DRM_INFO("28.636360000 MHz TV ref clk\n");
 652                                 break;
 653                         case 2:
 654                                 DRM_INFO("14.318180000 MHz TV ref clk\n");
 655                                 break;
 656                         case 3:
 657                                 DRM_INFO("27.000000000 MHz TV ref clk\n");
 658                                 break;
 659                         default:
 660                                 break;
 661                         }
 662                 }
 663         }
 664         return tv_std;
 665 }
 666
 667 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 668         0x00000000,             /* r100  */
 669         0x00280000,             /* rv100 */
 670         0x00000000,             /* rs100 */
 671         0x00880000,             /* rv200 */
 672         0x00000000,             /* rs200 */
 673         0x00000000,             /* r200  */
 674         0x00770000,             /* rv250 */
 675         0x00290000,             /* rs300 */
 676         0x00560000,             /* rv280 */
 677         0x00780000,             /* r300  */
 678         0x00770000,             /* r350  */
 679         0x00780000,             /* rv350 */
 680         0x00780000,             /* rv380 */
 681         0x01080000,             /* r420  */
 682         0x01080000,             /* r423  */
 683         0x01080000,             /* rv410 */
 684         0x00780000,             /* rs400 */
 685         0x00780000,             /* rs480 */
 686 };
 687
 688 static struct radeon_encoder_tv_dac
 689     *radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev)
 690 {
 691         struct radeon_encoder_tv_dac *tv_dac = NULL;
 692
 693         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 694
 695         if (!tv_dac)
 696                 return NULL;
 697
 698         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
 699         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
 700                 tv_dac->ps2_tvdac_adj = 0x00880000;
 701         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 702         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 703
 704         return tv_dac;
 705 }
 706
 707 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
 708                                                              radeon_encoder
 709                                                              *encoder)
 710 {
 711         struct drm_device *dev = encoder->base.dev;
 712         struct radeon_device *rdev = dev->dev_private;
 713         uint16_t dac_info;
 714         uint8_t rev, bg, dac;
 715         struct radeon_encoder_tv_dac *tv_dac = NULL;
 716
 717         if (rdev->bios == NULL)
 718                 return radeon_legacy_get_tv_dac_info_from_table(rdev);
 719
 720         /* first check TV table */
 721         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 722         if (dac_info) {
 723                 tv_dac =
 724                     kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 725
 726                 if (!tv_dac)
 727                         return NULL;
 728
 729                 rev = RBIOS8(dac_info + 0x3);
 730                 if (rev > 4) {
 731                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 732                         dac = RBIOS8(dac_info + 0xd) & 0xf;
 733                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 734
 735                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 736                         dac = RBIOS8(dac_info + 0xf) & 0xf;
 737                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 738
 739                         bg = RBIOS8(dac_info + 0x10) & 0xf;
 740                         dac = RBIOS8(dac_info + 0x11) & 0xf;
 741                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 742                 } else if (rev > 1) {
 743                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 744                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
 745                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 746
 747                         bg = RBIOS8(dac_info + 0xd) & 0xf;
 748                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
 749                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 750
 751                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 752                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
 753                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 754                 }
 755
 756                 tv_dac->tv_std = radeon_combios_get_tv_info(encoder);
 757
 758         } else {
 759                 /* then check CRT table */
 760                 dac_info =
 761                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 762                 if (dac_info) {
 763                         tv_dac =
 764                             kzalloc(sizeof(struct radeon_encoder_tv_dac),
 765                                     GFP_KERNEL);
 766
 767                         if (!tv_dac)
 768                                 return NULL;
 769
 770                         rev = RBIOS8(dac_info) & 0x3;
 771                         if (rev < 2) {
 772                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
 773                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
 774                                 tv_dac->ps2_tvdac_adj =
 775                                     (bg << 16) | (dac << 20);
 776                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 777                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 778                         } else {
 779                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
 780                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
 781                                 tv_dac->ps2_tvdac_adj =
 782                                     (bg << 16) | (dac << 20);
 783                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 784                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 785                         }
 786                 }
 787         }
 788
 789         return tv_dac;
 790 }
 791
 792 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
 793                                                                          radeon_device
 794                                                                          *rdev)
 795 {
 796         struct radeon_encoder_lvds *lvds = NULL;
 797         uint32_t fp_vert_stretch, fp_horz_stretch;
 798         uint32_t ppll_div_sel, ppll_val;
 799
 800         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 801
 802         if (!lvds)
 803                 return NULL;
 804
 805         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
 806         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
 807
 808         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
 809                 lvds->native_mode.panel_yres =
 810                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
 811                      RADEON_VERT_PANEL_SHIFT) + 1;
 812         else
 813                 lvds->native_mode.panel_yres =
 814                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
 815
 816         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
 817                 lvds->native_mode.panel_xres =
 818                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
 819                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
 820         else
 821                 lvds->native_mode.panel_xres =
 822                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
 823
 824         if ((lvds->native_mode.panel_xres < 640) ||
 825             (lvds->native_mode.panel_yres < 480)) {
 826                 lvds->native_mode.panel_xres = 640;
 827                 lvds->native_mode.panel_yres = 480;
 828         }
 829
 830         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
 831         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
 832         if ((ppll_val & 0x000707ff) == 0x1bb)
 833                 lvds->use_bios_dividers = false;
 834         else {
 835                 lvds->panel_ref_divider =
 836                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
 837                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
 838                 lvds->panel_fb_divider = ppll_val & 0x7ff;
 839
 840                 if ((lvds->panel_ref_divider != 0) &&
 841                     (lvds->panel_fb_divider > 3))
 842                         lvds->use_bios_dividers = true;
 843         }
 844         lvds->panel_vcc_delay = 200;
 845
 846         DRM_INFO("Panel info derived from registers\n");
 847         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
 848                  lvds->native_mode.panel_yres);
 849
 850         return lvds;
 851 }
 852
 853 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
 854                                                          *encoder)
 855 {
 856         struct drm_device *dev = encoder->base.dev;
 857         struct radeon_device *rdev = dev->dev_private;
 858         uint16_t lcd_info;
 859         uint32_t panel_setup;
 860         char stmp[30];
 861         int tmp, i;
 862         struct radeon_encoder_lvds *lvds = NULL;
 863
 864         if (rdev->bios == NULL)
 865                 return radeon_legacy_get_lvds_info_from_regs(rdev);
 866
 867         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
 868
 869         if (lcd_info) {
 870                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 871
 872                 if (!lvds)
 873                         return NULL;
 874
 875                 for (i = 0; i < 24; i++)
 876                         stmp[i] = RBIOS8(lcd_info + i + 1);
 877                 stmp[24] = 0;
 878
 879                 DRM_INFO("Panel ID String: %s\n", stmp);
 880
 881                 lvds->native_mode.panel_xres = RBIOS16(lcd_info + 0x19);
 882                 lvds->native_mode.panel_yres = RBIOS16(lcd_info + 0x1b);
 883
 884                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
 885                          lvds->native_mode.panel_yres);
 886
 887                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
 888                 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
 889                         lvds->panel_vcc_delay = 2000;
 890
 891                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
 892                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
 893                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
 894
 895                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
 896                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
 897                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
 898                 if ((lvds->panel_ref_divider != 0) &&
 899                     (lvds->panel_fb_divider > 3))
 900                         lvds->use_bios_dividers = true;
 901
 902                 panel_setup = RBIOS32(lcd_info + 0x39);
 903                 lvds->lvds_gen_cntl = 0xff00;
 904                 if (panel_setup & 0x1)
 905                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
 906
 907                 if ((panel_setup >> 4) & 0x1)
 908                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
 909
 910                 switch ((panel_setup >> 8) & 0x7) {
 911                 case 0:
 912                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
 913                         break;
 914                 case 1:
 915                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
 916                         break;
 917                 case 2:
 918                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
 919                         break;
 920                 default:
 921                         break;
 922                 }
 923
 924                 if ((panel_setup >> 16) & 0x1)
 925                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
 926
 927                 if ((panel_setup >> 17) & 0x1)
 928                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
 929
 930                 if ((panel_setup >> 18) & 0x1)
 931                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
 932
 933                 if ((panel_setup >> 23) & 0x1)
 934                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
 935
 936                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
 937
 938                 for (i = 0; i < 32; i++) {
 939                         tmp = RBIOS16(lcd_info + 64 + i * 2);
 940                         if (tmp == 0)
 941                                 break;
 942
 943                         if ((RBIOS16(tmp) == lvds->native_mode.panel_xres) &&
 944                             (RBIOS16(tmp + 2) ==
 945                              lvds->native_mode.panel_yres)) {
 946                                 lvds->native_mode.hblank =
 947                                     (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
 948                                 lvds->native_mode.hoverplus =
 949                                     (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) -
 950                                      1) * 8;
 951                                 lvds->native_mode.hsync_width =
 952                                     RBIOS8(tmp + 23) * 8;
 953
 954                                 lvds->native_mode.vblank = (RBIOS16(tmp + 24) -
 955                                                             RBIOS16(tmp + 26));
 956                                 lvds->native_mode.voverplus =
 957                                     ((RBIOS16(tmp + 28) & 0x7ff) -
 958                                      RBIOS16(tmp + 26));
 959                                 lvds->native_mode.vsync_width =
 960                                     ((RBIOS16(tmp + 28) & 0xf800) >> 11);
 961                                 lvds->native_mode.dotclock =
 962                                     RBIOS16(tmp + 9) * 10;
 963                                 lvds->native_mode.flags = 0;
 964                         }
 965                 }
 966                 encoder->native_mode = lvds->native_mode;
 967         } else
 968                 DRM_INFO("No panel info found in BIOS\n");
 969         return lvds;
 970 }
 971
 972 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
 973         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
 974         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
 975         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
 976         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
 977         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
 978         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
 979         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
 980         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
 981         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
 982         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
 983         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
 984         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
 985         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
 986         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
 987         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
 988         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
 989         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RS400 */
 990         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RS480 */
 991 };
 992
 993 static struct radeon_encoder_int_tmds
 994     *radeon_legacy_get_tmds_info_from_table(struct radeon_device *rdev)
 995 {
 996         int i;
 997         struct radeon_encoder_int_tmds *tmds = NULL;
 998
 999         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1000
1001         if (!tmds)
1002                 return NULL;
1003
1004         for (i = 0; i < 4; i++) {
1005                 tmds->tmds_pll[i].value =
1006                     default_tmds_pll[rdev->family][i].value;
1007                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1008         }
1009
1010         return tmds;
1011 }
1012
1013 struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct
1014                                                              radeon_encoder
1015                                                              *encoder)
1016 {
1017         struct drm_device *dev = encoder->base.dev;
1018         struct radeon_device *rdev = dev->dev_private;
1019         uint16_t tmds_info;
1020         int i, n;
1021         uint8_t ver;
1022         struct radeon_encoder_int_tmds *tmds = NULL;
1023
1024         if (rdev->bios == NULL)
1025                 return radeon_legacy_get_tmds_info_from_table(rdev);
1026
1027         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1028
1029         if (tmds_info) {
1030                 tmds =
1031                     kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1032
1033                 if (!tmds)
1034                         return NULL;
1035
1036                 ver = RBIOS8(tmds_info);
1037                 DRM_INFO("DFP table revision: %d\n", ver);
1038                 if (ver == 3) {
1039                         n = RBIOS8(tmds_info + 5) + 1;
1040                         if (n > 4)
1041                                 n = 4;
1042                         for (i = 0; i < n; i++) {
1043                                 tmds->tmds_pll[i].value =
1044                                     RBIOS32(tmds_info + i * 10 + 0x08);
1045                                 tmds->tmds_pll[i].freq =
1046                                     RBIOS16(tmds_info + i * 10 + 0x10);
1047                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1048                                           tmds->tmds_pll[i].freq,
1049                                           tmds->tmds_pll[i].value);
1050                         }
1051                 } else if (ver == 4) {
1052                         int stride = 0;
1053                         n = RBIOS8(tmds_info + 5) + 1;
1054                         if (n > 4)
1055                                 n = 4;
1056                         for (i = 0; i < n; i++) {
1057                                 tmds->tmds_pll[i].value =
1058                                     RBIOS32(tmds_info + stride + 0x08);
1059                                 tmds->tmds_pll[i].freq =
1060                                     RBIOS16(tmds_info + stride + 0x10);
1061                                 if (i == 0)
1062                                         stride += 10;
1063                                 else
1064                                         stride += 6;
1065                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1066                                           tmds->tmds_pll[i].freq,
1067                                           tmds->tmds_pll[i].value);
1068                         }
1069                 }
1070         } else
1071                 DRM_INFO("No TMDS info found in BIOS\n");
1072         return tmds;
1073 }
1074
1075 void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder)
1076 {
1077         struct drm_device *dev = encoder->base.dev;
1078         struct radeon_device *rdev = dev->dev_private;
1079         uint16_t ext_tmds_info;
1080         uint8_t ver;
1081
1082         if (rdev->bios == NULL)
1083                 return;
1084
1085         ext_tmds_info =
1086             combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1087         if (ext_tmds_info) {
1088                 ver = RBIOS8(ext_tmds_info);
1089                 DRM_INFO("External TMDS Table revision: %d\n", ver);
1090                 // TODO
1091         }
1092 }
1093
1094 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1095 {
1096         struct radeon_device *rdev = dev->dev_private;
1097         struct radeon_i2c_bus_rec ddc_i2c;
1098
1099         rdev->mode_info.connector_table = radeon_connector_table;
1100         if (rdev->mode_info.connector_table == CT_NONE) {
1101 #ifdef CONFIG_PPC_PMAC
1102                 if (machine_is_compatible("PowerBook3,3")) {
1103                         /* powerbook with VGA */
1104                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1105                 } else if (machine_is_compatible("PowerBook3,4") ||
1106                            machine_is_compatible("PowerBook3,5")) {
1107                         /* powerbook with internal tmds */
1108                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1109                 } else if (machine_is_compatible("PowerBook5,1") ||
1110                            machine_is_compatible("PowerBook5,2") ||
1111                            machine_is_compatible("PowerBook5,3") ||
1112                            machine_is_compatible("PowerBook5,4") ||
1113                            machine_is_compatible("PowerBook5,5")) {
1114                         /* powerbook with external single link tmds (sil164) */
1115                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1116                 } else if (machine_is_compatible("PowerBook5,6")) {
1117                         /* powerbook with external dual or single link tmds */
1118                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1119                 } else if (machine_is_compatible("PowerBook5,7") ||
1120                            machine_is_compatible("PowerBook5,8") ||
1121                            machine_is_compatible("PowerBook5,9")) {
1122                         /* PowerBook6,2 ? */
1123                         /* powerbook with external dual link tmds (sil1178?) */
1124                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1125                 } else if (machine_is_compatible("PowerBook4,1") ||
1126                            machine_is_compatible("PowerBook4,2") ||
1127                            machine_is_compatible("PowerBook4,3") ||
1128                            machine_is_compatible("PowerBook6,3") ||
1129                            machine_is_compatible("PowerBook6,5") ||
1130                            machine_is_compatible("PowerBook6,7")) {
1131                         /* ibook */
1132                         rdev->mode_info.connector_table = CT_IBOOK;
1133                 } else if (machine_is_compatible("PowerMac4,4")) {
1134                         /* emac */
1135                         rdev->mode_info.connector_table = CT_EMAC;
1136                 } else if (machine_is_compatible("PowerMac10,1")) {
1137                         /* mini with internal tmds */
1138                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1139                 } else if (machine_is_compatible("PowerMac10,2")) {
1140                         /* mini with external tmds */
1141                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1142                 } else if (machine_is_compatible("PowerMac12,1")) {
1143                         /* PowerMac8,1 ? */
1144                         /* imac g5 isight */
1145                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1146                 } else
1147 #endif /* CONFIG_PPC_PMAC */
1148                         rdev->mode_info.connector_table = CT_GENERIC;
1149         }
1150
1151         switch (rdev->mode_info.connector_table) {
1152         case CT_GENERIC:
1153                 DRM_INFO("Connector Table: %d (generic)\n",
1154                          rdev->mode_info.connector_table);
1155                 /* these are the most common settings */
1156                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1157                         /* VGA - primary dac */
1158                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1159                         radeon_add_legacy_encoder(dev,
1160                                                   radeon_get_encoder_id(dev,
1161                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1162                                                                         1),
1163                                                   ATOM_DEVICE_CRT1_SUPPORT);
1164                         radeon_add_legacy_connector(dev, 0,
1165                                                     ATOM_DEVICE_CRT1_SUPPORT,
1166                                                     DRM_MODE_CONNECTOR_VGA,
1167                                                     &ddc_i2c);
1168                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1169                         /* LVDS */
1170                         ddc_i2c = combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
1171                         radeon_add_legacy_encoder(dev,
1172                                                   radeon_get_encoder_id(dev,
1173                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1174                                                                         0),
1175                                                   ATOM_DEVICE_LCD1_SUPPORT);
1176                         radeon_add_legacy_connector(dev, 0,
1177                                                     ATOM_DEVICE_LCD1_SUPPORT,
1178                                                     DRM_MODE_CONNECTOR_LVDS,
1179                                                     &ddc_i2c);
1180
1181                         /* VGA - primary dac */
1182                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1183                         radeon_add_legacy_encoder(dev,
1184                                                   radeon_get_encoder_id(dev,
1185                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1186                                                                         1),
1187                                                   ATOM_DEVICE_CRT1_SUPPORT);
1188                         radeon_add_legacy_connector(dev, 1,
1189                                                     ATOM_DEVICE_CRT1_SUPPORT,
1190                                                     DRM_MODE_CONNECTOR_VGA,
1191                                                     &ddc_i2c);
1192                 } else {
1193                         /* DVI-I - tv dac, int tmds */
1194                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1195                         radeon_add_legacy_encoder(dev,
1196                                                   radeon_get_encoder_id(dev,
1197                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1198                                                                         0),
1199                                                   ATOM_DEVICE_DFP1_SUPPORT);
1200                         radeon_add_legacy_encoder(dev,
1201                                                   radeon_get_encoder_id(dev,
1202                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1203                                                                         2),
1204                                                   ATOM_DEVICE_CRT2_SUPPORT);
1205                         radeon_add_legacy_connector(dev, 0,
1206                                                     ATOM_DEVICE_DFP1_SUPPORT |
1207                                                     ATOM_DEVICE_CRT2_SUPPORT,
1208                                                     DRM_MODE_CONNECTOR_DVII,
1209                                                     &ddc_i2c);
1210
1211                         /* VGA - primary dac */
1212                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1213                         radeon_add_legacy_encoder(dev,
1214                                                   radeon_get_encoder_id(dev,
1215                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1216                                                                         1),
1217                                                   ATOM_DEVICE_CRT1_SUPPORT);
1218                         radeon_add_legacy_connector(dev, 1,
1219                                                     ATOM_DEVICE_CRT1_SUPPORT,
1220                                                     DRM_MODE_CONNECTOR_VGA,
1221                                                     &ddc_i2c);
1222                 }
1223
1224                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1225                         /* TV - tv dac */
1226                         radeon_add_legacy_encoder(dev,
1227                                                   radeon_get_encoder_id(dev,
1228                                                                         ATOM_DEVICE_TV1_SUPPORT,
1229                                                                         2),
1230                                                   ATOM_DEVICE_TV1_SUPPORT);
1231                         radeon_add_legacy_connector(dev, 2,
1232                                                     ATOM_DEVICE_TV1_SUPPORT,
1233                                                     DRM_MODE_CONNECTOR_SVIDEO,
1234                                                     &ddc_i2c);
1235                 }
1236                 break;
1237         case CT_IBOOK:
1238                 DRM_INFO("Connector Table: %d (ibook)\n",
1239                          rdev->mode_info.connector_table);
1240                 /* LVDS */
1241                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1242                 radeon_add_legacy_encoder(dev,
1243                                           radeon_get_encoder_id(dev,
1244                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1245                                                                 0),
1246                                           ATOM_DEVICE_LCD1_SUPPORT);
1247                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1248                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1249                 /* VGA - TV DAC */
1250                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1251                 radeon_add_legacy_encoder(dev,
1252                                           radeon_get_encoder_id(dev,
1253                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1254                                                                 2),
1255                                           ATOM_DEVICE_CRT2_SUPPORT);
1256                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1257                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1258                 /* TV - TV DAC */
1259                 radeon_add_legacy_encoder(dev,
1260                                           radeon_get_encoder_id(dev,
1261                                                                 ATOM_DEVICE_TV1_SUPPORT,
1262                                                                 2),
1263                                           ATOM_DEVICE_TV1_SUPPORT);
1264                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1265                                             DRM_MODE_CONNECTOR_SVIDEO,
1266                                             &ddc_i2c);
1267                 break;
1268         case CT_POWERBOOK_EXTERNAL:
1269                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1270                          rdev->mode_info.connector_table);
1271                 /* LVDS */
1272                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1273                 radeon_add_legacy_encoder(dev,
1274                                           radeon_get_encoder_id(dev,
1275                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1276                                                                 0),
1277                                           ATOM_DEVICE_LCD1_SUPPORT);
1278                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1279                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1280                 /* DVI-I - primary dac, ext tmds */
1281                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1282                 radeon_add_legacy_encoder(dev,
1283                                           radeon_get_encoder_id(dev,
1284                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1285                                                                 0),
1286                                           ATOM_DEVICE_DFP2_SUPPORT);
1287                 radeon_add_legacy_encoder(dev,
1288                                           radeon_get_encoder_id(dev,
1289                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1290                                                                 1),
1291                                           ATOM_DEVICE_CRT1_SUPPORT);
1292                 radeon_add_legacy_connector(dev, 1,
1293                                             ATOM_DEVICE_DFP2_SUPPORT |
1294                                             ATOM_DEVICE_CRT1_SUPPORT,
1295                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1296                 /* TV - TV DAC */
1297                 radeon_add_legacy_encoder(dev,
1298                                           radeon_get_encoder_id(dev,
1299                                                                 ATOM_DEVICE_TV1_SUPPORT,
1300                                                                 2),
1301                                           ATOM_DEVICE_TV1_SUPPORT);
1302                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1303                                             DRM_MODE_CONNECTOR_SVIDEO,
1304                                             &ddc_i2c);
1305                 break;
1306         case CT_POWERBOOK_INTERNAL:
1307                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1308                          rdev->mode_info.connector_table);
1309                 /* LVDS */
1310                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1311                 radeon_add_legacy_encoder(dev,
1312                                           radeon_get_encoder_id(dev,
1313                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1314                                                                 0),
1315                                           ATOM_DEVICE_LCD1_SUPPORT);
1316                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1317                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1318                 /* DVI-I - primary dac, int tmds */
1319                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1320                 radeon_add_legacy_encoder(dev,
1321                                           radeon_get_encoder_id(dev,
1322                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1323                                                                 0),
1324                                           ATOM_DEVICE_DFP1_SUPPORT);
1325                 radeon_add_legacy_encoder(dev,
1326                                           radeon_get_encoder_id(dev,
1327                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1328                                                                 1),
1329                                           ATOM_DEVICE_CRT1_SUPPORT);
1330                 radeon_add_legacy_connector(dev, 1,
1331                                             ATOM_DEVICE_DFP1_SUPPORT |
1332                                             ATOM_DEVICE_CRT1_SUPPORT,
1333                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1334                 /* TV - TV DAC */
1335                 radeon_add_legacy_encoder(dev,
1336                                           radeon_get_encoder_id(dev,
1337                                                                 ATOM_DEVICE_TV1_SUPPORT,
1338                                                                 2),
1339                                           ATOM_DEVICE_TV1_SUPPORT);
1340                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1341                                             DRM_MODE_CONNECTOR_SVIDEO,
1342                                             &ddc_i2c);
1343                 break;
1344         case CT_POWERBOOK_VGA:
1345                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1346                          rdev->mode_info.connector_table);
1347                 /* LVDS */
1348                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1349                 radeon_add_legacy_encoder(dev,
1350                                           radeon_get_encoder_id(dev,
1351                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1352                                                                 0),
1353                                           ATOM_DEVICE_LCD1_SUPPORT);
1354                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1355                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1356                 /* VGA - primary dac */
1357                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1358                 radeon_add_legacy_encoder(dev,
1359                                           radeon_get_encoder_id(dev,
1360                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1361                                                                 1),
1362                                           ATOM_DEVICE_CRT1_SUPPORT);
1363                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1364                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1365                 /* TV - TV DAC */
1366                 radeon_add_legacy_encoder(dev,
1367                                           radeon_get_encoder_id(dev,
1368                                                                 ATOM_DEVICE_TV1_SUPPORT,
1369                                                                 2),
1370                                           ATOM_DEVICE_TV1_SUPPORT);
1371                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1372                                             DRM_MODE_CONNECTOR_SVIDEO,
1373                                             &ddc_i2c);
1374                 break;
1375         case CT_MINI_EXTERNAL:
1376                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1377                          rdev->mode_info.connector_table);
1378                 /* DVI-I - tv dac, ext tmds */
1379                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1380                 radeon_add_legacy_encoder(dev,
1381                                           radeon_get_encoder_id(dev,
1382                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1383                                                                 0),
1384                                           ATOM_DEVICE_DFP2_SUPPORT);
1385                 radeon_add_legacy_encoder(dev,
1386                                           radeon_get_encoder_id(dev,
1387                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1388                                                                 2),
1389                                           ATOM_DEVICE_CRT2_SUPPORT);
1390                 radeon_add_legacy_connector(dev, 0,
1391                                             ATOM_DEVICE_DFP2_SUPPORT |
1392                                             ATOM_DEVICE_CRT2_SUPPORT,
1393                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1394                 /* TV - TV DAC */
1395                 radeon_add_legacy_encoder(dev,
1396                                           radeon_get_encoder_id(dev,
1397                                                                 ATOM_DEVICE_TV1_SUPPORT,
1398                                                                 2),
1399                                           ATOM_DEVICE_TV1_SUPPORT);
1400                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1401                                             DRM_MODE_CONNECTOR_SVIDEO,
1402                                             &ddc_i2c);
1403                 break;
1404         case CT_MINI_INTERNAL:
1405                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1406                          rdev->mode_info.connector_table);
1407                 /* DVI-I - tv dac, int tmds */
1408                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1409                 radeon_add_legacy_encoder(dev,
1410                                           radeon_get_encoder_id(dev,
1411                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1412                                                                 0),
1413                                           ATOM_DEVICE_DFP1_SUPPORT);
1414                 radeon_add_legacy_encoder(dev,
1415                                           radeon_get_encoder_id(dev,
1416                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1417                                                                 2),
1418                                           ATOM_DEVICE_CRT2_SUPPORT);
1419                 radeon_add_legacy_connector(dev, 0,
1420                                             ATOM_DEVICE_DFP1_SUPPORT |
1421                                             ATOM_DEVICE_CRT2_SUPPORT,
1422                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1423                 /* TV - TV DAC */
1424                 radeon_add_legacy_encoder(dev,
1425                                           radeon_get_encoder_id(dev,
1426                                                                 ATOM_DEVICE_TV1_SUPPORT,
1427                                                                 2),
1428                                           ATOM_DEVICE_TV1_SUPPORT);
1429                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1430                                             DRM_MODE_CONNECTOR_SVIDEO,
1431                                             &ddc_i2c);
1432                 break;
1433         case CT_IMAC_G5_ISIGHT:
1434                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1435                          rdev->mode_info.connector_table);
1436                 /* DVI-D - int tmds */
1437                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1438                 radeon_add_legacy_encoder(dev,
1439                                           radeon_get_encoder_id(dev,
1440                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1441                                                                 0),
1442                                           ATOM_DEVICE_DFP1_SUPPORT);
1443                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1444                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c);
1445                 /* VGA - tv dac */
1446                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1447                 radeon_add_legacy_encoder(dev,
1448                                           radeon_get_encoder_id(dev,
1449                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1450                                                                 2),
1451                                           ATOM_DEVICE_CRT2_SUPPORT);
1452                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1453                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1454                 /* TV - TV DAC */
1455                 radeon_add_legacy_encoder(dev,
1456                                           radeon_get_encoder_id(dev,
1457                                                                 ATOM_DEVICE_TV1_SUPPORT,
1458                                                                 2),
1459                                           ATOM_DEVICE_TV1_SUPPORT);
1460                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1461                                             DRM_MODE_CONNECTOR_SVIDEO,
1462                                             &ddc_i2c);
1463                 break;
1464         case CT_EMAC:
1465                 DRM_INFO("Connector Table: %d (emac)\n",
1466                          rdev->mode_info.connector_table);
1467                 /* VGA - primary dac */
1468                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1469                 radeon_add_legacy_encoder(dev,
1470                                           radeon_get_encoder_id(dev,
1471                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1472                                                                 1),
1473                                           ATOM_DEVICE_CRT1_SUPPORT);
1474                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1475                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1476                 /* VGA - tv dac */
1477                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1478                 radeon_add_legacy_encoder(dev,
1479                                           radeon_get_encoder_id(dev,
1480                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1481                                                                 2),
1482                                           ATOM_DEVICE_CRT2_SUPPORT);
1483                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1484                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1485                 /* TV - TV DAC */
1486                 radeon_add_legacy_encoder(dev,
1487                                           radeon_get_encoder_id(dev,
1488                                                                 ATOM_DEVICE_TV1_SUPPORT,
1489                                                                 2),
1490                                           ATOM_DEVICE_TV1_SUPPORT);
1491                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1492                                             DRM_MODE_CONNECTOR_SVIDEO,
1493                                             &ddc_i2c);
1494                 break;
1495         default:
1496                 DRM_INFO("Connector table: %d (invalid)\n",
1497                          rdev->mode_info.connector_table);
1498                 return false;
1499         }
1500
1501         radeon_link_encoder_connector(dev);
1502
1503         return true;
1504 }
1505
1506 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1507                                        int bios_index,
1508                                        enum radeon_combios_connector
1509                                        *legacy_connector,
1510                                        struct radeon_i2c_bus_rec *ddc_i2c)
1511 {
1512         struct radeon_device *rdev = dev->dev_private;
1513
1514         /* XPRESS DDC quirks */
1515         if ((rdev->family == CHIP_RS400 ||
1516              rdev->family == CHIP_RS480) &&
1517             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1518                 *ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1519         else if ((rdev->family == CHIP_RS400 ||
1520                   rdev->family == CHIP_RS480) &&
1521                  ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1522                 ddc_i2c->valid = true;
1523                 ddc_i2c->mask_clk_mask = (0x20 << 8);
1524                 ddc_i2c->mask_data_mask = 0x80;
1525                 ddc_i2c->a_clk_mask = (0x20 << 8);
1526                 ddc_i2c->a_data_mask = 0x80;
1527                 ddc_i2c->put_clk_mask = (0x20 << 8);
1528                 ddc_i2c->put_data_mask = 0x80;
1529                 ddc_i2c->get_clk_mask = (0x20 << 8);
1530                 ddc_i2c->get_data_mask = 0x80;
1531                 ddc_i2c->mask_clk_reg = RADEON_GPIOPAD_MASK;
1532                 ddc_i2c->mask_data_reg = RADEON_GPIOPAD_MASK;
1533                 ddc_i2c->a_clk_reg = RADEON_GPIOPAD_A;
1534                 ddc_i2c->a_data_reg = RADEON_GPIOPAD_A;
1535                 ddc_i2c->put_clk_reg = RADEON_GPIOPAD_EN;
1536                 ddc_i2c->put_data_reg = RADEON_GPIOPAD_EN;
1537                 ddc_i2c->get_clk_reg = RADEON_LCD_GPIO_Y_REG;
1538                 ddc_i2c->get_data_reg = RADEON_LCD_GPIO_Y_REG;
1539         }
1540
1541         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1542            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1543         if (dev->pdev->device == 0x515e &&
1544             dev->pdev->subsystem_vendor == 0x1014) {
1545                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1546                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1547                         return false;
1548         }
1549
1550         /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1551         if (dev->pdev->device == 0x5159 &&
1552             dev->pdev->subsystem_vendor == 0x1002 &&
1553             dev->pdev->subsystem_device == 0x013a) {
1554                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1555                         *legacy_connector = CONNECTOR_CRT_LEGACY;
1556
1557         }
1558
1559         /* X300 card with extra non-existent DVI port */
1560         if (dev->pdev->device == 0x5B60 &&
1561             dev->pdev->subsystem_vendor == 0x17af &&
1562             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1563                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1564                         return false;
1565         }
1566
1567         return true;
1568 }
1569
1570 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1571 {
1572         struct radeon_device *rdev = dev->dev_private;
1573         uint32_t conn_info, entry, devices;
1574         uint16_t tmp;
1575         enum radeon_combios_ddc ddc_type;
1576         enum radeon_combios_connector connector;
1577         int i = 0;
1578         struct radeon_i2c_bus_rec ddc_i2c;
1579
1580         if (rdev->bios == NULL)
1581                 return false;
1582
1583         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1584         if (conn_info) {
1585                 for (i = 0; i < 4; i++) {
1586                         entry = conn_info + 2 + i * 2;
1587
1588                         if (!RBIOS16(entry))
1589                                 break;
1590
1591                         tmp = RBIOS16(entry);
1592
1593                         connector = (tmp >> 12) & 0xf;
1594
1595                         ddc_type = (tmp >> 8) & 0xf;
1596                         switch (ddc_type) {
1597                         case DDC_MONID:
1598                                 ddc_i2c =
1599                                     combios_setup_i2c_bus(RADEON_GPIO_MONID);
1600                                 break;
1601                         case DDC_DVI:
1602                                 ddc_i2c =
1603                                     combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1604                                 break;
1605                         case DDC_VGA:
1606                                 ddc_i2c =
1607                                     combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1608                                 break;
1609                         case DDC_CRT2:
1610                                 ddc_i2c =
1611                                     combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1612                                 break;
1613                         default:
1614                                 break;
1615                         }
1616
1617                         radeon_apply_legacy_quirks(dev, i, &connector,
1618                                                    &ddc_i2c);
1619
1620                         switch (connector) {
1621                         case CONNECTOR_PROPRIETARY_LEGACY:
1622                                 if ((tmp >> 4) & 0x1)
1623                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
1624                                 else
1625                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
1626                                 radeon_add_legacy_encoder(dev,
1627                                                           radeon_get_encoder_id
1628                                                           (dev, devices, 0),
1629                                                           devices);
1630                                 radeon_add_legacy_connector(dev, i, devices,
1631                                                             legacy_connector_convert
1632                                                             [connector],
1633                                                             &ddc_i2c);
1634                                 break;
1635                         case CONNECTOR_CRT_LEGACY:
1636                                 if (tmp & 0x1) {
1637                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
1638                                         radeon_add_legacy_encoder(dev,
1639                                                                   radeon_get_encoder_id
1640                                                                   (dev,
1641                                                                    ATOM_DEVICE_CRT2_SUPPORT,
1642                                                                    2),
1643                                                                   ATOM_DEVICE_CRT2_SUPPORT);
1644                                 } else {
1645                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
1646                                         radeon_add_legacy_encoder(dev,
1647                                                                   radeon_get_encoder_id
1648                                                                   (dev,
1649                                                                    ATOM_DEVICE_CRT1_SUPPORT,
1650                                                                    1),
1651                                                                   ATOM_DEVICE_CRT1_SUPPORT);
1652                                 }
1653                                 radeon_add_legacy_connector(dev,
1654                                                             i,
1655                                                             devices,
1656                                                             legacy_connector_convert
1657                                                             [connector],
1658                                                             &ddc_i2c);
1659                                 break;
1660                         case CONNECTOR_DVI_I_LEGACY:
1661                                 devices = 0;
1662                                 if (tmp & 0x1) {
1663                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
1664                                         radeon_add_legacy_encoder(dev,
1665                                                                   radeon_get_encoder_id
1666                                                                   (dev,
1667                                                                    ATOM_DEVICE_CRT2_SUPPORT,
1668                                                                    2),
1669                                                                   ATOM_DEVICE_CRT2_SUPPORT);
1670                                 } else {
1671                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
1672                                         radeon_add_legacy_encoder(dev,
1673                                                                   radeon_get_encoder_id
1674                                                                   (dev,
1675                                                                    ATOM_DEVICE_CRT1_SUPPORT,
1676                                                                    1),
1677                                                                   ATOM_DEVICE_CRT1_SUPPORT);
1678                                 }
1679                                 if ((tmp >> 4) & 0x1) {
1680                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
1681                                         radeon_add_legacy_encoder(dev,
1682                                                                   radeon_get_encoder_id
1683                                                                   (dev,
1684                                                                    ATOM_DEVICE_DFP2_SUPPORT,
1685                                                                    0),
1686                                                                   ATOM_DEVICE_DFP2_SUPPORT);
1687                                 } else {
1688                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
1689                                         radeon_add_legacy_encoder(dev,
1690                                                                   radeon_get_encoder_id
1691                                                                   (dev,
1692                                                                    ATOM_DEVICE_DFP1_SUPPORT,
1693                                                                    0),
1694                                                                   ATOM_DEVICE_DFP1_SUPPORT);
1695                                 }
1696                                 radeon_add_legacy_connector(dev,
1697                                                             i,
1698                                                             devices,
1699                                                             legacy_connector_convert
1700                                                             [connector],
1701                                                             &ddc_i2c);
1702                                 break;
1703                         case CONNECTOR_DVI_D_LEGACY:
1704                                 if ((tmp >> 4) & 0x1)
1705                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
1706                                 else
1707                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
1708                                 radeon_add_legacy_encoder(dev,
1709                                                           radeon_get_encoder_id
1710                                                           (dev, devices, 0),
1711                                                           devices);
1712                                 radeon_add_legacy_connector(dev, i, devices,
1713                                                             legacy_connector_convert
1714                                                             [connector],
1715                                                             &ddc_i2c);
1716                                 break;
1717                         case CONNECTOR_CTV_LEGACY:
1718                         case CONNECTOR_STV_LEGACY:
1719                                 radeon_add_legacy_encoder(dev,
1720                                                           radeon_get_encoder_id
1721                                                           (dev,
1722                                                            ATOM_DEVICE_TV1_SUPPORT,
1723                                                            2),
1724                                                           ATOM_DEVICE_TV1_SUPPORT);
1725                                 radeon_add_legacy_connector(dev, i,
1726                                                             ATOM_DEVICE_TV1_SUPPORT,
1727                                                             legacy_connector_convert
1728                                                             [connector],
1729                                                             &ddc_i2c);
1730                                 break;
1731                         default:
1732                                 DRM_ERROR("Unknown connector type: %d\n",
1733                                           connector);
1734                                 continue;
1735                         }
1736
1737                 }
1738         } else {
1739                 uint16_t tmds_info =
1740                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1741                 if (tmds_info) {
1742                         DRM_DEBUG("Found DFP table, assuming DVI connector\n");
1743
1744                         radeon_add_legacy_encoder(dev,
1745                                                   radeon_get_encoder_id(dev,
1746                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1747                                                                         1),
1748                                                   ATOM_DEVICE_CRT1_SUPPORT);
1749                         radeon_add_legacy_encoder(dev,
1750                                                   radeon_get_encoder_id(dev,
1751                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1752                                                                         0),
1753                                                   ATOM_DEVICE_DFP1_SUPPORT);
1754
1755                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1756                         radeon_add_legacy_connector(dev,
1757                                                     0,
1758                                                     ATOM_DEVICE_CRT1_SUPPORT |
1759                                                     ATOM_DEVICE_DFP1_SUPPORT,
1760                                                     DRM_MODE_CONNECTOR_DVII,
1761                                                     &ddc_i2c);
1762                 } else {
1763                         DRM_DEBUG("No connector info found\n");
1764                         return false;
1765                 }
1766         }
1767
1768         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
1769                 uint16_t lcd_info =
1770                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1771                 if (lcd_info) {
1772                         uint16_t lcd_ddc_info =
1773                             combios_get_table_offset(dev,
1774                                                      COMBIOS_LCD_DDC_INFO_TABLE);
1775
1776                         radeon_add_legacy_encoder(dev,
1777                                                   radeon_get_encoder_id(dev,
1778                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1779                                                                         0),
1780                                                   ATOM_DEVICE_LCD1_SUPPORT);
1781
1782                         if (lcd_ddc_info) {
1783                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
1784                                 switch (ddc_type) {
1785                                 case DDC_MONID:
1786                                         ddc_i2c =
1787                                             combios_setup_i2c_bus
1788                                             (RADEON_GPIO_MONID);
1789                                         break;
1790                                 case DDC_DVI:
1791                                         ddc_i2c =
1792                                             combios_setup_i2c_bus
1793                                             (RADEON_GPIO_DVI_DDC);
1794                                         break;
1795                                 case DDC_VGA:
1796                                         ddc_i2c =
1797                                             combios_setup_i2c_bus
1798                                             (RADEON_GPIO_VGA_DDC);
1799                                         break;
1800                                 case DDC_CRT2:
1801                                         ddc_i2c =
1802                                             combios_setup_i2c_bus
1803                                             (RADEON_GPIO_CRT2_DDC);
1804                                         break;
1805                                 case DDC_LCD:
1806                                         ddc_i2c =
1807                                             combios_setup_i2c_bus
1808                                             (RADEON_LCD_GPIO_MASK);
1809                                         ddc_i2c.mask_clk_mask =
1810                                             RBIOS32(lcd_ddc_info + 3);
1811                                         ddc_i2c.mask_data_mask =
1812                                             RBIOS32(lcd_ddc_info + 7);
1813                                         ddc_i2c.a_clk_mask =
1814                                             RBIOS32(lcd_ddc_info + 3);
1815                                         ddc_i2c.a_data_mask =
1816                                             RBIOS32(lcd_ddc_info + 7);
1817                                         ddc_i2c.put_clk_mask =
1818                                             RBIOS32(lcd_ddc_info + 3);
1819                                         ddc_i2c.put_data_mask =
1820                                             RBIOS32(lcd_ddc_info + 7);
1821                                         ddc_i2c.get_clk_mask =
1822                                             RBIOS32(lcd_ddc_info + 3);
1823                                         ddc_i2c.get_data_mask =
1824                                             RBIOS32(lcd_ddc_info + 7);
1825                                         break;
1826                                 case DDC_GPIO:
1827                                         ddc_i2c =
1828                                             combios_setup_i2c_bus
1829                                             (RADEON_MDGPIO_EN_REG);
1830                                         ddc_i2c.mask_clk_mask =
1831                                             RBIOS32(lcd_ddc_info + 3);
1832                                         ddc_i2c.mask_data_mask =
1833                                             RBIOS32(lcd_ddc_info + 7);
1834                                         ddc_i2c.a_clk_mask =
1835                                             RBIOS32(lcd_ddc_info + 3);
1836                                         ddc_i2c.a_data_mask =
1837                                             RBIOS32(lcd_ddc_info + 7);
1838                                         ddc_i2c.put_clk_mask =
1839                                             RBIOS32(lcd_ddc_info + 3);
1840                                         ddc_i2c.put_data_mask =
1841                                             RBIOS32(lcd_ddc_info + 7);
1842                                         ddc_i2c.get_clk_mask =
1843                                             RBIOS32(lcd_ddc_info + 3);
1844                                         ddc_i2c.get_data_mask =
1845                                             RBIOS32(lcd_ddc_info + 7);
1846                                         break;
1847                                 default:
1848                                         ddc_i2c.valid = false;
1849                                         break;
1850                                 }
1851                                 DRM_DEBUG("LCD DDC Info Table found!\n");
1852                         } else
1853                                 ddc_i2c.valid = false;
1854
1855                         radeon_add_legacy_connector(dev,
1856                                                     5,
1857                                                     ATOM_DEVICE_LCD1_SUPPORT,
1858                                                     DRM_MODE_CONNECTOR_LVDS,
1859                                                     &ddc_i2c);
1860                 }
1861         }
1862
1863         /* check TV table */
1864         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1865                 uint32_t tv_info =
1866                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1867                 if (tv_info) {
1868                         if (RBIOS8(tv_info + 6) == 'T') {
1869                                 radeon_add_legacy_encoder(dev,
1870                                                           radeon_get_encoder_id
1871                                                           (dev,
1872                                                            ATOM_DEVICE_TV1_SUPPORT,
1873                                                            2),
1874                                                           ATOM_DEVICE_TV1_SUPPORT);
1875                                 radeon_add_legacy_connector(dev, 6,
1876                                                             ATOM_DEVICE_TV1_SUPPORT,
1877                                                             DRM_MODE_CONNECTOR_SVIDEO,
1878                                                             &ddc_i2c);
1879                         }
1880                 }
1881         }
1882
1883         radeon_link_encoder_connector(dev);
1884
1885         return true;
1886 }
1887
1888 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
1889 {
1890         struct radeon_device *rdev = dev->dev_private;
1891
1892         if (offset) {
1893                 while (RBIOS16(offset)) {
1894                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
1895                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
1896                         uint32_t val, and_mask, or_mask;
1897                         uint32_t tmp;
1898
1899                         offset += 2;
1900                         switch (cmd) {
1901                         case 0:
1902                                 val = RBIOS32(offset);
1903                                 offset += 4;
1904                                 WREG32(addr, val);
1905                                 break;
1906                         case 1:
1907                                 val = RBIOS32(offset);
1908                                 offset += 4;
1909                                 WREG32(addr, val);
1910                                 break;
1911                         case 2:
1912                                 and_mask = RBIOS32(offset);
1913                                 offset += 4;
1914                                 or_mask = RBIOS32(offset);
1915                                 offset += 4;
1916                                 tmp = RREG32(addr);
1917                                 tmp &= and_mask;
1918                                 tmp |= or_mask;
1919                                 WREG32(addr, tmp);
1920                                 break;
1921                         case 3:
1922                                 and_mask = RBIOS32(offset);
1923                                 offset += 4;
1924                                 or_mask = RBIOS32(offset);
1925                                 offset += 4;
1926                                 tmp = RREG32(addr);
1927                                 tmp &= and_mask;
1928                                 tmp |= or_mask;
1929                                 WREG32(addr, tmp);
1930                                 break;
1931                         case 4:
1932                                 val = RBIOS16(offset);
1933                                 offset += 2;
1934                                 udelay(val);
1935                                 break;
1936                         case 5:
1937                                 val = RBIOS16(offset);
1938                                 offset += 2;
1939                                 switch (addr) {
1940                                 case 8:
1941                                         while (val--) {
1942                                                 if (!
1943                                                     (RREG32_PLL
1944                                                      (RADEON_CLK_PWRMGT_CNTL) &
1945                                                      RADEON_MC_BUSY))
1946                                                         break;
1947                                         }
1948                                         break;
1949                                 case 9:
1950                                         while (val--) {
1951                                                 if ((RREG32(RADEON_MC_STATUS) &
1952                                                      RADEON_MC_IDLE))
1953                                                         break;
1954                                         }
1955                                         break;
1956                                 default:
1957                                         break;
1958                                 }
1959                                 break;
1960                         default:
1961                                 break;
1962                         }
1963                 }
1964         }
1965 }
1966
1967 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
1968 {
1969         struct radeon_device *rdev = dev->dev_private;
1970
1971         if (offset) {
1972                 while (RBIOS8(offset)) {
1973                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
1974                         uint8_t addr = (RBIOS8(offset) & 0x3f);
1975                         uint32_t val, shift, tmp;
1976                         uint32_t and_mask, or_mask;
1977
1978                         offset++;
1979                         switch (cmd) {
1980                         case 0:
1981                                 val = RBIOS32(offset);
1982                                 offset += 4;
1983                                 WREG32_PLL(addr, val);
1984                                 break;
1985                         case 1:
1986                                 shift = RBIOS8(offset) * 8;
1987                                 offset++;
1988                                 and_mask = RBIOS8(offset) << shift;
1989                                 and_mask |= ~(0xff << shift);
1990                                 offset++;
1991                                 or_mask = RBIOS8(offset) << shift;
1992                                 offset++;
1993                                 tmp = RREG32_PLL(addr);
1994                                 tmp &= and_mask;
1995                                 tmp |= or_mask;
1996                                 WREG32_PLL(addr, tmp);
1997                                 break;
1998                         case 2:
1999                         case 3:
2000                                 tmp = 1000;
2001                                 switch (addr) {
2002                                 case 1:
2003                                         udelay(150);
2004                                         break;
2005                                 case 2:
2006                                         udelay(1000);
2007                                         break;
2008                                 case 3:
2009                                         while (tmp--) {
2010                                                 if (!
2011                                                     (RREG32_PLL
2012                                                      (RADEON_CLK_PWRMGT_CNTL) &
2013                                                      RADEON_MC_BUSY))
2014                                                         break;
2015                                         }
2016                                         break;
2017                                 case 4:
2018                                         while (tmp--) {
2019                                                 if (RREG32_PLL
2020                                                     (RADEON_CLK_PWRMGT_CNTL) &
2021                                                     RADEON_DLL_READY)
2022                                                         break;
2023                                         }
2024                                         break;
2025                                 case 5:
2026                                         tmp =
2027                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2028                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
2029 #if 0
2030                                                 uint32_t mclk_cntl =
2031                                                     RREG32_PLL
2032                                                     (RADEON_MCLK_CNTL);
2033                                                 mclk_cntl &= 0xffff0000;
2034                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
2035                                                 WREG32_PLL(RADEON_MCLK_CNTL,
2036                                                            mclk_cntl);
2037                                                 udelay(10000);
2038 #endif
2039                                                 WREG32_PLL
2040                                                     (RADEON_CLK_PWRMGT_CNTL,
2041                                                      tmp &
2042                                                      ~RADEON_CG_NO1_DEBUG_0);
2043                                                 udelay(10000);
2044                                         }
2045                                         break;
2046                                 default:
2047                                         break;
2048                                 }
2049                                 break;
2050                         default:
2051                                 break;
2052                         }
2053                 }
2054         }
2055 }
2056
2057 static void combios_parse_ram_reset_table(struct drm_device *dev,
2058                                           uint16_t offset)
2059 {
2060         struct radeon_device *rdev = dev->dev_private;
2061         uint32_t tmp;
2062
2063         if (offset) {
2064                 uint8_t val = RBIOS8(offset);
2065                 while (val != 0xff) {
2066                         offset++;
2067
2068                         if (val == 0x0f) {
2069                                 uint32_t channel_complete_mask;
2070
2071                                 if (ASIC_IS_R300(rdev))
2072                                         channel_complete_mask =
2073                                             R300_MEM_PWRUP_COMPLETE;
2074                                 else
2075                                         channel_complete_mask =
2076                                             RADEON_MEM_PWRUP_COMPLETE;
2077                                 tmp = 20000;
2078                                 while (tmp--) {
2079                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
2080                                              channel_complete_mask) ==
2081                                             channel_complete_mask)
2082                                                 break;
2083                                 }
2084                         } else {
2085                                 uint32_t or_mask = RBIOS16(offset);
2086                                 offset += 2;
2087
2088                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2089                                 tmp &= RADEON_SDRAM_MODE_MASK;
2090                                 tmp |= or_mask;
2091                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2092
2093                                 or_mask = val << 24;
2094                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2095                                 tmp &= RADEON_B3MEM_RESET_MASK;
2096                                 tmp |= or_mask;
2097                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2098                         }
2099                         val = RBIOS8(offset);
2100                 }
2101         }
2102 }
2103
2104 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2105                                    int mem_addr_mapping)
2106 {
2107         struct radeon_device *rdev = dev->dev_private;
2108         uint32_t mem_cntl;
2109         uint32_t mem_size;
2110         uint32_t addr = 0;
2111
2112         mem_cntl = RREG32(RADEON_MEM_CNTL);
2113         if (mem_cntl & RV100_HALF_MODE)
2114                 ram /= 2;
2115         mem_size = ram;
2116         mem_cntl &= ~(0xff << 8);
2117         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2118         WREG32(RADEON_MEM_CNTL, mem_cntl);
2119         RREG32(RADEON_MEM_CNTL);
2120
2121         /* sdram reset ? */
2122
2123         /* something like this????  */
2124         while (ram--) {
2125                 addr = ram * 1024 * 1024;
2126                 /* write to each page */
2127                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2128                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2129                 /* read back and verify */
2130                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2131                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2132                         return 0;
2133         }
2134
2135         return mem_size;
2136 }
2137
2138 static void combios_write_ram_size(struct drm_device *dev)
2139 {
2140         struct radeon_device *rdev = dev->dev_private;
2141         uint8_t rev;
2142         uint16_t offset;
2143         uint32_t mem_size = 0;
2144         uint32_t mem_cntl = 0;
2145
2146         /* should do something smarter here I guess... */
2147         if (rdev->flags & RADEON_IS_IGP)
2148                 return;
2149
2150         /* first check detected mem table */
2151         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2152         if (offset) {
2153                 rev = RBIOS8(offset);
2154                 if (rev < 3) {
2155                         mem_cntl = RBIOS32(offset + 1);
2156                         mem_size = RBIOS16(offset + 5);
2157                         if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2158                             ((dev->pdev->device != 0x515e)
2159                              && (dev->pdev->device != 0x5969)))
2160                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
2161                 }
2162         }
2163
2164         if (!mem_size) {
2165                 offset =
2166                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2167                 if (offset) {
2168                         rev = RBIOS8(offset - 1);
2169                         if (rev < 1) {
2170                                 if (((rdev->flags & RADEON_FAMILY_MASK) <
2171                                      CHIP_R200)
2172                                     && ((dev->pdev->device != 0x515e)
2173                                         && (dev->pdev->device != 0x5969))) {
2174                                         int ram = 0;
2175                                         int mem_addr_mapping = 0;
2176
2177                                         while (RBIOS8(offset)) {
2178                                                 ram = RBIOS8(offset);
2179                                                 mem_addr_mapping =
2180                                                     RBIOS8(offset + 1);
2181                                                 if (mem_addr_mapping != 0x25)
2182                                                         ram *= 2;
2183                                                 mem_size =
2184                                                     combios_detect_ram(dev, ram,
2185                                                                        mem_addr_mapping);
2186                                                 if (mem_size)
2187                                                         break;
2188                                                 offset += 2;
2189                                         }
2190                                 } else
2191                                         mem_size = RBIOS8(offset);
2192                         } else {
2193                                 mem_size = RBIOS8(offset);
2194                                 mem_size *= 2;  /* convert to MB */
2195                         }
2196                 }
2197         }
2198
2199         mem_size *= (1024 * 1024);      /* convert to bytes */
2200         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2201 }
2202
2203 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2204 {
2205         uint16_t dyn_clk_info =
2206             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2207
2208         if (dyn_clk_info)
2209                 combios_parse_pll_table(dev, dyn_clk_info);
2210 }
2211
2212 void radeon_combios_asic_init(struct drm_device *dev)
2213 {
2214         struct radeon_device *rdev = dev->dev_private;
2215         uint16_t table;
2216
2217         /* port hardcoded mac stuff from radeonfb */
2218         if (rdev->bios == NULL)
2219                 return;
2220
2221         /* ASIC INIT 1 */
2222         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2223         if (table)
2224                 combios_parse_mmio_table(dev, table);
2225
2226         /* PLL INIT */
2227         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2228         if (table)
2229                 combios_parse_pll_table(dev, table);
2230
2231         /* ASIC INIT 2 */
2232         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2233         if (table)
2234                 combios_parse_mmio_table(dev, table);
2235
2236         if (!(rdev->flags & RADEON_IS_IGP)) {
2237                 /* ASIC INIT 4 */
2238                 table =
2239                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2240                 if (table)
2241                         combios_parse_mmio_table(dev, table);
2242
2243                 /* RAM RESET */
2244                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2245                 if (table)
2246                         combios_parse_ram_reset_table(dev, table);
2247
2248                 /* ASIC INIT 3 */
2249                 table =
2250                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2251                 if (table)
2252                         combios_parse_mmio_table(dev, table);
2253
2254                 /* write CONFIG_MEMSIZE */
2255                 combios_write_ram_size(dev);
2256         }
2257
2258         /* DYN CLK 1 */
2259         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2260         if (table)
2261                 combios_parse_pll_table(dev, table);
2262
2263 }
2264
2265 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2266 {
2267         struct radeon_device *rdev = dev->dev_private;
2268         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2269
2270         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2271         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2272         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2273
2274         /* let the bios control the backlight */
2275         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2276
2277         /* tell the bios not to handle mode switching */
2278         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2279                            RADEON_ACC_MODE_CHANGE);
2280
2281         /* tell the bios a driver is loaded */
2282         bios_7_scratch |= RADEON_DRV_LOADED;
2283
2284         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2285         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2286         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2287 }
2288
2289 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2290 {
2291         struct drm_device *dev = encoder->dev;
2292         struct radeon_device *rdev = dev->dev_private;
2293         uint32_t bios_6_scratch;
2294
2295         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2296
2297         if (lock)
2298                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2299         else
2300                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2301
2302         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2303 }
2304
2305 void
2306 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2307                                       struct drm_encoder *encoder,
2308                                       bool connected)
2309 {
2310         struct drm_device *dev = connector->dev;
2311         struct radeon_device *rdev = dev->dev_private;
2312         struct radeon_connector *radeon_connector =
2313             to_radeon_connector(connector);
2314         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2315         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2316         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2317
2318         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2319             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2320                 if (connected) {
2321                         DRM_DEBUG("TV1 connected\n");
2322                         /* fix me */
2323                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2324                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2325                         bios_5_scratch |= RADEON_TV1_ON;
2326                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
2327                 } else {
2328                         DRM_DEBUG("TV1 disconnected\n");
2329                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2330                         bios_5_scratch &= ~RADEON_TV1_ON;
2331                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2332                 }
2333         }
2334         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2335             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2336                 if (connected) {
2337                         DRM_DEBUG("LCD1 connected\n");
2338                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
2339                         bios_5_scratch |= RADEON_LCD1_ON;
2340                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2341                 } else {
2342                         DRM_DEBUG("LCD1 disconnected\n");
2343                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2344                         bios_5_scratch &= ~RADEON_LCD1_ON;
2345                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2346                 }
2347         }
2348         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2349             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2350                 if (connected) {
2351                         DRM_DEBUG("CRT1 connected\n");
2352                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2353                         bios_5_scratch |= RADEON_CRT1_ON;
2354                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2355                 } else {
2356                         DRM_DEBUG("CRT1 disconnected\n");
2357                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2358                         bios_5_scratch &= ~RADEON_CRT1_ON;
2359                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2360                 }
2361         }
2362         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2363             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2364                 if (connected) {
2365                         DRM_DEBUG("CRT2 connected\n");
2366                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2367                         bios_5_scratch |= RADEON_CRT2_ON;
2368                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2369                 } else {
2370                         DRM_DEBUG("CRT2 disconnected\n");
2371                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2372                         bios_5_scratch &= ~RADEON_CRT2_ON;
2373                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2374                 }
2375         }
2376         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2377             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2378                 if (connected) {
2379                         DRM_DEBUG("DFP1 connected\n");
2380                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
2381                         bios_5_scratch |= RADEON_DFP1_ON;
2382                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2383                 } else {
2384                         DRM_DEBUG("DFP1 disconnected\n");
2385                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2386                         bios_5_scratch &= ~RADEON_DFP1_ON;
2387                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2388                 }
2389         }
2390         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2391             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2392                 if (connected) {
2393                         DRM_DEBUG("DFP2 connected\n");
2394                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
2395                         bios_5_scratch |= RADEON_DFP2_ON;
2396                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2397                 } else {
2398                         DRM_DEBUG("DFP2 disconnected\n");
2399                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2400                         bios_5_scratch &= ~RADEON_DFP2_ON;
2401                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2402                 }
2403         }
2404         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2405         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2406 }
2407
2408 void
2409 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2410 {
2411         struct drm_device *dev = encoder->dev;
2412         struct radeon_device *rdev = dev->dev_private;
2413         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2414         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2415
2416         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2417                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2418                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
2419         }
2420         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2421                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
2422                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
2423         }
2424         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2425                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
2426                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
2427         }
2428         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2429                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
2430                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
2431         }
2432         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2433                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
2434                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
2435         }
2436         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2437                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
2438                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
2439         }
2440         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2441 }
2442
2443 void
2444 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2445 {
2446         struct drm_device *dev = encoder->dev;
2447         struct radeon_device *rdev = dev->dev_private;
2448         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2449         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2450
2451         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
2452                 if (on)
2453                         bios_6_scratch |= RADEON_TV_DPMS_ON;
2454                 else
2455                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
2456         }
2457         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2458                 if (on)
2459                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
2460                 else
2461                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
2462         }
2463         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2464                 if (on)
2465                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
2466                 else
2467                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
2468         }
2469         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
2470                 if (on)
2471                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
2472                 else
2473                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
2474         }
2475         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2476 }