2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
53 /* from radeon_legacy_encoder.c */
55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
58 union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
67 struct atom_context *ctx = rdev->mode_info.atom_context;
68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
78 if (atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
82 gpio = &i2c_info->asGPIO_Info[i];
84 if (gpio->sucI2cId.ucAccess == id) {
85 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
86 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
87 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
88 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
89 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
90 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
91 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
92 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
93 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
94 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
95 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
96 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
97 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
98 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
99 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
100 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
102 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
103 i2c.hw_capable = true;
105 i2c.hw_capable = false;
107 if (gpio->sucI2cId.ucAccess == 0xa0)
112 i2c.i2c_id = gpio->sucI2cId.ucAccess;
123 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
126 struct atom_context *ctx = rdev->mode_info.atom_context;
127 struct radeon_gpio_rec gpio;
128 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
129 struct _ATOM_GPIO_PIN_LUT *gpio_info;
130 ATOM_GPIO_PIN_ASSIGNMENT *pin;
131 u16 data_offset, size;
134 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
137 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
138 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
140 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
141 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
143 for (i = 0; i < num_indices; i++) {
144 pin = &gpio_info->asGPIO_Pin[i];
145 if (id == pin->ucGPIO_ID) {
146 gpio.id = pin->ucGPIO_ID;
147 gpio.reg = pin->usGpioPin_AIndex * 4;
148 gpio.mask = (1 << pin->ucGpioPinBitShift);
158 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
159 struct radeon_gpio_rec *gpio)
161 struct radeon_hpd hpd;
164 if (ASIC_IS_DCE4(rdev))
165 reg = EVERGREEN_DC_GPIO_HPD_A;
167 reg = AVIVO_DC_GPIO_HPD_A;
170 if (gpio->reg == reg) {
173 hpd.hpd = RADEON_HPD_1;
176 hpd.hpd = RADEON_HPD_2;
179 hpd.hpd = RADEON_HPD_3;
182 hpd.hpd = RADEON_HPD_4;
185 hpd.hpd = RADEON_HPD_5;
188 hpd.hpd = RADEON_HPD_6;
191 hpd.hpd = RADEON_HPD_NONE;
195 hpd.hpd = RADEON_HPD_NONE;
199 static bool radeon_atom_apply_quirks(struct drm_device *dev,
200 uint32_t supported_device,
202 struct radeon_i2c_bus_rec *i2c_bus,
204 struct radeon_hpd *hpd)
207 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
208 if ((dev->pdev->device == 0x791e) &&
209 (dev->pdev->subsystem_vendor == 0x1043) &&
210 (dev->pdev->subsystem_device == 0x826d)) {
211 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
212 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
213 *connector_type = DRM_MODE_CONNECTOR_DVID;
216 /* Asrock RS600 board lists the DVI port as HDMI */
217 if ((dev->pdev->device == 0x7941) &&
218 (dev->pdev->subsystem_vendor == 0x1849) &&
219 (dev->pdev->subsystem_device == 0x7941)) {
220 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
221 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
222 *connector_type = DRM_MODE_CONNECTOR_DVID;
225 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
226 if ((dev->pdev->device == 0x7941) &&
227 (dev->pdev->subsystem_vendor == 0x147b) &&
228 (dev->pdev->subsystem_device == 0x2412)) {
229 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
233 /* Falcon NW laptop lists vga ddc line for LVDS */
234 if ((dev->pdev->device == 0x5653) &&
235 (dev->pdev->subsystem_vendor == 0x1462) &&
236 (dev->pdev->subsystem_device == 0x0291)) {
237 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
238 i2c_bus->valid = false;
243 /* HIS X1300 is DVI+VGA, not DVI+DVI */
244 if ((dev->pdev->device == 0x7146) &&
245 (dev->pdev->subsystem_vendor == 0x17af) &&
246 (dev->pdev->subsystem_device == 0x2058)) {
247 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
251 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
252 if ((dev->pdev->device == 0x7142) &&
253 (dev->pdev->subsystem_vendor == 0x1458) &&
254 (dev->pdev->subsystem_device == 0x2134)) {
255 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
261 if ((dev->pdev->device == 0x71C5) &&
262 (dev->pdev->subsystem_vendor == 0x106b) &&
263 (dev->pdev->subsystem_device == 0x0080)) {
264 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
265 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
267 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
271 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
272 if ((dev->pdev->device == 0x9598) &&
273 (dev->pdev->subsystem_vendor == 0x1043) &&
274 (dev->pdev->subsystem_device == 0x01da)) {
275 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
276 *connector_type = DRM_MODE_CONNECTOR_DVII;
280 /* ASUS HD 3450 board lists the DVI port as HDMI */
281 if ((dev->pdev->device == 0x95C5) &&
282 (dev->pdev->subsystem_vendor == 0x1043) &&
283 (dev->pdev->subsystem_device == 0x01e2)) {
284 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
285 *connector_type = DRM_MODE_CONNECTOR_DVII;
289 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
290 * HDMI + VGA reporting as HDMI
292 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
293 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
294 *connector_type = DRM_MODE_CONNECTOR_VGA;
299 /* Acer laptop reports DVI-D as DVI-I */
300 if ((dev->pdev->device == 0x95c4) &&
301 (dev->pdev->subsystem_vendor == 0x1025) &&
302 (dev->pdev->subsystem_device == 0x013c)) {
303 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
304 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
305 *connector_type = DRM_MODE_CONNECTOR_DVID;
308 /* XFX Pine Group device rv730 reports no VGA DDC lines
309 * even though they are wired up to record 0x93
311 if ((dev->pdev->device == 0x9498) &&
312 (dev->pdev->subsystem_vendor == 0x1682) &&
313 (dev->pdev->subsystem_device == 0x2452)) {
314 struct radeon_device *rdev = dev->dev_private;
315 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
320 const int supported_devices_connector_convert[] = {
321 DRM_MODE_CONNECTOR_Unknown,
322 DRM_MODE_CONNECTOR_VGA,
323 DRM_MODE_CONNECTOR_DVII,
324 DRM_MODE_CONNECTOR_DVID,
325 DRM_MODE_CONNECTOR_DVIA,
326 DRM_MODE_CONNECTOR_SVIDEO,
327 DRM_MODE_CONNECTOR_Composite,
328 DRM_MODE_CONNECTOR_LVDS,
329 DRM_MODE_CONNECTOR_Unknown,
330 DRM_MODE_CONNECTOR_Unknown,
331 DRM_MODE_CONNECTOR_HDMIA,
332 DRM_MODE_CONNECTOR_HDMIB,
333 DRM_MODE_CONNECTOR_Unknown,
334 DRM_MODE_CONNECTOR_Unknown,
335 DRM_MODE_CONNECTOR_9PinDIN,
336 DRM_MODE_CONNECTOR_DisplayPort
339 const uint16_t supported_devices_connector_object_id_convert[] = {
340 CONNECTOR_OBJECT_ID_NONE,
341 CONNECTOR_OBJECT_ID_VGA,
342 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
343 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
344 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
345 CONNECTOR_OBJECT_ID_COMPOSITE,
346 CONNECTOR_OBJECT_ID_SVIDEO,
347 CONNECTOR_OBJECT_ID_LVDS,
348 CONNECTOR_OBJECT_ID_9PIN_DIN,
349 CONNECTOR_OBJECT_ID_9PIN_DIN,
350 CONNECTOR_OBJECT_ID_DISPLAYPORT,
351 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
352 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
353 CONNECTOR_OBJECT_ID_SVIDEO
356 const int object_connector_convert[] = {
357 DRM_MODE_CONNECTOR_Unknown,
358 DRM_MODE_CONNECTOR_DVII,
359 DRM_MODE_CONNECTOR_DVII,
360 DRM_MODE_CONNECTOR_DVID,
361 DRM_MODE_CONNECTOR_DVID,
362 DRM_MODE_CONNECTOR_VGA,
363 DRM_MODE_CONNECTOR_Composite,
364 DRM_MODE_CONNECTOR_SVIDEO,
365 DRM_MODE_CONNECTOR_Unknown,
366 DRM_MODE_CONNECTOR_Unknown,
367 DRM_MODE_CONNECTOR_9PinDIN,
368 DRM_MODE_CONNECTOR_Unknown,
369 DRM_MODE_CONNECTOR_HDMIA,
370 DRM_MODE_CONNECTOR_HDMIB,
371 DRM_MODE_CONNECTOR_LVDS,
372 DRM_MODE_CONNECTOR_9PinDIN,
373 DRM_MODE_CONNECTOR_Unknown,
374 DRM_MODE_CONNECTOR_Unknown,
375 DRM_MODE_CONNECTOR_Unknown,
376 DRM_MODE_CONNECTOR_DisplayPort,
377 DRM_MODE_CONNECTOR_eDP,
378 DRM_MODE_CONNECTOR_Unknown
381 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
383 struct radeon_device *rdev = dev->dev_private;
384 struct radeon_mode_info *mode_info = &rdev->mode_info;
385 struct atom_context *ctx = mode_info->atom_context;
386 int index = GetIndexIntoMasterTable(DATA, Object_Header);
387 u16 size, data_offset;
389 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
390 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
391 ATOM_OBJECT_HEADER *obj_header;
392 int i, j, path_size, device_support;
394 u16 igp_lane_info, conn_id, connector_object_id;
396 struct radeon_i2c_bus_rec ddc_bus;
397 struct radeon_gpio_rec gpio;
398 struct radeon_hpd hpd;
400 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
406 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
407 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
408 (ctx->bios + data_offset +
409 le16_to_cpu(obj_header->usDisplayPathTableOffset));
410 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
411 (ctx->bios + data_offset +
412 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
413 device_support = le16_to_cpu(obj_header->usDeviceSupport);
416 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
417 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
418 ATOM_DISPLAY_OBJECT_PATH *path;
420 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
421 path_size += le16_to_cpu(path->usSize);
423 if (device_support & le16_to_cpu(path->usDeviceTag)) {
424 uint8_t con_obj_id, con_obj_num, con_obj_type;
427 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
430 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
433 (le16_to_cpu(path->usConnObjectId) &
434 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
436 /* TODO CV support */
437 if (le16_to_cpu(path->usDeviceTag) ==
438 ATOM_DEVICE_CV_SUPPORT)
442 if ((rdev->flags & RADEON_IS_IGP) &&
444 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
445 uint16_t igp_offset = 0;
446 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
449 GetIndexIntoMasterTable(DATA,
450 IntegratedSystemInfo);
452 if (atom_parse_data_header(ctx, index, &size, &frev,
453 &crev, &igp_offset)) {
457 (ATOM_INTEGRATED_SYSTEM_INFO_V2
458 *) (ctx->bios + igp_offset);
461 uint32_t slot_config, ct;
463 if (con_obj_num == 1)
472 ct = (slot_config >> 16) & 0xff;
474 object_connector_convert
476 connector_object_id = ct;
478 slot_config & 0xffff;
486 object_connector_convert[con_obj_id];
487 connector_object_id = con_obj_id;
492 object_connector_convert[con_obj_id];
493 connector_object_id = con_obj_id;
496 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
499 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
501 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
504 (le16_to_cpu(path->usGraphicObjIds[j]) &
505 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
507 (le16_to_cpu(path->usGraphicObjIds[j]) &
508 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
510 (le16_to_cpu(path->usGraphicObjIds[j]) &
511 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
513 /* FIXME: add support for router objects */
514 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
515 if (enc_obj_num == 2)
520 radeon_add_atom_encoder(dev,
529 /* look up gpio for ddc, hpd */
530 if ((le16_to_cpu(path->usDeviceTag) &
531 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
532 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
533 if (le16_to_cpu(path->usConnObjectId) ==
534 le16_to_cpu(con_obj->asObjects[j].
536 ATOM_COMMON_RECORD_HEADER
538 (ATOM_COMMON_RECORD_HEADER
540 (ctx->bios + data_offset +
541 le16_to_cpu(con_obj->
544 ATOM_I2C_RECORD *i2c_record;
545 ATOM_HPD_INT_RECORD *hpd_record;
546 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
547 hpd.hpd = RADEON_HPD_NONE;
549 while (record->ucRecordType > 0
552 ATOM_MAX_OBJECT_RECORD_NUMBER) {
553 switch (record->ucRecordType) {
554 case ATOM_I2C_RECORD_TYPE:
559 (ATOM_I2C_ID_CONFIG_ACCESS *)
560 &i2c_record->sucI2cId;
561 ddc_bus = radeon_lookup_i2c_gpio(rdev,
565 case ATOM_HPD_INT_RECORD_TYPE:
567 (ATOM_HPD_INT_RECORD *)
569 gpio = radeon_lookup_gpio(rdev,
570 hpd_record->ucHPDIntGPIOID);
571 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
572 hpd.plugged_state = hpd_record->ucPlugged_PinState;
576 (ATOM_COMMON_RECORD_HEADER
586 hpd.hpd = RADEON_HPD_NONE;
587 ddc_bus.valid = false;
590 /* needed for aux chan transactions */
591 ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
593 conn_id = le16_to_cpu(path->usConnObjectId);
595 if (!radeon_atom_apply_quirks
596 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
597 &ddc_bus, &conn_id, &hpd))
600 radeon_add_atom_connector(dev,
604 connector_type, &ddc_bus,
605 linkb, igp_lane_info,
612 radeon_link_encoder_connector(dev);
617 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
621 struct radeon_device *rdev = dev->dev_private;
623 if (rdev->flags & RADEON_IS_IGP) {
624 return supported_devices_connector_object_id_convert
626 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
627 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
628 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
629 struct radeon_mode_info *mode_info = &rdev->mode_info;
630 struct atom_context *ctx = mode_info->atom_context;
631 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
632 uint16_t size, data_offset;
634 ATOM_XTMDS_INFO *xtmds;
636 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
637 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
639 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
640 if (connector_type == DRM_MODE_CONNECTOR_DVII)
641 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
643 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
645 if (connector_type == DRM_MODE_CONNECTOR_DVII)
646 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
648 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
651 return supported_devices_connector_object_id_convert
654 return supported_devices_connector_object_id_convert
659 struct bios_connector {
664 struct radeon_i2c_bus_rec ddc_bus;
665 struct radeon_hpd hpd;
668 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
672 struct radeon_device *rdev = dev->dev_private;
673 struct radeon_mode_info *mode_info = &rdev->mode_info;
674 struct atom_context *ctx = mode_info->atom_context;
675 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
676 uint16_t size, data_offset;
678 uint16_t device_support;
680 union atom_supported_devices *supported_devices;
681 int i, j, max_device;
682 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
684 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
688 (union atom_supported_devices *)(ctx->bios + data_offset);
690 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
693 max_device = ATOM_MAX_SUPPORTED_DEVICE;
695 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
697 for (i = 0; i < max_device; i++) {
698 ATOM_CONNECTOR_INFO_I2C ci =
699 supported_devices->info.asConnInfo[i];
701 bios_connectors[i].valid = false;
703 if (!(device_support & (1 << i))) {
707 if (i == ATOM_DEVICE_CV_INDEX) {
708 DRM_DEBUG("Skipping Component Video\n");
712 bios_connectors[i].connector_type =
713 supported_devices_connector_convert[ci.sucConnectorInfo.
717 if (bios_connectors[i].connector_type ==
718 DRM_MODE_CONNECTOR_Unknown)
721 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
723 bios_connectors[i].line_mux =
724 ci.sucI2cId.ucAccess;
726 /* give tv unique connector ids */
727 if (i == ATOM_DEVICE_TV1_INDEX) {
728 bios_connectors[i].ddc_bus.valid = false;
729 bios_connectors[i].line_mux = 50;
730 } else if (i == ATOM_DEVICE_TV2_INDEX) {
731 bios_connectors[i].ddc_bus.valid = false;
732 bios_connectors[i].line_mux = 51;
733 } else if (i == ATOM_DEVICE_CV_INDEX) {
734 bios_connectors[i].ddc_bus.valid = false;
735 bios_connectors[i].line_mux = 52;
737 bios_connectors[i].ddc_bus =
738 radeon_lookup_i2c_gpio(rdev,
739 bios_connectors[i].line_mux);
741 if ((crev > 1) && (frev > 1)) {
742 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
745 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
748 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
751 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
755 if (i == ATOM_DEVICE_DFP1_INDEX)
756 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
757 else if (i == ATOM_DEVICE_DFP2_INDEX)
758 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
760 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
763 /* Always set the connector type to VGA for CRT1/CRT2. if they are
764 * shared with a DVI port, we'll pick up the DVI connector when we
765 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
767 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
768 bios_connectors[i].connector_type =
769 DRM_MODE_CONNECTOR_VGA;
771 if (!radeon_atom_apply_quirks
772 (dev, (1 << i), &bios_connectors[i].connector_type,
773 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
774 &bios_connectors[i].hpd))
777 bios_connectors[i].valid = true;
778 bios_connectors[i].devices = (1 << i);
780 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
781 radeon_add_atom_encoder(dev,
782 radeon_get_encoder_id(dev,
787 radeon_add_legacy_encoder(dev,
788 radeon_get_encoder_id(dev,
794 /* combine shared connectors */
795 for (i = 0; i < max_device; i++) {
796 if (bios_connectors[i].valid) {
797 for (j = 0; j < max_device; j++) {
798 if (bios_connectors[j].valid && (i != j)) {
799 if (bios_connectors[i].line_mux ==
800 bios_connectors[j].line_mux) {
801 /* make sure not to combine LVDS */
802 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
803 bios_connectors[i].line_mux = 53;
804 bios_connectors[i].ddc_bus.valid = false;
807 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
808 bios_connectors[j].line_mux = 53;
809 bios_connectors[j].ddc_bus.valid = false;
812 /* combine analog and digital for DVI-I */
813 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
814 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
815 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
816 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
817 bios_connectors[i].devices |=
818 bios_connectors[j].devices;
819 bios_connectors[i].connector_type =
820 DRM_MODE_CONNECTOR_DVII;
821 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
822 bios_connectors[i].hpd =
823 bios_connectors[j].hpd;
824 bios_connectors[j].valid = false;
832 /* add the connectors */
833 for (i = 0; i < max_device; i++) {
834 if (bios_connectors[i].valid) {
835 uint16_t connector_object_id =
836 atombios_get_connector_object_id(dev,
837 bios_connectors[i].connector_type,
838 bios_connectors[i].devices);
839 radeon_add_atom_connector(dev,
840 bios_connectors[i].line_mux,
841 bios_connectors[i].devices,
844 &bios_connectors[i].ddc_bus,
847 &bios_connectors[i].hpd);
851 radeon_link_encoder_connector(dev);
856 union firmware_info {
857 ATOM_FIRMWARE_INFO info;
858 ATOM_FIRMWARE_INFO_V1_2 info_12;
859 ATOM_FIRMWARE_INFO_V1_3 info_13;
860 ATOM_FIRMWARE_INFO_V1_4 info_14;
861 ATOM_FIRMWARE_INFO_V2_1 info_21;
864 bool radeon_atom_get_clock_info(struct drm_device *dev)
866 struct radeon_device *rdev = dev->dev_private;
867 struct radeon_mode_info *mode_info = &rdev->mode_info;
868 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
869 union firmware_info *firmware_info;
871 struct radeon_pll *p1pll = &rdev->clock.p1pll;
872 struct radeon_pll *p2pll = &rdev->clock.p2pll;
873 struct radeon_pll *dcpll = &rdev->clock.dcpll;
874 struct radeon_pll *spll = &rdev->clock.spll;
875 struct radeon_pll *mpll = &rdev->clock.mpll;
876 uint16_t data_offset;
878 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
879 &frev, &crev, &data_offset)) {
881 (union firmware_info *)(mode_info->atom_context->bios +
884 p1pll->reference_freq =
885 le16_to_cpu(firmware_info->info.usReferenceClock);
886 p1pll->reference_div = 0;
890 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
893 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
895 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
898 p1pll->lcd_pll_out_min =
899 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
900 if (p1pll->lcd_pll_out_min == 0)
901 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
902 p1pll->lcd_pll_out_max =
903 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
904 if (p1pll->lcd_pll_out_max == 0)
905 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
907 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
908 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
911 if (p1pll->pll_out_min == 0) {
912 if (ASIC_IS_AVIVO(rdev))
913 p1pll->pll_out_min = 64800;
915 p1pll->pll_out_min = 20000;
916 } else if (p1pll->pll_out_min > 64800) {
917 /* Limiting the pll output range is a good thing generally as
918 * it limits the number of possible pll combinations for a given
919 * frequency presumably to the ones that work best on each card.
920 * However, certain duallink DVI monitors seem to like
921 * pll combinations that would be limited by this at least on
922 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
926 p1pll->pll_out_min = 64800;
930 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
932 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
937 spll->reference_freq =
938 le16_to_cpu(firmware_info->info.usReferenceClock);
939 spll->reference_div = 0;
942 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
944 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
947 if (spll->pll_out_min == 0) {
948 if (ASIC_IS_AVIVO(rdev))
949 spll->pll_out_min = 64800;
951 spll->pll_out_min = 20000;
955 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
957 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
960 mpll->reference_freq =
961 le16_to_cpu(firmware_info->info.usReferenceClock);
962 mpll->reference_div = 0;
965 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
967 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
970 if (mpll->pll_out_min == 0) {
971 if (ASIC_IS_AVIVO(rdev))
972 mpll->pll_out_min = 64800;
974 mpll->pll_out_min = 20000;
978 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
980 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
982 rdev->clock.default_sclk =
983 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
984 rdev->clock.default_mclk =
985 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
987 if (ASIC_IS_DCE4(rdev)) {
988 rdev->clock.default_dispclk =
989 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
990 if (rdev->clock.default_dispclk == 0)
991 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
992 rdev->clock.dp_extclk =
993 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1004 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1005 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1008 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1010 struct radeon_mode_info *mode_info = &rdev->mode_info;
1011 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1012 union igp_info *igp_info;
1016 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1017 &frev, &crev, &data_offset)) {
1018 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1022 if (igp_info->info.ucMemoryType & 0xf0)
1026 if (igp_info->info_2.ucMemoryType & 0x0f)
1030 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1037 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1038 struct radeon_encoder_int_tmds *tmds)
1040 struct drm_device *dev = encoder->base.dev;
1041 struct radeon_device *rdev = dev->dev_private;
1042 struct radeon_mode_info *mode_info = &rdev->mode_info;
1043 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1044 uint16_t data_offset;
1045 struct _ATOM_TMDS_INFO *tmds_info;
1050 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1051 &frev, &crev, &data_offset)) {
1053 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1056 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1057 for (i = 0; i < 4; i++) {
1058 tmds->tmds_pll[i].freq =
1059 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1060 tmds->tmds_pll[i].value =
1061 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1062 tmds->tmds_pll[i].value |=
1063 (tmds_info->asMiscInfo[i].
1064 ucPLL_VCO_Gain & 0x3f) << 6;
1065 tmds->tmds_pll[i].value |=
1066 (tmds_info->asMiscInfo[i].
1067 ucPLL_DutyCycle & 0xf) << 12;
1068 tmds->tmds_pll[i].value |=
1069 (tmds_info->asMiscInfo[i].
1070 ucPLL_VoltageSwing & 0xf) << 16;
1072 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1073 tmds->tmds_pll[i].freq,
1074 tmds->tmds_pll[i].value);
1076 if (maxfreq == tmds->tmds_pll[i].freq) {
1077 tmds->tmds_pll[i].freq = 0xffffffff;
1086 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1091 struct drm_device *dev = encoder->base.dev;
1092 struct radeon_device *rdev = dev->dev_private;
1093 struct radeon_mode_info *mode_info = &rdev->mode_info;
1094 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1095 uint16_t data_offset;
1096 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1098 struct radeon_atom_ss *ss = NULL;
1101 if (id > ATOM_MAX_SS_ENTRY)
1104 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1105 &frev, &crev, &data_offset)) {
1107 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1110 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1115 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1116 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1118 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1119 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1120 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1121 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1122 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1123 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1132 struct _ATOM_LVDS_INFO info;
1133 struct _ATOM_LVDS_INFO_V12 info_12;
1136 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1140 struct drm_device *dev = encoder->base.dev;
1141 struct radeon_device *rdev = dev->dev_private;
1142 struct radeon_mode_info *mode_info = &rdev->mode_info;
1143 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1144 uint16_t data_offset, misc;
1145 union lvds_info *lvds_info;
1147 struct radeon_encoder_atom_dig *lvds = NULL;
1149 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1150 &frev, &crev, &data_offset)) {
1152 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1154 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1159 lvds->native_mode.clock =
1160 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1161 lvds->native_mode.hdisplay =
1162 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1163 lvds->native_mode.vdisplay =
1164 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1165 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1166 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1167 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1168 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1169 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1170 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1171 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1172 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1173 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1174 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1175 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1176 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1177 lvds->panel_pwr_delay =
1178 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1179 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1181 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1182 if (misc & ATOM_VSYNC_POLARITY)
1183 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1184 if (misc & ATOM_HSYNC_POLARITY)
1185 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1186 if (misc & ATOM_COMPOSITESYNC)
1187 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1188 if (misc & ATOM_INTERLACE)
1189 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1190 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1191 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1193 /* set crtc values */
1194 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1196 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1198 if (ASIC_IS_AVIVO(rdev)) {
1199 if (radeon_new_pll == 0)
1200 lvds->pll_algo = PLL_ALGO_LEGACY;
1202 lvds->pll_algo = PLL_ALGO_NEW;
1204 if (radeon_new_pll == 1)
1205 lvds->pll_algo = PLL_ALGO_NEW;
1207 lvds->pll_algo = PLL_ALGO_LEGACY;
1210 encoder->native_mode = lvds->native_mode;
1215 struct radeon_encoder_primary_dac *
1216 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1218 struct drm_device *dev = encoder->base.dev;
1219 struct radeon_device *rdev = dev->dev_private;
1220 struct radeon_mode_info *mode_info = &rdev->mode_info;
1221 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1222 uint16_t data_offset;
1223 struct _COMPASSIONATE_DATA *dac_info;
1226 struct radeon_encoder_primary_dac *p_dac = NULL;
1228 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1229 &frev, &crev, &data_offset)) {
1230 dac_info = (struct _COMPASSIONATE_DATA *)
1231 (mode_info->atom_context->bios + data_offset);
1233 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1238 bg = dac_info->ucDAC1_BG_Adjustment;
1239 dac = dac_info->ucDAC1_DAC_Adjustment;
1240 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1246 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1247 struct drm_display_mode *mode)
1249 struct radeon_mode_info *mode_info = &rdev->mode_info;
1250 ATOM_ANALOG_TV_INFO *tv_info;
1251 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1252 ATOM_DTD_FORMAT *dtd_timings;
1253 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1255 u16 data_offset, misc;
1257 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1258 &frev, &crev, &data_offset))
1263 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1264 if (index > MAX_SUPPORTED_TV_TIMING)
1267 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1268 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1269 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1270 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1271 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1273 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1274 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1275 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1276 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1277 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1280 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1281 if (misc & ATOM_VSYNC_POLARITY)
1282 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1283 if (misc & ATOM_HSYNC_POLARITY)
1284 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1285 if (misc & ATOM_COMPOSITESYNC)
1286 mode->flags |= DRM_MODE_FLAG_CSYNC;
1287 if (misc & ATOM_INTERLACE)
1288 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1289 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1290 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1292 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1295 /* PAL timings appear to have wrong values for totals */
1296 mode->crtc_htotal -= 1;
1297 mode->crtc_vtotal -= 1;
1301 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1302 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1305 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1306 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1307 le16_to_cpu(dtd_timings->usHBlanking_Time);
1308 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1309 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1310 le16_to_cpu(dtd_timings->usHSyncOffset);
1311 mode->crtc_hsync_end = mode->crtc_hsync_start +
1312 le16_to_cpu(dtd_timings->usHSyncWidth);
1314 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1315 le16_to_cpu(dtd_timings->usVBlanking_Time);
1316 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1317 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1318 le16_to_cpu(dtd_timings->usVSyncOffset);
1319 mode->crtc_vsync_end = mode->crtc_vsync_start +
1320 le16_to_cpu(dtd_timings->usVSyncWidth);
1323 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1324 if (misc & ATOM_VSYNC_POLARITY)
1325 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1326 if (misc & ATOM_HSYNC_POLARITY)
1327 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1328 if (misc & ATOM_COMPOSITESYNC)
1329 mode->flags |= DRM_MODE_FLAG_CSYNC;
1330 if (misc & ATOM_INTERLACE)
1331 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1332 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1333 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1335 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1342 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1344 struct radeon_mode_info *mode_info = &rdev->mode_info;
1345 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1346 uint16_t data_offset;
1348 struct _ATOM_ANALOG_TV_INFO *tv_info;
1349 enum radeon_tv_std tv_std = TV_STD_NTSC;
1351 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1352 &frev, &crev, &data_offset)) {
1354 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1355 (mode_info->atom_context->bios + data_offset);
1357 switch (tv_info->ucTV_BootUpDefaultStandard) {
1359 tv_std = TV_STD_NTSC;
1360 DRM_INFO("Default TV standard: NTSC\n");
1363 tv_std = TV_STD_NTSC_J;
1364 DRM_INFO("Default TV standard: NTSC-J\n");
1367 tv_std = TV_STD_PAL;
1368 DRM_INFO("Default TV standard: PAL\n");
1371 tv_std = TV_STD_PAL_M;
1372 DRM_INFO("Default TV standard: PAL-M\n");
1375 tv_std = TV_STD_PAL_N;
1376 DRM_INFO("Default TV standard: PAL-N\n");
1379 tv_std = TV_STD_PAL_CN;
1380 DRM_INFO("Default TV standard: PAL-CN\n");
1383 tv_std = TV_STD_PAL_60;
1384 DRM_INFO("Default TV standard: PAL-60\n");
1387 tv_std = TV_STD_SECAM;
1388 DRM_INFO("Default TV standard: SECAM\n");
1391 tv_std = TV_STD_NTSC;
1392 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1399 struct radeon_encoder_tv_dac *
1400 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1402 struct drm_device *dev = encoder->base.dev;
1403 struct radeon_device *rdev = dev->dev_private;
1404 struct radeon_mode_info *mode_info = &rdev->mode_info;
1405 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1406 uint16_t data_offset;
1407 struct _COMPASSIONATE_DATA *dac_info;
1410 struct radeon_encoder_tv_dac *tv_dac = NULL;
1412 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1413 &frev, &crev, &data_offset)) {
1415 dac_info = (struct _COMPASSIONATE_DATA *)
1416 (mode_info->atom_context->bios + data_offset);
1418 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1423 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1424 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1425 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1427 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1428 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1429 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1431 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1432 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1433 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1435 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1440 static const char *thermal_controller_names[] = {
1451 static const char *pp_lib_thermal_controller_names[] = {
1465 struct _ATOM_POWERPLAY_INFO info;
1466 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1467 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1468 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1471 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1473 struct radeon_mode_info *mode_info = &rdev->mode_info;
1474 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1477 u32 misc, misc2 = 0, sclk, mclk;
1478 union power_info *power_info;
1479 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1480 struct _ATOM_PPLIB_STATE *power_state;
1481 int num_modes = 0, i, j;
1482 int state_index = 0, mode_index = 0;
1483 struct radeon_i2c_bus_rec i2c_bus;
1485 rdev->pm.default_power_state = NULL;
1487 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1488 &frev, &crev, &data_offset)) {
1489 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1491 /* add the i2c bus for thermal/fan chip */
1492 if (power_info->info.ucOverdriveThermalController > 0) {
1493 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1494 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1495 power_info->info.ucOverdriveControllerAddress >> 1);
1496 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1497 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1499 num_modes = power_info->info.ucNumOfPowerModeEntries;
1500 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1501 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1502 for (i = 0; i < num_modes; i++) {
1503 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1506 rdev->pm.power_state[state_index].num_clock_modes = 1;
1507 rdev->pm.power_state[state_index].clock_info[0].mclk =
1508 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1509 rdev->pm.power_state[state_index].clock_info[0].sclk =
1510 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1511 /* skip invalid modes */
1512 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1513 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1515 /* skip overclock modes for now */
1516 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1517 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1518 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1519 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1521 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1522 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1523 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1524 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1525 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1527 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1528 radeon_lookup_gpio(rdev,
1529 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1530 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1531 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1534 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1536 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1537 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1539 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1540 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1542 /* order matters! */
1543 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1544 rdev->pm.power_state[state_index].type =
1545 POWER_STATE_TYPE_POWERSAVE;
1546 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1547 rdev->pm.power_state[state_index].type =
1548 POWER_STATE_TYPE_BATTERY;
1549 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1550 rdev->pm.power_state[state_index].type =
1551 POWER_STATE_TYPE_BATTERY;
1552 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1553 rdev->pm.power_state[state_index].type =
1554 POWER_STATE_TYPE_BALANCED;
1555 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1556 rdev->pm.power_state[state_index].type =
1557 POWER_STATE_TYPE_PERFORMANCE;
1558 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1559 rdev->pm.power_state[state_index].type =
1560 POWER_STATE_TYPE_DEFAULT;
1561 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1562 rdev->pm.power_state[state_index].default_clock_mode =
1563 &rdev->pm.power_state[state_index].clock_info[0];
1568 rdev->pm.power_state[state_index].num_clock_modes = 1;
1569 rdev->pm.power_state[state_index].clock_info[0].mclk =
1570 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1571 rdev->pm.power_state[state_index].clock_info[0].sclk =
1572 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1573 /* skip invalid modes */
1574 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1575 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1577 /* skip overclock modes for now */
1578 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1579 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1580 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1581 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1583 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1584 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1585 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1586 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1587 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1588 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1590 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1591 radeon_lookup_gpio(rdev,
1592 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1593 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1594 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1597 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1599 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1600 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1602 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1603 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1605 /* order matters! */
1606 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1607 rdev->pm.power_state[state_index].type =
1608 POWER_STATE_TYPE_POWERSAVE;
1609 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1610 rdev->pm.power_state[state_index].type =
1611 POWER_STATE_TYPE_BATTERY;
1612 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1613 rdev->pm.power_state[state_index].type =
1614 POWER_STATE_TYPE_BATTERY;
1615 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1616 rdev->pm.power_state[state_index].type =
1617 POWER_STATE_TYPE_BALANCED;
1618 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1619 rdev->pm.power_state[state_index].type =
1620 POWER_STATE_TYPE_PERFORMANCE;
1621 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1622 rdev->pm.power_state[state_index].type =
1623 POWER_STATE_TYPE_BALANCED;
1624 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1625 rdev->pm.power_state[state_index].type =
1626 POWER_STATE_TYPE_DEFAULT;
1627 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1628 rdev->pm.power_state[state_index].default_clock_mode =
1629 &rdev->pm.power_state[state_index].clock_info[0];
1634 rdev->pm.power_state[state_index].num_clock_modes = 1;
1635 rdev->pm.power_state[state_index].clock_info[0].mclk =
1636 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1637 rdev->pm.power_state[state_index].clock_info[0].sclk =
1638 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1639 /* skip invalid modes */
1640 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1641 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1643 /* skip overclock modes for now */
1644 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1645 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1646 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1647 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1649 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1650 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1651 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1652 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1653 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1654 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1656 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1657 radeon_lookup_gpio(rdev,
1658 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1659 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1660 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1663 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1665 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1666 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1668 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1669 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1670 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1671 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1673 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1674 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1677 /* order matters! */
1678 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1679 rdev->pm.power_state[state_index].type =
1680 POWER_STATE_TYPE_POWERSAVE;
1681 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1682 rdev->pm.power_state[state_index].type =
1683 POWER_STATE_TYPE_BATTERY;
1684 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1685 rdev->pm.power_state[state_index].type =
1686 POWER_STATE_TYPE_BATTERY;
1687 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1688 rdev->pm.power_state[state_index].type =
1689 POWER_STATE_TYPE_BALANCED;
1690 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1691 rdev->pm.power_state[state_index].type =
1692 POWER_STATE_TYPE_PERFORMANCE;
1693 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1694 rdev->pm.power_state[state_index].type =
1695 POWER_STATE_TYPE_BALANCED;
1696 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1697 rdev->pm.power_state[state_index].type =
1698 POWER_STATE_TYPE_DEFAULT;
1699 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1700 rdev->pm.power_state[state_index].default_clock_mode =
1701 &rdev->pm.power_state[state_index].clock_info[0];
1707 } else if (frev == 4) {
1708 /* add the i2c bus for thermal/fan chip */
1709 /* no support for internal controller yet */
1710 if (power_info->info_4.sThermalController.ucType > 0) {
1711 if ((power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
1712 (power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV770)) {
1713 DRM_INFO("Internal thermal controller %s fan control\n",
1714 (power_info->info_4.sThermalController.ucFanParameters &
1715 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1717 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1718 pp_lib_thermal_controller_names[power_info->info_4.sThermalController.ucType],
1719 power_info->info_4.sThermalController.ucI2cAddress >> 1,
1720 (power_info->info_4.sThermalController.ucFanParameters &
1721 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1722 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info_4.sThermalController.ucI2cLine);
1723 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1726 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1728 power_state = (struct _ATOM_PPLIB_STATE *)
1729 (mode_info->atom_context->bios +
1731 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1732 i * power_info->info_4.ucStateEntrySize);
1733 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1734 (mode_info->atom_context->bios +
1736 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1737 (power_state->ucNonClockStateIndex *
1738 power_info->info_4.ucNonClockSize));
1739 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1740 if (rdev->flags & RADEON_IS_IGP) {
1741 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1742 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1743 (mode_info->atom_context->bios +
1745 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1746 (power_state->ucClockStateIndices[j] *
1747 power_info->info_4.ucClockInfoSize));
1748 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1749 sclk |= clock_info->ucLowEngineClockHigh << 16;
1750 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1751 /* skip invalid modes */
1752 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1754 /* skip overclock modes for now */
1755 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1756 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
1758 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1760 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1764 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1765 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1766 (mode_info->atom_context->bios +
1768 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1769 (power_state->ucClockStateIndices[j] *
1770 power_info->info_4.ucClockInfoSize));
1771 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1772 sclk |= clock_info->ucEngineClockHigh << 16;
1773 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1774 mclk |= clock_info->ucMemoryClockHigh << 16;
1775 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1776 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1777 /* skip invalid modes */
1778 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1779 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1781 /* skip overclock modes for now */
1782 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1783 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1784 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1785 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1787 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1789 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1794 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1796 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1797 misc2 = le16_to_cpu(non_clock_info->usClassification);
1798 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1799 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1800 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1801 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1802 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1803 rdev->pm.power_state[state_index].type =
1804 POWER_STATE_TYPE_BATTERY;
1806 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1807 rdev->pm.power_state[state_index].type =
1808 POWER_STATE_TYPE_BALANCED;
1810 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1811 rdev->pm.power_state[state_index].type =
1812 POWER_STATE_TYPE_PERFORMANCE;
1815 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1816 rdev->pm.power_state[state_index].type =
1817 POWER_STATE_TYPE_DEFAULT;
1818 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1819 rdev->pm.power_state[state_index].default_clock_mode =
1820 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1827 /* XXX figure out some good default low power mode for cards w/out power tables */
1830 if (rdev->pm.default_power_state == NULL) {
1831 /* add the default mode */
1832 rdev->pm.power_state[state_index].type =
1833 POWER_STATE_TYPE_DEFAULT;
1834 rdev->pm.power_state[state_index].num_clock_modes = 1;
1835 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1836 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1837 rdev->pm.power_state[state_index].default_clock_mode =
1838 &rdev->pm.power_state[state_index].clock_info[0];
1839 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1840 if (rdev->asic->get_pcie_lanes)
1841 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1843 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1844 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1847 rdev->pm.num_power_states = state_index;
1849 rdev->pm.current_power_state = rdev->pm.default_power_state;
1850 rdev->pm.current_clock_mode =
1851 rdev->pm.default_power_state->default_clock_mode;
1854 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1856 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1857 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1859 args.ucEnable = enable;
1861 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1864 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1866 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1867 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1869 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1870 return args.ulReturnEngineClock;
1873 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1875 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1876 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1878 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1879 return args.ulReturnMemoryClock;
1882 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1885 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1886 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1888 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1890 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1893 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1896 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1897 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1899 if (rdev->flags & RADEON_IS_IGP)
1902 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1904 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1907 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1909 struct radeon_device *rdev = dev->dev_private;
1910 uint32_t bios_2_scratch, bios_6_scratch;
1912 if (rdev->family >= CHIP_R600) {
1913 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1914 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1916 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1917 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1920 /* let the bios control the backlight */
1921 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1923 /* tell the bios not to handle mode switching */
1924 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1926 if (rdev->family >= CHIP_R600) {
1927 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1928 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1930 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1931 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1936 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1938 uint32_t scratch_reg;
1941 if (rdev->family >= CHIP_R600)
1942 scratch_reg = R600_BIOS_0_SCRATCH;
1944 scratch_reg = RADEON_BIOS_0_SCRATCH;
1946 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1947 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1950 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1952 uint32_t scratch_reg;
1955 if (rdev->family >= CHIP_R600)
1956 scratch_reg = R600_BIOS_0_SCRATCH;
1958 scratch_reg = RADEON_BIOS_0_SCRATCH;
1960 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1961 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1964 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1966 struct drm_device *dev = encoder->dev;
1967 struct radeon_device *rdev = dev->dev_private;
1968 uint32_t bios_6_scratch;
1970 if (rdev->family >= CHIP_R600)
1971 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1973 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1976 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1978 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1980 if (rdev->family >= CHIP_R600)
1981 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1983 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1986 /* at some point we may want to break this out into individual functions */
1988 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1989 struct drm_encoder *encoder,
1992 struct drm_device *dev = connector->dev;
1993 struct radeon_device *rdev = dev->dev_private;
1994 struct radeon_connector *radeon_connector =
1995 to_radeon_connector(connector);
1996 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1997 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1999 if (rdev->family >= CHIP_R600) {
2000 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2001 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2002 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2004 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2005 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2006 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2009 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2010 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2012 DRM_DEBUG("TV1 connected\n");
2013 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2014 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2016 DRM_DEBUG("TV1 disconnected\n");
2017 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2018 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2019 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2022 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2023 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2025 DRM_DEBUG("CV connected\n");
2026 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2027 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2029 DRM_DEBUG("CV disconnected\n");
2030 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2031 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2032 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2035 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2036 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2038 DRM_DEBUG("LCD1 connected\n");
2039 bios_0_scratch |= ATOM_S0_LCD1;
2040 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2041 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2043 DRM_DEBUG("LCD1 disconnected\n");
2044 bios_0_scratch &= ~ATOM_S0_LCD1;
2045 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2046 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2049 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2050 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2052 DRM_DEBUG("CRT1 connected\n");
2053 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2054 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2055 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2057 DRM_DEBUG("CRT1 disconnected\n");
2058 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2059 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2060 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2063 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2064 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2066 DRM_DEBUG("CRT2 connected\n");
2067 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2068 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2069 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2071 DRM_DEBUG("CRT2 disconnected\n");
2072 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2073 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2074 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2077 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2078 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2080 DRM_DEBUG("DFP1 connected\n");
2081 bios_0_scratch |= ATOM_S0_DFP1;
2082 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2083 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2085 DRM_DEBUG("DFP1 disconnected\n");
2086 bios_0_scratch &= ~ATOM_S0_DFP1;
2087 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2088 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2091 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2092 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2094 DRM_DEBUG("DFP2 connected\n");
2095 bios_0_scratch |= ATOM_S0_DFP2;
2096 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2097 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2099 DRM_DEBUG("DFP2 disconnected\n");
2100 bios_0_scratch &= ~ATOM_S0_DFP2;
2101 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2102 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2105 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2106 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2108 DRM_DEBUG("DFP3 connected\n");
2109 bios_0_scratch |= ATOM_S0_DFP3;
2110 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2111 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2113 DRM_DEBUG("DFP3 disconnected\n");
2114 bios_0_scratch &= ~ATOM_S0_DFP3;
2115 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2116 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2119 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2120 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2122 DRM_DEBUG("DFP4 connected\n");
2123 bios_0_scratch |= ATOM_S0_DFP4;
2124 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2125 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2127 DRM_DEBUG("DFP4 disconnected\n");
2128 bios_0_scratch &= ~ATOM_S0_DFP4;
2129 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2130 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2133 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2134 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2136 DRM_DEBUG("DFP5 connected\n");
2137 bios_0_scratch |= ATOM_S0_DFP5;
2138 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2139 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2141 DRM_DEBUG("DFP5 disconnected\n");
2142 bios_0_scratch &= ~ATOM_S0_DFP5;
2143 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2144 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2148 if (rdev->family >= CHIP_R600) {
2149 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2150 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2151 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2153 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2154 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2155 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2160 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2162 struct drm_device *dev = encoder->dev;
2163 struct radeon_device *rdev = dev->dev_private;
2164 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2165 uint32_t bios_3_scratch;
2167 if (rdev->family >= CHIP_R600)
2168 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2170 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2172 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2173 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2174 bios_3_scratch |= (crtc << 18);
2176 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2177 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2178 bios_3_scratch |= (crtc << 24);
2180 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2181 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2182 bios_3_scratch |= (crtc << 16);
2184 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2185 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2186 bios_3_scratch |= (crtc << 20);
2188 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2189 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2190 bios_3_scratch |= (crtc << 17);
2192 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2193 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2194 bios_3_scratch |= (crtc << 19);
2196 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2197 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2198 bios_3_scratch |= (crtc << 23);
2200 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2201 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2202 bios_3_scratch |= (crtc << 25);
2205 if (rdev->family >= CHIP_R600)
2206 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2208 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2212 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2214 struct drm_device *dev = encoder->dev;
2215 struct radeon_device *rdev = dev->dev_private;
2216 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2217 uint32_t bios_2_scratch;
2219 if (rdev->family >= CHIP_R600)
2220 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2222 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2224 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2226 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2228 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2230 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2232 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2234 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2236 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2238 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2240 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2242 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2244 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2246 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2248 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2250 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2252 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2254 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2256 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2258 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2260 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2262 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2264 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2266 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2268 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2270 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2272 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2274 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2276 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2278 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2280 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2282 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2285 if (rdev->family >= CHIP_R600)
2286 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2288 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);