drivers/gpu/drm/radeon/r600_cs.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/kernel.h>
  29 #include "drmP.h"
  30 #include "radeon.h"
  31 #include "r600d.h"
  32 #include "r600_reg_safe.h"
  33
  34 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
  35                                         struct radeon_cs_reloc **cs_reloc);
  36 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
  37                                         struct radeon_cs_reloc **cs_reloc);
  38 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
  39 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
  40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
  41
  42
  43 struct r600_cs_track {
  44         /* configuration we miror so that we use same code btw kms/ums */
  45         u32                     group_size;
  46         u32                     nbanks;
  47         u32                     npipes;
  48         /* value we track */
  49         u32                     sq_config;
  50         u32                     nsamples;
  51         u32                     cb_color_base_last[8];
  52         struct radeon_bo        *cb_color_bo[8];
  53         u64                     cb_color_bo_mc[8];
  54         u32                     cb_color_bo_offset[8];
  55         struct radeon_bo        *cb_color_frag_bo[8];
  56         struct radeon_bo        *cb_color_tile_bo[8];
  57         u32                     cb_color_info[8];
  58         u32                     cb_color_size_idx[8];
  59         u32                     cb_target_mask;
  60         u32                     cb_shader_mask;
  61         u32                     cb_color_size[8];
  62         u32                     vgt_strmout_en;
  63         u32                     vgt_strmout_buffer_en;
  64         u32                     db_depth_control;
  65         u32                     db_depth_info;
  66         u32                     db_depth_size_idx;
  67         u32                     db_depth_view;
  68         u32                     db_depth_size;
  69         u32                     db_offset;
  70         struct radeon_bo        *db_bo;
  71         u64                     db_bo_mc;
  72 };
  73
  74 #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc }
  75 #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc }
  76 #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 3, 0 }
  77 #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc }
  78 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 6, 0 }
  79 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc }
  80 #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0 }
  81 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16, vc }
  82
  83 struct gpu_formats {
  84         unsigned blockwidth;
  85         unsigned blockheight;
  86         unsigned blocksize;
  87         unsigned valid_color;
  88 };
  89
  90 static const struct gpu_formats color_formats_table[] = {
  91         /* 8 bit */
  92         FMT_8_BIT(V_038004_COLOR_8, 1),
  93         FMT_8_BIT(V_038004_COLOR_4_4, 1),
  94         FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
  95         FMT_8_BIT(V_038004_FMT_1, 0),
  96
  97         /* 16-bit */
  98         FMT_16_BIT(V_038004_COLOR_16, 1),
  99         FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
 100         FMT_16_BIT(V_038004_COLOR_8_8, 1),
 101         FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
 102         FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
 103         FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
 104         FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
 105         FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
 106
 107         /* 24-bit */
 108         FMT_24_BIT(V_038004_FMT_8_8_8),
 109
 110         /* 32-bit */
 111         FMT_32_BIT(V_038004_COLOR_32, 1),
 112         FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
 113         FMT_32_BIT(V_038004_COLOR_16_16, 1),
 114         FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
 115         FMT_32_BIT(V_038004_COLOR_8_24, 1),
 116         FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
 117         FMT_32_BIT(V_038004_COLOR_24_8, 1),
 118         FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
 119         FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
 120         FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
 121         FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
 122         FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
 123         FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
 124         FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
 125         FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
 126         FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
 127         FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
 128         FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
 129
 130         /* 48-bit */
 131         FMT_48_BIT(V_038004_FMT_16_16_16),
 132         FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
 133
 134         /* 64-bit */
 135         FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
 136         FMT_64_BIT(V_038004_COLOR_32_32, 1),
 137         FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
 138         FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
 139         FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
 140
 141         FMT_96_BIT(V_038004_FMT_32_32_32),
 142         FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
 143
 144         /* 128-bit */
 145         FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
 146         FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
 147
 148         [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
 149         [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
 150
 151         /* block compressed formats */
 152         [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
 153         [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
 154         [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
 155         [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
 156         [V_038004_FMT_BC5] = { 4, 4, 16, 0},
 157
 158 };
 159
 160 static inline bool fmt_is_valid_color(u32 format)
 161 {
 162         if (format >= ARRAY_SIZE(color_formats_table))
 163                 return false;
 164
 165         if (color_formats_table[format].valid_color)
 166                 return true;
 167
 168         return false;
 169 }
 170
 171 static inline bool fmt_is_valid_texture(u32 format)
 172 {
 173         if (format >= ARRAY_SIZE(color_formats_table))
 174                 return false;
 175
 176         if (color_formats_table[format].blockwidth > 0)
 177                 return true;
 178
 179         return false;
 180 }
 181
 182 static inline int fmt_get_blocksize(u32 format)
 183 {
 184         if (format >= ARRAY_SIZE(color_formats_table))
 185                 return 0;
 186
 187         return color_formats_table[format].blocksize;
 188 }
 189
 190 static inline int fmt_get_nblocksx(u32 format, u32 w)
 191 {
 192         unsigned bw;
 193
 194         if (format >= ARRAY_SIZE(color_formats_table))
 195                 return 0;
 196
 197         bw = color_formats_table[format].blockwidth;
 198         if (bw == 0)
 199                 return 0;
 200
 201         return (w + bw - 1) / bw;
 202 }
 203
 204 static inline int fmt_get_nblocksy(u32 format, u32 h)
 205 {
 206         unsigned bh;
 207
 208         if (format >= ARRAY_SIZE(color_formats_table))
 209                 return 0;
 210
 211         bh = color_formats_table[format].blockheight;
 212         if (bh == 0)
 213                 return 0;
 214
 215         return (h + bh - 1) / bh;
 216 }
 217
 218 static inline int r600_bpe_from_format(u32 *bpe, u32 format)
 219 {
 220         unsigned res;
 221
 222         if (format >= ARRAY_SIZE(color_formats_table))
 223                 goto fail;
 224
 225         res = color_formats_table[format].blocksize;
 226         if (res == 0)
 227                 goto fail;
 228
 229         *bpe = res;
 230         return 0;
 231
 232 fail:
 233         *bpe = 16;
 234         return -EINVAL;
 235 }
 236
 237 struct array_mode_checker {
 238         int array_mode;
 239         u32 group_size;
 240         u32 nbanks;
 241         u32 npipes;
 242         u32 nsamples;
 243         u32 blocksize;
 244 };
 245
 246 /* returns alignment in pixels for pitch/height/depth and bytes for base */
 247 static inline int r600_get_array_mode_alignment(struct array_mode_checker *values,
 248                                                 u32 *pitch_align,
 249                                                 u32 *height_align,
 250                                                 u32 *depth_align,
 251                                                 u64 *base_align)
 252 {
 253         u32 tile_width = 8;
 254         u32 tile_height = 8;
 255         u32 macro_tile_width = values->nbanks;
 256         u32 macro_tile_height = values->npipes;
 257         u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
 258         u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
 259
 260         switch (values->array_mode) {
 261         case ARRAY_LINEAR_GENERAL:
 262                 /* technically tile_width/_height for pitch/height */
 263                 *pitch_align = 1; /* tile_width */
 264                 *height_align = 1; /* tile_height */
 265                 *depth_align = 1;
 266                 *base_align = 1;
 267                 break;
 268         case ARRAY_LINEAR_ALIGNED:
 269                 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
 270                 *height_align = tile_height;
 271                 *depth_align = 1;
 272                 *base_align = values->group_size;
 273                 break;
 274         case ARRAY_1D_TILED_THIN1:
 275                 *pitch_align = max((u32)tile_width,
 276                                    (u32)(values->group_size /
 277                                          (tile_height * values->blocksize * values->nsamples)));
 278                 *height_align = tile_height;
 279                 *depth_align = 1;
 280                 *base_align = values->group_size;
 281                 break;
 282         case ARRAY_2D_TILED_THIN1:
 283                 *pitch_align = max((u32)macro_tile_width,
 284                                   (u32)(((values->group_size / tile_height) /
 285                                          (values->blocksize * values->nsamples)) *
 286                                         values->nbanks)) * tile_width;
 287                 *height_align = macro_tile_height * tile_height;
 288                 *depth_align = 1;
 289                 *base_align = max(macro_tile_bytes,
 290                                   (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
 291                 break;
 292         default:
 293                 return -EINVAL;
 294         }
 295
 296         return 0;
 297 }
 298
 299 static void r600_cs_track_init(struct r600_cs_track *track)
 300 {
 301         int i;
 302
 303         /* assume DX9 mode */
 304         track->sq_config = DX9_CONSTS;
 305         for (i = 0; i < 8; i++) {
 306                 track->cb_color_base_last[i] = 0;
 307                 track->cb_color_size[i] = 0;
 308                 track->cb_color_size_idx[i] = 0;
 309                 track->cb_color_info[i] = 0;
 310                 track->cb_color_bo[i] = NULL;
 311                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
 312                 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
 313         }
 314         track->cb_target_mask = 0xFFFFFFFF;
 315         track->cb_shader_mask = 0xFFFFFFFF;
 316         track->db_bo = NULL;
 317         track->db_bo_mc = 0xFFFFFFFF;
 318         /* assume the biggest format and that htile is enabled */
 319         track->db_depth_info = 7 | (1 << 25);
 320         track->db_depth_view = 0xFFFFC000;
 321         track->db_depth_size = 0xFFFFFFFF;
 322         track->db_depth_size_idx = 0;
 323         track->db_depth_control = 0xFFFFFFFF;
 324 }
 325
 326 static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
 327 {
 328         struct r600_cs_track *track = p->track;
 329         u32 slice_tile_max, size, tmp;
 330         u32 height, height_align, pitch, pitch_align, depth_align;
 331         u64 base_offset, base_align;
 332         struct array_mode_checker array_check;
 333         volatile u32 *ib = p->ib->ptr;
 334         unsigned array_mode;
 335         u32 format;
 336         if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
 337                 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
 338                 return -EINVAL;
 339         }
 340         size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
 341         format = G_0280A0_FORMAT(track->cb_color_info[i]);
 342         if (!fmt_is_valid_color(format)) {
 343                 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
 344                          __func__, __LINE__, format,
 345                         i, track->cb_color_info[i]);
 346                 return -EINVAL;
 347         }
 348         /* pitch in pixels */
 349         pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
 350         slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
 351         slice_tile_max *= 64;
 352         height = slice_tile_max / pitch;
 353         if (height > 8192)
 354                 height = 8192;
 355         array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
 356
 357         base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
 358         array_check.array_mode = array_mode;
 359         array_check.group_size = track->group_size;
 360         array_check.nbanks = track->nbanks;
 361         array_check.npipes = track->npipes;
 362         array_check.nsamples = track->nsamples;
 363         array_check.blocksize = fmt_get_blocksize(format);
 364         if (r600_get_array_mode_alignment(&array_check,
 365                                           &pitch_align, &height_align, &depth_align, &base_align)) {
 366                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
 367                          G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
 368                          track->cb_color_info[i]);
 369                 return -EINVAL;
 370         }
 371         switch (array_mode) {
 372         case V_0280A0_ARRAY_LINEAR_GENERAL:
 373                 break;
 374         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 375                 break;
 376         case V_0280A0_ARRAY_1D_TILED_THIN1:
 377                 /* avoid breaking userspace */
 378                 if (height > 7)
 379                         height &= ~0x7;
 380                 break;
 381         case V_0280A0_ARRAY_2D_TILED_THIN1:
 382                 break;
 383         default:
 384                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
 385                         G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
 386                         track->cb_color_info[i]);
 387                 return -EINVAL;
 388         }
 389
 390         if (!IS_ALIGNED(pitch, pitch_align)) {
 391                 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
 392                          __func__, __LINE__, pitch);
 393                 return -EINVAL;
 394         }
 395         if (!IS_ALIGNED(height, height_align)) {
 396                 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
 397                          __func__, __LINE__, height);
 398                 return -EINVAL;
 399         }
 400         if (!IS_ALIGNED(base_offset, base_align)) {
 401                 dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset);
 402                 return -EINVAL;
 403         }
 404
 405         /* check offset */
 406         tmp = fmt_get_nblocksy(format, height) * fmt_get_nblocksx(format, pitch) * fmt_get_blocksize(format);
 407         if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
 408                 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
 409                         /* the initial DDX does bad things with the CB size occasionally */
 410                         /* it rounds up height too far for slice tile max but the BO is smaller */
 411                         /* r600c,g also seem to flush at bad times in some apps resulting in
 412                          * bogus values here. So for linear just allow anything to avoid breaking
 413                          * broken userspace.
 414                          */
 415                 } else {
 416                         dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i]));
 417                         return -EINVAL;
 418                 }
 419         }
 420         /* limit max tile */
 421         tmp = (height * pitch) >> 6;
 422         if (tmp < slice_tile_max)
 423                 slice_tile_max = tmp;
 424         tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
 425                 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
 426         ib[track->cb_color_size_idx[i]] = tmp;
 427         return 0;
 428 }
 429
 430 static int r600_cs_track_check(struct radeon_cs_parser *p)
 431 {
 432         struct r600_cs_track *track = p->track;
 433         u32 tmp;
 434         int r, i;
 435         volatile u32 *ib = p->ib->ptr;
 436
 437         /* on legacy kernel we don't perform advanced check */
 438         if (p->rdev == NULL)
 439                 return 0;
 440         /* we don't support out buffer yet */
 441         if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
 442                 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
 443                 return -EINVAL;
 444         }
 445         /* check that we have a cb for each enabled target, we don't check
 446          * shader_mask because it seems mesa isn't always setting it :(
 447          */
 448         tmp = track->cb_target_mask;
 449         for (i = 0; i < 8; i++) {
 450                 if ((tmp >> (i * 4)) & 0xF) {
 451                         /* at least one component is enabled */
 452                         if (track->cb_color_bo[i] == NULL) {
 453                                 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
 454                                         __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
 455                                 return -EINVAL;
 456                         }
 457                         /* perform rewrite of CB_COLOR[0-7]_SIZE */
 458                         r = r600_cs_track_validate_cb(p, i);
 459                         if (r)
 460                                 return r;
 461                 }
 462         }
 463         /* Check depth buffer */
 464         if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
 465                 G_028800_Z_ENABLE(track->db_depth_control)) {
 466                 u32 nviews, bpe, ntiles, size, slice_tile_max;
 467                 u32 height, height_align, pitch, pitch_align, depth_align;
 468                 u64 base_offset, base_align;
 469                 struct array_mode_checker array_check;
 470                 int array_mode;
 471
 472                 if (track->db_bo == NULL) {
 473                         dev_warn(p->dev, "z/stencil with no depth buffer\n");
 474                         return -EINVAL;
 475                 }
 476                 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
 477                         dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
 478                         return -EINVAL;
 479                 }
 480                 switch (G_028010_FORMAT(track->db_depth_info)) {
 481                 case V_028010_DEPTH_16:
 482                         bpe = 2;
 483                         break;
 484                 case V_028010_DEPTH_X8_24:
 485                 case V_028010_DEPTH_8_24:
 486                 case V_028010_DEPTH_X8_24_FLOAT:
 487                 case V_028010_DEPTH_8_24_FLOAT:
 488                 case V_028010_DEPTH_32_FLOAT:
 489                         bpe = 4;
 490                         break;
 491                 case V_028010_DEPTH_X24_8_32_FLOAT:
 492                         bpe = 8;
 493                         break;
 494                 default:
 495                         dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
 496                         return -EINVAL;
 497                 }
 498                 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
 499                         if (!track->db_depth_size_idx) {
 500                                 dev_warn(p->dev, "z/stencil buffer size not set\n");
 501                                 return -EINVAL;
 502                         }
 503                         tmp = radeon_bo_size(track->db_bo) - track->db_offset;
 504                         tmp = (tmp / bpe) >> 6;
 505                         if (!tmp) {
 506                                 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
 507                                                 track->db_depth_size, bpe, track->db_offset,
 508                                                 radeon_bo_size(track->db_bo));
 509                                 return -EINVAL;
 510                         }
 511                         ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
 512                 } else {
 513                         size = radeon_bo_size(track->db_bo);
 514                         /* pitch in pixels */
 515                         pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
 516                         slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
 517                         slice_tile_max *= 64;
 518                         height = slice_tile_max / pitch;
 519                         if (height > 8192)
 520                                 height = 8192;
 521                         base_offset = track->db_bo_mc + track->db_offset;
 522                         array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
 523                         array_check.array_mode = array_mode;
 524                         array_check.group_size = track->group_size;
 525                         array_check.nbanks = track->nbanks;
 526                         array_check.npipes = track->npipes;
 527                         array_check.nsamples = track->nsamples;
 528                         array_check.blocksize = bpe;
 529                         if (r600_get_array_mode_alignment(&array_check,
 530                                                           &pitch_align, &height_align, &depth_align, &base_align)) {
 531                                 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
 532                                          G_028010_ARRAY_MODE(track->db_depth_info),
 533                                          track->db_depth_info);
 534                                 return -EINVAL;
 535                         }
 536                         switch (array_mode) {
 537                         case V_028010_ARRAY_1D_TILED_THIN1:
 538                                 /* don't break userspace */
 539                                 height &= ~0x7;
 540                                 break;
 541                         case V_028010_ARRAY_2D_TILED_THIN1:
 542                                 break;
 543                         default:
 544                                 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
 545                                          G_028010_ARRAY_MODE(track->db_depth_info),
 546                                          track->db_depth_info);
 547                                 return -EINVAL;
 548                         }
 549
 550                         if (!IS_ALIGNED(pitch, pitch_align)) {
 551                                 dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
 552                                          __func__, __LINE__, pitch);
 553                                 return -EINVAL;
 554                         }
 555                         if (!IS_ALIGNED(height, height_align)) {
 556                                 dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
 557                                          __func__, __LINE__, height);
 558                                 return -EINVAL;
 559                         }
 560                         if (!IS_ALIGNED(base_offset, base_align)) {
 561                                 dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset);
 562                                 return -EINVAL;
 563                         }
 564
 565                         ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
 566                         nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
 567                         tmp = ntiles * bpe * 64 * nviews;
 568                         if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
 569                                 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %u have %lu)\n",
 570                                                 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
 571                                                 radeon_bo_size(track->db_bo));
 572                                 return -EINVAL;
 573                         }
 574                 }
 575         }
 576         return 0;
 577 }
 578
 579 /**
 580  * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
 581  * @parser:     parser structure holding parsing context.
 582  * @pkt:        where to store packet informations
 583  *
 584  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 585  * if packet is bigger than remaining ib size. or if packets is unknown.
 586  **/
 587 int r600_cs_packet_parse(struct radeon_cs_parser *p,
 588                         struct radeon_cs_packet *pkt,
 589                         unsigned idx)
 590 {
 591         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 592         uint32_t header;
 593
 594         if (idx >= ib_chunk->length_dw) {
 595                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 596                           idx, ib_chunk->length_dw);
 597                 return -EINVAL;
 598         }
 599         header = radeon_get_ib_value(p, idx);
 600         pkt->idx = idx;
 601         pkt->type = CP_PACKET_GET_TYPE(header);
 602         pkt->count = CP_PACKET_GET_COUNT(header);
 603         pkt->one_reg_wr = 0;
 604         switch (pkt->type) {
 605         case PACKET_TYPE0:
 606                 pkt->reg = CP_PACKET0_GET_REG(header);
 607                 break;
 608         case PACKET_TYPE3:
 609                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 610                 break;
 611         case PACKET_TYPE2:
 612                 pkt->count = -1;
 613                 break;
 614         default:
 615                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 616                 return -EINVAL;
 617         }
 618         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 619                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 620                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 621                 return -EINVAL;
 622         }
 623         return 0;
 624 }
 625
 626 /**
 627  * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
 628  * @parser:             parser structure holding parsing context.
 629  * @data:               pointer to relocation data
 630  * @offset_start:       starting offset
 631  * @offset_mask:        offset mask (to align start offset on)
 632  * @reloc:              reloc informations
 633  *
 634  * Check next packet is relocation packet3, do bo validation and compute
 635  * GPU offset using the provided start.
 636  **/
 637 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
 638                                         struct radeon_cs_reloc **cs_reloc)
 639 {
 640         struct radeon_cs_chunk *relocs_chunk;
 641         struct radeon_cs_packet p3reloc;
 642         unsigned idx;
 643         int r;
 644
 645         if (p->chunk_relocs_idx == -1) {
 646                 DRM_ERROR("No relocation chunk !\n");
 647                 return -EINVAL;
 648         }
 649         *cs_reloc = NULL;
 650         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 651         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 652         if (r) {
 653                 return r;
 654         }
 655         p->idx += p3reloc.count + 2;
 656         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 657                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 658                           p3reloc.idx);
 659                 return -EINVAL;
 660         }
 661         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 662         if (idx >= relocs_chunk->length_dw) {
 663                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 664                           idx, relocs_chunk->length_dw);
 665                 return -EINVAL;
 666         }
 667         /* FIXME: we assume reloc size is 4 dwords */
 668         *cs_reloc = p->relocs_ptr[(idx / 4)];
 669         return 0;
 670 }
 671
 672 /**
 673  * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
 674  * @parser:             parser structure holding parsing context.
 675  * @data:               pointer to relocation data
 676  * @offset_start:       starting offset
 677  * @offset_mask:        offset mask (to align start offset on)
 678  * @reloc:              reloc informations
 679  *
 680  * Check next packet is relocation packet3, do bo validation and compute
 681  * GPU offset using the provided start.
 682  **/
 683 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
 684                                         struct radeon_cs_reloc **cs_reloc)
 685 {
 686         struct radeon_cs_chunk *relocs_chunk;
 687         struct radeon_cs_packet p3reloc;
 688         unsigned idx;
 689         int r;
 690
 691         if (p->chunk_relocs_idx == -1) {
 692                 DRM_ERROR("No relocation chunk !\n");
 693                 return -EINVAL;
 694         }
 695         *cs_reloc = NULL;
 696         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 697         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 698         if (r) {
 699                 return r;
 700         }
 701         p->idx += p3reloc.count + 2;
 702         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 703                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 704                           p3reloc.idx);
 705                 return -EINVAL;
 706         }
 707         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 708         if (idx >= relocs_chunk->length_dw) {
 709                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 710                           idx, relocs_chunk->length_dw);
 711                 return -EINVAL;
 712         }
 713         *cs_reloc = p->relocs;
 714         (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
 715         (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
 716         return 0;
 717 }
 718
 719 /**
 720  * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
 721  * @parser:             parser structure holding parsing context.
 722  *
 723  * Check next packet is relocation packet3, do bo validation and compute
 724  * GPU offset using the provided start.
 725  **/
 726 static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
 727 {
 728         struct radeon_cs_packet p3reloc;
 729         int r;
 730
 731         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 732         if (r) {
 733                 return 0;
 734         }
 735         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 736                 return 0;
 737         }
 738         return 1;
 739 }
 740
 741 /**
 742  * r600_cs_packet_next_vline() - parse userspace VLINE packet
 743  * @parser:             parser structure holding parsing context.
 744  *
 745  * Userspace sends a special sequence for VLINE waits.
 746  * PACKET0 - VLINE_START_END + value
 747  * PACKET3 - WAIT_REG_MEM poll vline status reg
 748  * RELOC (P3) - crtc_id in reloc.
 749  *
 750  * This function parses this and relocates the VLINE START END
 751  * and WAIT_REG_MEM packets to the correct crtc.
 752  * It also detects a switched off crtc and nulls out the
 753  * wait in that case.
 754  */
 755 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
 756 {
 757         struct drm_mode_object *obj;
 758         struct drm_crtc *crtc;
 759         struct radeon_crtc *radeon_crtc;
 760         struct radeon_cs_packet p3reloc, wait_reg_mem;
 761         int crtc_id;
 762         int r;
 763         uint32_t header, h_idx, reg, wait_reg_mem_info;
 764         volatile uint32_t *ib;
 765
 766         ib = p->ib->ptr;
 767
 768         /* parse the WAIT_REG_MEM */
 769         r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
 770         if (r)
 771                 return r;
 772
 773         /* check its a WAIT_REG_MEM */
 774         if (wait_reg_mem.type != PACKET_TYPE3 ||
 775             wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
 776                 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
 777                 r = -EINVAL;
 778                 return r;
 779         }
 780
 781         wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
 782         /* bit 4 is reg (0) or mem (1) */
 783         if (wait_reg_mem_info & 0x10) {
 784                 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
 785                 r = -EINVAL;
 786                 return r;
 787         }
 788         /* waiting for value to be equal */
 789         if ((wait_reg_mem_info & 0x7) != 0x3) {
 790                 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
 791                 r = -EINVAL;
 792                 return r;
 793         }
 794         if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
 795                 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
 796                 r = -EINVAL;
 797                 return r;
 798         }
 799
 800         if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
 801                 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
 802                 r = -EINVAL;
 803                 return r;
 804         }
 805
 806         /* jump over the NOP */
 807         r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
 808         if (r)
 809                 return r;
 810
 811         h_idx = p->idx - 2;
 812         p->idx += wait_reg_mem.count + 2;
 813         p->idx += p3reloc.count + 2;
 814
 815         header = radeon_get_ib_value(p, h_idx);
 816         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
 817         reg = CP_PACKET0_GET_REG(header);
 818
 819         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 820         if (!obj) {
 821                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
 822                 r = -EINVAL;
 823                 goto out;
 824         }
 825         crtc = obj_to_crtc(obj);
 826         radeon_crtc = to_radeon_crtc(crtc);
 827         crtc_id = radeon_crtc->crtc_id;
 828
 829         if (!crtc->enabled) {
 830                 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
 831                 ib[h_idx + 2] = PACKET2(0);
 832                 ib[h_idx + 3] = PACKET2(0);
 833                 ib[h_idx + 4] = PACKET2(0);
 834                 ib[h_idx + 5] = PACKET2(0);
 835                 ib[h_idx + 6] = PACKET2(0);
 836                 ib[h_idx + 7] = PACKET2(0);
 837                 ib[h_idx + 8] = PACKET2(0);
 838         } else if (crtc_id == 1) {
 839                 switch (reg) {
 840                 case AVIVO_D1MODE_VLINE_START_END:
 841                         header &= ~R600_CP_PACKET0_REG_MASK;
 842                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
 843                         break;
 844                 default:
 845                         DRM_ERROR("unknown crtc reloc\n");
 846                         r = -EINVAL;
 847                         goto out;
 848                 }
 849                 ib[h_idx] = header;
 850                 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
 851         }
 852 out:
 853         return r;
 854 }
 855
 856 static int r600_packet0_check(struct radeon_cs_parser *p,
 857                                 struct radeon_cs_packet *pkt,
 858                                 unsigned idx, unsigned reg)
 859 {
 860         int r;
 861
 862         switch (reg) {
 863         case AVIVO_D1MODE_VLINE_START_END:
 864                 r = r600_cs_packet_parse_vline(p);
 865                 if (r) {
 866                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 867                                         idx, reg);
 868                         return r;
 869                 }
 870                 break;
 871         default:
 872                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
 873                        reg, idx);
 874                 return -EINVAL;
 875         }
 876         return 0;
 877 }
 878
 879 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
 880                                 struct radeon_cs_packet *pkt)
 881 {
 882         unsigned reg, i;
 883         unsigned idx;
 884         int r;
 885
 886         idx = pkt->idx + 1;
 887         reg = pkt->reg;
 888         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
 889                 r = r600_packet0_check(p, pkt, idx, reg);
 890                 if (r) {
 891                         return r;
 892                 }
 893         }
 894         return 0;
 895 }
 896
 897 /**
 898  * r600_cs_check_reg() - check if register is authorized or not
 899  * @parser: parser structure holding parsing context
 900  * @reg: register we are testing
 901  * @idx: index into the cs buffer
 902  *
 903  * This function will test against r600_reg_safe_bm and return 0
 904  * if register is safe. If register is not flag as safe this function
 905  * will test it against a list of register needind special handling.
 906  */
 907 static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
 908 {
 909         struct r600_cs_track *track = (struct r600_cs_track *)p->track;
 910         struct radeon_cs_reloc *reloc;
 911         u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm);
 912         u32 m, i, tmp, *ib;
 913         int r;
 914
 915         i = (reg >> 7);
 916         if (i > last_reg) {
 917                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
 918                 return -EINVAL;
 919         }
 920         m = 1 << ((reg >> 2) & 31);
 921         if (!(r600_reg_safe_bm[i] & m))
 922                 return 0;
 923         ib = p->ib->ptr;
 924         switch (reg) {
 925         /* force following reg to 0 in an attemp to disable out buffer
 926          * which will need us to better understand how it works to perform
 927          * security check on it (Jerome)
 928          */
 929         case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
 930         case R_008C44_SQ_ESGS_RING_SIZE:
 931         case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
 932         case R_008C54_SQ_ESTMP_RING_SIZE:
 933         case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
 934         case R_008C74_SQ_FBUF_RING_SIZE:
 935         case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
 936         case R_008C5C_SQ_GSTMP_RING_SIZE:
 937         case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
 938         case R_008C4C_SQ_GSVS_RING_SIZE:
 939         case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
 940         case R_008C6C_SQ_PSTMP_RING_SIZE:
 941         case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
 942         case R_008C7C_SQ_REDUC_RING_SIZE:
 943         case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
 944         case R_008C64_SQ_VSTMP_RING_SIZE:
 945         case R_0288C8_SQ_GS_VERT_ITEMSIZE:
 946                 /* get value to populate the IB don't remove */
 947                 tmp =radeon_get_ib_value(p, idx);
 948                 ib[idx] = 0;
 949                 break;
 950         case SQ_CONFIG:
 951                 track->sq_config = radeon_get_ib_value(p, idx);
 952                 break;
 953         case R_028800_DB_DEPTH_CONTROL:
 954                 track->db_depth_control = radeon_get_ib_value(p, idx);
 955                 break;
 956         case R_028010_DB_DEPTH_INFO:
 957                 if (r600_cs_packet_next_is_pkt3_nop(p)) {
 958                         r = r600_cs_packet_next_reloc(p, &reloc);
 959                         if (r) {
 960                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
 961                                          "0x%04X\n", reg);
 962                                 return -EINVAL;
 963                         }
 964                         track->db_depth_info = radeon_get_ib_value(p, idx);
 965                         ib[idx] &= C_028010_ARRAY_MODE;
 966                         track->db_depth_info &= C_028010_ARRAY_MODE;
 967                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
 968                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
 969                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
 970                         } else {
 971                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
 972                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
 973                         }
 974                 } else
 975                         track->db_depth_info = radeon_get_ib_value(p, idx);
 976                 break;
 977         case R_028004_DB_DEPTH_VIEW:
 978                 track->db_depth_view = radeon_get_ib_value(p, idx);
 979                 break;
 980         case R_028000_DB_DEPTH_SIZE:
 981                 track->db_depth_size = radeon_get_ib_value(p, idx);
 982                 track->db_depth_size_idx = idx;
 983                 break;
 984         case R_028AB0_VGT_STRMOUT_EN:
 985                 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
 986                 break;
 987         case R_028B20_VGT_STRMOUT_BUFFER_EN:
 988                 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
 989                 break;
 990         case R_028238_CB_TARGET_MASK:
 991                 track->cb_target_mask = radeon_get_ib_value(p, idx);
 992                 break;
 993         case R_02823C_CB_SHADER_MASK:
 994                 track->cb_shader_mask = radeon_get_ib_value(p, idx);
 995                 break;
 996         case R_028C04_PA_SC_AA_CONFIG:
 997                 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
 998                 track->nsamples = 1 << tmp;
 999                 break;
1000         case R_0280A0_CB_COLOR0_INFO:
1001         case R_0280A4_CB_COLOR1_INFO:
1002         case R_0280A8_CB_COLOR2_INFO:
1003         case R_0280AC_CB_COLOR3_INFO:
1004         case R_0280B0_CB_COLOR4_INFO:
1005         case R_0280B4_CB_COLOR5_INFO:
1006         case R_0280B8_CB_COLOR6_INFO:
1007         case R_0280BC_CB_COLOR7_INFO:
1008                 if (r600_cs_packet_next_is_pkt3_nop(p)) {
1009                         r = r600_cs_packet_next_reloc(p, &reloc);
1010                         if (r) {
1011                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1012                                 return -EINVAL;
1013                         }
1014                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1015                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1016                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1017                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1018                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1019                         } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1020                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1021                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1022                         }
1023                 } else {
1024                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1025                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1026                 }
1027                 break;
1028         case R_028060_CB_COLOR0_SIZE:
1029         case R_028064_CB_COLOR1_SIZE:
1030         case R_028068_CB_COLOR2_SIZE:
1031         case R_02806C_CB_COLOR3_SIZE:
1032         case R_028070_CB_COLOR4_SIZE:
1033         case R_028074_CB_COLOR5_SIZE:
1034         case R_028078_CB_COLOR6_SIZE:
1035         case R_02807C_CB_COLOR7_SIZE:
1036                 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1037                 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1038                 track->cb_color_size_idx[tmp] = idx;
1039                 break;
1040                 /* This register were added late, there is userspace
1041                  * which does provide relocation for those but set
1042                  * 0 offset. In order to avoid breaking old userspace
1043                  * we detect this and set address to point to last
1044                  * CB_COLOR0_BASE, note that if userspace doesn't set
1045                  * CB_COLOR0_BASE before this register we will report
1046                  * error. Old userspace always set CB_COLOR0_BASE
1047                  * before any of this.
1048                  */
1049         case R_0280E0_CB_COLOR0_FRAG:
1050         case R_0280E4_CB_COLOR1_FRAG:
1051         case R_0280E8_CB_COLOR2_FRAG:
1052         case R_0280EC_CB_COLOR3_FRAG:
1053         case R_0280F0_CB_COLOR4_FRAG:
1054         case R_0280F4_CB_COLOR5_FRAG:
1055         case R_0280F8_CB_COLOR6_FRAG:
1056         case R_0280FC_CB_COLOR7_FRAG:
1057                 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1058                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1059                         if (!track->cb_color_base_last[tmp]) {
1060                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1061                                 return -EINVAL;
1062                         }
1063                         ib[idx] = track->cb_color_base_last[tmp];
1064                         track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1065                 } else {
1066                         r = r600_cs_packet_next_reloc(p, &reloc);
1067                         if (r) {
1068                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1069                                 return -EINVAL;
1070                         }
1071                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1072                         track->cb_color_frag_bo[tmp] = reloc->robj;
1073                 }
1074                 break;
1075         case R_0280C0_CB_COLOR0_TILE:
1076         case R_0280C4_CB_COLOR1_TILE:
1077         case R_0280C8_CB_COLOR2_TILE:
1078         case R_0280CC_CB_COLOR3_TILE:
1079         case R_0280D0_CB_COLOR4_TILE:
1080         case R_0280D4_CB_COLOR5_TILE:
1081         case R_0280D8_CB_COLOR6_TILE:
1082         case R_0280DC_CB_COLOR7_TILE:
1083                 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1084                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1085                         if (!track->cb_color_base_last[tmp]) {
1086                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1087                                 return -EINVAL;
1088                         }
1089                         ib[idx] = track->cb_color_base_last[tmp];
1090                         track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1091                 } else {
1092                         r = r600_cs_packet_next_reloc(p, &reloc);
1093                         if (r) {
1094                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1095                                 return -EINVAL;
1096                         }
1097                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1098                         track->cb_color_tile_bo[tmp] = reloc->robj;
1099                 }
1100                 break;
1101         case CB_COLOR0_BASE:
1102         case CB_COLOR1_BASE:
1103         case CB_COLOR2_BASE:
1104         case CB_COLOR3_BASE:
1105         case CB_COLOR4_BASE:
1106         case CB_COLOR5_BASE:
1107         case CB_COLOR6_BASE:
1108         case CB_COLOR7_BASE:
1109                 r = r600_cs_packet_next_reloc(p, &reloc);
1110                 if (r) {
1111                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1112                                         "0x%04X\n", reg);
1113                         return -EINVAL;
1114                 }
1115                 tmp = (reg - CB_COLOR0_BASE) / 4;
1116                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1117                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1118                 track->cb_color_base_last[tmp] = ib[idx];
1119                 track->cb_color_bo[tmp] = reloc->robj;
1120                 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1121                 break;
1122         case DB_DEPTH_BASE:
1123                 r = r600_cs_packet_next_reloc(p, &reloc);
1124                 if (r) {
1125                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1126                                         "0x%04X\n", reg);
1127                         return -EINVAL;
1128                 }
1129                 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1130                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1131                 track->db_bo = reloc->robj;
1132                 track->db_bo_mc = reloc->lobj.gpu_offset;
1133                 break;
1134         case DB_HTILE_DATA_BASE:
1135         case SQ_PGM_START_FS:
1136         case SQ_PGM_START_ES:
1137         case SQ_PGM_START_VS:
1138         case SQ_PGM_START_GS:
1139         case SQ_PGM_START_PS:
1140         case SQ_ALU_CONST_CACHE_GS_0:
1141         case SQ_ALU_CONST_CACHE_GS_1:
1142         case SQ_ALU_CONST_CACHE_GS_2:
1143         case SQ_ALU_CONST_CACHE_GS_3:
1144         case SQ_ALU_CONST_CACHE_GS_4:
1145         case SQ_ALU_CONST_CACHE_GS_5:
1146         case SQ_ALU_CONST_CACHE_GS_6:
1147         case SQ_ALU_CONST_CACHE_GS_7:
1148         case SQ_ALU_CONST_CACHE_GS_8:
1149         case SQ_ALU_CONST_CACHE_GS_9:
1150         case SQ_ALU_CONST_CACHE_GS_10:
1151         case SQ_ALU_CONST_CACHE_GS_11:
1152         case SQ_ALU_CONST_CACHE_GS_12:
1153         case SQ_ALU_CONST_CACHE_GS_13:
1154         case SQ_ALU_CONST_CACHE_GS_14:
1155         case SQ_ALU_CONST_CACHE_GS_15:
1156         case SQ_ALU_CONST_CACHE_PS_0:
1157         case SQ_ALU_CONST_CACHE_PS_1:
1158         case SQ_ALU_CONST_CACHE_PS_2:
1159         case SQ_ALU_CONST_CACHE_PS_3:
1160         case SQ_ALU_CONST_CACHE_PS_4:
1161         case SQ_ALU_CONST_CACHE_PS_5:
1162         case SQ_ALU_CONST_CACHE_PS_6:
1163         case SQ_ALU_CONST_CACHE_PS_7:
1164         case SQ_ALU_CONST_CACHE_PS_8:
1165         case SQ_ALU_CONST_CACHE_PS_9:
1166         case SQ_ALU_CONST_CACHE_PS_10:
1167         case SQ_ALU_CONST_CACHE_PS_11:
1168         case SQ_ALU_CONST_CACHE_PS_12:
1169         case SQ_ALU_CONST_CACHE_PS_13:
1170         case SQ_ALU_CONST_CACHE_PS_14:
1171         case SQ_ALU_CONST_CACHE_PS_15:
1172         case SQ_ALU_CONST_CACHE_VS_0:
1173         case SQ_ALU_CONST_CACHE_VS_1:
1174         case SQ_ALU_CONST_CACHE_VS_2:
1175         case SQ_ALU_CONST_CACHE_VS_3:
1176         case SQ_ALU_CONST_CACHE_VS_4:
1177         case SQ_ALU_CONST_CACHE_VS_5:
1178         case SQ_ALU_CONST_CACHE_VS_6:
1179         case SQ_ALU_CONST_CACHE_VS_7:
1180         case SQ_ALU_CONST_CACHE_VS_8:
1181         case SQ_ALU_CONST_CACHE_VS_9:
1182         case SQ_ALU_CONST_CACHE_VS_10:
1183         case SQ_ALU_CONST_CACHE_VS_11:
1184         case SQ_ALU_CONST_CACHE_VS_12:
1185         case SQ_ALU_CONST_CACHE_VS_13:
1186         case SQ_ALU_CONST_CACHE_VS_14:
1187         case SQ_ALU_CONST_CACHE_VS_15:
1188                 r = r600_cs_packet_next_reloc(p, &reloc);
1189                 if (r) {
1190                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1191                                         "0x%04X\n", reg);
1192                         return -EINVAL;
1193                 }
1194                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1195                 break;
1196         default:
1197                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1198                 return -EINVAL;
1199         }
1200         return 0;
1201 }
1202
1203 static inline unsigned mip_minify(unsigned size, unsigned level)
1204 {
1205         unsigned val;
1206
1207         val = max(1U, size >> level);
1208         if (level > 0)
1209                 val = roundup_pow_of_two(val);
1210         return val;
1211 }
1212
1213 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1214                               unsigned w0, unsigned h0, unsigned d0, unsigned format,
1215                               unsigned block_align, unsigned height_align, unsigned base_align,
1216                               unsigned *l0_size, unsigned *mipmap_size)
1217 {
1218         unsigned offset, i, level;
1219         unsigned width, height, depth, size;
1220         unsigned blocksize;
1221         unsigned nbx, nby;
1222         unsigned nlevels = llevel - blevel + 1;
1223
1224         *l0_size = -1;
1225         blocksize = fmt_get_blocksize(format);
1226
1227         w0 = mip_minify(w0, 0);
1228         h0 = mip_minify(h0, 0);
1229         d0 = mip_minify(d0, 0);
1230         for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1231                 width = mip_minify(w0, i);
1232                 nbx = fmt_get_nblocksx(format, width);
1233
1234                 nbx = round_up(nbx, block_align);
1235
1236                 height = mip_minify(h0, i);
1237                 nby = fmt_get_nblocksy(format, height);
1238                 nby = round_up(nby, height_align);
1239
1240                 depth = mip_minify(d0, i);
1241
1242                 size = nbx * nby * blocksize;
1243                 if (nfaces)
1244                         size *= nfaces;
1245                 else
1246                         size *= depth;
1247
1248                 if (i == 0)
1249                         *l0_size = size;
1250
1251                 if (i == 0 || i == 1)
1252                         offset = round_up(offset, base_align);
1253
1254                 offset += size;
1255         }
1256         *mipmap_size = offset;
1257         if (llevel == 0)
1258                 *mipmap_size = *l0_size;
1259         if (!blevel)
1260                 *mipmap_size -= *l0_size;
1261 }
1262
1263 /**
1264  * r600_check_texture_resource() - check if register is authorized or not
1265  * @p: parser structure holding parsing context
1266  * @idx: index into the cs buffer
1267  * @texture: texture's bo structure
1268  * @mipmap: mipmap's bo structure
1269  *
1270  * This function will check that the resource has valid field and that
1271  * the texture and mipmap bo object are big enough to cover this resource.
1272  */
1273 static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
1274                                               struct radeon_bo *texture,
1275                                               struct radeon_bo *mipmap,
1276                                               u64 base_offset,
1277                                               u64 mip_offset,
1278                                               u32 tiling_flags)
1279 {
1280         struct r600_cs_track *track = p->track;
1281         u32 nfaces, llevel, blevel, w0, h0, d0;
1282         u32 word0, word1, l0_size, mipmap_size;
1283         u32 height_align, pitch, pitch_align, depth_align;
1284         u32 array, barray, larray;
1285         u64 base_align;
1286         struct array_mode_checker array_check;
1287         u32 format;
1288
1289         /* on legacy kernel we don't perform advanced check */
1290         if (p->rdev == NULL)
1291                 return 0;
1292
1293         /* convert to bytes */
1294         base_offset <<= 8;
1295         mip_offset <<= 8;
1296
1297         word0 = radeon_get_ib_value(p, idx + 0);
1298         if (tiling_flags & RADEON_TILING_MACRO)
1299                 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1300         else if (tiling_flags & RADEON_TILING_MICRO)
1301                 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1302         word1 = radeon_get_ib_value(p, idx + 1);
1303         w0 = G_038000_TEX_WIDTH(word0) + 1;
1304         h0 = G_038004_TEX_HEIGHT(word1) + 1;
1305         d0 = G_038004_TEX_DEPTH(word1);
1306         nfaces = 1;
1307         switch (G_038000_DIM(word0)) {
1308         case V_038000_SQ_TEX_DIM_1D:
1309         case V_038000_SQ_TEX_DIM_2D:
1310         case V_038000_SQ_TEX_DIM_3D:
1311                 break;
1312         case V_038000_SQ_TEX_DIM_CUBEMAP:
1313                 if (p->family >= CHIP_RV770)
1314                         nfaces = 8;
1315                 else
1316                         nfaces = 6;
1317                 break;
1318         case V_038000_SQ_TEX_DIM_1D_ARRAY:
1319         case V_038000_SQ_TEX_DIM_2D_ARRAY:
1320                 array = 1;
1321                 break;
1322         case V_038000_SQ_TEX_DIM_2D_MSAA:
1323         case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1324         default:
1325                 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1326                 return -EINVAL;
1327         }
1328         format = G_038004_DATA_FORMAT(word1);
1329         if (!fmt_is_valid_texture(format)) {
1330                 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1331                          __func__, __LINE__, format);
1332                 return -EINVAL;
1333         }
1334
1335         /* pitch in texels */
1336         pitch = (G_038000_PITCH(word0) + 1) * 8;
1337         array_check.array_mode = G_038000_TILE_MODE(word0);
1338         array_check.group_size = track->group_size;
1339         array_check.nbanks = track->nbanks;
1340         array_check.npipes = track->npipes;
1341         array_check.nsamples = 1;
1342         array_check.blocksize = fmt_get_blocksize(format);
1343         if (r600_get_array_mode_alignment(&array_check,
1344                                           &pitch_align, &height_align, &depth_align, &base_align)) {
1345                 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1346                          __func__, __LINE__, G_038000_TILE_MODE(word0));
1347                 return -EINVAL;
1348         }
1349
1350         /* XXX check height as well... */
1351
1352         if (!IS_ALIGNED(pitch, pitch_align)) {
1353                 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1354                          __func__, __LINE__, pitch);
1355                 return -EINVAL;
1356         }
1357         if (!IS_ALIGNED(base_offset, base_align)) {
1358                 dev_warn(p->dev, "%s:%d tex base offset (0x%llx) invalid\n",
1359                          __func__, __LINE__, base_offset);
1360                 return -EINVAL;
1361         }
1362         if (!IS_ALIGNED(mip_offset, base_align)) {
1363                 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx) invalid\n",
1364                          __func__, __LINE__, mip_offset);
1365                 return -EINVAL;
1366         }
1367
1368         word0 = radeon_get_ib_value(p, idx + 4);
1369         word1 = radeon_get_ib_value(p, idx + 5);
1370         blevel = G_038010_BASE_LEVEL(word0);
1371         llevel = G_038014_LAST_LEVEL(word1);
1372         if (array == 1) {
1373                 barray = G_038014_BASE_ARRAY(word1);
1374                 larray = G_038014_LAST_ARRAY(word1);
1375
1376                 nfaces = larray - barray + 1;
1377         }
1378         r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format,
1379                           pitch_align, height_align, base_align,
1380                           &l0_size, &mipmap_size);
1381         /* using get ib will give us the offset into the texture bo */
1382         word0 = radeon_get_ib_value(p, idx + 2) << 8;
1383         if ((l0_size + word0) > radeon_bo_size(texture)) {
1384                 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1385                         w0, h0, format, word0, l0_size, radeon_bo_size(texture));
1386                 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
1387                 return -EINVAL;
1388         }
1389         /* using get ib will give us the offset into the mipmap bo */
1390         word0 = radeon_get_ib_value(p, idx + 3) << 8;
1391         if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
1392                 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1393                   w0, h0, format, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));*/
1394         }
1395         return 0;
1396 }
1397
1398 static int r600_packet3_check(struct radeon_cs_parser *p,
1399                                 struct radeon_cs_packet *pkt)
1400 {
1401         struct radeon_cs_reloc *reloc;
1402         struct r600_cs_track *track;
1403         volatile u32 *ib;
1404         unsigned idx;
1405         unsigned i;
1406         unsigned start_reg, end_reg, reg;
1407         int r;
1408         u32 idx_value;
1409
1410         track = (struct r600_cs_track *)p->track;
1411         ib = p->ib->ptr;
1412         idx = pkt->idx + 1;
1413         idx_value = radeon_get_ib_value(p, idx);
1414
1415         switch (pkt->opcode) {
1416         case PACKET3_START_3D_CMDBUF:
1417                 if (p->family >= CHIP_RV770 || pkt->count) {
1418                         DRM_ERROR("bad START_3D\n");
1419                         return -EINVAL;
1420                 }
1421                 break;
1422         case PACKET3_CONTEXT_CONTROL:
1423                 if (pkt->count != 1) {
1424                         DRM_ERROR("bad CONTEXT_CONTROL\n");
1425                         return -EINVAL;
1426                 }
1427                 break;
1428         case PACKET3_INDEX_TYPE:
1429         case PACKET3_NUM_INSTANCES:
1430                 if (pkt->count) {
1431                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1432                         return -EINVAL;
1433                 }
1434                 break;
1435         case PACKET3_DRAW_INDEX:
1436                 if (pkt->count != 3) {
1437                         DRM_ERROR("bad DRAW_INDEX\n");
1438                         return -EINVAL;
1439                 }
1440                 r = r600_cs_packet_next_reloc(p, &reloc);
1441                 if (r) {
1442                         DRM_ERROR("bad DRAW_INDEX\n");
1443                         return -EINVAL;
1444                 }
1445                 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1446                 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1447                 r = r600_cs_track_check(p);
1448                 if (r) {
1449                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1450                         return r;
1451                 }
1452                 break;
1453         case PACKET3_DRAW_INDEX_AUTO:
1454                 if (pkt->count != 1) {
1455                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1456                         return -EINVAL;
1457                 }
1458                 r = r600_cs_track_check(p);
1459                 if (r) {
1460                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1461                         return r;
1462                 }
1463                 break;
1464         case PACKET3_DRAW_INDEX_IMMD_BE:
1465         case PACKET3_DRAW_INDEX_IMMD:
1466                 if (pkt->count < 2) {
1467                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1468                         return -EINVAL;
1469                 }
1470                 r = r600_cs_track_check(p);
1471                 if (r) {
1472                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1473                         return r;
1474                 }
1475                 break;
1476         case PACKET3_WAIT_REG_MEM:
1477                 if (pkt->count != 5) {
1478                         DRM_ERROR("bad WAIT_REG_MEM\n");
1479                         return -EINVAL;
1480                 }
1481                 /* bit 4 is reg (0) or mem (1) */
1482                 if (idx_value & 0x10) {
1483                         r = r600_cs_packet_next_reloc(p, &reloc);
1484                         if (r) {
1485                                 DRM_ERROR("bad WAIT_REG_MEM\n");
1486                                 return -EINVAL;
1487                         }
1488                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1489                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1490                 }
1491                 break;
1492         case PACKET3_SURFACE_SYNC:
1493                 if (pkt->count != 3) {
1494                         DRM_ERROR("bad SURFACE_SYNC\n");
1495                         return -EINVAL;
1496                 }
1497                 /* 0xffffffff/0x0 is flush all cache flag */
1498                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1499                     radeon_get_ib_value(p, idx + 2) != 0) {
1500                         r = r600_cs_packet_next_reloc(p, &reloc);
1501                         if (r) {
1502                                 DRM_ERROR("bad SURFACE_SYNC\n");
1503                                 return -EINVAL;
1504                         }
1505                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1506                 }
1507                 break;
1508         case PACKET3_EVENT_WRITE:
1509                 if (pkt->count != 2 && pkt->count != 0) {
1510                         DRM_ERROR("bad EVENT_WRITE\n");
1511                         return -EINVAL;
1512                 }
1513                 if (pkt->count) {
1514                         r = r600_cs_packet_next_reloc(p, &reloc);
1515                         if (r) {
1516                                 DRM_ERROR("bad EVENT_WRITE\n");
1517                                 return -EINVAL;
1518                         }
1519                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1520                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1521                 }
1522                 break;
1523         case PACKET3_EVENT_WRITE_EOP:
1524                 if (pkt->count != 4) {
1525                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
1526                         return -EINVAL;
1527                 }
1528                 r = r600_cs_packet_next_reloc(p, &reloc);
1529                 if (r) {
1530                         DRM_ERROR("bad EVENT_WRITE\n");
1531                         return -EINVAL;
1532                 }
1533                 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1534                 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1535                 break;
1536         case PACKET3_SET_CONFIG_REG:
1537                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1538                 end_reg = 4 * pkt->count + start_reg - 4;
1539                 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1540                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1541                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1542                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1543                         return -EINVAL;
1544                 }
1545                 for (i = 0; i < pkt->count; i++) {
1546                         reg = start_reg + (4 * i);
1547                         r = r600_cs_check_reg(p, reg, idx+1+i);
1548                         if (r)
1549                                 return r;
1550                 }
1551                 break;
1552         case PACKET3_SET_CONTEXT_REG:
1553                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1554                 end_reg = 4 * pkt->count + start_reg - 4;
1555                 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1556                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1557                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1558                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1559                         return -EINVAL;
1560                 }
1561                 for (i = 0; i < pkt->count; i++) {
1562                         reg = start_reg + (4 * i);
1563                         r = r600_cs_check_reg(p, reg, idx+1+i);
1564                         if (r)
1565                                 return r;
1566                 }
1567                 break;
1568         case PACKET3_SET_RESOURCE:
1569                 if (pkt->count % 7) {
1570                         DRM_ERROR("bad SET_RESOURCE\n");
1571                         return -EINVAL;
1572                 }
1573                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1574                 end_reg = 4 * pkt->count + start_reg - 4;
1575                 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1576                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
1577                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
1578                         DRM_ERROR("bad SET_RESOURCE\n");
1579                         return -EINVAL;
1580                 }
1581                 for (i = 0; i < (pkt->count / 7); i++) {
1582                         struct radeon_bo *texture, *mipmap;
1583                         u32 size, offset, base_offset, mip_offset;
1584
1585                         switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1586                         case SQ_TEX_VTX_VALID_TEXTURE:
1587                                 /* tex base */
1588                                 r = r600_cs_packet_next_reloc(p, &reloc);
1589                                 if (r) {
1590                                         DRM_ERROR("bad SET_RESOURCE\n");
1591                                         return -EINVAL;
1592                                 }
1593                                 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1594                                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1595                                         ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1596                                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1597                                         ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1598                                 texture = reloc->robj;
1599                                 /* tex mip base */
1600                                 r = r600_cs_packet_next_reloc(p, &reloc);
1601                                 if (r) {
1602                                         DRM_ERROR("bad SET_RESOURCE\n");
1603                                         return -EINVAL;
1604                                 }
1605                                 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1606                                 mipmap = reloc->robj;
1607                                 r = r600_check_texture_resource(p,  idx+(i*7)+1,
1608                                                                 texture, mipmap,
1609                                                                 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
1610                                                                 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
1611                                                                 reloc->lobj.tiling_flags);
1612                                 if (r)
1613                                         return r;
1614                                 ib[idx+1+(i*7)+2] += base_offset;
1615                                 ib[idx+1+(i*7)+3] += mip_offset;
1616                                 break;
1617                         case SQ_TEX_VTX_VALID_BUFFER:
1618                                 /* vtx base */
1619                                 r = r600_cs_packet_next_reloc(p, &reloc);
1620                                 if (r) {
1621                                         DRM_ERROR("bad SET_RESOURCE\n");
1622                                         return -EINVAL;
1623                                 }
1624                                 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1625                                 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
1626                                 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1627                                         /* force size to size of the buffer */
1628                                         dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
1629                                                  size + offset, radeon_bo_size(reloc->robj));
1630                                         ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1631                                 }
1632                                 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1633                                 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1634                                 break;
1635                         case SQ_TEX_VTX_INVALID_TEXTURE:
1636                         case SQ_TEX_VTX_INVALID_BUFFER:
1637                         default:
1638                                 DRM_ERROR("bad SET_RESOURCE\n");
1639                                 return -EINVAL;
1640                         }
1641                 }
1642                 break;
1643         case PACKET3_SET_ALU_CONST:
1644                 if (track->sq_config & DX9_CONSTS) {
1645                         start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1646                         end_reg = 4 * pkt->count + start_reg - 4;
1647                         if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1648                             (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1649                             (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1650                                 DRM_ERROR("bad SET_ALU_CONST\n");
1651                                 return -EINVAL;
1652                         }
1653                 }
1654                 break;
1655         case PACKET3_SET_BOOL_CONST:
1656                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
1657                 end_reg = 4 * pkt->count + start_reg - 4;
1658                 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
1659                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1660                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1661                         DRM_ERROR("bad SET_BOOL_CONST\n");
1662                         return -EINVAL;
1663                 }
1664                 break;
1665         case PACKET3_SET_LOOP_CONST:
1666                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
1667                 end_reg = 4 * pkt->count + start_reg - 4;
1668                 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
1669                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1670                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1671                         DRM_ERROR("bad SET_LOOP_CONST\n");
1672                         return -EINVAL;
1673                 }
1674                 break;
1675         case PACKET3_SET_CTL_CONST:
1676                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
1677                 end_reg = 4 * pkt->count + start_reg - 4;
1678                 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
1679                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1680                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1681                         DRM_ERROR("bad SET_CTL_CONST\n");
1682                         return -EINVAL;
1683                 }
1684                 break;
1685         case PACKET3_SET_SAMPLER:
1686                 if (pkt->count % 3) {
1687                         DRM_ERROR("bad SET_SAMPLER\n");
1688                         return -EINVAL;
1689                 }
1690                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
1691                 end_reg = 4 * pkt->count + start_reg - 4;
1692                 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
1693                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
1694                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
1695                         DRM_ERROR("bad SET_SAMPLER\n");
1696                         return -EINVAL;
1697                 }
1698                 break;
1699         case PACKET3_SURFACE_BASE_UPDATE:
1700                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
1701                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1702                         return -EINVAL;
1703                 }
1704                 if (pkt->count) {
1705                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1706                         return -EINVAL;
1707                 }
1708                 break;
1709         case PACKET3_NOP:
1710                 break;
1711         default:
1712                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1713                 return -EINVAL;
1714         }
1715         return 0;
1716 }
1717
1718 int r600_cs_parse(struct radeon_cs_parser *p)
1719 {
1720         struct radeon_cs_packet pkt;
1721         struct r600_cs_track *track;
1722         int r;
1723
1724         if (p->track == NULL) {
1725                 /* initialize tracker, we are in kms */
1726                 track = kzalloc(sizeof(*track), GFP_KERNEL);
1727                 if (track == NULL)
1728                         return -ENOMEM;
1729                 r600_cs_track_init(track);
1730                 if (p->rdev->family < CHIP_RV770) {
1731                         track->npipes = p->rdev->config.r600.tiling_npipes;
1732                         track->nbanks = p->rdev->config.r600.tiling_nbanks;
1733                         track->group_size = p->rdev->config.r600.tiling_group_size;
1734                 } else if (p->rdev->family <= CHIP_RV740) {
1735                         track->npipes = p->rdev->config.rv770.tiling_npipes;
1736                         track->nbanks = p->rdev->config.rv770.tiling_nbanks;
1737                         track->group_size = p->rdev->config.rv770.tiling_group_size;
1738                 }
1739                 p->track = track;
1740         }
1741         do {
1742                 r = r600_cs_packet_parse(p, &pkt, p->idx);
1743                 if (r) {
1744                         kfree(p->track);
1745                         p->track = NULL;
1746                         return r;
1747                 }
1748                 p->idx += pkt.count + 2;
1749                 switch (pkt.type) {
1750                 case PACKET_TYPE0:
1751                         r = r600_cs_parse_packet0(p, &pkt);
1752                         break;
1753                 case PACKET_TYPE2:
1754                         break;
1755                 case PACKET_TYPE3:
1756                         r = r600_packet3_check(p, &pkt);
1757                         break;
1758                 default:
1759                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1760                         kfree(p->track);
1761                         p->track = NULL;
1762                         return -EINVAL;
1763                 }
1764                 if (r) {
1765                         kfree(p->track);
1766                         p->track = NULL;
1767                         return r;
1768                 }
1769         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1770 #if 0
1771         for (r = 0; r < p->ib->length_dw; r++) {
1772                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
1773                 mdelay(1);
1774         }
1775 #endif
1776         kfree(p->track);
1777         p->track = NULL;
1778         return 0;
1779 }
1780
1781 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
1782 {
1783         if (p->chunk_relocs_idx == -1) {
1784                 return 0;
1785         }
1786         p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
1787         if (p->relocs == NULL) {
1788                 return -ENOMEM;
1789         }
1790         return 0;
1791 }
1792
1793 /**
1794  * cs_parser_fini() - clean parser states
1795  * @parser:     parser structure holding parsing context.
1796  * @error:      error number
1797  *
1798  * If error is set than unvalidate buffer, otherwise just free memory
1799  * used by parsing context.
1800  **/
1801 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
1802 {
1803         unsigned i;
1804
1805         kfree(parser->relocs);
1806         for (i = 0; i < parser->nchunks; i++) {
1807                 kfree(parser->chunks[i].kdata);
1808                 kfree(parser->chunks[i].kpage[0]);
1809                 kfree(parser->chunks[i].kpage[1]);
1810         }
1811         kfree(parser->chunks);
1812         kfree(parser->chunks_array);
1813 }
1814
1815 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
1816                         unsigned family, u32 *ib, int *l)
1817 {
1818         struct radeon_cs_parser parser;
1819         struct radeon_cs_chunk *ib_chunk;
1820         struct radeon_ib fake_ib;
1821         struct r600_cs_track *track;
1822         int r;
1823
1824         /* initialize tracker */
1825         track = kzalloc(sizeof(*track), GFP_KERNEL);
1826         if (track == NULL)
1827                 return -ENOMEM;
1828         r600_cs_track_init(track);
1829         r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
1830         /* initialize parser */
1831         memset(&parser, 0, sizeof(struct radeon_cs_parser));
1832         parser.filp = filp;
1833         parser.dev = &dev->pdev->dev;
1834         parser.rdev = NULL;
1835         parser.family = family;
1836         parser.ib = &fake_ib;
1837         parser.track = track;
1838         fake_ib.ptr = ib;
1839         r = radeon_cs_parser_init(&parser, data);
1840         if (r) {
1841                 DRM_ERROR("Failed to initialize parser !\n");
1842                 r600_cs_parser_fini(&parser, r);
1843                 return r;
1844         }
1845         r = r600_cs_parser_relocs_legacy(&parser);
1846         if (r) {
1847                 DRM_ERROR("Failed to parse relocation !\n");
1848                 r600_cs_parser_fini(&parser, r);
1849                 return r;
1850         }
1851         /* Copy the packet into the IB, the parser will read from the
1852          * input memory (cached) and write to the IB (which can be
1853          * uncached). */
1854         ib_chunk = &parser.chunks[parser.chunk_ib_idx];
1855         parser.ib->length_dw = ib_chunk->length_dw;
1856         *l = parser.ib->length_dw;
1857         r = r600_cs_parse(&parser);
1858         if (r) {
1859                 DRM_ERROR("Invalid command stream !\n");
1860                 r600_cs_parser_fini(&parser, r);
1861                 return r;
1862         }
1863         r = radeon_cs_finish_pages(&parser);
1864         if (r) {
1865                 DRM_ERROR("Invalid command stream !\n");
1866                 r600_cs_parser_fini(&parser, r);
1867                 return r;
1868         }
1869         r600_cs_parser_fini(&parser, r);
1870         return r;
1871 }
1872
1873 void r600_cs_legacy_init(void)
1874 {
1875         r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
1876 }