drivers/gpu/drm/radeon/r600_blit_shaders.c

   1 /*
   2  * Copyright 2009 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  */
  26
  27 #include <linux/types.h>
  28 #include <linux/kernel.h>
  29
  30 /*
  31  * R6xx+ cards need to use the 3D engine to blit data which requires
  32  * quite a bit of hw state setup.  Rather than pull the whole 3D driver
  33  * (which normally generates the 3D state) into the DRM, we opt to use
  34  * statically generated state tables.  The regsiter state and shaders
  35  * were hand generated to support blitting functionality.  See the 3D
  36  * driver or documentation for descriptions of the registers and
  37  * shader instructions.
  38  */
  39
  40 const u32 r6xx_default_state[] =
  41 {
  42         0xc0002400, /* START_3D_CMDBUF */
  43         0x00000000,
  44
  45         0xc0012800, /* CONTEXT_CONTROL */
  46         0x80000000,
  47         0x80000000,
  48
  49         0xc0016800,
  50         0x00000010,
  51         0x00008000, /* WAIT_UNTIL */
  52
  53         0xc0016800,
  54         0x00000542,
  55         0x07000003, /* TA_CNTL_AUX */
  56
  57         0xc0016800,
  58         0x000005c5,
  59         0x00000000, /* VC_ENHANCE */
  60
  61         0xc0016800,
  62         0x00000363,
  63         0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
  64
  65         0xc0016800,
  66         0x0000060c,
  67         0x82000000, /* DB_DEBUG */
  68
  69         0xc0016800,
  70         0x0000060e,
  71         0x01020204, /* DB_WATERMARKS */
  72
  73         0xc0026f00,
  74         0x00000000,
  75         0x00000000, /* SQ_VTX_BASE_VTX_LOC */
  76         0x00000000, /* SQ_VTX_START_INST_LOC */
  77
  78         0xc0096900,
  79         0x0000022a,
  80         0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
  81         0x00000000,
  82         0x00000000,
  83         0x00000000,
  84         0x00000000,
  85         0x00000000,
  86         0x00000000,
  87         0x00000000,
  88         0x00000000,
  89
  90         0xc0016900,
  91         0x00000004,
  92         0x00000000, /* DB_DEPTH_INFO */
  93
  94         0xc0026900,
  95         0x0000000a,
  96         0x00000000, /* DB_STENCIL_CLEAR */
  97         0x00000000, /* DB_DEPTH_CLEAR */
  98
  99         0xc0016900,
 100         0x00000200,
 101         0x00000000, /* DB_DEPTH_CONTROL */
 102
 103         0xc0026900,
 104         0x00000343,
 105         0x00000060, /* DB_RENDER_CONTROL */
 106         0x00000040, /* DB_RENDER_OVERRIDE */
 107
 108         0xc0016900,
 109         0x00000351,
 110         0x0000aa00, /* DB_ALPHA_TO_MASK */
 111
 112         0xc00f6900,
 113         0x00000100,
 114         0x00000800, /* VGT_MAX_VTX_INDX */
 115         0x00000000, /* VGT_MIN_VTX_INDX */
 116         0x00000000, /* VGT_INDX_OFFSET */
 117         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
 118         0x00000000, /* SX_ALPHA_TEST_CONTROL */
 119         0x00000000, /* CB_BLEND_RED */
 120         0x00000000,
 121         0x00000000,
 122         0x00000000,
 123         0x00000000, /* CB_FOG_RED */
 124         0x00000000,
 125         0x00000000,
 126         0x00000000, /* DB_STENCILREFMASK */
 127         0x00000000, /* DB_STENCILREFMASK_BF */
 128         0x00000000, /* SX_ALPHA_REF */
 129
 130         0xc0066900,
 131         0x0000010f,
 132         0x00000000, /* PA_CL_VPORT_XSCALE */
 133         0x00000000,
 134         0x00000000,
 135         0x00000000,
 136         0x00000000,
 137         0x00000000,
 138
 139         0xc0046900,
 140         0x0000030c,
 141         0x01000000, /* CB_CLRCMP_CNTL */
 142         0x00000000,
 143         0x00000000,
 144         0x00000000,
 145
 146         0xc0046900,
 147         0x00000048,
 148         0x3f800000, /* CB_CLEAR_RED */
 149         0x00000000,
 150         0x3f800000,
 151         0x3f800000,
 152
 153         0xc0016900,
 154         0x00000080,
 155         0x00000000, /* PA_SC_WINDOW_OFFSET */
 156
 157         0xc00a6900,
 158         0x00000083,
 159         0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
 160         0x00000000, /* PA_SC_CLIPRECT_0_TL */
 161         0x20002000,
 162         0x00000000,
 163         0x20002000,
 164         0x00000000,
 165         0x20002000,
 166         0x00000000,
 167         0x20002000,
 168         0x00000000, /* PA_SC_EDGERULE */
 169
 170         0xc0406900,
 171         0x00000094,
 172         0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
 173         0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
 174         0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
 175         0x20002000,
 176         0x80000000,
 177         0x20002000,
 178         0x80000000,
 179         0x20002000,
 180         0x80000000,
 181         0x20002000,
 182         0x80000000,
 183         0x20002000,
 184         0x80000000,
 185         0x20002000,
 186         0x80000000,
 187         0x20002000,
 188         0x80000000,
 189         0x20002000,
 190         0x80000000,
 191         0x20002000,
 192         0x80000000,
 193         0x20002000,
 194         0x80000000,
 195         0x20002000,
 196         0x80000000,
 197         0x20002000,
 198         0x80000000,
 199         0x20002000,
 200         0x80000000,
 201         0x20002000,
 202         0x80000000,
 203         0x20002000,
 204         0x00000000, /* PA_SC_VPORT_ZMIN_0 */
 205         0x3f800000,
 206         0x00000000,
 207         0x3f800000,
 208         0x00000000,
 209         0x3f800000,
 210         0x00000000,
 211         0x3f800000,
 212         0x00000000,
 213         0x3f800000,
 214         0x00000000,
 215         0x3f800000,
 216         0x00000000,
 217         0x3f800000,
 218         0x00000000,
 219         0x3f800000,
 220         0x00000000,
 221         0x3f800000,
 222         0x00000000,
 223         0x3f800000,
 224         0x00000000,
 225         0x3f800000,
 226         0x00000000,
 227         0x3f800000,
 228         0x00000000,
 229         0x3f800000,
 230         0x00000000,
 231         0x3f800000,
 232         0x00000000,
 233         0x3f800000,
 234         0x00000000,
 235         0x3f800000,
 236
 237         0xc0026900,
 238         0x00000292,
 239         0x00000000, /* PA_SC_MPASS_PS_CNTL */
 240         0x00004010, /* PA_SC_MODE_CNTL */
 241
 242         0xc0096900,
 243         0x00000300,
 244         0x00000000, /* PA_SC_LINE_CNTL */
 245         0x00000000, /* PA_SC_AA_CONFIG */
 246         0x0000002d, /* PA_SU_VTX_CNTL */
 247         0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
 248         0x3f800000,
 249         0x3f800000,
 250         0x3f800000,
 251         0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
 252         0x00000000,
 253
 254         0xc0016900,
 255         0x00000312,
 256         0xffffffff, /* PA_SC_AA_MASK */
 257
 258         0xc0066900,
 259         0x0000037e,
 260         0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
 261         0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
 262         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
 263         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
 264         0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
 265         0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
 266
 267         0xc0046900,
 268         0x000001b6,
 269         0x00000000, /* SPI_INPUT_Z */
 270         0x00000000, /* SPI_FOG_CNTL */
 271         0x00000000, /* SPI_FOG_FUNC_SCALE */
 272         0x00000000, /* SPI_FOG_FUNC_BIAS */
 273
 274         0xc0016900,
 275         0x00000225,
 276         0x00000000, /* SQ_PGM_START_FS */
 277
 278         0xc0016900,
 279         0x00000229,
 280         0x00000000, /* SQ_PGM_RESOURCES_FS */
 281
 282         0xc0016900,
 283         0x00000237,
 284         0x00000000, /* SQ_PGM_CF_OFFSET_FS */
 285
 286         0xc0026900,
 287         0x000002a8,
 288         0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
 289         0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
 290
 291         0xc0116900,
 292         0x00000280,
 293         0x00000000, /* PA_SU_POINT_SIZE */
 294         0x00000000, /* PA_SU_POINT_MINMAX */
 295         0x00000008, /* PA_SU_LINE_CNTL */
 296         0x00000000, /* PA_SC_LINE_STIPPLE */
 297         0x00000000, /* VGT_OUTPUT_PATH_CNTL */
 298         0x00000000, /* VGT_HOS_CNTL */
 299         0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
 300         0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
 301         0x00000000, /* VGT_HOS_REUSE_DEPTH */
 302         0x00000000, /* VGT_GROUP_PRIM_TYPE */
 303         0x00000000, /* VGT_GROUP_FIRST_DECR */
 304         0x00000000, /* VGT_GROUP_DECR */
 305         0x00000000, /* VGT_GROUP_VECT_0_CNTL */
 306         0x00000000, /* VGT_GROUP_VECT_1_CNTL */
 307         0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
 308         0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
 309         0x00000000, /* VGT_GS_MODE */
 310
 311         0xc0016900,
 312         0x000002a1,
 313         0x00000000, /* VGT_PRIMITIVEID_EN */
 314
 315         0xc0016900,
 316         0x000002a5,
 317         0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
 318
 319         0xc0036900,
 320         0x000002ac,
 321         0x00000000, /* VGT_STRMOUT_EN */
 322         0x00000000, /* VGT_REUSE_OFF */
 323         0x00000000, /* VGT_VTX_CNT_EN */
 324
 325         0xc0016900,
 326         0x000002c8,
 327         0x00000000, /* VGT_STRMOUT_BUFFER_EN */
 328
 329         0xc0076900,
 330         0x00000202,
 331         0x00cc0000, /* CB_COLOR_CONTROL */
 332         0x00000210, /* DB_SHADER_CNTL */
 333         0x00010000, /* PA_CL_CLIP_CNTL */
 334         0x00000244, /* PA_SU_SC_MODE_CNTL */
 335         0x00000100, /* PA_CL_VTE_CNTL */
 336         0x00000000, /* PA_CL_VS_OUT_CNTL */
 337         0x00000000, /* PA_CL_NANINF_CNTL */
 338
 339         0xc0026900,
 340         0x0000008e,
 341         0x0000000f, /* CB_TARGET_MASK */
 342         0x0000000f, /* CB_SHADER_MASK */
 343
 344         0xc0016900,
 345         0x000001e8,
 346         0x00000001, /* CB_SHADER_CONTROL */
 347
 348         0xc0016900,
 349         0x00000185,
 350         0x00000000, /* SPI_VS_OUT_ID_0 */
 351
 352         0xc0016900,
 353         0x00000191,
 354         0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
 355
 356         0xc0056900,
 357         0x000001b1,
 358         0x00000000, /* SPI_VS_OUT_CONFIG */
 359         0x00000000, /* SPI_THREAD_GROUPING */
 360         0x00000001, /* SPI_PS_IN_CONTROL_0 */
 361         0x00000000, /* SPI_PS_IN_CONTROL_1 */
 362         0x00000000, /* SPI_INTERP_CONTROL_0 */
 363
 364         0xc0036e00, /* SET_SAMPLER */
 365         0x00000000,
 366         0x00000012,
 367         0x00000000,
 368         0x00000000,
 369 };
 370
 371 const u32 r7xx_default_state[] =
 372 {
 373         0xc0012800, /* CONTEXT_CONTROL */
 374         0x80000000,
 375         0x80000000,
 376
 377         0xc0016800,
 378         0x00000010,
 379         0x00008000, /* WAIT_UNTIL */
 380
 381         0xc0016800,
 382         0x00000542,
 383         0x07000002, /* TA_CNTL_AUX */
 384
 385         0xc0016800,
 386         0x000005c5,
 387         0x00000000, /* VC_ENHANCE */
 388
 389         0xc0016800,
 390         0x00000363,
 391         0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
 392
 393         0xc0016800,
 394         0x0000060c,
 395         0x00000000, /* DB_DEBUG */
 396
 397         0xc0016800,
 398         0x0000060e,
 399         0x00420204, /* DB_WATERMARKS */
 400
 401         0xc0026f00,
 402         0x00000000,
 403         0x00000000, /* SQ_VTX_BASE_VTX_LOC */
 404         0x00000000, /* SQ_VTX_START_INST_LOC */
 405
 406         0xc0096900,
 407         0x0000022a,
 408         0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
 409         0x00000000,
 410         0x00000000,
 411         0x00000000,
 412         0x00000000,
 413         0x00000000,
 414         0x00000000,
 415         0x00000000,
 416         0x00000000,
 417
 418         0xc0016900,
 419         0x00000004,
 420         0x00000000, /* DB_DEPTH_INFO */
 421
 422         0xc0026900,
 423         0x0000000a,
 424         0x00000000, /* DB_STENCIL_CLEAR */
 425         0x00000000, /* DB_DEPTH_CLEAR */
 426
 427         0xc0016900,
 428         0x00000200,
 429         0x00000000, /* DB_DEPTH_CONTROL */
 430
 431         0xc0026900,
 432         0x00000343,
 433         0x00000060, /* DB_RENDER_CONTROL */
 434         0x00000000, /* DB_RENDER_OVERRIDE */
 435
 436         0xc0016900,
 437         0x00000351,
 438         0x0000aa00, /* DB_ALPHA_TO_MASK */
 439
 440         0xc0096900,
 441         0x00000100,
 442         0x00000800, /* VGT_MAX_VTX_INDX */
 443         0x00000000, /* VGT_MIN_VTX_INDX */
 444         0x00000000, /* VGT_INDX_OFFSET */
 445         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
 446         0x00000000, /* SX_ALPHA_TEST_CONTROL */
 447         0x00000000, /* CB_BLEND_RED */
 448         0x00000000,
 449         0x00000000,
 450         0x00000000,
 451
 452         0xc0036900,
 453         0x0000010c,
 454         0x00000000, /* DB_STENCILREFMASK */
 455         0x00000000, /* DB_STENCILREFMASK_BF */
 456         0x00000000, /* SX_ALPHA_REF */
 457
 458         0xc0066900,
 459         0x0000010f,
 460         0x00000000, /* PA_CL_VPORT_XSCALE */
 461         0x00000000,
 462         0x00000000,
 463         0x00000000,
 464         0x00000000,
 465         0x00000000,
 466
 467         0xc0046900,
 468         0x0000030c, /* CB_CLRCMP_CNTL */
 469         0x01000000,
 470         0x00000000,
 471         0x00000000,
 472         0x00000000,
 473
 474         0xc0016900,
 475         0x00000080,
 476         0x00000000, /* PA_SC_WINDOW_OFFSET */
 477
 478         0xc00a6900,
 479         0x00000083,
 480         0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
 481         0x00000000, /* PA_SC_CLIPRECT_0_TL */
 482         0x20002000,
 483         0x00000000,
 484         0x20002000,
 485         0x00000000,
 486         0x20002000,
 487         0x00000000,
 488         0x20002000,
 489         0xaaaaaaaa, /* PA_SC_EDGERULE */
 490
 491         0xc0406900,
 492         0x00000094,
 493         0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
 494         0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
 495         0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
 496         0x20002000,
 497         0x80000000,
 498         0x20002000,
 499         0x80000000,
 500         0x20002000,
 501         0x80000000,
 502         0x20002000,
 503         0x80000000,
 504         0x20002000,
 505         0x80000000,
 506         0x20002000,
 507         0x80000000,
 508         0x20002000,
 509         0x80000000,
 510         0x20002000,
 511         0x80000000,
 512         0x20002000,
 513         0x80000000,
 514         0x20002000,
 515         0x80000000,
 516         0x20002000,
 517         0x80000000,
 518         0x20002000,
 519         0x80000000,
 520         0x20002000,
 521         0x80000000,
 522         0x20002000,
 523         0x80000000,
 524         0x20002000,
 525         0x00000000, /* PA_SC_VPORT_ZMIN_0 */
 526         0x3f800000,
 527         0x00000000,
 528         0x3f800000,
 529         0x00000000,
 530         0x3f800000,
 531         0x00000000,
 532         0x3f800000,
 533         0x00000000,
 534         0x3f800000,
 535         0x00000000,
 536         0x3f800000,
 537         0x00000000,
 538         0x3f800000,
 539         0x00000000,
 540         0x3f800000,
 541         0x00000000,
 542         0x3f800000,
 543         0x00000000,
 544         0x3f800000,
 545         0x00000000,
 546         0x3f800000,
 547         0x00000000,
 548         0x3f800000,
 549         0x00000000,
 550         0x3f800000,
 551         0x00000000,
 552         0x3f800000,
 553         0x00000000,
 554         0x3f800000,
 555         0x00000000,
 556         0x3f800000,
 557
 558         0xc0026900,
 559         0x00000292,
 560         0x00000000, /* PA_SC_MPASS_PS_CNTL */
 561         0x00514000, /* PA_SC_MODE_CNTL */
 562
 563         0xc0096900,
 564         0x00000300,
 565         0x00000000, /* PA_SC_LINE_CNTL */
 566         0x00000000, /* PA_SC_AA_CONFIG */
 567         0x0000002d, /* PA_SU_VTX_CNTL */
 568         0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
 569         0x3f800000,
 570         0x3f800000,
 571         0x3f800000,
 572         0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
 573         0x00000000,
 574
 575         0xc0016900,
 576         0x00000312,
 577         0xffffffff, /* PA_SC_AA_MASK */
 578
 579         0xc0066900,
 580         0x0000037e,
 581         0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
 582         0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
 583         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
 584         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
 585         0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
 586         0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
 587
 588         0xc0046900,
 589         0x000001b6,
 590         0x00000000, /* SPI_INPUT_Z */
 591         0x00000000, /* SPI_FOG_CNTL */
 592         0x00000000, /* SPI_FOG_FUNC_SCALE */
 593         0x00000000, /* SPI_FOG_FUNC_BIAS */
 594
 595         0xc0016900,
 596         0x00000225,
 597         0x00000000, /* SQ_PGM_START_FS */
 598
 599         0xc0016900,
 600         0x00000229,
 601         0x00000000, /* SQ_PGM_RESOURCES_FS */
 602
 603         0xc0016900,
 604         0x00000237,
 605         0x00000000, /* SQ_PGM_CF_OFFSET_FS */
 606
 607         0xc0026900,
 608         0x000002a8,
 609         0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
 610         0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
 611
 612         0xc0116900,
 613         0x00000280,
 614         0x00000000, /* PA_SU_POINT_SIZE */
 615         0x00000000, /* PA_SU_POINT_MINMAX */
 616         0x00000008, /* PA_SU_LINE_CNTL */
 617         0x00000000, /* PA_SC_LINE_STIPPLE */
 618         0x00000000, /* VGT_OUTPUT_PATH_CNTL */
 619         0x00000000, /* VGT_HOS_CNTL */
 620         0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
 621         0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
 622         0x00000000, /* VGT_HOS_REUSE_DEPTH */
 623         0x00000000, /* VGT_GROUP_PRIM_TYPE */
 624         0x00000000, /* VGT_GROUP_FIRST_DECR */
 625         0x00000000, /* VGT_GROUP_DECR */
 626         0x00000000, /* VGT_GROUP_VECT_0_CNTL */
 627         0x00000000, /* VGT_GROUP_VECT_1_CNTL */
 628         0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
 629         0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
 630         0x00000000, /* VGT_GS_MODE */
 631
 632         0xc0016900,
 633         0x000002a1,
 634         0x00000000, /* VGT_PRIMITIVEID_EN */
 635
 636         0xc0016900,
 637         0x000002a5,
 638         0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
 639
 640         0xc0036900,
 641         0x000002ac,
 642         0x00000000, /* VGT_STRMOUT_EN */
 643         0x00000000, /* VGT_REUSE_OFF */
 644         0x00000000, /* VGT_VTX_CNT_EN */
 645
 646         0xc0016900,
 647         0x000002c8,
 648         0x00000000, /* VGT_STRMOUT_BUFFER_EN */
 649
 650         0xc0076900,
 651         0x00000202,
 652         0x00cc0000, /* CB_COLOR_CONTROL */
 653         0x00000210, /* DB_SHADER_CNTL */
 654         0x00010000, /* PA_CL_CLIP_CNTL */
 655         0x00000244, /* PA_SU_SC_MODE_CNTL */
 656         0x00000100, /* PA_CL_VTE_CNTL */
 657         0x00000000, /* PA_CL_VS_OUT_CNTL */
 658         0x00000000, /* PA_CL_NANINF_CNTL */
 659
 660         0xc0026900,
 661         0x0000008e,
 662         0x0000000f, /* CB_TARGET_MASK */
 663         0x0000000f, /* CB_SHADER_MASK */
 664
 665         0xc0016900,
 666         0x000001e8,
 667         0x00000001, /* CB_SHADER_CONTROL */
 668
 669         0xc0016900,
 670         0x00000185,
 671         0x00000000, /* SPI_VS_OUT_ID_0 */
 672
 673         0xc0016900,
 674         0x00000191,
 675         0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
 676
 677         0xc0056900,
 678         0x000001b1,
 679         0x00000000, /* SPI_VS_OUT_CONFIG */
 680         0x00000001, /* SPI_THREAD_GROUPING */
 681         0x00000001, /* SPI_PS_IN_CONTROL_0 */
 682         0x00000000, /* SPI_PS_IN_CONTROL_1 */
 683         0x00000000, /* SPI_INTERP_CONTROL_0 */
 684
 685         0xc0036e00, /* SET_SAMPLER */
 686         0x00000000,
 687         0x00000012,
 688         0x00000000,
 689         0x00000000,
 690 };
 691
 692 /* same for r6xx/r7xx */
 693 const u32 r6xx_vs[] =
 694 {
 695         0x00000004,
 696         0x81000000,
 697         0x0000203c,
 698         0x94000b08,
 699         0x00004000,
 700         0x14200b1a,
 701         0x00000000,
 702         0x00000000,
 703         0x3c000000,
 704         0x68cd1000,
 705         0x00080000,
 706         0x00000000,
 707 };
 708
 709 const u32 r6xx_ps[] =
 710 {
 711         0x00000002,
 712         0x80800000,
 713         0x00000000,
 714         0x94200688,
 715         0x00000010,
 716         0x000d1000,
 717         0xb0800000,
 718         0x00000000,
 719 };
 720
 721 const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);
 722 const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);
 723 const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
 724 const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);