drivers/gpu/drm/radeon/r600_blit_kms.c

   1 /*
   2  * Copyright 2009 Advanced Micro Devices, Inc.
   3  * Copyright 2009 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include "drmP.h"
  27 #include "drm.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30
  31 #include "r600d.h"
  32 #include "r600_blit_shaders.h"
  33
  34 #define DI_PT_RECTLIST        0x11
  35 #define DI_INDEX_SIZE_16_BIT  0x0
  36 #define DI_SRC_SEL_AUTO_INDEX 0x2
  37
  38 #define FMT_8                 0x1
  39 #define FMT_5_6_5             0x8
  40 #define FMT_8_8_8_8           0x1a
  41 #define COLOR_8               0x1
  42 #define COLOR_5_6_5           0x8
  43 #define COLOR_8_8_8_8         0x1a
  44
  45 #define RECT_UNIT_H           32
  46 #define RECT_UNIT_W           (RADEON_GPU_PAGE_SIZE / 4 / RECT_UNIT_H)
  47
  48 /* emits 21 on rv770+, 23 on r600 */
  49 static void
  50 set_render_target(struct radeon_device *rdev, int format,
  51                   int w, int h, u64 gpu_addr)
  52 {
  53         u32 cb_color_info;
  54         int pitch, slice;
  55
  56         h = ALIGN(h, 8);
  57         if (h < 8)
  58                 h = 8;
  59
  60         cb_color_info = CB_FORMAT(format) |
  61                 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
  62                 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
  63         pitch = (w / 8) - 1;
  64         slice = ((w * h) / 64) - 1;
  65
  66         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  67         radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  68         radeon_ring_write(rdev, gpu_addr >> 8);
  69
  70         if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
  71                 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
  72                 radeon_ring_write(rdev, 2 << 0);
  73         }
  74
  75         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  76         radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  77         radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
  78
  79         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  80         radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  81         radeon_ring_write(rdev, 0);
  82
  83         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  84         radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  85         radeon_ring_write(rdev, cb_color_info);
  86
  87         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  88         radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  89         radeon_ring_write(rdev, 0);
  90
  91         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  92         radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  93         radeon_ring_write(rdev, 0);
  94
  95         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  96         radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  97         radeon_ring_write(rdev, 0);
  98 }
  99
 100 /* emits 5dw */
 101 static void
 102 cp_set_surface_sync(struct radeon_device *rdev,
 103                     u32 sync_type, u32 size,
 104                     u64 mc_addr)
 105 {
 106         u32 cp_coher_size;
 107
 108         if (size == 0xffffffff)
 109                 cp_coher_size = 0xffffffff;
 110         else
 111                 cp_coher_size = ((size + 255) >> 8);
 112
 113         radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
 114         radeon_ring_write(rdev, sync_type);
 115         radeon_ring_write(rdev, cp_coher_size);
 116         radeon_ring_write(rdev, mc_addr >> 8);
 117         radeon_ring_write(rdev, 10); /* poll interval */
 118 }
 119
 120 /* emits 21dw + 1 surface sync = 26dw */
 121 static void
 122 set_shaders(struct radeon_device *rdev)
 123 {
 124         u64 gpu_addr;
 125         u32 sq_pgm_resources;
 126
 127         /* setup shader regs */
 128         sq_pgm_resources = (1 << 0);
 129
 130         /* VS */
 131         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 132         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 133         radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 134         radeon_ring_write(rdev, gpu_addr >> 8);
 135
 136         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 137         radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 138         radeon_ring_write(rdev, sq_pgm_resources);
 139
 140         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 141         radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 142         radeon_ring_write(rdev, 0);
 143
 144         /* PS */
 145         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
 146         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 147         radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 148         radeon_ring_write(rdev, gpu_addr >> 8);
 149
 150         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 151         radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 152         radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
 153
 154         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 155         radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 156         radeon_ring_write(rdev, 2);
 157
 158         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 159         radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 160         radeon_ring_write(rdev, 0);
 161
 162         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 163         cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 164 }
 165
 166 /* emits 9 + 1 sync (5) = 14*/
 167 static void
 168 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 169 {
 170         u32 sq_vtx_constant_word2;
 171
 172         sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
 173                 SQ_VTXC_STRIDE(16);
 174 #ifdef __BIG_ENDIAN
 175         sq_vtx_constant_word2 |=  SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
 176 #endif
 177
 178         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
 179         radeon_ring_write(rdev, 0x460);
 180         radeon_ring_write(rdev, gpu_addr & 0xffffffff);
 181         radeon_ring_write(rdev, 48 - 1);
 182         radeon_ring_write(rdev, sq_vtx_constant_word2);
 183         radeon_ring_write(rdev, 1 << 0);
 184         radeon_ring_write(rdev, 0);
 185         radeon_ring_write(rdev, 0);
 186         radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
 187
 188         if ((rdev->family == CHIP_RV610) ||
 189             (rdev->family == CHIP_RV620) ||
 190             (rdev->family == CHIP_RS780) ||
 191             (rdev->family == CHIP_RS880) ||
 192             (rdev->family == CHIP_RV710))
 193                 cp_set_surface_sync(rdev,
 194                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
 195         else
 196                 cp_set_surface_sync(rdev,
 197                                     PACKET3_VC_ACTION_ENA, 48, gpu_addr);
 198 }
 199
 200 /* emits 9 */
 201 static void
 202 set_tex_resource(struct radeon_device *rdev,
 203                  int format, int w, int h, int pitch,
 204                  u64 gpu_addr)
 205 {
 206         uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
 207
 208         if (h < 1)
 209                 h = 1;
 210
 211         sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) |
 212                 S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
 213         sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) |
 214                 S_038000_TEX_WIDTH(w - 1);
 215
 216         sq_tex_resource_word1 = S_038004_DATA_FORMAT(format);
 217         sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1);
 218
 219         sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) |
 220                 S_038010_DST_SEL_X(SQ_SEL_X) |
 221                 S_038010_DST_SEL_Y(SQ_SEL_Y) |
 222                 S_038010_DST_SEL_Z(SQ_SEL_Z) |
 223                 S_038010_DST_SEL_W(SQ_SEL_W);
 224
 225         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
 226         radeon_ring_write(rdev, 0);
 227         radeon_ring_write(rdev, sq_tex_resource_word0);
 228         radeon_ring_write(rdev, sq_tex_resource_word1);
 229         radeon_ring_write(rdev, gpu_addr >> 8);
 230         radeon_ring_write(rdev, gpu_addr >> 8);
 231         radeon_ring_write(rdev, sq_tex_resource_word4);
 232         radeon_ring_write(rdev, 0);
 233         radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
 234 }
 235
 236 /* emits 12 */
 237 static void
 238 set_scissors(struct radeon_device *rdev, int x1, int y1,
 239              int x2, int y2)
 240 {
 241         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 242         radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 243         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
 244         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 245
 246         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 247         radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 248         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 249         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 250
 251         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 252         radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 253         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 254         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 255 }
 256
 257 /* emits 10 */
 258 static void
 259 draw_auto(struct radeon_device *rdev)
 260 {
 261         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 262         radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
 263         radeon_ring_write(rdev, DI_PT_RECTLIST);
 264
 265         radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
 266         radeon_ring_write(rdev,
 267 #ifdef __BIG_ENDIAN
 268                           (2 << 2) |
 269 #endif
 270                           DI_INDEX_SIZE_16_BIT);
 271
 272         radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
 273         radeon_ring_write(rdev, 1);
 274
 275         radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
 276         radeon_ring_write(rdev, 3);
 277         radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
 278
 279 }
 280
 281 /* emits 14 */
 282 static void
 283 set_default_state(struct radeon_device *rdev)
 284 {
 285         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
 286         u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
 287         int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
 288         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 289         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 290         u64 gpu_addr;
 291         int dwords;
 292
 293         switch (rdev->family) {
 294         case CHIP_R600:
 295                 num_ps_gprs = 192;
 296                 num_vs_gprs = 56;
 297                 num_temp_gprs = 4;
 298                 num_gs_gprs = 0;
 299                 num_es_gprs = 0;
 300                 num_ps_threads = 136;
 301                 num_vs_threads = 48;
 302                 num_gs_threads = 4;
 303                 num_es_threads = 4;
 304                 num_ps_stack_entries = 128;
 305                 num_vs_stack_entries = 128;
 306                 num_gs_stack_entries = 0;
 307                 num_es_stack_entries = 0;
 308                 break;
 309         case CHIP_RV630:
 310         case CHIP_RV635:
 311                 num_ps_gprs = 84;
 312                 num_vs_gprs = 36;
 313                 num_temp_gprs = 4;
 314                 num_gs_gprs = 0;
 315                 num_es_gprs = 0;
 316                 num_ps_threads = 144;
 317                 num_vs_threads = 40;
 318                 num_gs_threads = 4;
 319                 num_es_threads = 4;
 320                 num_ps_stack_entries = 40;
 321                 num_vs_stack_entries = 40;
 322                 num_gs_stack_entries = 32;
 323                 num_es_stack_entries = 16;
 324                 break;
 325         case CHIP_RV610:
 326         case CHIP_RV620:
 327         case CHIP_RS780:
 328         case CHIP_RS880:
 329         default:
 330                 num_ps_gprs = 84;
 331                 num_vs_gprs = 36;
 332                 num_temp_gprs = 4;
 333                 num_gs_gprs = 0;
 334                 num_es_gprs = 0;
 335                 num_ps_threads = 136;
 336                 num_vs_threads = 48;
 337                 num_gs_threads = 4;
 338                 num_es_threads = 4;
 339                 num_ps_stack_entries = 40;
 340                 num_vs_stack_entries = 40;
 341                 num_gs_stack_entries = 32;
 342                 num_es_stack_entries = 16;
 343                 break;
 344         case CHIP_RV670:
 345                 num_ps_gprs = 144;
 346                 num_vs_gprs = 40;
 347                 num_temp_gprs = 4;
 348                 num_gs_gprs = 0;
 349                 num_es_gprs = 0;
 350                 num_ps_threads = 136;
 351                 num_vs_threads = 48;
 352                 num_gs_threads = 4;
 353                 num_es_threads = 4;
 354                 num_ps_stack_entries = 40;
 355                 num_vs_stack_entries = 40;
 356                 num_gs_stack_entries = 32;
 357                 num_es_stack_entries = 16;
 358                 break;
 359         case CHIP_RV770:
 360                 num_ps_gprs = 192;
 361                 num_vs_gprs = 56;
 362                 num_temp_gprs = 4;
 363                 num_gs_gprs = 0;
 364                 num_es_gprs = 0;
 365                 num_ps_threads = 188;
 366                 num_vs_threads = 60;
 367                 num_gs_threads = 0;
 368                 num_es_threads = 0;
 369                 num_ps_stack_entries = 256;
 370                 num_vs_stack_entries = 256;
 371                 num_gs_stack_entries = 0;
 372                 num_es_stack_entries = 0;
 373                 break;
 374         case CHIP_RV730:
 375         case CHIP_RV740:
 376                 num_ps_gprs = 84;
 377                 num_vs_gprs = 36;
 378                 num_temp_gprs = 4;
 379                 num_gs_gprs = 0;
 380                 num_es_gprs = 0;
 381                 num_ps_threads = 188;
 382                 num_vs_threads = 60;
 383                 num_gs_threads = 0;
 384                 num_es_threads = 0;
 385                 num_ps_stack_entries = 128;
 386                 num_vs_stack_entries = 128;
 387                 num_gs_stack_entries = 0;
 388                 num_es_stack_entries = 0;
 389                 break;
 390         case CHIP_RV710:
 391                 num_ps_gprs = 192;
 392                 num_vs_gprs = 56;
 393                 num_temp_gprs = 4;
 394                 num_gs_gprs = 0;
 395                 num_es_gprs = 0;
 396                 num_ps_threads = 144;
 397                 num_vs_threads = 48;
 398                 num_gs_threads = 0;
 399                 num_es_threads = 0;
 400                 num_ps_stack_entries = 128;
 401                 num_vs_stack_entries = 128;
 402                 num_gs_stack_entries = 0;
 403                 num_es_stack_entries = 0;
 404                 break;
 405         }
 406
 407         if ((rdev->family == CHIP_RV610) ||
 408             (rdev->family == CHIP_RV620) ||
 409             (rdev->family == CHIP_RS780) ||
 410             (rdev->family == CHIP_RS880) ||
 411             (rdev->family == CHIP_RV710))
 412                 sq_config = 0;
 413         else
 414                 sq_config = VC_ENABLE;
 415
 416         sq_config |= (DX9_CONSTS |
 417                       ALU_INST_PREFER_VECTOR |
 418                       PS_PRIO(0) |
 419                       VS_PRIO(1) |
 420                       GS_PRIO(2) |
 421                       ES_PRIO(3));
 422
 423         sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
 424                                   NUM_VS_GPRS(num_vs_gprs) |
 425                                   NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 426         sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
 427                                   NUM_ES_GPRS(num_es_gprs));
 428         sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
 429                                    NUM_VS_THREADS(num_vs_threads) |
 430                                    NUM_GS_THREADS(num_gs_threads) |
 431                                    NUM_ES_THREADS(num_es_threads));
 432         sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 433                                     NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 434         sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 435                                     NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 436
 437         /* emit an IB pointing at default state */
 438         dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
 439         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
 440         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 441         radeon_ring_write(rdev,
 442 #ifdef __BIG_ENDIAN
 443                           (2 << 0) |
 444 #endif
 445                           (gpu_addr & 0xFFFFFFFC));
 446         radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
 447         radeon_ring_write(rdev, dwords);
 448
 449         /* SQ config */
 450         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
 451         radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
 452         radeon_ring_write(rdev, sq_config);
 453         radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
 454         radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
 455         radeon_ring_write(rdev, sq_thread_resource_mgmt);
 456         radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
 457         radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
 458 }
 459
 460 static uint32_t i2f(uint32_t input)
 461 {
 462         u32 result, i, exponent, fraction;
 463
 464         if ((input & 0x3fff) == 0)
 465                 result = 0; /* 0 is a special case */
 466         else {
 467                 exponent = 140; /* exponent biased by 127; */
 468                 fraction = (input & 0x3fff) << 10; /* cheat and only
 469                                                       handle numbers below 2^^15 */
 470                 for (i = 0; i < 14; i++) {
 471                         if (fraction & 0x800000)
 472                                 break;
 473                         else {
 474                                 fraction = fraction << 1; /* keep
 475                                                              shifting left until top bit = 1 */
 476                                 exponent = exponent - 1;
 477                         }
 478                 }
 479                 result = exponent << 23 | (fraction & 0x7fffff); /* mask
 480                                                                     off top bit; assumed 1 */
 481         }
 482         return result;
 483 }
 484
 485 int r600_blit_init(struct radeon_device *rdev)
 486 {
 487         u32 obj_size;
 488         int i, r, dwords;
 489         void *ptr;
 490         u32 packet2s[16];
 491         int num_packet2s = 0;
 492
 493         rdev->r600_blit.primitives.set_render_target = set_render_target;
 494         rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
 495         rdev->r600_blit.primitives.set_shaders = set_shaders;
 496         rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
 497         rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
 498         rdev->r600_blit.primitives.set_scissors = set_scissors;
 499         rdev->r600_blit.primitives.draw_auto = draw_auto;
 500         rdev->r600_blit.primitives.set_default_state = set_default_state;
 501
 502         rdev->r600_blit.ring_size_common = 40; /* shaders + def state */
 503         rdev->r600_blit.ring_size_common += 10; /* fence emit for VB IB */
 504         rdev->r600_blit.ring_size_common += 5; /* done copy */
 505         rdev->r600_blit.ring_size_common += 10; /* fence emit for done copy */
 506
 507         rdev->r600_blit.ring_size_per_loop = 76;
 508         /* set_render_target emits 2 extra dwords on rv6xx */
 509         if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
 510                 rdev->r600_blit.ring_size_per_loop += 2;
 511
 512         rdev->r600_blit.max_dim = 8192;
 513
 514         /* pin copy shader into vram if already initialized */
 515         if (rdev->r600_blit.shader_obj)
 516                 goto done;
 517
 518         mutex_init(&rdev->r600_blit.mutex);
 519         rdev->r600_blit.state_offset = 0;
 520
 521         if (rdev->family >= CHIP_RV770)
 522                 rdev->r600_blit.state_len = r7xx_default_size;
 523         else
 524                 rdev->r600_blit.state_len = r6xx_default_size;
 525
 526         dwords = rdev->r600_blit.state_len;
 527         while (dwords & 0xf) {
 528                 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
 529                 dwords++;
 530         }
 531
 532         obj_size = dwords * 4;
 533         obj_size = ALIGN(obj_size, 256);
 534
 535         rdev->r600_blit.vs_offset = obj_size;
 536         obj_size += r6xx_vs_size * 4;
 537         obj_size = ALIGN(obj_size, 256);
 538
 539         rdev->r600_blit.ps_offset = obj_size;
 540         obj_size += r6xx_ps_size * 4;
 541         obj_size = ALIGN(obj_size, 256);
 542
 543         r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
 544                                 &rdev->r600_blit.shader_obj);
 545         if (r) {
 546                 DRM_ERROR("r600 failed to allocate shader\n");
 547                 return r;
 548         }
 549
 550         DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
 551                   obj_size,
 552                   rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 553
 554         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 555         if (unlikely(r != 0))
 556                 return r;
 557         r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
 558         if (r) {
 559                 DRM_ERROR("failed to map blit object %d\n", r);
 560                 return r;
 561         }
 562         if (rdev->family >= CHIP_RV770)
 563                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 564                             r7xx_default_state, rdev->r600_blit.state_len * 4);
 565         else
 566                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 567                             r6xx_default_state, rdev->r600_blit.state_len * 4);
 568         if (num_packet2s)
 569                 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
 570                             packet2s, num_packet2s * 4);
 571         for (i = 0; i < r6xx_vs_size; i++)
 572                 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
 573         for (i = 0; i < r6xx_ps_size; i++)
 574                 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
 575         radeon_bo_kunmap(rdev->r600_blit.shader_obj);
 576         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 577
 578 done:
 579         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 580         if (unlikely(r != 0))
 581                 return r;
 582         r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 583                           &rdev->r600_blit.shader_gpu_addr);
 584         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 585         if (r) {
 586                 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
 587                 return r;
 588         }
 589         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 590         return 0;
 591 }
 592
 593 void r600_blit_fini(struct radeon_device *rdev)
 594 {
 595         int r;
 596
 597         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 598         if (rdev->r600_blit.shader_obj == NULL)
 599                 return;
 600         /* If we can't reserve the bo, unref should be enough to destroy
 601          * it when it becomes idle.
 602          */
 603         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 604         if (!r) {
 605                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
 606                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 607         }
 608         radeon_bo_unref(&rdev->r600_blit.shader_obj);
 609 }
 610
 611 static int r600_vb_ib_get(struct radeon_device *rdev)
 612 {
 613         int r;
 614         r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
 615         if (r) {
 616                 DRM_ERROR("failed to get IB for vertex buffer\n");
 617                 return r;
 618         }
 619
 620         rdev->r600_blit.vb_total = 64*1024;
 621         rdev->r600_blit.vb_used = 0;
 622         return 0;
 623 }
 624
 625 static void r600_vb_ib_put(struct radeon_device *rdev)
 626 {
 627         radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
 628         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
 629 }
 630
 631 static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
 632                                       int *width, int *height, int max_dim)
 633 {
 634         unsigned max_pages;
 635         unsigned pages = num_gpu_pages;
 636         int w, h;
 637
 638         if (num_gpu_pages == 0) {
 639                 /* not supposed to be called with no pages, but just in case */
 640                 h = 0;
 641                 w = 0;
 642                 pages = 0;
 643                 WARN_ON(1);
 644         } else {
 645                 int rect_order = 2;
 646                 h = RECT_UNIT_H;
 647                 while (num_gpu_pages / rect_order) {
 648                         h *= 2;
 649                         rect_order *= 4;
 650                         if (h >= max_dim) {
 651                                 h = max_dim;
 652                                 break;
 653                         }
 654                 }
 655                 max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H);
 656                 if (pages > max_pages)
 657                         pages = max_pages;
 658                 w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
 659                 w = (w / RECT_UNIT_W) * RECT_UNIT_W;
 660                 pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
 661                 BUG_ON(pages == 0);
 662         }
 663
 664
 665         DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
 666
 667         /* return width and height only of the caller wants it */
 668         if (height)
 669                 *height = h;
 670         if (width)
 671                 *width = w;
 672
 673         return pages;
 674 }
 675
 676
 677 int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages)
 678 {
 679         int r;
 680         int ring_size;
 681         int num_loops = 0;
 682         int dwords_per_loop = rdev->r600_blit.ring_size_per_loop;
 683
 684         r = r600_vb_ib_get(rdev);
 685         if (r)
 686                 return r;
 687
 688         /* num loops */
 689         while (num_gpu_pages) {
 690                 num_gpu_pages -=
 691                         r600_blit_create_rect(num_gpu_pages, NULL, NULL,
 692                                               rdev->r600_blit.max_dim);
 693                 num_loops++;
 694         }
 695
 696         /* calculate number of loops correctly */
 697         ring_size = num_loops * dwords_per_loop;
 698         ring_size += rdev->r600_blit.ring_size_common;
 699         r = radeon_ring_lock(rdev, ring_size);
 700         if (r)
 701                 return r;
 702
 703         rdev->r600_blit.primitives.set_default_state(rdev);
 704         rdev->r600_blit.primitives.set_shaders(rdev);
 705         return 0;
 706 }
 707
 708 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
 709 {
 710         int r;
 711
 712         if (rdev->r600_blit.vb_ib)
 713                 r600_vb_ib_put(rdev);
 714
 715         if (fence)
 716                 r = radeon_fence_emit(rdev, fence);
 717
 718         radeon_ring_unlock_commit(rdev);
 719 }
 720
 721 void r600_kms_blit_copy(struct radeon_device *rdev,
 722                         u64 src_gpu_addr, u64 dst_gpu_addr,
 723                         unsigned num_gpu_pages)
 724 {
 725         u64 vb_gpu_addr;
 726         u32 *vb;
 727
 728         DRM_DEBUG("emitting copy %16llx %16llx %d %d\n",
 729                   src_gpu_addr, dst_gpu_addr,
 730                   num_gpu_pages, rdev->r600_blit.vb_used);
 731         vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
 732
 733         while (num_gpu_pages) {
 734                 int w, h;
 735                 unsigned size_in_bytes;
 736                 unsigned pages_per_loop =
 737                         r600_blit_create_rect(num_gpu_pages, &w, &h,
 738                                               rdev->r600_blit.max_dim);
 739
 740                 size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
 741                 DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
 742
 743                 if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
 744                         WARN_ON(1);
 745                 }
 746
 747                 vb[0] = 0;
 748                 vb[1] = 0;
 749                 vb[2] = 0;
 750                 vb[3] = 0;
 751
 752                 vb[4] = 0;
 753                 vb[5] = i2f(h);
 754                 vb[6] = 0;
 755                 vb[7] = i2f(h);
 756
 757                 vb[8] = i2f(w);
 758                 vb[9] = i2f(h);
 759                 vb[10] = i2f(w);
 760                 vb[11] = i2f(h);
 761
 762                 rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8,
 763                                                             w, h, w, src_gpu_addr);
 764                 rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
 765                                                                PACKET3_TC_ACTION_ENA,
 766                                                                size_in_bytes, src_gpu_addr);
 767                 rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8,
 768                                                              w, h, dst_gpu_addr);
 769                 rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h);
 770                 vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
 771                 rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr);
 772                 rdev->r600_blit.primitives.draw_auto(rdev);
 773                 rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
 774                                     PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 775                                     size_in_bytes, dst_gpu_addr);
 776
 777                 vb += 12;
 778                 rdev->r600_blit.vb_used += 4*12;
 779                 src_gpu_addr += size_in_bytes;
 780                 dst_gpu_addr += size_in_bytes;
 781                 num_gpu_pages -= pages_per_loop;
 782         }
 783 }