2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
32 #include "radeon_reg.h"
34 #include "radeon_asic.h"
35 #include "radeon_drm.h"
36 #include "r100_track.h"
39 #include "r300_reg_safe.h"
41 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
44 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
45 * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
46 * However, scheduling such write to the ring seems harmless, i suspect
47 * the CP read collide with the flush somehow, or maybe the MC, hard to
48 * tell. (Jerome Glisse)
52 * rv370,rv380 PCIE GART
54 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
56 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
61 /* Workaround HW bug do flush 2 times */
62 for (i = 0; i < 2; i++) {
63 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
64 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
65 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
66 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
71 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
73 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
75 if (i < 0 || i > rdev->gart.num_gpu_pages) {
78 addr = (lower_32_bits(addr) >> 8) |
79 ((upper_32_bits(addr) & 0xff) << 24) |
81 /* on x86 we want this to be CPU endian, on powerpc
82 * on powerpc without HW swappers, it'll get swapped on way
83 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
84 writel(addr, ((void __iomem *)ptr) + (i * 4));
88 int rv370_pcie_gart_init(struct radeon_device *rdev)
92 if (rdev->gart.table.vram.robj) {
93 WARN(1, "RV370 PCIE GART already initialized.\n");
96 /* Initialize common gart structure */
97 r = radeon_gart_init(rdev);
100 r = rv370_debugfs_pcie_gart_info_init(rdev);
102 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
103 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
104 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
105 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
106 return radeon_gart_table_vram_alloc(rdev);
109 int rv370_pcie_gart_enable(struct radeon_device *rdev)
115 if (rdev->gart.table.vram.robj == NULL) {
116 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
119 r = radeon_gart_table_vram_pin(rdev);
122 radeon_gart_restore(rdev);
123 /* discard memory request outside of configured range */
124 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
125 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
126 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
127 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
128 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
129 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
130 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
131 table_addr = rdev->gart.table_addr;
132 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
133 /* FIXME: setup default page */
134 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
135 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
137 WREG32_PCIE(0x18, 0);
138 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
139 tmp |= RADEON_PCIE_TX_GART_EN;
140 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
141 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
142 rv370_pcie_gart_tlb_flush(rdev);
143 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
144 (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
145 rdev->gart.ready = true;
149 void rv370_pcie_gart_disable(struct radeon_device *rdev)
154 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
155 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
156 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
157 if (rdev->gart.table.vram.robj) {
158 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
159 if (likely(r == 0)) {
160 radeon_bo_kunmap(rdev->gart.table.vram.robj);
161 radeon_bo_unpin(rdev->gart.table.vram.robj);
162 radeon_bo_unreserve(rdev->gart.table.vram.robj);
167 void rv370_pcie_gart_fini(struct radeon_device *rdev)
169 radeon_gart_fini(rdev);
170 rv370_pcie_gart_disable(rdev);
171 radeon_gart_table_vram_free(rdev);
174 void r300_fence_ring_emit(struct radeon_device *rdev,
175 struct radeon_fence *fence)
177 /* Who ever call radeon_fence_emit should call ring_lock and ask
178 * for enough space (today caller are ib schedule and buffer move) */
179 /* Write SC register so SC & US assert idle */
180 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
181 radeon_ring_write(rdev, 0);
182 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
183 radeon_ring_write(rdev, 0);
185 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
186 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
187 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
188 radeon_ring_write(rdev, R300_ZC_FLUSH);
189 /* Wait until IDLE & CLEAN */
190 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
191 radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
192 RADEON_WAIT_2D_IDLECLEAN |
193 RADEON_WAIT_DMA_GUI_IDLE));
194 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
195 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
196 RADEON_HDP_READ_BUFFER_INVALIDATE);
197 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
198 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
199 /* Emit fence sequence & fire IRQ */
200 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
201 radeon_ring_write(rdev, fence->seq);
202 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
203 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
206 void r300_ring_start(struct radeon_device *rdev)
208 unsigned gb_tile_config;
211 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
212 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
213 switch(rdev->num_gb_pipes) {
215 gb_tile_config |= R300_PIPE_COUNT_R300;
218 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
221 gb_tile_config |= R300_PIPE_COUNT_R420;
225 gb_tile_config |= R300_PIPE_COUNT_RV350;
229 r = radeon_ring_lock(rdev, 64);
233 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
234 radeon_ring_write(rdev,
235 RADEON_ISYNC_ANY2D_IDLE3D |
236 RADEON_ISYNC_ANY3D_IDLE2D |
237 RADEON_ISYNC_WAIT_IDLEGUI |
238 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
239 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
240 radeon_ring_write(rdev, gb_tile_config);
241 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
242 radeon_ring_write(rdev,
243 RADEON_WAIT_2D_IDLECLEAN |
244 RADEON_WAIT_3D_IDLECLEAN);
245 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
246 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
247 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
248 radeon_ring_write(rdev, 0);
249 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
250 radeon_ring_write(rdev, 0);
251 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
252 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
253 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
254 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
255 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
256 radeon_ring_write(rdev,
257 RADEON_WAIT_2D_IDLECLEAN |
258 RADEON_WAIT_3D_IDLECLEAN);
259 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
260 radeon_ring_write(rdev, 0);
261 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
262 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
263 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
264 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
265 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
266 radeon_ring_write(rdev,
267 ((6 << R300_MS_X0_SHIFT) |
268 (6 << R300_MS_Y0_SHIFT) |
269 (6 << R300_MS_X1_SHIFT) |
270 (6 << R300_MS_Y1_SHIFT) |
271 (6 << R300_MS_X2_SHIFT) |
272 (6 << R300_MS_Y2_SHIFT) |
273 (6 << R300_MSBD0_Y_SHIFT) |
274 (6 << R300_MSBD0_X_SHIFT)));
275 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
276 radeon_ring_write(rdev,
277 ((6 << R300_MS_X3_SHIFT) |
278 (6 << R300_MS_Y3_SHIFT) |
279 (6 << R300_MS_X4_SHIFT) |
280 (6 << R300_MS_Y4_SHIFT) |
281 (6 << R300_MS_X5_SHIFT) |
282 (6 << R300_MS_Y5_SHIFT) |
283 (6 << R300_MSBD1_SHIFT)));
284 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
285 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
286 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
287 radeon_ring_write(rdev,
288 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
289 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
290 radeon_ring_write(rdev,
291 R300_GEOMETRY_ROUND_NEAREST |
292 R300_COLOR_ROUND_NEAREST);
293 radeon_ring_unlock_commit(rdev);
296 void r300_errata(struct radeon_device *rdev)
298 rdev->pll_errata = 0;
300 if (rdev->family == CHIP_R300 &&
301 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
302 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
306 int r300_mc_wait_for_idle(struct radeon_device *rdev)
311 for (i = 0; i < rdev->usec_timeout; i++) {
313 tmp = RREG32(RADEON_MC_STATUS);
314 if (tmp & R300_MC_IDLE) {
322 void r300_gpu_init(struct radeon_device *rdev)
324 uint32_t gb_tile_config, tmp;
326 r100_hdp_reset(rdev);
327 /* FIXME: rv380 one pipes ? */
328 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
329 (rdev->family == CHIP_R350)) {
331 rdev->num_gb_pipes = 2;
333 /* rv350,rv370,rv380,r300 AD */
334 rdev->num_gb_pipes = 1;
336 rdev->num_z_pipes = 1;
337 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
338 switch (rdev->num_gb_pipes) {
340 gb_tile_config |= R300_PIPE_COUNT_R300;
343 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
346 gb_tile_config |= R300_PIPE_COUNT_R420;
350 gb_tile_config |= R300_PIPE_COUNT_RV350;
353 WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
355 if (r100_gui_wait_for_idle(rdev)) {
356 printk(KERN_WARNING "Failed to wait GUI idle while "
357 "programming pipes. Bad things might happen.\n");
360 tmp = RREG32(R300_DST_PIPE_CONFIG);
361 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
363 WREG32(R300_RB2D_DSTCACHE_MODE,
364 R300_DC_AUTOFLUSH_ENABLE |
365 R300_DC_DC_DISABLE_IGNORE_PE);
367 if (r100_gui_wait_for_idle(rdev)) {
368 printk(KERN_WARNING "Failed to wait GUI idle while "
369 "programming pipes. Bad things might happen.\n");
371 if (r300_mc_wait_for_idle(rdev)) {
372 printk(KERN_WARNING "Failed to wait MC idle while "
373 "programming pipes. Bad things might happen.\n");
375 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
376 rdev->num_gb_pipes, rdev->num_z_pipes);
379 int r300_ga_reset(struct radeon_device *rdev)
385 reinit_cp = rdev->cp.ready;
386 rdev->cp.ready = false;
387 for (i = 0; i < rdev->usec_timeout; i++) {
388 WREG32(RADEON_CP_CSQ_MODE, 0);
389 WREG32(RADEON_CP_CSQ_CNTL, 0);
390 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
391 (void)RREG32(RADEON_RBBM_SOFT_RESET);
393 WREG32(RADEON_RBBM_SOFT_RESET, 0);
394 /* Wait to prevent race in RBBM_STATUS */
396 tmp = RREG32(RADEON_RBBM_STATUS);
397 if (tmp & ((1 << 20) | (1 << 26))) {
398 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
399 /* GA still busy soft reset it */
400 WREG32(0x429C, 0x200);
401 WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
402 WREG32(R300_RE_SCISSORS_TL, 0);
403 WREG32(R300_RE_SCISSORS_BR, 0);
406 /* Wait to prevent race in RBBM_STATUS */
408 tmp = RREG32(RADEON_RBBM_STATUS);
409 if (!(tmp & ((1 << 20) | (1 << 26)))) {
413 for (i = 0; i < rdev->usec_timeout; i++) {
414 tmp = RREG32(RADEON_RBBM_STATUS);
415 if (!(tmp & ((1 << 20) | (1 << 26)))) {
416 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
419 return r100_cp_init(rdev, rdev->cp.ring_size);
425 tmp = RREG32(RADEON_RBBM_STATUS);
426 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
430 int r300_gpu_reset(struct radeon_device *rdev)
434 /* reset order likely matter */
435 status = RREG32(RADEON_RBBM_STATUS);
437 r100_hdp_reset(rdev);
439 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
440 r100_rb2d_reset(rdev);
443 if (status & ((1 << 20) | (1 << 26))) {
447 status = RREG32(RADEON_RBBM_STATUS);
448 if (status & (1 << 16)) {
451 /* Check if GPU is idle */
452 status = RREG32(RADEON_RBBM_STATUS);
453 if (status & RADEON_RBBM_ACTIVE) {
454 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
457 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
463 * r300,r350,rv350,rv380 VRAM info
465 void r300_mc_init(struct radeon_device *rdev)
470 /* DDR for all card after R300 & IGP */
471 rdev->mc.vram_is_ddr = true;
472 tmp = RREG32(RADEON_MEM_CNTL);
473 tmp &= R300_MEM_NUM_CHANNELS_MASK;
475 case 0: rdev->mc.vram_width = 64; break;
476 case 1: rdev->mc.vram_width = 128; break;
477 case 2: rdev->mc.vram_width = 256; break;
478 default: rdev->mc.vram_width = 128; break;
480 r100_vram_init_sizes(rdev);
481 base = rdev->mc.aper_base;
482 if (rdev->flags & RADEON_IS_IGP)
483 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
484 radeon_vram_location(rdev, &rdev->mc, base);
485 if (!(rdev->flags & RADEON_IS_AGP))
486 radeon_gtt_location(rdev, &rdev->mc);
487 radeon_update_bandwidth_info(rdev);
490 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
492 uint32_t link_width_cntl, mask;
494 if (rdev->flags & RADEON_IS_IGP)
497 if (!(rdev->flags & RADEON_IS_PCIE))
500 /* FIXME wait for idle */
504 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
507 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
510 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
513 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
516 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
519 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
523 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
527 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
529 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
530 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
533 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
534 RADEON_PCIE_LC_RECONFIG_NOW |
535 RADEON_PCIE_LC_RECONFIG_LATER |
536 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
537 link_width_cntl |= mask;
538 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
539 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
540 RADEON_PCIE_LC_RECONFIG_NOW));
542 /* wait for lane set to complete */
543 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
544 while (link_width_cntl == 0xffffffff)
545 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
549 int rv370_get_pcie_lanes(struct radeon_device *rdev)
553 if (rdev->flags & RADEON_IS_IGP)
556 if (!(rdev->flags & RADEON_IS_PCIE))
559 /* FIXME wait for idle */
561 if (rdev->family < CHIP_R600)
562 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
564 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
566 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
567 case RADEON_PCIE_LC_LINK_WIDTH_X0:
569 case RADEON_PCIE_LC_LINK_WIDTH_X1:
571 case RADEON_PCIE_LC_LINK_WIDTH_X2:
573 case RADEON_PCIE_LC_LINK_WIDTH_X4:
575 case RADEON_PCIE_LC_LINK_WIDTH_X8:
577 case RADEON_PCIE_LC_LINK_WIDTH_X16:
583 #if defined(CONFIG_DEBUG_FS)
584 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
586 struct drm_info_node *node = (struct drm_info_node *) m->private;
587 struct drm_device *dev = node->minor->dev;
588 struct radeon_device *rdev = dev->dev_private;
591 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
592 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
593 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
594 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
595 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
596 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
598 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
600 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
601 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
602 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
603 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
604 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
608 static struct drm_info_list rv370_pcie_gart_info_list[] = {
609 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
613 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
615 #if defined(CONFIG_DEBUG_FS)
616 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
622 static int r300_packet0_check(struct radeon_cs_parser *p,
623 struct radeon_cs_packet *pkt,
624 unsigned idx, unsigned reg)
626 struct radeon_cs_reloc *reloc;
627 struct r100_cs_track *track;
628 volatile uint32_t *ib;
629 uint32_t tmp, tile_flags = 0;
635 track = (struct r100_cs_track *)p->track;
636 idx_value = radeon_get_ib_value(p, idx);
639 case AVIVO_D1MODE_VLINE_START_END:
640 case RADEON_CRTC_GUI_TRIG_VLINE:
641 r = r100_cs_packet_parse_vline(p);
643 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
645 r100_cs_dump_packet(p, pkt);
649 case RADEON_DST_PITCH_OFFSET:
650 case RADEON_SRC_PITCH_OFFSET:
651 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
655 case R300_RB3D_COLOROFFSET0:
656 case R300_RB3D_COLOROFFSET1:
657 case R300_RB3D_COLOROFFSET2:
658 case R300_RB3D_COLOROFFSET3:
659 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
660 r = r100_cs_packet_next_reloc(p, &reloc);
662 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
664 r100_cs_dump_packet(p, pkt);
667 track->cb[i].robj = reloc->robj;
668 track->cb[i].offset = idx_value;
669 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
671 case R300_ZB_DEPTHOFFSET:
672 r = r100_cs_packet_next_reloc(p, &reloc);
674 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
676 r100_cs_dump_packet(p, pkt);
679 track->zb.robj = reloc->robj;
680 track->zb.offset = idx_value;
681 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
683 case R300_TX_OFFSET_0:
684 case R300_TX_OFFSET_0+4:
685 case R300_TX_OFFSET_0+8:
686 case R300_TX_OFFSET_0+12:
687 case R300_TX_OFFSET_0+16:
688 case R300_TX_OFFSET_0+20:
689 case R300_TX_OFFSET_0+24:
690 case R300_TX_OFFSET_0+28:
691 case R300_TX_OFFSET_0+32:
692 case R300_TX_OFFSET_0+36:
693 case R300_TX_OFFSET_0+40:
694 case R300_TX_OFFSET_0+44:
695 case R300_TX_OFFSET_0+48:
696 case R300_TX_OFFSET_0+52:
697 case R300_TX_OFFSET_0+56:
698 case R300_TX_OFFSET_0+60:
699 i = (reg - R300_TX_OFFSET_0) >> 2;
700 r = r100_cs_packet_next_reloc(p, &reloc);
702 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
704 r100_cs_dump_packet(p, pkt);
708 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
709 tile_flags |= R300_TXO_MACRO_TILE;
710 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
711 tile_flags |= R300_TXO_MICRO_TILE;
712 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
713 tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
715 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
718 track->textures[i].robj = reloc->robj;
720 /* Tracked registers */
723 track->vap_vf_cntl = idx_value;
727 track->vtx_size = idx_value & 0x7F;
730 /* VAP_VF_MAX_VTX_INDX */
731 track->max_indx = idx_value & 0x00FFFFFFUL;
734 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
735 if (p->rdev->family < CHIP_RV515)
737 track->vap_alt_nverts = idx_value & 0xFFFFFF;
741 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
742 if (p->rdev->family < CHIP_RV515) {
748 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
754 /* RB3D_COLORPITCH0 */
755 /* RB3D_COLORPITCH1 */
756 /* RB3D_COLORPITCH2 */
757 /* RB3D_COLORPITCH3 */
758 r = r100_cs_packet_next_reloc(p, &reloc);
760 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
762 r100_cs_dump_packet(p, pkt);
766 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
767 tile_flags |= R300_COLOR_TILE_ENABLE;
768 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
769 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
770 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
771 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
773 tmp = idx_value & ~(0x7 << 16);
776 i = (reg - 0x4E38) >> 2;
777 track->cb[i].pitch = idx_value & 0x3FFE;
778 switch (((idx_value >> 21) & 0xF)) {
782 track->cb[i].cpp = 1;
788 track->cb[i].cpp = 2;
791 track->cb[i].cpp = 4;
794 track->cb[i].cpp = 8;
797 track->cb[i].cpp = 16;
800 DRM_ERROR("Invalid color buffer format (%d) !\n",
801 ((idx_value >> 21) & 0xF));
808 track->z_enabled = true;
810 track->z_enabled = false;
815 switch ((idx_value & 0xF)) {
824 DRM_ERROR("Invalid z buffer format (%d) !\n",
831 r = r100_cs_packet_next_reloc(p, &reloc);
833 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
835 r100_cs_dump_packet(p, pkt);
839 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
840 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
841 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
842 tile_flags |= R300_DEPTHMICROTILE_TILED;
843 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
844 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
846 tmp = idx_value & ~(0x7 << 16);
850 track->zb.pitch = idx_value & 0x3FFC;
853 for (i = 0; i < 16; i++) {
856 enabled = !!(idx_value & (1 << i));
857 track->textures[i].enabled = enabled;
876 /* TX_FORMAT1_[0-15] */
877 i = (reg - 0x44C0) >> 2;
878 tmp = (idx_value >> 25) & 0x3;
879 track->textures[i].tex_coord_type = tmp;
880 switch ((idx_value & 0x1F)) {
881 case R300_TX_FORMAT_X8:
882 case R300_TX_FORMAT_Y4X4:
883 case R300_TX_FORMAT_Z3Y3X2:
884 track->textures[i].cpp = 1;
886 case R300_TX_FORMAT_X16:
887 case R300_TX_FORMAT_Y8X8:
888 case R300_TX_FORMAT_Z5Y6X5:
889 case R300_TX_FORMAT_Z6Y5X5:
890 case R300_TX_FORMAT_W4Z4Y4X4:
891 case R300_TX_FORMAT_W1Z5Y5X5:
892 case R300_TX_FORMAT_D3DMFT_CxV8U8:
893 case R300_TX_FORMAT_B8G8_B8G8:
894 case R300_TX_FORMAT_G8R8_G8B8:
895 track->textures[i].cpp = 2;
897 case R300_TX_FORMAT_Y16X16:
898 case R300_TX_FORMAT_Z11Y11X10:
899 case R300_TX_FORMAT_Z10Y11X11:
900 case R300_TX_FORMAT_W8Z8Y8X8:
901 case R300_TX_FORMAT_W2Z10Y10X10:
903 case R300_TX_FORMAT_FL_I32:
905 track->textures[i].cpp = 4;
907 case R300_TX_FORMAT_W16Z16Y16X16:
908 case R300_TX_FORMAT_FL_R16G16B16A16:
909 case R300_TX_FORMAT_FL_I32A32:
910 track->textures[i].cpp = 8;
912 case R300_TX_FORMAT_FL_R32G32B32A32:
913 track->textures[i].cpp = 16;
915 case R300_TX_FORMAT_DXT1:
916 track->textures[i].cpp = 1;
917 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
919 case R300_TX_FORMAT_ATI2N:
920 if (p->rdev->family < CHIP_R420) {
921 DRM_ERROR("Invalid texture format %u\n",
925 /* The same rules apply as for DXT3/5. */
927 case R300_TX_FORMAT_DXT3:
928 case R300_TX_FORMAT_DXT5:
929 track->textures[i].cpp = 1;
930 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
933 DRM_ERROR("Invalid texture format %u\n",
955 /* TX_FILTER0_[0-15] */
956 i = (reg - 0x4400) >> 2;
957 tmp = idx_value & 0x7;
958 if (tmp == 2 || tmp == 4 || tmp == 6) {
959 track->textures[i].roundup_w = false;
961 tmp = (idx_value >> 3) & 0x7;
962 if (tmp == 2 || tmp == 4 || tmp == 6) {
963 track->textures[i].roundup_h = false;
982 /* TX_FORMAT2_[0-15] */
983 i = (reg - 0x4500) >> 2;
984 tmp = idx_value & 0x3FFF;
985 track->textures[i].pitch = tmp + 1;
986 if (p->rdev->family >= CHIP_RV515) {
987 tmp = ((idx_value >> 15) & 1) << 11;
988 track->textures[i].width_11 = tmp;
989 tmp = ((idx_value >> 16) & 1) << 11;
990 track->textures[i].height_11 = tmp;
993 if (idx_value & (1 << 14)) {
994 /* The same rules apply as for DXT1. */
995 track->textures[i].compress_format =
996 R100_TRACK_COMP_DXT1;
998 } else if (idx_value & (1 << 14)) {
999 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1019 /* TX_FORMAT0_[0-15] */
1020 i = (reg - 0x4480) >> 2;
1021 tmp = idx_value & 0x7FF;
1022 track->textures[i].width = tmp + 1;
1023 tmp = (idx_value >> 11) & 0x7FF;
1024 track->textures[i].height = tmp + 1;
1025 tmp = (idx_value >> 26) & 0xF;
1026 track->textures[i].num_levels = tmp;
1027 tmp = idx_value & (1 << 31);
1028 track->textures[i].use_pitch = !!tmp;
1029 tmp = (idx_value >> 22) & 0xF;
1030 track->textures[i].txdepth = tmp;
1032 case R300_ZB_ZPASS_ADDR:
1033 r = r100_cs_packet_next_reloc(p, &reloc);
1035 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1037 r100_cs_dump_packet(p, pkt);
1040 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1043 /* RB3D_COLOR_CHANNEL_MASK */
1044 track->color_channel_mask = idx_value;
1048 track->fastfill = !!(idx_value & (1 << 2));
1051 /* RB3D_BLENDCNTL */
1052 track->blend_read_enable = !!(idx_value & (1 << 2));
1055 /* valid register only on RV530 */
1056 if (p->rdev->family == CHIP_RV530)
1058 /* fallthrough do not move */
1064 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1069 static int r300_packet3_check(struct radeon_cs_parser *p,
1070 struct radeon_cs_packet *pkt)
1072 struct radeon_cs_reloc *reloc;
1073 struct r100_cs_track *track;
1074 volatile uint32_t *ib;
1080 track = (struct r100_cs_track *)p->track;
1081 switch(pkt->opcode) {
1082 case PACKET3_3D_LOAD_VBPNTR:
1083 r = r100_packet3_load_vbpntr(p, pkt, idx);
1087 case PACKET3_INDX_BUFFER:
1088 r = r100_cs_packet_next_reloc(p, &reloc);
1090 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1091 r100_cs_dump_packet(p, pkt);
1094 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1095 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1101 case PACKET3_3D_DRAW_IMMD:
1102 /* Number of dwords is vtx_size * (num_vertices - 1)
1103 * PRIM_WALK must be equal to 3 vertex data in embedded
1105 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1106 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1109 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1110 track->immd_dwords = pkt->count - 1;
1111 r = r100_cs_track_check(p->rdev, track);
1116 case PACKET3_3D_DRAW_IMMD_2:
1117 /* Number of dwords is vtx_size * (num_vertices - 1)
1118 * PRIM_WALK must be equal to 3 vertex data in embedded
1120 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1121 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1124 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1125 track->immd_dwords = pkt->count;
1126 r = r100_cs_track_check(p->rdev, track);
1131 case PACKET3_3D_DRAW_VBUF:
1132 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1133 r = r100_cs_track_check(p->rdev, track);
1138 case PACKET3_3D_DRAW_VBUF_2:
1139 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1140 r = r100_cs_track_check(p->rdev, track);
1145 case PACKET3_3D_DRAW_INDX:
1146 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1147 r = r100_cs_track_check(p->rdev, track);
1152 case PACKET3_3D_DRAW_INDX_2:
1153 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1154 r = r100_cs_track_check(p->rdev, track);
1162 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1168 int r300_cs_parse(struct radeon_cs_parser *p)
1170 struct radeon_cs_packet pkt;
1171 struct r100_cs_track *track;
1174 track = kzalloc(sizeof(*track), GFP_KERNEL);
1175 r100_cs_track_clear(p->rdev, track);
1178 r = r100_cs_packet_parse(p, &pkt, p->idx);
1182 p->idx += pkt.count + 2;
1185 r = r100_cs_parse_packet0(p, &pkt,
1186 p->rdev->config.r300.reg_safe_bm,
1187 p->rdev->config.r300.reg_safe_bm_size,
1188 &r300_packet0_check);
1193 r = r300_packet3_check(p, &pkt);
1196 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1202 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1206 void r300_set_reg_safe(struct radeon_device *rdev)
1208 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1209 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1212 void r300_mc_program(struct radeon_device *rdev)
1214 struct r100_mc_save save;
1217 r = r100_debugfs_mc_info_init(rdev);
1219 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1222 /* Stops all mc clients */
1223 r100_mc_stop(rdev, &save);
1224 if (rdev->flags & RADEON_IS_AGP) {
1225 WREG32(R_00014C_MC_AGP_LOCATION,
1226 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1227 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1228 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1229 WREG32(R_00015C_AGP_BASE_2,
1230 upper_32_bits(rdev->mc.agp_base) & 0xff);
1232 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1233 WREG32(R_000170_AGP_BASE, 0);
1234 WREG32(R_00015C_AGP_BASE_2, 0);
1236 /* Wait for mc idle */
1237 if (r300_mc_wait_for_idle(rdev))
1238 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1239 /* Program MC, should be a 32bits limited address space */
1240 WREG32(R_000148_MC_FB_LOCATION,
1241 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1242 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1243 r100_mc_resume(rdev, &save);
1246 void r300_clock_startup(struct radeon_device *rdev)
1250 if (radeon_dynclks != -1 && radeon_dynclks)
1251 radeon_legacy_set_clock_gating(rdev, 1);
1252 /* We need to force on some of the block */
1253 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1254 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1255 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1256 tmp |= S_00000D_FORCE_VAP(1);
1257 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1260 static int r300_startup(struct radeon_device *rdev)
1264 /* set common regs */
1265 r100_set_common_regs(rdev);
1267 r300_mc_program(rdev);
1269 r300_clock_startup(rdev);
1270 /* Initialize GPU configuration (# pipes, ...) */
1271 r300_gpu_init(rdev);
1272 /* Initialize GART (initialize after TTM so we can allocate
1273 * memory through TTM but finalize after TTM) */
1274 if (rdev->flags & RADEON_IS_PCIE) {
1275 r = rv370_pcie_gart_enable(rdev);
1280 if (rdev->family == CHIP_R300 ||
1281 rdev->family == CHIP_R350 ||
1282 rdev->family == CHIP_RV350)
1283 r100_enable_bm(rdev);
1285 if (rdev->flags & RADEON_IS_PCI) {
1286 r = r100_pci_gart_enable(rdev);
1292 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1293 /* 1M ring buffer */
1294 r = r100_cp_init(rdev, 1024 * 1024);
1296 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1299 r = r100_wb_init(rdev);
1301 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1302 r = r100_ib_init(rdev);
1304 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1310 int r300_resume(struct radeon_device *rdev)
1312 /* Make sur GART are not working */
1313 if (rdev->flags & RADEON_IS_PCIE)
1314 rv370_pcie_gart_disable(rdev);
1315 if (rdev->flags & RADEON_IS_PCI)
1316 r100_pci_gart_disable(rdev);
1317 /* Resume clock before doing reset */
1318 r300_clock_startup(rdev);
1319 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1320 if (radeon_gpu_reset(rdev)) {
1321 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1322 RREG32(R_000E40_RBBM_STATUS),
1323 RREG32(R_0007C0_CP_STAT));
1326 radeon_combios_asic_init(rdev->ddev);
1327 /* Resume clock after posting */
1328 r300_clock_startup(rdev);
1329 /* Initialize surface registers */
1330 radeon_surface_init(rdev);
1331 return r300_startup(rdev);
1334 int r300_suspend(struct radeon_device *rdev)
1336 r100_cp_disable(rdev);
1337 r100_wb_disable(rdev);
1338 r100_irq_disable(rdev);
1339 if (rdev->flags & RADEON_IS_PCIE)
1340 rv370_pcie_gart_disable(rdev);
1341 if (rdev->flags & RADEON_IS_PCI)
1342 r100_pci_gart_disable(rdev);
1346 void r300_fini(struct radeon_device *rdev)
1348 radeon_pm_fini(rdev);
1352 radeon_gem_fini(rdev);
1353 if (rdev->flags & RADEON_IS_PCIE)
1354 rv370_pcie_gart_fini(rdev);
1355 if (rdev->flags & RADEON_IS_PCI)
1356 r100_pci_gart_fini(rdev);
1357 radeon_agp_fini(rdev);
1358 radeon_irq_kms_fini(rdev);
1359 radeon_fence_driver_fini(rdev);
1360 radeon_bo_fini(rdev);
1361 radeon_atombios_fini(rdev);
1366 int r300_init(struct radeon_device *rdev)
1371 r100_vga_render_disable(rdev);
1372 /* Initialize scratch registers */
1373 radeon_scratch_init(rdev);
1374 /* Initialize surface registers */
1375 radeon_surface_init(rdev);
1376 /* TODO: disable VGA need to use VGA request */
1378 if (!radeon_get_bios(rdev)) {
1379 if (ASIC_IS_AVIVO(rdev))
1382 if (rdev->is_atom_bios) {
1383 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1386 r = radeon_combios_init(rdev);
1390 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1391 if (radeon_gpu_reset(rdev)) {
1393 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1394 RREG32(R_000E40_RBBM_STATUS),
1395 RREG32(R_0007C0_CP_STAT));
1397 /* check if cards are posted or not */
1398 if (radeon_boot_test_post_card(rdev) == false)
1400 /* Set asic errata */
1402 /* Initialize clocks */
1403 radeon_get_clock_info(rdev->ddev);
1404 /* Initialize power management */
1405 radeon_pm_init(rdev);
1406 /* initialize AGP */
1407 if (rdev->flags & RADEON_IS_AGP) {
1408 r = radeon_agp_init(rdev);
1410 radeon_agp_disable(rdev);
1413 /* initialize memory controller */
1416 r = radeon_fence_driver_init(rdev);
1419 r = radeon_irq_kms_init(rdev);
1422 /* Memory manager */
1423 r = radeon_bo_init(rdev);
1426 if (rdev->flags & RADEON_IS_PCIE) {
1427 r = rv370_pcie_gart_init(rdev);
1431 if (rdev->flags & RADEON_IS_PCI) {
1432 r = r100_pci_gart_init(rdev);
1436 r300_set_reg_safe(rdev);
1437 rdev->accel_working = true;
1438 r = r300_startup(rdev);
1440 /* Somethings want wront with the accel init stop accel */
1441 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1445 radeon_irq_kms_fini(rdev);
1446 if (rdev->flags & RADEON_IS_PCIE)
1447 rv370_pcie_gart_fini(rdev);
1448 if (rdev->flags & RADEON_IS_PCI)
1449 r100_pci_gart_fini(rdev);
1450 radeon_agp_fini(rdev);
1451 rdev->accel_working = false;