2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
32 #include "radeon_reg.h"
34 #include "radeon_asic.h"
35 #include "radeon_drm.h"
36 #include "r100_track.h"
39 #include "r300_reg_safe.h"
41 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
44 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
45 * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
46 * However, scheduling such write to the ring seems harmless, i suspect
47 * the CP read collide with the flush somehow, or maybe the MC, hard to
48 * tell. (Jerome Glisse)
52 * rv370,rv380 PCIE GART
54 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
56 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
61 /* Workaround HW bug do flush 2 times */
62 for (i = 0; i < 2; i++) {
63 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
64 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
65 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
66 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
71 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
73 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
75 if (i < 0 || i > rdev->gart.num_gpu_pages) {
78 addr = (lower_32_bits(addr) >> 8) |
79 ((upper_32_bits(addr) & 0xff) << 24) |
81 /* on x86 we want this to be CPU endian, on powerpc
82 * on powerpc without HW swappers, it'll get swapped on way
83 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
84 writel(addr, ((void __iomem *)ptr) + (i * 4));
88 int rv370_pcie_gart_init(struct radeon_device *rdev)
92 if (rdev->gart.table.vram.robj) {
93 WARN(1, "RV370 PCIE GART already initialized.\n");
96 /* Initialize common gart structure */
97 r = radeon_gart_init(rdev);
100 r = rv370_debugfs_pcie_gart_info_init(rdev);
102 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
103 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
104 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
105 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
106 return radeon_gart_table_vram_alloc(rdev);
109 int rv370_pcie_gart_enable(struct radeon_device *rdev)
115 if (rdev->gart.table.vram.robj == NULL) {
116 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
119 r = radeon_gart_table_vram_pin(rdev);
122 radeon_gart_restore(rdev);
123 /* discard memory request outside of configured range */
124 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
125 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
126 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
127 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
128 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
129 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
130 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
131 table_addr = rdev->gart.table_addr;
132 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
133 /* FIXME: setup default page */
134 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
135 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
137 WREG32_PCIE(0x18, 0);
138 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
139 tmp |= RADEON_PCIE_TX_GART_EN;
140 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
141 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
142 rv370_pcie_gart_tlb_flush(rdev);
143 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
144 (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
145 rdev->gart.ready = true;
149 void rv370_pcie_gart_disable(struct radeon_device *rdev)
154 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
155 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
156 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
157 if (rdev->gart.table.vram.robj) {
158 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
159 if (likely(r == 0)) {
160 radeon_bo_kunmap(rdev->gart.table.vram.robj);
161 radeon_bo_unpin(rdev->gart.table.vram.robj);
162 radeon_bo_unreserve(rdev->gart.table.vram.robj);
167 void rv370_pcie_gart_fini(struct radeon_device *rdev)
169 radeon_gart_fini(rdev);
170 rv370_pcie_gart_disable(rdev);
171 radeon_gart_table_vram_free(rdev);
174 void r300_fence_ring_emit(struct radeon_device *rdev,
175 struct radeon_fence *fence)
177 /* Who ever call radeon_fence_emit should call ring_lock and ask
178 * for enough space (today caller are ib schedule and buffer move) */
179 /* Write SC register so SC & US assert idle */
180 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
181 radeon_ring_write(rdev, 0);
182 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
183 radeon_ring_write(rdev, 0);
185 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
186 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
187 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
188 radeon_ring_write(rdev, R300_ZC_FLUSH);
189 /* Wait until IDLE & CLEAN */
190 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
191 radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
192 RADEON_WAIT_2D_IDLECLEAN |
193 RADEON_WAIT_DMA_GUI_IDLE));
194 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
195 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
196 RADEON_HDP_READ_BUFFER_INVALIDATE);
197 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
198 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
199 /* Emit fence sequence & fire IRQ */
200 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
201 radeon_ring_write(rdev, fence->seq);
202 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
203 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
206 void r300_ring_start(struct radeon_device *rdev)
208 unsigned gb_tile_config;
211 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
212 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
213 switch(rdev->num_gb_pipes) {
215 gb_tile_config |= R300_PIPE_COUNT_R300;
218 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
221 gb_tile_config |= R300_PIPE_COUNT_R420;
225 gb_tile_config |= R300_PIPE_COUNT_RV350;
229 r = radeon_ring_lock(rdev, 64);
233 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
234 radeon_ring_write(rdev,
235 RADEON_ISYNC_ANY2D_IDLE3D |
236 RADEON_ISYNC_ANY3D_IDLE2D |
237 RADEON_ISYNC_WAIT_IDLEGUI |
238 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
239 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
240 radeon_ring_write(rdev, gb_tile_config);
241 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
242 radeon_ring_write(rdev,
243 RADEON_WAIT_2D_IDLECLEAN |
244 RADEON_WAIT_3D_IDLECLEAN);
245 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
246 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
247 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
248 radeon_ring_write(rdev, 0);
249 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
250 radeon_ring_write(rdev, 0);
251 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
252 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
253 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
254 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
255 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
256 radeon_ring_write(rdev,
257 RADEON_WAIT_2D_IDLECLEAN |
258 RADEON_WAIT_3D_IDLECLEAN);
259 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
260 radeon_ring_write(rdev, 0);
261 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
262 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
263 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
264 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
265 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
266 radeon_ring_write(rdev,
267 ((6 << R300_MS_X0_SHIFT) |
268 (6 << R300_MS_Y0_SHIFT) |
269 (6 << R300_MS_X1_SHIFT) |
270 (6 << R300_MS_Y1_SHIFT) |
271 (6 << R300_MS_X2_SHIFT) |
272 (6 << R300_MS_Y2_SHIFT) |
273 (6 << R300_MSBD0_Y_SHIFT) |
274 (6 << R300_MSBD0_X_SHIFT)));
275 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
276 radeon_ring_write(rdev,
277 ((6 << R300_MS_X3_SHIFT) |
278 (6 << R300_MS_Y3_SHIFT) |
279 (6 << R300_MS_X4_SHIFT) |
280 (6 << R300_MS_Y4_SHIFT) |
281 (6 << R300_MS_X5_SHIFT) |
282 (6 << R300_MS_Y5_SHIFT) |
283 (6 << R300_MSBD1_SHIFT)));
284 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
285 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
286 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
287 radeon_ring_write(rdev,
288 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
289 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
290 radeon_ring_write(rdev,
291 R300_GEOMETRY_ROUND_NEAREST |
292 R300_COLOR_ROUND_NEAREST);
293 radeon_ring_unlock_commit(rdev);
296 void r300_errata(struct radeon_device *rdev)
298 rdev->pll_errata = 0;
300 if (rdev->family == CHIP_R300 &&
301 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
302 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
306 int r300_mc_wait_for_idle(struct radeon_device *rdev)
311 for (i = 0; i < rdev->usec_timeout; i++) {
313 tmp = RREG32(RADEON_MC_STATUS);
314 if (tmp & R300_MC_IDLE) {
322 void r300_gpu_init(struct radeon_device *rdev)
324 uint32_t gb_tile_config, tmp;
326 r100_hdp_reset(rdev);
327 /* FIXME: rv380 one pipes ? */
328 if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
330 rdev->num_gb_pipes = 2;
332 /* rv350,rv370,rv380 */
333 rdev->num_gb_pipes = 1;
335 rdev->num_z_pipes = 1;
336 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
337 switch (rdev->num_gb_pipes) {
339 gb_tile_config |= R300_PIPE_COUNT_R300;
342 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
345 gb_tile_config |= R300_PIPE_COUNT_R420;
349 gb_tile_config |= R300_PIPE_COUNT_RV350;
352 WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
354 if (r100_gui_wait_for_idle(rdev)) {
355 printk(KERN_WARNING "Failed to wait GUI idle while "
356 "programming pipes. Bad things might happen.\n");
359 tmp = RREG32(R300_DST_PIPE_CONFIG);
360 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
362 WREG32(R300_RB2D_DSTCACHE_MODE,
363 R300_DC_AUTOFLUSH_ENABLE |
364 R300_DC_DC_DISABLE_IGNORE_PE);
366 if (r100_gui_wait_for_idle(rdev)) {
367 printk(KERN_WARNING "Failed to wait GUI idle while "
368 "programming pipes. Bad things might happen.\n");
370 if (r300_mc_wait_for_idle(rdev)) {
371 printk(KERN_WARNING "Failed to wait MC idle while "
372 "programming pipes. Bad things might happen.\n");
374 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
375 rdev->num_gb_pipes, rdev->num_z_pipes);
378 int r300_ga_reset(struct radeon_device *rdev)
384 reinit_cp = rdev->cp.ready;
385 rdev->cp.ready = false;
386 for (i = 0; i < rdev->usec_timeout; i++) {
387 WREG32(RADEON_CP_CSQ_MODE, 0);
388 WREG32(RADEON_CP_CSQ_CNTL, 0);
389 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
390 (void)RREG32(RADEON_RBBM_SOFT_RESET);
392 WREG32(RADEON_RBBM_SOFT_RESET, 0);
393 /* Wait to prevent race in RBBM_STATUS */
395 tmp = RREG32(RADEON_RBBM_STATUS);
396 if (tmp & ((1 << 20) | (1 << 26))) {
397 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
398 /* GA still busy soft reset it */
399 WREG32(0x429C, 0x200);
400 WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
401 WREG32(R300_RE_SCISSORS_TL, 0);
402 WREG32(R300_RE_SCISSORS_BR, 0);
405 /* Wait to prevent race in RBBM_STATUS */
407 tmp = RREG32(RADEON_RBBM_STATUS);
408 if (!(tmp & ((1 << 20) | (1 << 26)))) {
412 for (i = 0; i < rdev->usec_timeout; i++) {
413 tmp = RREG32(RADEON_RBBM_STATUS);
414 if (!(tmp & ((1 << 20) | (1 << 26)))) {
415 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
418 return r100_cp_init(rdev, rdev->cp.ring_size);
424 tmp = RREG32(RADEON_RBBM_STATUS);
425 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
429 int r300_gpu_reset(struct radeon_device *rdev)
433 /* reset order likely matter */
434 status = RREG32(RADEON_RBBM_STATUS);
436 r100_hdp_reset(rdev);
438 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
439 r100_rb2d_reset(rdev);
442 if (status & ((1 << 20) | (1 << 26))) {
446 status = RREG32(RADEON_RBBM_STATUS);
447 if (status & (1 << 16)) {
450 /* Check if GPU is idle */
451 status = RREG32(RADEON_RBBM_STATUS);
452 if (status & RADEON_RBBM_ACTIVE) {
453 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
456 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
462 * r300,r350,rv350,rv380 VRAM info
464 void r300_mc_init(struct radeon_device *rdev)
469 /* DDR for all card after R300 & IGP */
470 rdev->mc.vram_is_ddr = true;
471 tmp = RREG32(RADEON_MEM_CNTL);
472 tmp &= R300_MEM_NUM_CHANNELS_MASK;
474 case 0: rdev->mc.vram_width = 64; break;
475 case 1: rdev->mc.vram_width = 128; break;
476 case 2: rdev->mc.vram_width = 256; break;
477 default: rdev->mc.vram_width = 128; break;
479 r100_vram_init_sizes(rdev);
480 base = rdev->mc.aper_base;
481 if (rdev->flags & RADEON_IS_IGP)
482 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
483 radeon_vram_location(rdev, &rdev->mc, base);
484 if (!(rdev->flags & RADEON_IS_AGP))
485 radeon_gtt_location(rdev, &rdev->mc);
486 radeon_update_bandwidth_info(rdev);
489 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
491 uint32_t link_width_cntl, mask;
493 if (rdev->flags & RADEON_IS_IGP)
496 if (!(rdev->flags & RADEON_IS_PCIE))
499 /* FIXME wait for idle */
503 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
506 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
509 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
512 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
515 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
518 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
522 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
526 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
528 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
529 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
532 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
533 RADEON_PCIE_LC_RECONFIG_NOW |
534 RADEON_PCIE_LC_RECONFIG_LATER |
535 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
536 link_width_cntl |= mask;
537 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
538 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
539 RADEON_PCIE_LC_RECONFIG_NOW));
541 /* wait for lane set to complete */
542 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
543 while (link_width_cntl == 0xffffffff)
544 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
548 int rv370_get_pcie_lanes(struct radeon_device *rdev)
552 if (rdev->flags & RADEON_IS_IGP)
555 if (!(rdev->flags & RADEON_IS_PCIE))
558 /* FIXME wait for idle */
560 if (rdev->family < CHIP_R600)
561 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
563 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
565 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
566 case RADEON_PCIE_LC_LINK_WIDTH_X0:
568 case RADEON_PCIE_LC_LINK_WIDTH_X1:
570 case RADEON_PCIE_LC_LINK_WIDTH_X2:
572 case RADEON_PCIE_LC_LINK_WIDTH_X4:
574 case RADEON_PCIE_LC_LINK_WIDTH_X8:
576 case RADEON_PCIE_LC_LINK_WIDTH_X16:
582 #if defined(CONFIG_DEBUG_FS)
583 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
585 struct drm_info_node *node = (struct drm_info_node *) m->private;
586 struct drm_device *dev = node->minor->dev;
587 struct radeon_device *rdev = dev->dev_private;
590 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
591 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
592 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
593 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
594 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
595 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
596 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
597 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
598 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
599 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
600 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
601 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
602 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
603 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
607 static struct drm_info_list rv370_pcie_gart_info_list[] = {
608 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
612 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
614 #if defined(CONFIG_DEBUG_FS)
615 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
621 static int r300_packet0_check(struct radeon_cs_parser *p,
622 struct radeon_cs_packet *pkt,
623 unsigned idx, unsigned reg)
625 struct radeon_cs_reloc *reloc;
626 struct r100_cs_track *track;
627 volatile uint32_t *ib;
628 uint32_t tmp, tile_flags = 0;
634 track = (struct r100_cs_track *)p->track;
635 idx_value = radeon_get_ib_value(p, idx);
638 case AVIVO_D1MODE_VLINE_START_END:
639 case RADEON_CRTC_GUI_TRIG_VLINE:
640 r = r100_cs_packet_parse_vline(p);
642 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
644 r100_cs_dump_packet(p, pkt);
648 case RADEON_DST_PITCH_OFFSET:
649 case RADEON_SRC_PITCH_OFFSET:
650 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
654 case R300_RB3D_COLOROFFSET0:
655 case R300_RB3D_COLOROFFSET1:
656 case R300_RB3D_COLOROFFSET2:
657 case R300_RB3D_COLOROFFSET3:
658 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
659 r = r100_cs_packet_next_reloc(p, &reloc);
661 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
663 r100_cs_dump_packet(p, pkt);
666 track->cb[i].robj = reloc->robj;
667 track->cb[i].offset = idx_value;
668 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
670 case R300_ZB_DEPTHOFFSET:
671 r = r100_cs_packet_next_reloc(p, &reloc);
673 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
675 r100_cs_dump_packet(p, pkt);
678 track->zb.robj = reloc->robj;
679 track->zb.offset = idx_value;
680 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
682 case R300_TX_OFFSET_0:
683 case R300_TX_OFFSET_0+4:
684 case R300_TX_OFFSET_0+8:
685 case R300_TX_OFFSET_0+12:
686 case R300_TX_OFFSET_0+16:
687 case R300_TX_OFFSET_0+20:
688 case R300_TX_OFFSET_0+24:
689 case R300_TX_OFFSET_0+28:
690 case R300_TX_OFFSET_0+32:
691 case R300_TX_OFFSET_0+36:
692 case R300_TX_OFFSET_0+40:
693 case R300_TX_OFFSET_0+44:
694 case R300_TX_OFFSET_0+48:
695 case R300_TX_OFFSET_0+52:
696 case R300_TX_OFFSET_0+56:
697 case R300_TX_OFFSET_0+60:
698 i = (reg - R300_TX_OFFSET_0) >> 2;
699 r = r100_cs_packet_next_reloc(p, &reloc);
701 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
703 r100_cs_dump_packet(p, pkt);
707 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
708 tile_flags |= R300_TXO_MACRO_TILE;
709 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
710 tile_flags |= R300_TXO_MICRO_TILE;
711 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
712 tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
714 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
717 track->textures[i].robj = reloc->robj;
719 /* Tracked registers */
722 track->vap_vf_cntl = idx_value;
726 track->vtx_size = idx_value & 0x7F;
729 /* VAP_VF_MAX_VTX_INDX */
730 track->max_indx = idx_value & 0x00FFFFFFUL;
734 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
735 if (p->rdev->family < CHIP_RV515) {
741 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
747 /* RB3D_COLORPITCH0 */
748 /* RB3D_COLORPITCH1 */
749 /* RB3D_COLORPITCH2 */
750 /* RB3D_COLORPITCH3 */
751 r = r100_cs_packet_next_reloc(p, &reloc);
753 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
755 r100_cs_dump_packet(p, pkt);
759 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
760 tile_flags |= R300_COLOR_TILE_ENABLE;
761 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
762 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
763 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
764 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
766 tmp = idx_value & ~(0x7 << 16);
770 i = (reg - 0x4E38) >> 2;
771 track->cb[i].pitch = idx_value & 0x3FFE;
772 switch (((idx_value >> 21) & 0xF)) {
776 track->cb[i].cpp = 1;
782 track->cb[i].cpp = 2;
785 track->cb[i].cpp = 4;
788 track->cb[i].cpp = 8;
791 track->cb[i].cpp = 16;
794 DRM_ERROR("Invalid color buffer format (%d) !\n",
795 ((idx_value >> 21) & 0xF));
802 track->z_enabled = true;
804 track->z_enabled = false;
809 switch ((idx_value & 0xF)) {
818 DRM_ERROR("Invalid z buffer format (%d) !\n",
825 r = r100_cs_packet_next_reloc(p, &reloc);
827 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
829 r100_cs_dump_packet(p, pkt);
833 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
834 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
835 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
836 tile_flags |= R300_DEPTHMICROTILE_TILED;
837 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
838 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
840 tmp = idx_value & ~(0x7 << 16);
844 track->zb.pitch = idx_value & 0x3FFC;
847 for (i = 0; i < 16; i++) {
850 enabled = !!(idx_value & (1 << i));
851 track->textures[i].enabled = enabled;
870 /* TX_FORMAT1_[0-15] */
871 i = (reg - 0x44C0) >> 2;
872 tmp = (idx_value >> 25) & 0x3;
873 track->textures[i].tex_coord_type = tmp;
874 switch ((idx_value & 0x1F)) {
875 case R300_TX_FORMAT_X8:
876 case R300_TX_FORMAT_Y4X4:
877 case R300_TX_FORMAT_Z3Y3X2:
878 track->textures[i].cpp = 1;
880 case R300_TX_FORMAT_X16:
881 case R300_TX_FORMAT_Y8X8:
882 case R300_TX_FORMAT_Z5Y6X5:
883 case R300_TX_FORMAT_Z6Y5X5:
884 case R300_TX_FORMAT_W4Z4Y4X4:
885 case R300_TX_FORMAT_W1Z5Y5X5:
886 case R300_TX_FORMAT_D3DMFT_CxV8U8:
887 case R300_TX_FORMAT_B8G8_B8G8:
888 case R300_TX_FORMAT_G8R8_G8B8:
889 track->textures[i].cpp = 2;
891 case R300_TX_FORMAT_Y16X16:
892 case R300_TX_FORMAT_Z11Y11X10:
893 case R300_TX_FORMAT_Z10Y11X11:
894 case R300_TX_FORMAT_W8Z8Y8X8:
895 case R300_TX_FORMAT_W2Z10Y10X10:
897 case R300_TX_FORMAT_FL_I32:
899 track->textures[i].cpp = 4;
901 case R300_TX_FORMAT_W16Z16Y16X16:
902 case R300_TX_FORMAT_FL_R16G16B16A16:
903 case R300_TX_FORMAT_FL_I32A32:
904 track->textures[i].cpp = 8;
906 case R300_TX_FORMAT_FL_R32G32B32A32:
907 track->textures[i].cpp = 16;
909 case R300_TX_FORMAT_DXT1:
910 track->textures[i].cpp = 1;
911 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
913 case R300_TX_FORMAT_ATI2N:
914 if (p->rdev->family < CHIP_R420) {
915 DRM_ERROR("Invalid texture format %u\n",
919 /* The same rules apply as for DXT3/5. */
921 case R300_TX_FORMAT_DXT3:
922 case R300_TX_FORMAT_DXT5:
923 track->textures[i].cpp = 1;
924 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
927 DRM_ERROR("Invalid texture format %u\n",
949 /* TX_FILTER0_[0-15] */
950 i = (reg - 0x4400) >> 2;
951 tmp = idx_value & 0x7;
952 if (tmp == 2 || tmp == 4 || tmp == 6) {
953 track->textures[i].roundup_w = false;
955 tmp = (idx_value >> 3) & 0x7;
956 if (tmp == 2 || tmp == 4 || tmp == 6) {
957 track->textures[i].roundup_h = false;
976 /* TX_FORMAT2_[0-15] */
977 i = (reg - 0x4500) >> 2;
978 tmp = idx_value & 0x3FFF;
979 track->textures[i].pitch = tmp + 1;
980 if (p->rdev->family >= CHIP_RV515) {
981 tmp = ((idx_value >> 15) & 1) << 11;
982 track->textures[i].width_11 = tmp;
983 tmp = ((idx_value >> 16) & 1) << 11;
984 track->textures[i].height_11 = tmp;
987 if (idx_value & (1 << 14)) {
988 /* The same rules apply as for DXT1. */
989 track->textures[i].compress_format =
990 R100_TRACK_COMP_DXT1;
992 } else if (idx_value & (1 << 14)) {
993 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1013 /* TX_FORMAT0_[0-15] */
1014 i = (reg - 0x4480) >> 2;
1015 tmp = idx_value & 0x7FF;
1016 track->textures[i].width = tmp + 1;
1017 tmp = (idx_value >> 11) & 0x7FF;
1018 track->textures[i].height = tmp + 1;
1019 tmp = (idx_value >> 26) & 0xF;
1020 track->textures[i].num_levels = tmp;
1021 tmp = idx_value & (1 << 31);
1022 track->textures[i].use_pitch = !!tmp;
1023 tmp = (idx_value >> 22) & 0xF;
1024 track->textures[i].txdepth = tmp;
1026 case R300_ZB_ZPASS_ADDR:
1027 r = r100_cs_packet_next_reloc(p, &reloc);
1029 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1031 r100_cs_dump_packet(p, pkt);
1034 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1037 /* RB3D_COLOR_CHANNEL_MASK */
1038 track->color_channel_mask = idx_value;
1042 track->fastfill = !!(idx_value & (1 << 2));
1045 /* RB3D_BLENDCNTL */
1046 track->blend_read_enable = !!(idx_value & (1 << 2));
1049 /* valid register only on RV530 */
1050 if (p->rdev->family == CHIP_RV530)
1052 /* fallthrough do not move */
1054 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1061 static int r300_packet3_check(struct radeon_cs_parser *p,
1062 struct radeon_cs_packet *pkt)
1064 struct radeon_cs_reloc *reloc;
1065 struct r100_cs_track *track;
1066 volatile uint32_t *ib;
1072 track = (struct r100_cs_track *)p->track;
1073 switch(pkt->opcode) {
1074 case PACKET3_3D_LOAD_VBPNTR:
1075 r = r100_packet3_load_vbpntr(p, pkt, idx);
1079 case PACKET3_INDX_BUFFER:
1080 r = r100_cs_packet_next_reloc(p, &reloc);
1082 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1083 r100_cs_dump_packet(p, pkt);
1086 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1087 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1093 case PACKET3_3D_DRAW_IMMD:
1094 /* Number of dwords is vtx_size * (num_vertices - 1)
1095 * PRIM_WALK must be equal to 3 vertex data in embedded
1097 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1098 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1101 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1102 track->immd_dwords = pkt->count - 1;
1103 r = r100_cs_track_check(p->rdev, track);
1108 case PACKET3_3D_DRAW_IMMD_2:
1109 /* Number of dwords is vtx_size * (num_vertices - 1)
1110 * PRIM_WALK must be equal to 3 vertex data in embedded
1112 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1113 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1116 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1117 track->immd_dwords = pkt->count;
1118 r = r100_cs_track_check(p->rdev, track);
1123 case PACKET3_3D_DRAW_VBUF:
1124 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1125 r = r100_cs_track_check(p->rdev, track);
1130 case PACKET3_3D_DRAW_VBUF_2:
1131 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1132 r = r100_cs_track_check(p->rdev, track);
1137 case PACKET3_3D_DRAW_INDX:
1138 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1139 r = r100_cs_track_check(p->rdev, track);
1144 case PACKET3_3D_DRAW_INDX_2:
1145 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1146 r = r100_cs_track_check(p->rdev, track);
1154 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1160 int r300_cs_parse(struct radeon_cs_parser *p)
1162 struct radeon_cs_packet pkt;
1163 struct r100_cs_track *track;
1166 track = kzalloc(sizeof(*track), GFP_KERNEL);
1167 r100_cs_track_clear(p->rdev, track);
1170 r = r100_cs_packet_parse(p, &pkt, p->idx);
1174 p->idx += pkt.count + 2;
1177 r = r100_cs_parse_packet0(p, &pkt,
1178 p->rdev->config.r300.reg_safe_bm,
1179 p->rdev->config.r300.reg_safe_bm_size,
1180 &r300_packet0_check);
1185 r = r300_packet3_check(p, &pkt);
1188 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1194 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1198 void r300_set_reg_safe(struct radeon_device *rdev)
1200 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1201 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1204 void r300_mc_program(struct radeon_device *rdev)
1206 struct r100_mc_save save;
1209 r = r100_debugfs_mc_info_init(rdev);
1211 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1214 /* Stops all mc clients */
1215 r100_mc_stop(rdev, &save);
1216 if (rdev->flags & RADEON_IS_AGP) {
1217 WREG32(R_00014C_MC_AGP_LOCATION,
1218 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1219 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1220 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1221 WREG32(R_00015C_AGP_BASE_2,
1222 upper_32_bits(rdev->mc.agp_base) & 0xff);
1224 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1225 WREG32(R_000170_AGP_BASE, 0);
1226 WREG32(R_00015C_AGP_BASE_2, 0);
1228 /* Wait for mc idle */
1229 if (r300_mc_wait_for_idle(rdev))
1230 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1231 /* Program MC, should be a 32bits limited address space */
1232 WREG32(R_000148_MC_FB_LOCATION,
1233 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1234 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1235 r100_mc_resume(rdev, &save);
1238 void r300_clock_startup(struct radeon_device *rdev)
1242 if (radeon_dynclks != -1 && radeon_dynclks)
1243 radeon_legacy_set_clock_gating(rdev, 1);
1244 /* We need to force on some of the block */
1245 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1246 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1247 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1248 tmp |= S_00000D_FORCE_VAP(1);
1249 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1252 static int r300_startup(struct radeon_device *rdev)
1256 /* set common regs */
1257 r100_set_common_regs(rdev);
1259 r300_mc_program(rdev);
1261 r300_clock_startup(rdev);
1262 /* Initialize GPU configuration (# pipes, ...) */
1263 r300_gpu_init(rdev);
1264 /* Initialize GART (initialize after TTM so we can allocate
1265 * memory through TTM but finalize after TTM) */
1266 if (rdev->flags & RADEON_IS_PCIE) {
1267 r = rv370_pcie_gart_enable(rdev);
1272 if (rdev->family == CHIP_R300 ||
1273 rdev->family == CHIP_R350 ||
1274 rdev->family == CHIP_RV350)
1275 r100_enable_bm(rdev);
1277 if (rdev->flags & RADEON_IS_PCI) {
1278 r = r100_pci_gart_enable(rdev);
1284 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1285 /* 1M ring buffer */
1286 r = r100_cp_init(rdev, 1024 * 1024);
1288 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1291 r = r100_wb_init(rdev);
1293 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1294 r = r100_ib_init(rdev);
1296 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1302 int r300_resume(struct radeon_device *rdev)
1304 /* Make sur GART are not working */
1305 if (rdev->flags & RADEON_IS_PCIE)
1306 rv370_pcie_gart_disable(rdev);
1307 if (rdev->flags & RADEON_IS_PCI)
1308 r100_pci_gart_disable(rdev);
1309 /* Resume clock before doing reset */
1310 r300_clock_startup(rdev);
1311 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1312 if (radeon_gpu_reset(rdev)) {
1313 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1314 RREG32(R_000E40_RBBM_STATUS),
1315 RREG32(R_0007C0_CP_STAT));
1318 radeon_combios_asic_init(rdev->ddev);
1319 /* Resume clock after posting */
1320 r300_clock_startup(rdev);
1321 /* Initialize surface registers */
1322 radeon_surface_init(rdev);
1323 return r300_startup(rdev);
1326 int r300_suspend(struct radeon_device *rdev)
1328 r100_cp_disable(rdev);
1329 r100_wb_disable(rdev);
1330 r100_irq_disable(rdev);
1331 if (rdev->flags & RADEON_IS_PCIE)
1332 rv370_pcie_gart_disable(rdev);
1333 if (rdev->flags & RADEON_IS_PCI)
1334 r100_pci_gart_disable(rdev);
1338 void r300_fini(struct radeon_device *rdev)
1340 radeon_pm_fini(rdev);
1344 radeon_gem_fini(rdev);
1345 if (rdev->flags & RADEON_IS_PCIE)
1346 rv370_pcie_gart_fini(rdev);
1347 if (rdev->flags & RADEON_IS_PCI)
1348 r100_pci_gart_fini(rdev);
1349 radeon_agp_fini(rdev);
1350 radeon_irq_kms_fini(rdev);
1351 radeon_fence_driver_fini(rdev);
1352 radeon_bo_fini(rdev);
1353 radeon_atombios_fini(rdev);
1358 int r300_init(struct radeon_device *rdev)
1363 r100_vga_render_disable(rdev);
1364 /* Initialize scratch registers */
1365 radeon_scratch_init(rdev);
1366 /* Initialize surface registers */
1367 radeon_surface_init(rdev);
1368 /* TODO: disable VGA need to use VGA request */
1370 if (!radeon_get_bios(rdev)) {
1371 if (ASIC_IS_AVIVO(rdev))
1374 if (rdev->is_atom_bios) {
1375 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1378 r = radeon_combios_init(rdev);
1382 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1383 if (radeon_gpu_reset(rdev)) {
1385 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1386 RREG32(R_000E40_RBBM_STATUS),
1387 RREG32(R_0007C0_CP_STAT));
1389 /* check if cards are posted or not */
1390 if (radeon_boot_test_post_card(rdev) == false)
1392 /* Set asic errata */
1394 /* Initialize clocks */
1395 radeon_get_clock_info(rdev->ddev);
1396 /* Initialize power management */
1397 radeon_pm_init(rdev);
1398 /* initialize AGP */
1399 if (rdev->flags & RADEON_IS_AGP) {
1400 r = radeon_agp_init(rdev);
1402 radeon_agp_disable(rdev);
1405 /* initialize memory controller */
1408 r = radeon_fence_driver_init(rdev);
1411 r = radeon_irq_kms_init(rdev);
1414 /* Memory manager */
1415 r = radeon_bo_init(rdev);
1418 if (rdev->flags & RADEON_IS_PCIE) {
1419 r = rv370_pcie_gart_init(rdev);
1423 if (rdev->flags & RADEON_IS_PCI) {
1424 r = r100_pci_gart_init(rdev);
1428 r300_set_reg_safe(rdev);
1429 rdev->accel_working = true;
1430 r = r300_startup(rdev);
1432 /* Somethings want wront with the accel init stop accel */
1433 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1437 radeon_irq_kms_fini(rdev);
1438 if (rdev->flags & RADEON_IS_PCIE)
1439 rv370_pcie_gart_fini(rdev);
1440 if (rdev->flags & RADEON_IS_PCI)
1441 r100_pci_gart_fini(rdev);
1442 radeon_agp_fini(rdev);
1443 rdev->accel_working = false;