2 #define R100_TRACK_MAX_TEXTURE 3
3 #define R200_TRACK_MAX_TEXTURE 6
4 #define R300_TRACK_MAX_TEXTURE 16
12 struct r100_cs_track_cb {
13 struct radeon_bo *robj;
19 struct r100_cs_track_array {
20 struct radeon_bo *robj;
24 struct r100_cs_cube_info {
25 struct radeon_bo *robj;
31 #define R100_TRACK_COMP_NONE 0
32 #define R100_TRACK_COMP_DXT1 1
33 #define R100_TRACK_COMP_DXT35 2
35 struct r100_cs_track_texture {
36 struct radeon_bo *robj;
37 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
43 unsigned tex_coord_type;
52 unsigned compress_format;
55 struct r100_cs_track_limits {
61 struct r100_cs_track {
62 struct radeon_device *rdev;
68 unsigned vap_alt_nverts;
72 unsigned color_channel_mask;
73 struct r100_cs_track_array arrays[11];
74 struct r100_cs_track_cb cb[R300_MAX_CB];
75 struct r100_cs_track_cb zb;
76 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
80 bool blend_read_enable;
83 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
84 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
85 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
86 struct radeon_cs_reloc **cs_reloc);
87 void r100_cs_dump_packet(struct radeon_cs_parser *p,
88 struct radeon_cs_packet *pkt);
90 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
92 int r200_packet0_check(struct radeon_cs_parser *p,
93 struct radeon_cs_packet *pkt,
94 unsigned idx, unsigned reg);
98 static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
99 struct radeon_cs_packet *pkt,
106 struct radeon_cs_reloc *reloc;
109 r = r100_cs_packet_next_reloc(p, &reloc);
111 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
113 r100_cs_dump_packet(p, pkt);
116 value = radeon_get_ib_value(p, idx);
117 tmp = value & 0x003fffff;
118 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
120 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
121 tile_flags |= RADEON_DST_TILE_MACRO;
122 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
123 if (reg == RADEON_SRC_PITCH_OFFSET) {
124 DRM_ERROR("Cannot src blit from microtiled surface\n");
125 r100_cs_dump_packet(p, pkt);
128 tile_flags |= RADEON_DST_TILE_MICRO;
132 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
136 static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
137 struct radeon_cs_packet *pkt,
141 struct radeon_cs_reloc *reloc;
142 struct r100_cs_track *track;
144 volatile uint32_t *ib;
148 track = (struct r100_cs_track *)p->track;
149 c = radeon_get_ib_value(p, idx++) & 0x1F;
150 track->num_arrays = c;
151 for (i = 0; i < (c - 1); i+=2, idx+=3) {
152 r = r100_cs_packet_next_reloc(p, &reloc);
154 DRM_ERROR("No reloc for packet3 %d\n",
156 r100_cs_dump_packet(p, pkt);
159 idx_value = radeon_get_ib_value(p, idx);
160 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
162 track->arrays[i + 0].esize = idx_value >> 8;
163 track->arrays[i + 0].robj = reloc->robj;
164 track->arrays[i + 0].esize &= 0x7F;
165 r = r100_cs_packet_next_reloc(p, &reloc);
167 DRM_ERROR("No reloc for packet3 %d\n",
169 r100_cs_dump_packet(p, pkt);
172 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
173 track->arrays[i + 1].robj = reloc->robj;
174 track->arrays[i + 1].esize = idx_value >> 24;
175 track->arrays[i + 1].esize &= 0x7F;
178 r = r100_cs_packet_next_reloc(p, &reloc);
180 DRM_ERROR("No reloc for packet3 %d\n",
182 r100_cs_dump_packet(p, pkt);
185 idx_value = radeon_get_ib_value(p, idx);
186 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
187 track->arrays[i + 0].robj = reloc->robj;
188 track->arrays[i + 0].esize = idx_value >> 8;
189 track->arrays[i + 0].esize &= 0x7F;