drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/module.h>
  45
  46 #include "r100_reg_safe.h"
  47 #include "rn50_reg_safe.h"
  48
  49 /* Firmware Names */
  50 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  51 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  52 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  53 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  54 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  55 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  56 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  57
  58 MODULE_FIRMWARE(FIRMWARE_R100);
  59 MODULE_FIRMWARE(FIRMWARE_R200);
  60 MODULE_FIRMWARE(FIRMWARE_R300);
  61 MODULE_FIRMWARE(FIRMWARE_R420);
  62 MODULE_FIRMWARE(FIRMWARE_RS690);
  63 MODULE_FIRMWARE(FIRMWARE_RS600);
  64 MODULE_FIRMWARE(FIRMWARE_R520);
  65
  66 #include "r100_track.h"
  67
  68 /* This files gather functions specifics to:
  69  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  70  */
  71
  72 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
  73                             struct radeon_cs_packet *pkt,
  74                             unsigned idx,
  75                             unsigned reg)
  76 {
  77         int r;
  78         u32 tile_flags = 0;
  79         u32 tmp;
  80         struct radeon_cs_reloc *reloc;
  81         u32 value;
  82
  83         r = r100_cs_packet_next_reloc(p, &reloc);
  84         if (r) {
  85                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  86                           idx, reg);
  87                 r100_cs_dump_packet(p, pkt);
  88                 return r;
  89         }
  90         value = radeon_get_ib_value(p, idx);
  91         tmp = value & 0x003fffff;
  92         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
  93
  94         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
  95                 tile_flags |= RADEON_DST_TILE_MACRO;
  96         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
  97                 if (reg == RADEON_SRC_PITCH_OFFSET) {
  98                         DRM_ERROR("Cannot src blit from microtiled surface\n");
  99                         r100_cs_dump_packet(p, pkt);
 100                         return -EINVAL;
 101                 }
 102                 tile_flags |= RADEON_DST_TILE_MICRO;
 103         }
 104
 105         tmp |= tile_flags;
 106         p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
 107         return 0;
 108 }
 109
 110 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
 111                              struct radeon_cs_packet *pkt,
 112                              int idx)
 113 {
 114         unsigned c, i;
 115         struct radeon_cs_reloc *reloc;
 116         struct r100_cs_track *track;
 117         int r = 0;
 118         volatile uint32_t *ib;
 119         u32 idx_value;
 120
 121         ib = p->ib->ptr;
 122         track = (struct r100_cs_track *)p->track;
 123         c = radeon_get_ib_value(p, idx++) & 0x1F;
 124         if (c > 16) {
 125             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
 126                       pkt->opcode);
 127             r100_cs_dump_packet(p, pkt);
 128             return -EINVAL;
 129         }
 130         track->num_arrays = c;
 131         for (i = 0; i < (c - 1); i+=2, idx+=3) {
 132                 r = r100_cs_packet_next_reloc(p, &reloc);
 133                 if (r) {
 134                         DRM_ERROR("No reloc for packet3 %d\n",
 135                                   pkt->opcode);
 136                         r100_cs_dump_packet(p, pkt);
 137                         return r;
 138                 }
 139                 idx_value = radeon_get_ib_value(p, idx);
 140                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
 141
 142                 track->arrays[i + 0].esize = idx_value >> 8;
 143                 track->arrays[i + 0].robj = reloc->robj;
 144                 track->arrays[i + 0].esize &= 0x7F;
 145                 r = r100_cs_packet_next_reloc(p, &reloc);
 146                 if (r) {
 147                         DRM_ERROR("No reloc for packet3 %d\n",
 148                                   pkt->opcode);
 149                         r100_cs_dump_packet(p, pkt);
 150                         return r;
 151                 }
 152                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
 153                 track->arrays[i + 1].robj = reloc->robj;
 154                 track->arrays[i + 1].esize = idx_value >> 24;
 155                 track->arrays[i + 1].esize &= 0x7F;
 156         }
 157         if (c & 1) {
 158                 r = r100_cs_packet_next_reloc(p, &reloc);
 159                 if (r) {
 160                         DRM_ERROR("No reloc for packet3 %d\n",
 161                                           pkt->opcode);
 162                         r100_cs_dump_packet(p, pkt);
 163                         return r;
 164                 }
 165                 idx_value = radeon_get_ib_value(p, idx);
 166                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
 167                 track->arrays[i + 0].robj = reloc->robj;
 168                 track->arrays[i + 0].esize = idx_value >> 8;
 169                 track->arrays[i + 0].esize &= 0x7F;
 170         }
 171         return r;
 172 }
 173
 174 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
 175 {
 176         /* enable the pflip int */
 177         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 178 }
 179
 180 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
 181 {
 182         /* disable the pflip int */
 183         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 184 }
 185
 186 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 187 {
 188         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 189         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 190         int i;
 191
 192         /* Lock the graphics update lock */
 193         /* update the scanout addresses */
 194         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 195
 196         /* Wait for update_pending to go high. */
 197         for (i = 0; i < rdev->usec_timeout; i++) {
 198                 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
 199                         break;
 200                 udelay(1);
 201         }
 202         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 203
 204         /* Unlock the lock, so double-buffering can take place inside vblank */
 205         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 206         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 207
 208         /* Return current update_pending status: */
 209         return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
 210 }
 211
 212 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 213 {
 214         int i;
 215         rdev->pm.dynpm_can_upclock = true;
 216         rdev->pm.dynpm_can_downclock = true;
 217
 218         switch (rdev->pm.dynpm_planned_action) {
 219         case DYNPM_ACTION_MINIMUM:
 220                 rdev->pm.requested_power_state_index = 0;
 221                 rdev->pm.dynpm_can_downclock = false;
 222                 break;
 223         case DYNPM_ACTION_DOWNCLOCK:
 224                 if (rdev->pm.current_power_state_index == 0) {
 225                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 226                         rdev->pm.dynpm_can_downclock = false;
 227                 } else {
 228                         if (rdev->pm.active_crtc_count > 1) {
 229                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 230                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 231                                                 continue;
 232                                         else if (i >= rdev->pm.current_power_state_index) {
 233                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 234                                                 break;
 235                                         } else {
 236                                                 rdev->pm.requested_power_state_index = i;
 237                                                 break;
 238                                         }
 239                                 }
 240                         } else
 241                                 rdev->pm.requested_power_state_index =
 242                                         rdev->pm.current_power_state_index - 1;
 243                 }
 244                 /* don't use the power state if crtcs are active and no display flag is set */
 245                 if ((rdev->pm.active_crtc_count > 0) &&
 246                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 247                      RADEON_PM_MODE_NO_DISPLAY)) {
 248                         rdev->pm.requested_power_state_index++;
 249                 }
 250                 break;
 251         case DYNPM_ACTION_UPCLOCK:
 252                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 253                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 254                         rdev->pm.dynpm_can_upclock = false;
 255                 } else {
 256                         if (rdev->pm.active_crtc_count > 1) {
 257                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 258                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 259                                                 continue;
 260                                         else if (i <= rdev->pm.current_power_state_index) {
 261                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 262                                                 break;
 263                                         } else {
 264                                                 rdev->pm.requested_power_state_index = i;
 265                                                 break;
 266                                         }
 267                                 }
 268                         } else
 269                                 rdev->pm.requested_power_state_index =
 270                                         rdev->pm.current_power_state_index + 1;
 271                 }
 272                 break;
 273         case DYNPM_ACTION_DEFAULT:
 274                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 275                 rdev->pm.dynpm_can_upclock = false;
 276                 break;
 277         case DYNPM_ACTION_NONE:
 278         default:
 279                 DRM_ERROR("Requested mode for not defined action\n");
 280                 return;
 281         }
 282         /* only one clock mode per power state */
 283         rdev->pm.requested_clock_mode_index = 0;
 284
 285         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 286                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 287                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 288                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 289                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 290                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 291                   pcie_lanes);
 292 }
 293
 294 void r100_pm_init_profile(struct radeon_device *rdev)
 295 {
 296         /* default */
 297         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 298         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 299         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 300         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 301         /* low sh */
 302         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 303         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 304         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 305         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 306         /* mid sh */
 307         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 308         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 309         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 310         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 311         /* high sh */
 312         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 313         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 314         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 315         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 316         /* low mh */
 317         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 318         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 319         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 320         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 321         /* mid mh */
 322         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 323         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 324         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 325         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 326         /* high mh */
 327         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 328         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 329         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 330         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 331 }
 332
 333 void r100_pm_misc(struct radeon_device *rdev)
 334 {
 335         int requested_index = rdev->pm.requested_power_state_index;
 336         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 337         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 338         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 339
 340         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 341                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 342                         tmp = RREG32(voltage->gpio.reg);
 343                         if (voltage->active_high)
 344                                 tmp |= voltage->gpio.mask;
 345                         else
 346                                 tmp &= ~(voltage->gpio.mask);
 347                         WREG32(voltage->gpio.reg, tmp);
 348                         if (voltage->delay)
 349                                 udelay(voltage->delay);
 350                 } else {
 351                         tmp = RREG32(voltage->gpio.reg);
 352                         if (voltage->active_high)
 353                                 tmp &= ~voltage->gpio.mask;
 354                         else
 355                                 tmp |= voltage->gpio.mask;
 356                         WREG32(voltage->gpio.reg, tmp);
 357                         if (voltage->delay)
 358                                 udelay(voltage->delay);
 359                 }
 360         }
 361
 362         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 363         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 364         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 365         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 366         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 367         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 368                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 369                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 370                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 371                 else
 372                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 373                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 374                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 375                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 376                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 377         } else
 378                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 379
 380         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 381                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 382                 if (voltage->delay) {
 383                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 384                         switch (voltage->delay) {
 385                         case 33:
 386                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 387                                 break;
 388                         case 66:
 389                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 390                                 break;
 391                         case 99:
 392                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 393                                 break;
 394                         case 132:
 395                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 396                                 break;
 397                         }
 398                 } else
 399                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 400         } else
 401                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 402
 403         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 404                 sclk_cntl &= ~FORCE_HDP;
 405         else
 406                 sclk_cntl |= FORCE_HDP;
 407
 408         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 409         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 410         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 411
 412         /* set pcie lanes */
 413         if ((rdev->flags & RADEON_IS_PCIE) &&
 414             !(rdev->flags & RADEON_IS_IGP) &&
 415             rdev->asic->set_pcie_lanes &&
 416             (ps->pcie_lanes !=
 417              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 418                 radeon_set_pcie_lanes(rdev,
 419                                       ps->pcie_lanes);
 420                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 421         }
 422 }
 423
 424 void r100_pm_prepare(struct radeon_device *rdev)
 425 {
 426         struct drm_device *ddev = rdev->ddev;
 427         struct drm_crtc *crtc;
 428         struct radeon_crtc *radeon_crtc;
 429         u32 tmp;
 430
 431         /* disable any active CRTCs */
 432         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 433                 radeon_crtc = to_radeon_crtc(crtc);
 434                 if (radeon_crtc->enabled) {
 435                         if (radeon_crtc->crtc_id) {
 436                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 437                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 438                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 439                         } else {
 440                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 441                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 442                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 443                         }
 444                 }
 445         }
 446 }
 447
 448 void r100_pm_finish(struct radeon_device *rdev)
 449 {
 450         struct drm_device *ddev = rdev->ddev;
 451         struct drm_crtc *crtc;
 452         struct radeon_crtc *radeon_crtc;
 453         u32 tmp;
 454
 455         /* enable any active CRTCs */
 456         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 457                 radeon_crtc = to_radeon_crtc(crtc);
 458                 if (radeon_crtc->enabled) {
 459                         if (radeon_crtc->crtc_id) {
 460                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 461                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 462                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 463                         } else {
 464                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 465                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 466                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 467                         }
 468                 }
 469         }
 470 }
 471
 472 bool r100_gui_idle(struct radeon_device *rdev)
 473 {
 474         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 475                 return false;
 476         else
 477                 return true;
 478 }
 479
 480 /* hpd for digital panel detect/disconnect */
 481 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 482 {
 483         bool connected = false;
 484
 485         switch (hpd) {
 486         case RADEON_HPD_1:
 487                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 488                         connected = true;
 489                 break;
 490         case RADEON_HPD_2:
 491                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 492                         connected = true;
 493                 break;
 494         default:
 495                 break;
 496         }
 497         return connected;
 498 }
 499
 500 void r100_hpd_set_polarity(struct radeon_device *rdev,
 501                            enum radeon_hpd_id hpd)
 502 {
 503         u32 tmp;
 504         bool connected = r100_hpd_sense(rdev, hpd);
 505
 506         switch (hpd) {
 507         case RADEON_HPD_1:
 508                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 509                 if (connected)
 510                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 511                 else
 512                         tmp |= RADEON_FP_DETECT_INT_POL;
 513                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 514                 break;
 515         case RADEON_HPD_2:
 516                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 517                 if (connected)
 518                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 519                 else
 520                         tmp |= RADEON_FP2_DETECT_INT_POL;
 521                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 522                 break;
 523         default:
 524                 break;
 525         }
 526 }
 527
 528 void r100_hpd_init(struct radeon_device *rdev)
 529 {
 530         struct drm_device *dev = rdev->ddev;
 531         struct drm_connector *connector;
 532
 533         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 534                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 535                 switch (radeon_connector->hpd.hpd) {
 536                 case RADEON_HPD_1:
 537                         rdev->irq.hpd[0] = true;
 538                         break;
 539                 case RADEON_HPD_2:
 540                         rdev->irq.hpd[1] = true;
 541                         break;
 542                 default:
 543                         break;
 544                 }
 545                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 546         }
 547         if (rdev->irq.installed)
 548                 r100_irq_set(rdev);
 549 }
 550
 551 void r100_hpd_fini(struct radeon_device *rdev)
 552 {
 553         struct drm_device *dev = rdev->ddev;
 554         struct drm_connector *connector;
 555
 556         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 557                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 558                 switch (radeon_connector->hpd.hpd) {
 559                 case RADEON_HPD_1:
 560                         rdev->irq.hpd[0] = false;
 561                         break;
 562                 case RADEON_HPD_2:
 563                         rdev->irq.hpd[1] = false;
 564                         break;
 565                 default:
 566                         break;
 567                 }
 568         }
 569 }
 570
 571 /*
 572  * PCI GART
 573  */
 574 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 575 {
 576         /* TODO: can we do somethings here ? */
 577         /* It seems hw only cache one entry so we should discard this
 578          * entry otherwise if first GPU GART read hit this entry it
 579          * could end up in wrong address. */
 580 }
 581
 582 int r100_pci_gart_init(struct radeon_device *rdev)
 583 {
 584         int r;
 585
 586         if (rdev->gart.ptr) {
 587                 WARN(1, "R100 PCI GART already initialized\n");
 588                 return 0;
 589         }
 590         /* Initialize common gart structure */
 591         r = radeon_gart_init(rdev);
 592         if (r)
 593                 return r;
 594         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 595         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 596         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 597         return radeon_gart_table_ram_alloc(rdev);
 598 }
 599
 600 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 601 void r100_enable_bm(struct radeon_device *rdev)
 602 {
 603         uint32_t tmp;
 604         /* Enable bus mastering */
 605         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 606         WREG32(RADEON_BUS_CNTL, tmp);
 607 }
 608
 609 int r100_pci_gart_enable(struct radeon_device *rdev)
 610 {
 611         uint32_t tmp;
 612
 613         radeon_gart_restore(rdev);
 614         /* discard memory request outside of configured range */
 615         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 616         WREG32(RADEON_AIC_CNTL, tmp);
 617         /* set address range for PCI address translate */
 618         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 619         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 620         /* set PCI GART page-table base address */
 621         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 622         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 623         WREG32(RADEON_AIC_CNTL, tmp);
 624         r100_pci_gart_tlb_flush(rdev);
 625         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 626                  (unsigned)(rdev->mc.gtt_size >> 20),
 627                  (unsigned long long)rdev->gart.table_addr);
 628         rdev->gart.ready = true;
 629         return 0;
 630 }
 631
 632 void r100_pci_gart_disable(struct radeon_device *rdev)
 633 {
 634         uint32_t tmp;
 635
 636         /* discard memory request outside of configured range */
 637         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 638         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 639         WREG32(RADEON_AIC_LO_ADDR, 0);
 640         WREG32(RADEON_AIC_HI_ADDR, 0);
 641 }
 642
 643 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 644 {
 645         u32 *gtt = rdev->gart.ptr;
 646
 647         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 648                 return -EINVAL;
 649         }
 650         gtt[i] = cpu_to_le32(lower_32_bits(addr));
 651         return 0;
 652 }
 653
 654 void r100_pci_gart_fini(struct radeon_device *rdev)
 655 {
 656         radeon_gart_fini(rdev);
 657         r100_pci_gart_disable(rdev);
 658         radeon_gart_table_ram_free(rdev);
 659 }
 660
 661 int r100_irq_set(struct radeon_device *rdev)
 662 {
 663         uint32_t tmp = 0;
 664
 665         if (!rdev->irq.installed) {
 666                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 667                 WREG32(R_000040_GEN_INT_CNTL, 0);
 668                 return -EINVAL;
 669         }
 670         if (rdev->irq.sw_int) {
 671                 tmp |= RADEON_SW_INT_ENABLE;
 672         }
 673         if (rdev->irq.gui_idle) {
 674                 tmp |= RADEON_GUI_IDLE_MASK;
 675         }
 676         if (rdev->irq.crtc_vblank_int[0] ||
 677             rdev->irq.pflip[0]) {
 678                 tmp |= RADEON_CRTC_VBLANK_MASK;
 679         }
 680         if (rdev->irq.crtc_vblank_int[1] ||
 681             rdev->irq.pflip[1]) {
 682                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 683         }
 684         if (rdev->irq.hpd[0]) {
 685                 tmp |= RADEON_FP_DETECT_MASK;
 686         }
 687         if (rdev->irq.hpd[1]) {
 688                 tmp |= RADEON_FP2_DETECT_MASK;
 689         }
 690         WREG32(RADEON_GEN_INT_CNTL, tmp);
 691
 692         /* read back to post the write */
 693         RREG32(RADEON_GEN_INT_CNTL);
 694
 695         return 0;
 696 }
 697
 698 void r100_irq_disable(struct radeon_device *rdev)
 699 {
 700         u32 tmp;
 701
 702         WREG32(R_000040_GEN_INT_CNTL, 0);
 703         /* Wait and acknowledge irq */
 704         mdelay(1);
 705         tmp = RREG32(R_000044_GEN_INT_STATUS);
 706         WREG32(R_000044_GEN_INT_STATUS, tmp);
 707 }
 708
 709 static uint32_t r100_irq_ack(struct radeon_device *rdev)
 710 {
 711         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 712         uint32_t irq_mask = RADEON_SW_INT_TEST |
 713                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 714                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 715
 716         /* the interrupt works, but the status bit is permanently asserted */
 717         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 718                 if (!rdev->irq.gui_idle_acked)
 719                         irq_mask |= RADEON_GUI_IDLE_STAT;
 720         }
 721
 722         if (irqs) {
 723                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 724         }
 725         return irqs & irq_mask;
 726 }
 727
 728 int r100_irq_process(struct radeon_device *rdev)
 729 {
 730         uint32_t status, msi_rearm;
 731         bool queue_hotplug = false;
 732
 733         /* reset gui idle ack.  the status bit is broken */
 734         rdev->irq.gui_idle_acked = false;
 735
 736         status = r100_irq_ack(rdev);
 737         if (!status) {
 738                 return IRQ_NONE;
 739         }
 740         if (rdev->shutdown) {
 741                 return IRQ_NONE;
 742         }
 743         while (status) {
 744                 /* SW interrupt */
 745                 if (status & RADEON_SW_INT_TEST) {
 746                         radeon_fence_process(rdev);
 747                 }
 748                 /* gui idle interrupt */
 749                 if (status & RADEON_GUI_IDLE_STAT) {
 750                         rdev->irq.gui_idle_acked = true;
 751                         rdev->pm.gui_idle = true;
 752                         wake_up(&rdev->irq.idle_queue);
 753                 }
 754                 /* Vertical blank interrupts */
 755                 if (status & RADEON_CRTC_VBLANK_STAT) {
 756                         if (rdev->irq.crtc_vblank_int[0]) {
 757                                 drm_handle_vblank(rdev->ddev, 0);
 758                                 rdev->pm.vblank_sync = true;
 759                                 wake_up(&rdev->irq.vblank_queue);
 760                         }
 761                         if (rdev->irq.pflip[0])
 762                                 radeon_crtc_handle_flip(rdev, 0);
 763                 }
 764                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 765                         if (rdev->irq.crtc_vblank_int[1]) {
 766                                 drm_handle_vblank(rdev->ddev, 1);
 767                                 rdev->pm.vblank_sync = true;
 768                                 wake_up(&rdev->irq.vblank_queue);
 769                         }
 770                         if (rdev->irq.pflip[1])
 771                                 radeon_crtc_handle_flip(rdev, 1);
 772                 }
 773                 if (status & RADEON_FP_DETECT_STAT) {
 774                         queue_hotplug = true;
 775                         DRM_DEBUG("HPD1\n");
 776                 }
 777                 if (status & RADEON_FP2_DETECT_STAT) {
 778                         queue_hotplug = true;
 779                         DRM_DEBUG("HPD2\n");
 780                 }
 781                 status = r100_irq_ack(rdev);
 782         }
 783         /* reset gui idle ack.  the status bit is broken */
 784         rdev->irq.gui_idle_acked = false;
 785         if (queue_hotplug)
 786                 schedule_work(&rdev->hotplug_work);
 787         if (rdev->msi_enabled) {
 788                 switch (rdev->family) {
 789                 case CHIP_RS400:
 790                 case CHIP_RS480:
 791                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 792                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 793                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 794                         break;
 795                 default:
 796                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 797                         break;
 798                 }
 799         }
 800         return IRQ_HANDLED;
 801 }
 802
 803 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 804 {
 805         if (crtc == 0)
 806                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 807         else
 808                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 809 }
 810
 811 /* Who ever call radeon_fence_emit should call ring_lock and ask
 812  * for enough space (today caller are ib schedule and buffer move) */
 813 void r100_fence_ring_emit(struct radeon_device *rdev,
 814                           struct radeon_fence *fence)
 815 {
 816         /* We have to make sure that caches are flushed before
 817          * CPU might read something from VRAM. */
 818         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 819         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 820         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 821         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 822         /* Wait until IDLE & CLEAN */
 823         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 824         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 825         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 826         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 827                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 828         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 829         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 830         /* Emit fence sequence & fire IRQ */
 831         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 832         radeon_ring_write(rdev, fence->seq);
 833         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 834         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 835 }
 836
 837 int r100_copy_blit(struct radeon_device *rdev,
 838                    uint64_t src_offset,
 839                    uint64_t dst_offset,
 840                    unsigned num_gpu_pages,
 841                    struct radeon_fence *fence)
 842 {
 843         uint32_t cur_pages;
 844         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
 845         uint32_t pitch;
 846         uint32_t stride_pixels;
 847         unsigned ndw;
 848         int num_loops;
 849         int r = 0;
 850
 851         /* radeon limited to 16k stride */
 852         stride_bytes &= 0x3fff;
 853         /* radeon pitch is /64 */
 854         pitch = stride_bytes / 64;
 855         stride_pixels = stride_bytes / 4;
 856         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
 857
 858         /* Ask for enough room for blit + flush + fence */
 859         ndw = 64 + (10 * num_loops);
 860         r = radeon_ring_lock(rdev, ndw);
 861         if (r) {
 862                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 863                 return -EINVAL;
 864         }
 865         while (num_gpu_pages > 0) {
 866                 cur_pages = num_gpu_pages;
 867                 if (cur_pages > 8191) {
 868                         cur_pages = 8191;
 869                 }
 870                 num_gpu_pages -= cur_pages;
 871
 872                 /* pages are in Y direction - height
 873                    page width in X direction - width */
 874                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 875                 radeon_ring_write(rdev,
 876                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 877                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 878                                   RADEON_GMC_SRC_CLIPPING |
 879                                   RADEON_GMC_DST_CLIPPING |
 880                                   RADEON_GMC_BRUSH_NONE |
 881                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 882                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 883                                   RADEON_ROP3_S |
 884                                   RADEON_DP_SRC_SOURCE_MEMORY |
 885                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 886                                   RADEON_GMC_WR_MSK_DIS);
 887                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 888                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 889                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 890                 radeon_ring_write(rdev, 0);
 891                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 892                 radeon_ring_write(rdev, num_gpu_pages);
 893                 radeon_ring_write(rdev, num_gpu_pages);
 894                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 895         }
 896         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 897         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 898         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 899         radeon_ring_write(rdev,
 900                           RADEON_WAIT_2D_IDLECLEAN |
 901                           RADEON_WAIT_HOST_IDLECLEAN |
 902                           RADEON_WAIT_DMA_GUI_IDLE);
 903         if (fence) {
 904                 r = radeon_fence_emit(rdev, fence);
 905         }
 906         radeon_ring_unlock_commit(rdev);
 907         return r;
 908 }
 909
 910 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 911 {
 912         unsigned i;
 913         u32 tmp;
 914
 915         for (i = 0; i < rdev->usec_timeout; i++) {
 916                 tmp = RREG32(R_000E40_RBBM_STATUS);
 917                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 918                         return 0;
 919                 }
 920                 udelay(1);
 921         }
 922         return -1;
 923 }
 924
 925 void r100_ring_start(struct radeon_device *rdev)
 926 {
 927         int r;
 928
 929         r = radeon_ring_lock(rdev, 2);
 930         if (r) {
 931                 return;
 932         }
 933         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 934         radeon_ring_write(rdev,
 935                           RADEON_ISYNC_ANY2D_IDLE3D |
 936                           RADEON_ISYNC_ANY3D_IDLE2D |
 937                           RADEON_ISYNC_WAIT_IDLEGUI |
 938                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 939         radeon_ring_unlock_commit(rdev);
 940 }
 941
 942
 943 /* Load the microcode for the CP */
 944 static int r100_cp_init_microcode(struct radeon_device *rdev)
 945 {
 946         struct platform_device *pdev;
 947         const char *fw_name = NULL;
 948         int err;
 949
 950         DRM_DEBUG_KMS("\n");
 951
 952         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 953         err = IS_ERR(pdev);
 954         if (err) {
 955                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 956                 return -EINVAL;
 957         }
 958         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 959             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 960             (rdev->family == CHIP_RS200)) {
 961                 DRM_INFO("Loading R100 Microcode\n");
 962                 fw_name = FIRMWARE_R100;
 963         } else if ((rdev->family == CHIP_R200) ||
 964                    (rdev->family == CHIP_RV250) ||
 965                    (rdev->family == CHIP_RV280) ||
 966                    (rdev->family == CHIP_RS300)) {
 967                 DRM_INFO("Loading R200 Microcode\n");
 968                 fw_name = FIRMWARE_R200;
 969         } else if ((rdev->family == CHIP_R300) ||
 970                    (rdev->family == CHIP_R350) ||
 971                    (rdev->family == CHIP_RV350) ||
 972                    (rdev->family == CHIP_RV380) ||
 973                    (rdev->family == CHIP_RS400) ||
 974                    (rdev->family == CHIP_RS480)) {
 975                 DRM_INFO("Loading R300 Microcode\n");
 976                 fw_name = FIRMWARE_R300;
 977         } else if ((rdev->family == CHIP_R420) ||
 978                    (rdev->family == CHIP_R423) ||
 979                    (rdev->family == CHIP_RV410)) {
 980                 DRM_INFO("Loading R400 Microcode\n");
 981                 fw_name = FIRMWARE_R420;
 982         } else if ((rdev->family == CHIP_RS690) ||
 983                    (rdev->family == CHIP_RS740)) {
 984                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 985                 fw_name = FIRMWARE_RS690;
 986         } else if (rdev->family == CHIP_RS600) {
 987                 DRM_INFO("Loading RS600 Microcode\n");
 988                 fw_name = FIRMWARE_RS600;
 989         } else if ((rdev->family == CHIP_RV515) ||
 990                    (rdev->family == CHIP_R520) ||
 991                    (rdev->family == CHIP_RV530) ||
 992                    (rdev->family == CHIP_R580) ||
 993                    (rdev->family == CHIP_RV560) ||
 994                    (rdev->family == CHIP_RV570)) {
 995                 DRM_INFO("Loading R500 Microcode\n");
 996                 fw_name = FIRMWARE_R520;
 997         }
 998
 999         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1000         platform_device_unregister(pdev);
1001         if (err) {
1002                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1003                        fw_name);
1004         } else if (rdev->me_fw->size % 8) {
1005                 printk(KERN_ERR
1006                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1007                        rdev->me_fw->size, fw_name);
1008                 err = -EINVAL;
1009                 release_firmware(rdev->me_fw);
1010                 rdev->me_fw = NULL;
1011         }
1012         return err;
1013 }
1014
1015 static void r100_cp_load_microcode(struct radeon_device *rdev)
1016 {
1017         const __be32 *fw_data;
1018         int i, size;
1019
1020         if (r100_gui_wait_for_idle(rdev)) {
1021                 printk(KERN_WARNING "Failed to wait GUI idle while "
1022                        "programming pipes. Bad things might happen.\n");
1023         }
1024
1025         if (rdev->me_fw) {
1026                 size = rdev->me_fw->size / 4;
1027                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1028                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1029                 for (i = 0; i < size; i += 2) {
1030                         WREG32(RADEON_CP_ME_RAM_DATAH,
1031                                be32_to_cpup(&fw_data[i]));
1032                         WREG32(RADEON_CP_ME_RAM_DATAL,
1033                                be32_to_cpup(&fw_data[i + 1]));
1034                 }
1035         }
1036 }
1037
1038 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1039 {
1040         unsigned rb_bufsz;
1041         unsigned rb_blksz;
1042         unsigned max_fetch;
1043         unsigned pre_write_timer;
1044         unsigned pre_write_limit;
1045         unsigned indirect2_start;
1046         unsigned indirect1_start;
1047         uint32_t tmp;
1048         int r;
1049
1050         if (r100_debugfs_cp_init(rdev)) {
1051                 DRM_ERROR("Failed to register debugfs file for CP !\n");
1052         }
1053         if (!rdev->me_fw) {
1054                 r = r100_cp_init_microcode(rdev);
1055                 if (r) {
1056                         DRM_ERROR("Failed to load firmware!\n");
1057                         return r;
1058                 }
1059         }
1060
1061         /* Align ring size */
1062         rb_bufsz = drm_order(ring_size / 8);
1063         ring_size = (1 << (rb_bufsz + 1)) * 4;
1064         r100_cp_load_microcode(rdev);
1065         r = radeon_ring_init(rdev, ring_size);
1066         if (r) {
1067                 return r;
1068         }
1069         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1070          * the rptr copy in system ram */
1071         rb_blksz = 9;
1072         /* cp will read 128bytes at a time (4 dwords) */
1073         max_fetch = 1;
1074         rdev->cp.align_mask = 16 - 1;
1075         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1076         pre_write_timer = 64;
1077         /* Force CP_RB_WPTR write if written more than one time before the
1078          * delay expire
1079          */
1080         pre_write_limit = 0;
1081         /* Setup the cp cache like this (cache size is 96 dwords) :
1082          *      RING            0  to 15
1083          *      INDIRECT1       16 to 79
1084          *      INDIRECT2       80 to 95
1085          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1086          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1087          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1088          * Idea being that most of the gpu cmd will be through indirect1 buffer
1089          * so it gets the bigger cache.
1090          */
1091         indirect2_start = 80;
1092         indirect1_start = 16;
1093         /* cp setup */
1094         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1095         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1096                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1097                REG_SET(RADEON_MAX_FETCH, max_fetch));
1098 #ifdef __BIG_ENDIAN
1099         tmp |= RADEON_BUF_SWAP_32BIT;
1100 #endif
1101         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1102
1103         /* Set ring address */
1104         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1105         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1106         /* Force read & write ptr to 0 */
1107         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1108         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1109         rdev->cp.wptr = 0;
1110         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1111
1112         /* set the wb address whether it's enabled or not */
1113         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1114                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1115         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1116
1117         if (rdev->wb.enabled)
1118                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1119         else {
1120                 tmp |= RADEON_RB_NO_UPDATE;
1121                 WREG32(R_000770_SCRATCH_UMSK, 0);
1122         }
1123
1124         WREG32(RADEON_CP_RB_CNTL, tmp);
1125         udelay(10);
1126         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1127         /* Set cp mode to bus mastering & enable cp*/
1128         WREG32(RADEON_CP_CSQ_MODE,
1129                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1130                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1131         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1132         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1133         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1134         radeon_ring_start(rdev);
1135         r = radeon_ring_test(rdev);
1136         if (r) {
1137                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1138                 return r;
1139         }
1140         rdev->cp.ready = true;
1141         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1142         return 0;
1143 }
1144
1145 void r100_cp_fini(struct radeon_device *rdev)
1146 {
1147         if (r100_cp_wait_for_idle(rdev)) {
1148                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1149         }
1150         /* Disable ring */
1151         r100_cp_disable(rdev);
1152         radeon_ring_fini(rdev);
1153         DRM_INFO("radeon: cp finalized\n");
1154 }
1155
1156 void r100_cp_disable(struct radeon_device *rdev)
1157 {
1158         /* Disable ring */
1159         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1160         rdev->cp.ready = false;
1161         WREG32(RADEON_CP_CSQ_MODE, 0);
1162         WREG32(RADEON_CP_CSQ_CNTL, 0);
1163         WREG32(R_000770_SCRATCH_UMSK, 0);
1164         if (r100_gui_wait_for_idle(rdev)) {
1165                 printk(KERN_WARNING "Failed to wait GUI idle while "
1166                        "programming pipes. Bad things might happen.\n");
1167         }
1168 }
1169
1170 void r100_cp_commit(struct radeon_device *rdev)
1171 {
1172         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1173         (void)RREG32(RADEON_CP_RB_WPTR);
1174 }
1175
1176
1177 /*
1178  * CS functions
1179  */
1180 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1181                           struct radeon_cs_packet *pkt,
1182                           const unsigned *auth, unsigned n,
1183                           radeon_packet0_check_t check)
1184 {
1185         unsigned reg;
1186         unsigned i, j, m;
1187         unsigned idx;
1188         int r;
1189
1190         idx = pkt->idx + 1;
1191         reg = pkt->reg;
1192         /* Check that register fall into register range
1193          * determined by the number of entry (n) in the
1194          * safe register bitmap.
1195          */
1196         if (pkt->one_reg_wr) {
1197                 if ((reg >> 7) > n) {
1198                         return -EINVAL;
1199                 }
1200         } else {
1201                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1202                         return -EINVAL;
1203                 }
1204         }
1205         for (i = 0; i <= pkt->count; i++, idx++) {
1206                 j = (reg >> 7);
1207                 m = 1 << ((reg >> 2) & 31);
1208                 if (auth[j] & m) {
1209                         r = check(p, pkt, idx, reg);
1210                         if (r) {
1211                                 return r;
1212                         }
1213                 }
1214                 if (pkt->one_reg_wr) {
1215                         if (!(auth[j] & m)) {
1216                                 break;
1217                         }
1218                 } else {
1219                         reg += 4;
1220                 }
1221         }
1222         return 0;
1223 }
1224
1225 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1226                          struct radeon_cs_packet *pkt)
1227 {
1228         volatile uint32_t *ib;
1229         unsigned i;
1230         unsigned idx;
1231
1232         ib = p->ib->ptr;
1233         idx = pkt->idx;
1234         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1235                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1236         }
1237 }
1238
1239 /**
1240  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1241  * @parser:     parser structure holding parsing context.
1242  * @pkt:        where to store packet informations
1243  *
1244  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1245  * if packet is bigger than remaining ib size. or if packets is unknown.
1246  **/
1247 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1248                          struct radeon_cs_packet *pkt,
1249                          unsigned idx)
1250 {
1251         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1252         uint32_t header;
1253
1254         if (idx >= ib_chunk->length_dw) {
1255                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1256                           idx, ib_chunk->length_dw);
1257                 return -EINVAL;
1258         }
1259         header = radeon_get_ib_value(p, idx);
1260         pkt->idx = idx;
1261         pkt->type = CP_PACKET_GET_TYPE(header);
1262         pkt->count = CP_PACKET_GET_COUNT(header);
1263         switch (pkt->type) {
1264         case PACKET_TYPE0:
1265                 pkt->reg = CP_PACKET0_GET_REG(header);
1266                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1267                 break;
1268         case PACKET_TYPE3:
1269                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1270                 break;
1271         case PACKET_TYPE2:
1272                 pkt->count = -1;
1273                 break;
1274         default:
1275                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1276                 return -EINVAL;
1277         }
1278         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1279                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1280                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1281                 return -EINVAL;
1282         }
1283         return 0;
1284 }
1285
1286 /**
1287  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1288  * @parser:             parser structure holding parsing context.
1289  *
1290  * Userspace sends a special sequence for VLINE waits.
1291  * PACKET0 - VLINE_START_END + value
1292  * PACKET0 - WAIT_UNTIL +_value
1293  * RELOC (P3) - crtc_id in reloc.
1294  *
1295  * This function parses this and relocates the VLINE START END
1296  * and WAIT UNTIL packets to the correct crtc.
1297  * It also detects a switched off crtc and nulls out the
1298  * wait in that case.
1299  */
1300 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1301 {
1302         struct drm_mode_object *obj;
1303         struct drm_crtc *crtc;
1304         struct radeon_crtc *radeon_crtc;
1305         struct radeon_cs_packet p3reloc, waitreloc;
1306         int crtc_id;
1307         int r;
1308         uint32_t header, h_idx, reg;
1309         volatile uint32_t *ib;
1310
1311         ib = p->ib->ptr;
1312
1313         /* parse the wait until */
1314         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1315         if (r)
1316                 return r;
1317
1318         /* check its a wait until and only 1 count */
1319         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1320             waitreloc.count != 0) {
1321                 DRM_ERROR("vline wait had illegal wait until segment\n");
1322                 return -EINVAL;
1323         }
1324
1325         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1326                 DRM_ERROR("vline wait had illegal wait until\n");
1327                 return -EINVAL;
1328         }
1329
1330         /* jump over the NOP */
1331         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1332         if (r)
1333                 return r;
1334
1335         h_idx = p->idx - 2;
1336         p->idx += waitreloc.count + 2;
1337         p->idx += p3reloc.count + 2;
1338
1339         header = radeon_get_ib_value(p, h_idx);
1340         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1341         reg = CP_PACKET0_GET_REG(header);
1342         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1343         if (!obj) {
1344                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1345                 return -EINVAL;
1346         }
1347         crtc = obj_to_crtc(obj);
1348         radeon_crtc = to_radeon_crtc(crtc);
1349         crtc_id = radeon_crtc->crtc_id;
1350
1351         if (!crtc->enabled) {
1352                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1353                 ib[h_idx + 2] = PACKET2(0);
1354                 ib[h_idx + 3] = PACKET2(0);
1355         } else if (crtc_id == 1) {
1356                 switch (reg) {
1357                 case AVIVO_D1MODE_VLINE_START_END:
1358                         header &= ~R300_CP_PACKET0_REG_MASK;
1359                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1360                         break;
1361                 case RADEON_CRTC_GUI_TRIG_VLINE:
1362                         header &= ~R300_CP_PACKET0_REG_MASK;
1363                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1364                         break;
1365                 default:
1366                         DRM_ERROR("unknown crtc reloc\n");
1367                         return -EINVAL;
1368                 }
1369                 ib[h_idx] = header;
1370                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1371         }
1372
1373         return 0;
1374 }
1375
1376 /**
1377  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1378  * @parser:             parser structure holding parsing context.
1379  * @data:               pointer to relocation data
1380  * @offset_start:       starting offset
1381  * @offset_mask:        offset mask (to align start offset on)
1382  * @reloc:              reloc informations
1383  *
1384  * Check next packet is relocation packet3, do bo validation and compute
1385  * GPU offset using the provided start.
1386  **/
1387 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1388                               struct radeon_cs_reloc **cs_reloc)
1389 {
1390         struct radeon_cs_chunk *relocs_chunk;
1391         struct radeon_cs_packet p3reloc;
1392         unsigned idx;
1393         int r;
1394
1395         if (p->chunk_relocs_idx == -1) {
1396                 DRM_ERROR("No relocation chunk !\n");
1397                 return -EINVAL;
1398         }
1399         *cs_reloc = NULL;
1400         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1401         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1402         if (r) {
1403                 return r;
1404         }
1405         p->idx += p3reloc.count + 2;
1406         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1407                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1408                           p3reloc.idx);
1409                 r100_cs_dump_packet(p, &p3reloc);
1410                 return -EINVAL;
1411         }
1412         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1413         if (idx >= relocs_chunk->length_dw) {
1414                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1415                           idx, relocs_chunk->length_dw);
1416                 r100_cs_dump_packet(p, &p3reloc);
1417                 return -EINVAL;
1418         }
1419         /* FIXME: we assume reloc size is 4 dwords */
1420         *cs_reloc = p->relocs_ptr[(idx / 4)];
1421         return 0;
1422 }
1423
1424 static int r100_get_vtx_size(uint32_t vtx_fmt)
1425 {
1426         int vtx_size;
1427         vtx_size = 2;
1428         /* ordered according to bits in spec */
1429         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1430                 vtx_size++;
1431         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1432                 vtx_size += 3;
1433         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1434                 vtx_size++;
1435         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1436                 vtx_size++;
1437         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1438                 vtx_size += 3;
1439         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1440                 vtx_size++;
1441         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1442                 vtx_size++;
1443         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1444                 vtx_size += 2;
1445         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1446                 vtx_size += 2;
1447         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1448                 vtx_size++;
1449         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1450                 vtx_size += 2;
1451         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1452                 vtx_size++;
1453         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1454                 vtx_size += 2;
1455         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1456                 vtx_size++;
1457         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1458                 vtx_size++;
1459         /* blend weight */
1460         if (vtx_fmt & (0x7 << 15))
1461                 vtx_size += (vtx_fmt >> 15) & 0x7;
1462         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1463                 vtx_size += 3;
1464         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1465                 vtx_size += 2;
1466         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1467                 vtx_size++;
1468         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1469                 vtx_size++;
1470         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1471                 vtx_size++;
1472         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1473                 vtx_size++;
1474         return vtx_size;
1475 }
1476
1477 static int r100_packet0_check(struct radeon_cs_parser *p,
1478                               struct radeon_cs_packet *pkt,
1479                               unsigned idx, unsigned reg)
1480 {
1481         struct radeon_cs_reloc *reloc;
1482         struct r100_cs_track *track;
1483         volatile uint32_t *ib;
1484         uint32_t tmp;
1485         int r;
1486         int i, face;
1487         u32 tile_flags = 0;
1488         u32 idx_value;
1489
1490         ib = p->ib->ptr;
1491         track = (struct r100_cs_track *)p->track;
1492
1493         idx_value = radeon_get_ib_value(p, idx);
1494
1495         switch (reg) {
1496         case RADEON_CRTC_GUI_TRIG_VLINE:
1497                 r = r100_cs_packet_parse_vline(p);
1498                 if (r) {
1499                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1500                                   idx, reg);
1501                         r100_cs_dump_packet(p, pkt);
1502                         return r;
1503                 }
1504                 break;
1505                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1506                  * range access */
1507         case RADEON_DST_PITCH_OFFSET:
1508         case RADEON_SRC_PITCH_OFFSET:
1509                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1510                 if (r)
1511                         return r;
1512                 break;
1513         case RADEON_RB3D_DEPTHOFFSET:
1514                 r = r100_cs_packet_next_reloc(p, &reloc);
1515                 if (r) {
1516                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1517                                   idx, reg);
1518                         r100_cs_dump_packet(p, pkt);
1519                         return r;
1520                 }
1521                 track->zb.robj = reloc->robj;
1522                 track->zb.offset = idx_value;
1523                 track->zb_dirty = true;
1524                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1525                 break;
1526         case RADEON_RB3D_COLOROFFSET:
1527                 r = r100_cs_packet_next_reloc(p, &reloc);
1528                 if (r) {
1529                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1530                                   idx, reg);
1531                         r100_cs_dump_packet(p, pkt);
1532                         return r;
1533                 }
1534                 track->cb[0].robj = reloc->robj;
1535                 track->cb[0].offset = idx_value;
1536                 track->cb_dirty = true;
1537                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1538                 break;
1539         case RADEON_PP_TXOFFSET_0:
1540         case RADEON_PP_TXOFFSET_1:
1541         case RADEON_PP_TXOFFSET_2:
1542                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1543                 r = r100_cs_packet_next_reloc(p, &reloc);
1544                 if (r) {
1545                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1546                                   idx, reg);
1547                         r100_cs_dump_packet(p, pkt);
1548                         return r;
1549                 }
1550                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1551                 track->textures[i].robj = reloc->robj;
1552                 track->tex_dirty = true;
1553                 break;
1554         case RADEON_PP_CUBIC_OFFSET_T0_0:
1555         case RADEON_PP_CUBIC_OFFSET_T0_1:
1556         case RADEON_PP_CUBIC_OFFSET_T0_2:
1557         case RADEON_PP_CUBIC_OFFSET_T0_3:
1558         case RADEON_PP_CUBIC_OFFSET_T0_4:
1559                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1560                 r = r100_cs_packet_next_reloc(p, &reloc);
1561                 if (r) {
1562                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1563                                   idx, reg);
1564                         r100_cs_dump_packet(p, pkt);
1565                         return r;
1566                 }
1567                 track->textures[0].cube_info[i].offset = idx_value;
1568                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1569                 track->textures[0].cube_info[i].robj = reloc->robj;
1570                 track->tex_dirty = true;
1571                 break;
1572         case RADEON_PP_CUBIC_OFFSET_T1_0:
1573         case RADEON_PP_CUBIC_OFFSET_T1_1:
1574         case RADEON_PP_CUBIC_OFFSET_T1_2:
1575         case RADEON_PP_CUBIC_OFFSET_T1_3:
1576         case RADEON_PP_CUBIC_OFFSET_T1_4:
1577                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1578                 r = r100_cs_packet_next_reloc(p, &reloc);
1579                 if (r) {
1580                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1581                                   idx, reg);
1582                         r100_cs_dump_packet(p, pkt);
1583                         return r;
1584                 }
1585                 track->textures[1].cube_info[i].offset = idx_value;
1586                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1587                 track->textures[1].cube_info[i].robj = reloc->robj;
1588                 track->tex_dirty = true;
1589                 break;
1590         case RADEON_PP_CUBIC_OFFSET_T2_0:
1591         case RADEON_PP_CUBIC_OFFSET_T2_1:
1592         case RADEON_PP_CUBIC_OFFSET_T2_2:
1593         case RADEON_PP_CUBIC_OFFSET_T2_3:
1594         case RADEON_PP_CUBIC_OFFSET_T2_4:
1595                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1596                 r = r100_cs_packet_next_reloc(p, &reloc);
1597                 if (r) {
1598                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1599                                   idx, reg);
1600                         r100_cs_dump_packet(p, pkt);
1601                         return r;
1602                 }
1603                 track->textures[2].cube_info[i].offset = idx_value;
1604                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1605                 track->textures[2].cube_info[i].robj = reloc->robj;
1606                 track->tex_dirty = true;
1607                 break;
1608         case RADEON_RE_WIDTH_HEIGHT:
1609                 track->maxy = ((idx_value >> 16) & 0x7FF);
1610                 track->cb_dirty = true;
1611                 track->zb_dirty = true;
1612                 break;
1613         case RADEON_RB3D_COLORPITCH:
1614                 r = r100_cs_packet_next_reloc(p, &reloc);
1615                 if (r) {
1616                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1617                                   idx, reg);
1618                         r100_cs_dump_packet(p, pkt);
1619                         return r;
1620                 }
1621
1622                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1623                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1624                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1625                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1626
1627                 tmp = idx_value & ~(0x7 << 16);
1628                 tmp |= tile_flags;
1629                 ib[idx] = tmp;
1630
1631                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1632                 track->cb_dirty = true;
1633                 break;
1634         case RADEON_RB3D_DEPTHPITCH:
1635                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1636                 track->zb_dirty = true;
1637                 break;
1638         case RADEON_RB3D_CNTL:
1639                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1640                 case 7:
1641                 case 8:
1642                 case 9:
1643                 case 11:
1644                 case 12:
1645                         track->cb[0].cpp = 1;
1646                         break;
1647                 case 3:
1648                 case 4:
1649                 case 15:
1650                         track->cb[0].cpp = 2;
1651                         break;
1652                 case 6:
1653                         track->cb[0].cpp = 4;
1654                         break;
1655                 default:
1656                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1657                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1658                         return -EINVAL;
1659                 }
1660                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1661                 track->cb_dirty = true;
1662                 track->zb_dirty = true;
1663                 break;
1664         case RADEON_RB3D_ZSTENCILCNTL:
1665                 switch (idx_value & 0xf) {
1666                 case 0:
1667                         track->zb.cpp = 2;
1668                         break;
1669                 case 2:
1670                 case 3:
1671                 case 4:
1672                 case 5:
1673                 case 9:
1674                 case 11:
1675                         track->zb.cpp = 4;
1676                         break;
1677                 default:
1678                         break;
1679                 }
1680                 track->zb_dirty = true;
1681                 break;
1682         case RADEON_RB3D_ZPASS_ADDR:
1683                 r = r100_cs_packet_next_reloc(p, &reloc);
1684                 if (r) {
1685                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1686                                   idx, reg);
1687                         r100_cs_dump_packet(p, pkt);
1688                         return r;
1689                 }
1690                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1691                 break;
1692         case RADEON_PP_CNTL:
1693                 {
1694                         uint32_t temp = idx_value >> 4;
1695                         for (i = 0; i < track->num_texture; i++)
1696                                 track->textures[i].enabled = !!(temp & (1 << i));
1697                         track->tex_dirty = true;
1698                 }
1699                 break;
1700         case RADEON_SE_VF_CNTL:
1701                 track->vap_vf_cntl = idx_value;
1702                 break;
1703         case RADEON_SE_VTX_FMT:
1704                 track->vtx_size = r100_get_vtx_size(idx_value);
1705                 break;
1706         case RADEON_PP_TEX_SIZE_0:
1707         case RADEON_PP_TEX_SIZE_1:
1708         case RADEON_PP_TEX_SIZE_2:
1709                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1710                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1711                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1712                 track->tex_dirty = true;
1713                 break;
1714         case RADEON_PP_TEX_PITCH_0:
1715         case RADEON_PP_TEX_PITCH_1:
1716         case RADEON_PP_TEX_PITCH_2:
1717                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1718                 track->textures[i].pitch = idx_value + 32;
1719                 track->tex_dirty = true;
1720                 break;
1721         case RADEON_PP_TXFILTER_0:
1722         case RADEON_PP_TXFILTER_1:
1723         case RADEON_PP_TXFILTER_2:
1724                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1725                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1726                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1727                 tmp = (idx_value >> 23) & 0x7;
1728                 if (tmp == 2 || tmp == 6)
1729                         track->textures[i].roundup_w = false;
1730                 tmp = (idx_value >> 27) & 0x7;
1731                 if (tmp == 2 || tmp == 6)
1732                         track->textures[i].roundup_h = false;
1733                 track->tex_dirty = true;
1734                 break;
1735         case RADEON_PP_TXFORMAT_0:
1736         case RADEON_PP_TXFORMAT_1:
1737         case RADEON_PP_TXFORMAT_2:
1738                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1739                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1740                         track->textures[i].use_pitch = 1;
1741                 } else {
1742                         track->textures[i].use_pitch = 0;
1743                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1744                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1745                 }
1746                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1747                         track->textures[i].tex_coord_type = 2;
1748                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1749                 case RADEON_TXFORMAT_I8:
1750                 case RADEON_TXFORMAT_RGB332:
1751                 case RADEON_TXFORMAT_Y8:
1752                         track->textures[i].cpp = 1;
1753                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1754                         break;
1755                 case RADEON_TXFORMAT_AI88:
1756                 case RADEON_TXFORMAT_ARGB1555:
1757                 case RADEON_TXFORMAT_RGB565:
1758                 case RADEON_TXFORMAT_ARGB4444:
1759                 case RADEON_TXFORMAT_VYUY422:
1760                 case RADEON_TXFORMAT_YVYU422:
1761                 case RADEON_TXFORMAT_SHADOW16:
1762                 case RADEON_TXFORMAT_LDUDV655:
1763                 case RADEON_TXFORMAT_DUDV88:
1764                         track->textures[i].cpp = 2;
1765                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1766                         break;
1767                 case RADEON_TXFORMAT_ARGB8888:
1768                 case RADEON_TXFORMAT_RGBA8888:
1769                 case RADEON_TXFORMAT_SHADOW32:
1770                 case RADEON_TXFORMAT_LDUDUV8888:
1771                         track->textures[i].cpp = 4;
1772                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1773                         break;
1774                 case RADEON_TXFORMAT_DXT1:
1775                         track->textures[i].cpp = 1;
1776                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1777                         break;
1778                 case RADEON_TXFORMAT_DXT23:
1779                 case RADEON_TXFORMAT_DXT45:
1780                         track->textures[i].cpp = 1;
1781                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1782                         break;
1783                 }
1784                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1785                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1786                 track->tex_dirty = true;
1787                 break;
1788         case RADEON_PP_CUBIC_FACES_0:
1789         case RADEON_PP_CUBIC_FACES_1:
1790         case RADEON_PP_CUBIC_FACES_2:
1791                 tmp = idx_value;
1792                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1793                 for (face = 0; face < 4; face++) {
1794                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1795                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1796                 }
1797                 track->tex_dirty = true;
1798                 break;
1799         default:
1800                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1801                        reg, idx);
1802                 return -EINVAL;
1803         }
1804         return 0;
1805 }
1806
1807 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1808                                          struct radeon_cs_packet *pkt,
1809                                          struct radeon_bo *robj)
1810 {
1811         unsigned idx;
1812         u32 value;
1813         idx = pkt->idx + 1;
1814         value = radeon_get_ib_value(p, idx + 2);
1815         if ((value + 1) > radeon_bo_size(robj)) {
1816                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1817                           "(need %u have %lu) !\n",
1818                           value + 1,
1819                           radeon_bo_size(robj));
1820                 return -EINVAL;
1821         }
1822         return 0;
1823 }
1824
1825 static int r100_packet3_check(struct radeon_cs_parser *p,
1826                               struct radeon_cs_packet *pkt)
1827 {
1828         struct radeon_cs_reloc *reloc;
1829         struct r100_cs_track *track;
1830         unsigned idx;
1831         volatile uint32_t *ib;
1832         int r;
1833
1834         ib = p->ib->ptr;
1835         idx = pkt->idx + 1;
1836         track = (struct r100_cs_track *)p->track;
1837         switch (pkt->opcode) {
1838         case PACKET3_3D_LOAD_VBPNTR:
1839                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1840                 if (r)
1841                         return r;
1842                 break;
1843         case PACKET3_INDX_BUFFER:
1844                 r = r100_cs_packet_next_reloc(p, &reloc);
1845                 if (r) {
1846                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1847                         r100_cs_dump_packet(p, pkt);
1848                         return r;
1849                 }
1850                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1851                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1852                 if (r) {
1853                         return r;
1854                 }
1855                 break;
1856         case 0x23:
1857                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1858                 r = r100_cs_packet_next_reloc(p, &reloc);
1859                 if (r) {
1860                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1861                         r100_cs_dump_packet(p, pkt);
1862                         return r;
1863                 }
1864                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1865                 track->num_arrays = 1;
1866                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1867
1868                 track->arrays[0].robj = reloc->robj;
1869                 track->arrays[0].esize = track->vtx_size;
1870
1871                 track->max_indx = radeon_get_ib_value(p, idx+1);
1872
1873                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1874                 track->immd_dwords = pkt->count - 1;
1875                 r = r100_cs_track_check(p->rdev, track);
1876                 if (r)
1877                         return r;
1878                 break;
1879         case PACKET3_3D_DRAW_IMMD:
1880                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1881                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1882                         return -EINVAL;
1883                 }
1884                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1885                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1886                 track->immd_dwords = pkt->count - 1;
1887                 r = r100_cs_track_check(p->rdev, track);
1888                 if (r)
1889                         return r;
1890                 break;
1891                 /* triggers drawing using in-packet vertex data */
1892         case PACKET3_3D_DRAW_IMMD_2:
1893                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1894                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1895                         return -EINVAL;
1896                 }
1897                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1898                 track->immd_dwords = pkt->count;
1899                 r = r100_cs_track_check(p->rdev, track);
1900                 if (r)
1901                         return r;
1902                 break;
1903                 /* triggers drawing using in-packet vertex data */
1904         case PACKET3_3D_DRAW_VBUF_2:
1905                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1906                 r = r100_cs_track_check(p->rdev, track);
1907                 if (r)
1908                         return r;
1909                 break;
1910                 /* triggers drawing of vertex buffers setup elsewhere */
1911         case PACKET3_3D_DRAW_INDX_2:
1912                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1913                 r = r100_cs_track_check(p->rdev, track);
1914                 if (r)
1915                         return r;
1916                 break;
1917                 /* triggers drawing using indices to vertex buffer */
1918         case PACKET3_3D_DRAW_VBUF:
1919                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1920                 r = r100_cs_track_check(p->rdev, track);
1921                 if (r)
1922                         return r;
1923                 break;
1924                 /* triggers drawing of vertex buffers setup elsewhere */
1925         case PACKET3_3D_DRAW_INDX:
1926                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1927                 r = r100_cs_track_check(p->rdev, track);
1928                 if (r)
1929                         return r;
1930                 break;
1931                 /* triggers drawing using indices to vertex buffer */
1932         case PACKET3_3D_CLEAR_HIZ:
1933         case PACKET3_3D_CLEAR_ZMASK:
1934                 if (p->rdev->hyperz_filp != p->filp)
1935                         return -EINVAL;
1936                 break;
1937         case PACKET3_NOP:
1938                 break;
1939         default:
1940                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1941                 return -EINVAL;
1942         }
1943         return 0;
1944 }
1945
1946 int r100_cs_parse(struct radeon_cs_parser *p)
1947 {
1948         struct radeon_cs_packet pkt;
1949         struct r100_cs_track *track;
1950         int r;
1951
1952         track = kzalloc(sizeof(*track), GFP_KERNEL);
1953         r100_cs_track_clear(p->rdev, track);
1954         p->track = track;
1955         do {
1956                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1957                 if (r) {
1958                         return r;
1959                 }
1960                 p->idx += pkt.count + 2;
1961                 switch (pkt.type) {
1962                         case PACKET_TYPE0:
1963                                 if (p->rdev->family >= CHIP_R200)
1964                                         r = r100_cs_parse_packet0(p, &pkt,
1965                                                                   p->rdev->config.r100.reg_safe_bm,
1966                                                                   p->rdev->config.r100.reg_safe_bm_size,
1967                                                                   &r200_packet0_check);
1968                                 else
1969                                         r = r100_cs_parse_packet0(p, &pkt,
1970                                                                   p->rdev->config.r100.reg_safe_bm,
1971                                                                   p->rdev->config.r100.reg_safe_bm_size,
1972                                                                   &r100_packet0_check);
1973                                 break;
1974                         case PACKET_TYPE2:
1975                                 break;
1976                         case PACKET_TYPE3:
1977                                 r = r100_packet3_check(p, &pkt);
1978                                 break;
1979                         default:
1980                                 DRM_ERROR("Unknown packet type %d !\n",
1981                                           pkt.type);
1982                                 return -EINVAL;
1983                 }
1984                 if (r) {
1985                         return r;
1986                 }
1987         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1988         return 0;
1989 }
1990
1991
1992 /*
1993  * Global GPU functions
1994  */
1995 void r100_errata(struct radeon_device *rdev)
1996 {
1997         rdev->pll_errata = 0;
1998
1999         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2000                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2001         }
2002
2003         if (rdev->family == CHIP_RV100 ||
2004             rdev->family == CHIP_RS100 ||
2005             rdev->family == CHIP_RS200) {
2006                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2007         }
2008 }
2009
2010 /* Wait for vertical sync on primary CRTC */
2011 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2012 {
2013         uint32_t crtc_gen_cntl, tmp;
2014         int i;
2015
2016         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2017         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2018             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2019                 return;
2020         }
2021         /* Clear the CRTC_VBLANK_SAVE bit */
2022         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2023         for (i = 0; i < rdev->usec_timeout; i++) {
2024                 tmp = RREG32(RADEON_CRTC_STATUS);
2025                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2026                         return;
2027                 }
2028                 DRM_UDELAY(1);
2029         }
2030 }
2031
2032 /* Wait for vertical sync on secondary CRTC */
2033 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2034 {
2035         uint32_t crtc2_gen_cntl, tmp;
2036         int i;
2037
2038         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2039         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2040             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2041                 return;
2042
2043         /* Clear the CRTC_VBLANK_SAVE bit */
2044         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2045         for (i = 0; i < rdev->usec_timeout; i++) {
2046                 tmp = RREG32(RADEON_CRTC2_STATUS);
2047                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2048                         return;
2049                 }
2050                 DRM_UDELAY(1);
2051         }
2052 }
2053
2054 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2055 {
2056         unsigned i;
2057         uint32_t tmp;
2058
2059         for (i = 0; i < rdev->usec_timeout; i++) {
2060                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2061                 if (tmp >= n) {
2062                         return 0;
2063                 }
2064                 DRM_UDELAY(1);
2065         }
2066         return -1;
2067 }
2068
2069 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2070 {
2071         unsigned i;
2072         uint32_t tmp;
2073
2074         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2075                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2076                        " Bad things might happen.\n");
2077         }
2078         for (i = 0; i < rdev->usec_timeout; i++) {
2079                 tmp = RREG32(RADEON_RBBM_STATUS);
2080                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2081                         return 0;
2082                 }
2083                 DRM_UDELAY(1);
2084         }
2085         return -1;
2086 }
2087
2088 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2089 {
2090         unsigned i;
2091         uint32_t tmp;
2092
2093         for (i = 0; i < rdev->usec_timeout; i++) {
2094                 /* read MC_STATUS */
2095                 tmp = RREG32(RADEON_MC_STATUS);
2096                 if (tmp & RADEON_MC_IDLE) {
2097                         return 0;
2098                 }
2099                 DRM_UDELAY(1);
2100         }
2101         return -1;
2102 }
2103
2104 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2105 {
2106         lockup->last_cp_rptr = cp->rptr;
2107         lockup->last_jiffies = jiffies;
2108 }
2109
2110 /**
2111  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2112  * @rdev:       radeon device structure
2113  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
2114  * @cp:         radeon_cp structure holding CP information
2115  *
2116  * We don't need to initialize the lockup tracking information as we will either
2117  * have CP rptr to a different value of jiffies wrap around which will force
2118  * initialization of the lockup tracking informations.
2119  *
2120  * A possible false positivie is if we get call after while and last_cp_rptr ==
2121  * the current CP rptr, even if it's unlikely it might happen. To avoid this
2122  * if the elapsed time since last call is bigger than 2 second than we return
2123  * false and update the tracking information. Due to this the caller must call
2124  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2125  * the fencing code should be cautious about that.
2126  *
2127  * Caller should write to the ring to force CP to do something so we don't get
2128  * false positive when CP is just gived nothing to do.
2129  *
2130  **/
2131 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2132 {
2133         unsigned long cjiffies, elapsed;
2134
2135         cjiffies = jiffies;
2136         if (!time_after(cjiffies, lockup->last_jiffies)) {
2137                 /* likely a wrap around */
2138                 lockup->last_cp_rptr = cp->rptr;
2139                 lockup->last_jiffies = jiffies;
2140                 return false;
2141         }
2142         if (cp->rptr != lockup->last_cp_rptr) {
2143                 /* CP is still working no lockup */
2144                 lockup->last_cp_rptr = cp->rptr;
2145                 lockup->last_jiffies = jiffies;
2146                 return false;
2147         }
2148         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2149         if (elapsed >= 10000) {
2150                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2151                 return true;
2152         }
2153         /* give a chance to the GPU ... */
2154         return false;
2155 }
2156
2157 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2158 {
2159         u32 rbbm_status;
2160         int r;
2161
2162         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2163         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2164                 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2165                 return false;
2166         }
2167         /* force CP activities */
2168         r = radeon_ring_lock(rdev, 2);
2169         if (!r) {
2170                 /* PACKET2 NOP */
2171                 radeon_ring_write(rdev, 0x80000000);
2172                 radeon_ring_write(rdev, 0x80000000);
2173                 radeon_ring_unlock_commit(rdev);
2174         }
2175         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2176         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2177 }
2178
2179 void r100_bm_disable(struct radeon_device *rdev)
2180 {
2181         u32 tmp;
2182         u16 tmp16;
2183
2184         /* disable bus mastering */
2185         tmp = RREG32(R_000030_BUS_CNTL);
2186         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2187         mdelay(1);
2188         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2189         mdelay(1);
2190         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2191         tmp = RREG32(RADEON_BUS_CNTL);
2192         mdelay(1);
2193         pci_read_config_word(rdev->pdev, 0x4, &tmp16);
2194         pci_write_config_word(rdev->pdev, 0x4, tmp16 & 0xFFFB);
2195         mdelay(1);
2196 }
2197
2198 int r100_asic_reset(struct radeon_device *rdev)
2199 {
2200         struct r100_mc_save save;
2201         u32 status, tmp;
2202         int ret = 0;
2203
2204         status = RREG32(R_000E40_RBBM_STATUS);
2205         if (!G_000E40_GUI_ACTIVE(status)) {
2206                 return 0;
2207         }
2208         r100_mc_stop(rdev, &save);
2209         status = RREG32(R_000E40_RBBM_STATUS);
2210         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2211         /* stop CP */
2212         WREG32(RADEON_CP_CSQ_CNTL, 0);
2213         tmp = RREG32(RADEON_CP_RB_CNTL);
2214         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2215         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2216         WREG32(RADEON_CP_RB_WPTR, 0);
2217         WREG32(RADEON_CP_RB_CNTL, tmp);
2218         /* save PCI state */
2219         pci_save_state(rdev->pdev);
2220         /* disable bus mastering */
2221         r100_bm_disable(rdev);
2222         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2223                                         S_0000F0_SOFT_RESET_RE(1) |
2224                                         S_0000F0_SOFT_RESET_PP(1) |
2225                                         S_0000F0_SOFT_RESET_RB(1));
2226         RREG32(R_0000F0_RBBM_SOFT_RESET);
2227         mdelay(500);
2228         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2229         mdelay(1);
2230         status = RREG32(R_000E40_RBBM_STATUS);
2231         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2232         /* reset CP */
2233         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2234         RREG32(R_0000F0_RBBM_SOFT_RESET);
2235         mdelay(500);
2236         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2237         mdelay(1);
2238         status = RREG32(R_000E40_RBBM_STATUS);
2239         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2240         /* restore PCI & busmastering */
2241         pci_restore_state(rdev->pdev);
2242         r100_enable_bm(rdev);
2243         /* Check if GPU is idle */
2244         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2245                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2246                 dev_err(rdev->dev, "failed to reset GPU\n");
2247                 rdev->gpu_lockup = true;
2248                 ret = -1;
2249         } else
2250                 dev_info(rdev->dev, "GPU reset succeed\n");
2251         r100_mc_resume(rdev, &save);
2252         return ret;
2253 }
2254
2255 void r100_set_common_regs(struct radeon_device *rdev)
2256 {
2257         struct drm_device *dev = rdev->ddev;
2258         bool force_dac2 = false;
2259         u32 tmp;
2260
2261         /* set these so they don't interfere with anything */
2262         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2263         WREG32(RADEON_SUBPIC_CNTL, 0);
2264         WREG32(RADEON_VIPH_CONTROL, 0);
2265         WREG32(RADEON_I2C_CNTL_1, 0);
2266         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2267         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2268         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2269
2270         /* always set up dac2 on rn50 and some rv100 as lots
2271          * of servers seem to wire it up to a VGA port but
2272          * don't report it in the bios connector
2273          * table.
2274          */
2275         switch (dev->pdev->device) {
2276                 /* RN50 */
2277         case 0x515e:
2278         case 0x5969:
2279                 force_dac2 = true;
2280                 break;
2281                 /* RV100*/
2282         case 0x5159:
2283         case 0x515a:
2284                 /* DELL triple head servers */
2285                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2286                     ((dev->pdev->subsystem_device == 0x016c) ||
2287                      (dev->pdev->subsystem_device == 0x016d) ||
2288                      (dev->pdev->subsystem_device == 0x016e) ||
2289                      (dev->pdev->subsystem_device == 0x016f) ||
2290                      (dev->pdev->subsystem_device == 0x0170) ||
2291                      (dev->pdev->subsystem_device == 0x017d) ||
2292                      (dev->pdev->subsystem_device == 0x017e) ||
2293                      (dev->pdev->subsystem_device == 0x0183) ||
2294                      (dev->pdev->subsystem_device == 0x018a) ||
2295                      (dev->pdev->subsystem_device == 0x019a)))
2296                         force_dac2 = true;
2297                 break;
2298         }
2299
2300         if (force_dac2) {
2301                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2302                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2303                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2304
2305                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2306                    enable it, even it's detected.
2307                 */
2308
2309                 /* force it to crtc0 */
2310                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2311                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2312                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2313
2314                 /* set up the TV DAC */
2315                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2316                                  RADEON_TV_DAC_STD_MASK |
2317                                  RADEON_TV_DAC_RDACPD |
2318                                  RADEON_TV_DAC_GDACPD |
2319                                  RADEON_TV_DAC_BDACPD |
2320                                  RADEON_TV_DAC_BGADJ_MASK |
2321                                  RADEON_TV_DAC_DACADJ_MASK);
2322                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2323                                 RADEON_TV_DAC_NHOLD |
2324                                 RADEON_TV_DAC_STD_PS2 |
2325                                 (0x58 << 16));
2326
2327                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2328                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2329                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2330         }
2331
2332         /* switch PM block to ACPI mode */
2333         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2334         tmp &= ~RADEON_PM_MODE_SEL;
2335         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2336
2337 }
2338
2339 /*
2340  * VRAM info
2341  */
2342 static void r100_vram_get_type(struct radeon_device *rdev)
2343 {
2344         uint32_t tmp;
2345
2346         rdev->mc.vram_is_ddr = false;
2347         if (rdev->flags & RADEON_IS_IGP)
2348                 rdev->mc.vram_is_ddr = true;
2349         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2350                 rdev->mc.vram_is_ddr = true;
2351         if ((rdev->family == CHIP_RV100) ||
2352             (rdev->family == CHIP_RS100) ||
2353             (rdev->family == CHIP_RS200)) {
2354                 tmp = RREG32(RADEON_MEM_CNTL);
2355                 if (tmp & RV100_HALF_MODE) {
2356                         rdev->mc.vram_width = 32;
2357                 } else {
2358                         rdev->mc.vram_width = 64;
2359                 }
2360                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2361                         rdev->mc.vram_width /= 4;
2362                         rdev->mc.vram_is_ddr = true;
2363                 }
2364         } else if (rdev->family <= CHIP_RV280) {
2365                 tmp = RREG32(RADEON_MEM_CNTL);
2366                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2367                         rdev->mc.vram_width = 128;
2368                 } else {
2369                         rdev->mc.vram_width = 64;
2370                 }
2371         } else {
2372                 /* newer IGPs */
2373                 rdev->mc.vram_width = 128;
2374         }
2375 }
2376
2377 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2378 {
2379         u32 aper_size;
2380         u8 byte;
2381
2382         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2383
2384         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2385          * that is has the 2nd generation multifunction PCI interface
2386          */
2387         if (rdev->family == CHIP_RV280 ||
2388             rdev->family >= CHIP_RV350) {
2389                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2390                        ~RADEON_HDP_APER_CNTL);
2391                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2392                 return aper_size * 2;
2393         }
2394
2395         /* Older cards have all sorts of funny issues to deal with. First
2396          * check if it's a multifunction card by reading the PCI config
2397          * header type... Limit those to one aperture size
2398          */
2399         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2400         if (byte & 0x80) {
2401                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2402                 DRM_INFO("Limiting VRAM to one aperture\n");
2403                 return aper_size;
2404         }
2405
2406         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2407          * have set it up. We don't write this as it's broken on some ASICs but
2408          * we expect the BIOS to have done the right thing (might be too optimistic...)
2409          */
2410         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2411                 return aper_size * 2;
2412         return aper_size;
2413 }
2414
2415 void r100_vram_init_sizes(struct radeon_device *rdev)
2416 {
2417         u64 config_aper_size;
2418
2419         /* work out accessible VRAM */
2420         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2421         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2422         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2423         /* FIXME we don't use the second aperture yet when we could use it */
2424         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2425                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2426         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2427         if (rdev->flags & RADEON_IS_IGP) {
2428                 uint32_t tom;
2429                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2430                 tom = RREG32(RADEON_NB_TOM);
2431                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2432                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2433                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2434         } else {
2435                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2436                 /* Some production boards of m6 will report 0
2437                  * if it's 8 MB
2438                  */
2439                 if (rdev->mc.real_vram_size == 0) {
2440                         rdev->mc.real_vram_size = 8192 * 1024;
2441                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2442                 }
2443                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2444                  * Novell bug 204882 + along with lots of ubuntu ones
2445                  */
2446                 if (rdev->mc.aper_size > config_aper_size)
2447                         config_aper_size = rdev->mc.aper_size;
2448
2449                 if (config_aper_size > rdev->mc.real_vram_size)
2450                         rdev->mc.mc_vram_size = config_aper_size;
2451                 else
2452                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2453         }
2454 }
2455
2456 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2457 {
2458         uint32_t temp;
2459
2460         temp = RREG32(RADEON_CONFIG_CNTL);
2461         if (state == false) {
2462                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2463                 temp |= RADEON_CFG_VGA_IO_DIS;
2464         } else {
2465                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2466         }
2467         WREG32(RADEON_CONFIG_CNTL, temp);
2468 }
2469
2470 void r100_mc_init(struct radeon_device *rdev)
2471 {
2472         u64 base;
2473
2474         r100_vram_get_type(rdev);
2475         r100_vram_init_sizes(rdev);
2476         base = rdev->mc.aper_base;
2477         if (rdev->flags & RADEON_IS_IGP)
2478                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2479         radeon_vram_location(rdev, &rdev->mc, base);
2480         rdev->mc.gtt_base_align = 0;
2481         if (!(rdev->flags & RADEON_IS_AGP))
2482                 radeon_gtt_location(rdev, &rdev->mc);
2483         radeon_update_bandwidth_info(rdev);
2484 }
2485
2486
2487 /*
2488  * Indirect registers accessor
2489  */
2490 void r100_pll_errata_after_index(struct radeon_device *rdev)
2491 {
2492         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2493                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2494                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2495         }
2496 }
2497
2498 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2499 {
2500         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2501          * or the chip could hang on a subsequent access
2502          */
2503         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2504                 udelay(5000);
2505         }
2506
2507         /* This function is required to workaround a hardware bug in some (all?)
2508          * revisions of the R300.  This workaround should be called after every
2509          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2510          * may not be correct.
2511          */
2512         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2513                 uint32_t save, tmp;
2514
2515                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2516                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2517                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2518                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2519                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2520         }
2521 }
2522
2523 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2524 {
2525         uint32_t data;
2526
2527         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2528         r100_pll_errata_after_index(rdev);
2529         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2530         r100_pll_errata_after_data(rdev);
2531         return data;
2532 }
2533
2534 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2535 {
2536         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2537         r100_pll_errata_after_index(rdev);
2538         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2539         r100_pll_errata_after_data(rdev);
2540 }
2541
2542 void r100_set_safe_registers(struct radeon_device *rdev)
2543 {
2544         if (ASIC_IS_RN50(rdev)) {
2545                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2546                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2547         } else if (rdev->family < CHIP_R200) {
2548                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2549                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2550         } else {
2551                 r200_set_safe_registers(rdev);
2552         }
2553 }
2554
2555 /*
2556  * Debugfs info
2557  */
2558 #if defined(CONFIG_DEBUG_FS)
2559 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2560 {
2561         struct drm_info_node *node = (struct drm_info_node *) m->private;
2562         struct drm_device *dev = node->minor->dev;
2563         struct radeon_device *rdev = dev->dev_private;
2564         uint32_t reg, value;
2565         unsigned i;
2566
2567         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2568         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2569         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2570         for (i = 0; i < 64; i++) {
2571                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2572                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2573                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2574                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2575                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2576         }
2577         return 0;
2578 }
2579
2580 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2581 {
2582         struct drm_info_node *node = (struct drm_info_node *) m->private;
2583         struct drm_device *dev = node->minor->dev;
2584         struct radeon_device *rdev = dev->dev_private;
2585         uint32_t rdp, wdp;
2586         unsigned count, i, j;
2587
2588         radeon_ring_free_size(rdev);
2589         rdp = RREG32(RADEON_CP_RB_RPTR);
2590         wdp = RREG32(RADEON_CP_RB_WPTR);
2591         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2592         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2593         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2594         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2595         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2596         seq_printf(m, "%u dwords in ring\n", count);
2597         for (j = 0; j <= count; j++) {
2598                 i = (rdp + j) & rdev->cp.ptr_mask;
2599                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2600         }
2601         return 0;
2602 }
2603
2604
2605 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2606 {
2607         struct drm_info_node *node = (struct drm_info_node *) m->private;
2608         struct drm_device *dev = node->minor->dev;
2609         struct radeon_device *rdev = dev->dev_private;
2610         uint32_t csq_stat, csq2_stat, tmp;
2611         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2612         unsigned i;
2613
2614         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2615         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2616         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2617         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2618         r_rptr = (csq_stat >> 0) & 0x3ff;
2619         r_wptr = (csq_stat >> 10) & 0x3ff;
2620         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2621         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2622         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2623         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2624         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2625         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2626         seq_printf(m, "Ring rptr %u\n", r_rptr);
2627         seq_printf(m, "Ring wptr %u\n", r_wptr);
2628         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2629         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2630         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2631         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2632         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2633          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2634         seq_printf(m, "Ring fifo:\n");
2635         for (i = 0; i < 256; i++) {
2636                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2637                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2638                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2639         }
2640         seq_printf(m, "Indirect1 fifo:\n");
2641         for (i = 256; i <= 512; i++) {
2642                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2643                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2644                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2645         }
2646         seq_printf(m, "Indirect2 fifo:\n");
2647         for (i = 640; i < ib1_wptr; i++) {
2648                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2649                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2650                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2651         }
2652         return 0;
2653 }
2654
2655 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2656 {
2657         struct drm_info_node *node = (struct drm_info_node *) m->private;
2658         struct drm_device *dev = node->minor->dev;
2659         struct radeon_device *rdev = dev->dev_private;
2660         uint32_t tmp;
2661
2662         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2663         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2664         tmp = RREG32(RADEON_MC_FB_LOCATION);
2665         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2666         tmp = RREG32(RADEON_BUS_CNTL);
2667         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2668         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2669         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2670         tmp = RREG32(RADEON_AGP_BASE);
2671         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2672         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2673         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2674         tmp = RREG32(0x01D0);
2675         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2676         tmp = RREG32(RADEON_AIC_LO_ADDR);
2677         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2678         tmp = RREG32(RADEON_AIC_HI_ADDR);
2679         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2680         tmp = RREG32(0x01E4);
2681         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2682         return 0;
2683 }
2684
2685 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2686         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2687 };
2688
2689 static struct drm_info_list r100_debugfs_cp_list[] = {
2690         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2691         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2692 };
2693
2694 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2695         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2696 };
2697 #endif
2698
2699 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2700 {
2701 #if defined(CONFIG_DEBUG_FS)
2702         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2703 #else
2704         return 0;
2705 #endif
2706 }
2707
2708 int r100_debugfs_cp_init(struct radeon_device *rdev)
2709 {
2710 #if defined(CONFIG_DEBUG_FS)
2711         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2712 #else
2713         return 0;
2714 #endif
2715 }
2716
2717 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2718 {
2719 #if defined(CONFIG_DEBUG_FS)
2720         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2721 #else
2722         return 0;
2723 #endif
2724 }
2725
2726 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2727                          uint32_t tiling_flags, uint32_t pitch,
2728                          uint32_t offset, uint32_t obj_size)
2729 {
2730         int surf_index = reg * 16;
2731         int flags = 0;
2732
2733         if (rdev->family <= CHIP_RS200) {
2734                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2735                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2736                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2737                 if (tiling_flags & RADEON_TILING_MACRO)
2738                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2739         } else if (rdev->family <= CHIP_RV280) {
2740                 if (tiling_flags & (RADEON_TILING_MACRO))
2741                         flags |= R200_SURF_TILE_COLOR_MACRO;
2742                 if (tiling_flags & RADEON_TILING_MICRO)
2743                         flags |= R200_SURF_TILE_COLOR_MICRO;
2744         } else {
2745                 if (tiling_flags & RADEON_TILING_MACRO)
2746                         flags |= R300_SURF_TILE_MACRO;
2747                 if (tiling_flags & RADEON_TILING_MICRO)
2748                         flags |= R300_SURF_TILE_MICRO;
2749         }
2750
2751         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2752                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2753         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2754                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2755
2756         /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2757         if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2758                 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2759                         if (ASIC_IS_RN50(rdev))
2760                                 pitch /= 16;
2761         }
2762
2763         /* r100/r200 divide by 16 */
2764         if (rdev->family < CHIP_R300)
2765                 flags |= pitch / 16;
2766         else
2767                 flags |= pitch / 8;
2768
2769
2770         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2771         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2772         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2773         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2774         return 0;
2775 }
2776
2777 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2778 {
2779         int surf_index = reg * 16;
2780         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2781 }
2782
2783 void r100_bandwidth_update(struct radeon_device *rdev)
2784 {
2785         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2786         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2787         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2788         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2789         fixed20_12 memtcas_ff[8] = {
2790                 dfixed_init(1),
2791                 dfixed_init(2),
2792                 dfixed_init(3),
2793                 dfixed_init(0),
2794                 dfixed_init_half(1),
2795                 dfixed_init_half(2),
2796                 dfixed_init(0),
2797         };
2798         fixed20_12 memtcas_rs480_ff[8] = {
2799                 dfixed_init(0),
2800                 dfixed_init(1),
2801                 dfixed_init(2),
2802                 dfixed_init(3),
2803                 dfixed_init(0),
2804                 dfixed_init_half(1),
2805                 dfixed_init_half(2),
2806                 dfixed_init_half(3),
2807         };
2808         fixed20_12 memtcas2_ff[8] = {
2809                 dfixed_init(0),
2810                 dfixed_init(1),
2811                 dfixed_init(2),
2812                 dfixed_init(3),
2813                 dfixed_init(4),
2814                 dfixed_init(5),
2815                 dfixed_init(6),
2816                 dfixed_init(7),
2817         };
2818         fixed20_12 memtrbs[8] = {
2819                 dfixed_init(1),
2820                 dfixed_init_half(1),
2821                 dfixed_init(2),
2822                 dfixed_init_half(2),
2823                 dfixed_init(3),
2824                 dfixed_init_half(3),
2825                 dfixed_init(4),
2826                 dfixed_init_half(4)
2827         };
2828         fixed20_12 memtrbs_r4xx[8] = {
2829                 dfixed_init(4),
2830                 dfixed_init(5),
2831                 dfixed_init(6),
2832                 dfixed_init(7),
2833                 dfixed_init(8),
2834                 dfixed_init(9),
2835                 dfixed_init(10),
2836                 dfixed_init(11)
2837         };
2838         fixed20_12 min_mem_eff;
2839         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2840         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2841         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2842                 disp_drain_rate2, read_return_rate;
2843         fixed20_12 time_disp1_drop_priority;
2844         int c;
2845         int cur_size = 16;       /* in octawords */
2846         int critical_point = 0, critical_point2;
2847 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2848         int stop_req, max_stop_req;
2849         struct drm_display_mode *mode1 = NULL;
2850         struct drm_display_mode *mode2 = NULL;
2851         uint32_t pixel_bytes1 = 0;
2852         uint32_t pixel_bytes2 = 0;
2853
2854         radeon_update_display_priority(rdev);
2855
2856         if (rdev->mode_info.crtcs[0]->base.enabled) {
2857                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2858                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2859         }
2860         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2861                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2862                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2863                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2864                 }
2865         }
2866
2867         min_mem_eff.full = dfixed_const_8(0);
2868         /* get modes */
2869         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2870                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2871                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2872                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2873                 /* check crtc enables */
2874                 if (mode2)
2875                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2876                 if (mode1)
2877                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2878                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2879         }
2880
2881         /*
2882          * determine is there is enough bw for current mode
2883          */
2884         sclk_ff = rdev->pm.sclk;
2885         mclk_ff = rdev->pm.mclk;
2886
2887         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2888         temp_ff.full = dfixed_const(temp);
2889         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2890
2891         pix_clk.full = 0;
2892         pix_clk2.full = 0;
2893         peak_disp_bw.full = 0;
2894         if (mode1) {
2895                 temp_ff.full = dfixed_const(1000);
2896                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2897                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2898                 temp_ff.full = dfixed_const(pixel_bytes1);
2899                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2900         }
2901         if (mode2) {
2902                 temp_ff.full = dfixed_const(1000);
2903                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2904                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2905                 temp_ff.full = dfixed_const(pixel_bytes2);
2906                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2907         }
2908
2909         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2910         if (peak_disp_bw.full >= mem_bw.full) {
2911                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2912                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2913         }
2914
2915         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2916         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2917         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2918                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2919                 mem_trp  = ((temp & 0x3)) + 1;
2920                 mem_tras = ((temp & 0x70) >> 4) + 1;
2921         } else if (rdev->family == CHIP_R300 ||
2922                    rdev->family == CHIP_R350) { /* r300, r350 */
2923                 mem_trcd = (temp & 0x7) + 1;
2924                 mem_trp = ((temp >> 8) & 0x7) + 1;
2925                 mem_tras = ((temp >> 11) & 0xf) + 4;
2926         } else if (rdev->family == CHIP_RV350 ||
2927                    rdev->family <= CHIP_RV380) {
2928                 /* rv3x0 */
2929                 mem_trcd = (temp & 0x7) + 3;
2930                 mem_trp = ((temp >> 8) & 0x7) + 3;
2931                 mem_tras = ((temp >> 11) & 0xf) + 6;
2932         } else if (rdev->family == CHIP_R420 ||
2933                    rdev->family == CHIP_R423 ||
2934                    rdev->family == CHIP_RV410) {
2935                 /* r4xx */
2936                 mem_trcd = (temp & 0xf) + 3;
2937                 if (mem_trcd > 15)
2938                         mem_trcd = 15;
2939                 mem_trp = ((temp >> 8) & 0xf) + 3;
2940                 if (mem_trp > 15)
2941                         mem_trp = 15;
2942                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2943                 if (mem_tras > 31)
2944                         mem_tras = 31;
2945         } else { /* RV200, R200 */
2946                 mem_trcd = (temp & 0x7) + 1;
2947                 mem_trp = ((temp >> 8) & 0x7) + 1;
2948                 mem_tras = ((temp >> 12) & 0xf) + 4;
2949         }
2950         /* convert to FF */
2951         trcd_ff.full = dfixed_const(mem_trcd);
2952         trp_ff.full = dfixed_const(mem_trp);
2953         tras_ff.full = dfixed_const(mem_tras);
2954
2955         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2956         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2957         data = (temp & (7 << 20)) >> 20;
2958         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2959                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2960                         tcas_ff = memtcas_rs480_ff[data];
2961                 else
2962                         tcas_ff = memtcas_ff[data];
2963         } else
2964                 tcas_ff = memtcas2_ff[data];
2965
2966         if (rdev->family == CHIP_RS400 ||
2967             rdev->family == CHIP_RS480) {
2968                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2969                 data = (temp >> 23) & 0x7;
2970                 if (data < 5)
2971                         tcas_ff.full += dfixed_const(data);
2972         }
2973
2974         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2975                 /* on the R300, Tcas is included in Trbs.
2976                  */
2977                 temp = RREG32(RADEON_MEM_CNTL);
2978                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2979                 if (data == 1) {
2980                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2981                                 temp = RREG32(R300_MC_IND_INDEX);
2982                                 temp &= ~R300_MC_IND_ADDR_MASK;
2983                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2984                                 WREG32(R300_MC_IND_INDEX, temp);
2985                                 temp = RREG32(R300_MC_IND_DATA);
2986                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2987                         } else {
2988                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2989                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2990                         }
2991                 } else {
2992                         temp = RREG32(R300_MC_READ_CNTL_AB);
2993                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2994                 }
2995                 if (rdev->family == CHIP_RV410 ||
2996                     rdev->family == CHIP_R420 ||
2997                     rdev->family == CHIP_R423)
2998                         trbs_ff = memtrbs_r4xx[data];
2999                 else
3000                         trbs_ff = memtrbs[data];
3001                 tcas_ff.full += trbs_ff.full;
3002         }
3003
3004         sclk_eff_ff.full = sclk_ff.full;
3005
3006         if (rdev->flags & RADEON_IS_AGP) {
3007                 fixed20_12 agpmode_ff;
3008                 agpmode_ff.full = dfixed_const(radeon_agpmode);
3009                 temp_ff.full = dfixed_const_666(16);
3010                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3011         }
3012         /* TODO PCIE lanes may affect this - agpmode == 16?? */
3013
3014         if (ASIC_IS_R300(rdev)) {
3015                 sclk_delay_ff.full = dfixed_const(250);
3016         } else {
3017                 if ((rdev->family == CHIP_RV100) ||
3018                     rdev->flags & RADEON_IS_IGP) {
3019                         if (rdev->mc.vram_is_ddr)
3020                                 sclk_delay_ff.full = dfixed_const(41);
3021                         else
3022                                 sclk_delay_ff.full = dfixed_const(33);
3023                 } else {
3024                         if (rdev->mc.vram_width == 128)
3025                                 sclk_delay_ff.full = dfixed_const(57);
3026                         else
3027                                 sclk_delay_ff.full = dfixed_const(41);
3028                 }
3029         }
3030
3031         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3032
3033         if (rdev->mc.vram_is_ddr) {
3034                 if (rdev->mc.vram_width == 32) {
3035                         k1.full = dfixed_const(40);
3036                         c  = 3;
3037                 } else {
3038                         k1.full = dfixed_const(20);
3039                         c  = 1;
3040                 }
3041         } else {
3042                 k1.full = dfixed_const(40);
3043                 c  = 3;
3044         }
3045
3046         temp_ff.full = dfixed_const(2);
3047         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3048         temp_ff.full = dfixed_const(c);
3049         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3050         temp_ff.full = dfixed_const(4);
3051         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3052         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3053         mc_latency_mclk.full += k1.full;
3054
3055         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3056         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3057
3058         /*
3059           HW cursor time assuming worst case of full size colour cursor.
3060         */
3061         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3062         temp_ff.full += trcd_ff.full;
3063         if (temp_ff.full < tras_ff.full)
3064                 temp_ff.full = tras_ff.full;
3065         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3066
3067         temp_ff.full = dfixed_const(cur_size);
3068         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3069         /*
3070           Find the total latency for the display data.
3071         */
3072         disp_latency_overhead.full = dfixed_const(8);
3073         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3074         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3075         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3076
3077         if (mc_latency_mclk.full > mc_latency_sclk.full)
3078                 disp_latency.full = mc_latency_mclk.full;
3079         else
3080                 disp_latency.full = mc_latency_sclk.full;
3081
3082         /* setup Max GRPH_STOP_REQ default value */
3083         if (ASIC_IS_RV100(rdev))
3084                 max_stop_req = 0x5c;
3085         else
3086                 max_stop_req = 0x7c;
3087
3088         if (mode1) {
3089                 /*  CRTC1
3090                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3091                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3092                 */
3093                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3094
3095                 if (stop_req > max_stop_req)
3096                         stop_req = max_stop_req;
3097
3098                 /*
3099                   Find the drain rate of the display buffer.
3100                 */
3101                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3102                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3103
3104                 /*
3105                   Find the critical point of the display buffer.
3106                 */
3107                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3108                 crit_point_ff.full += dfixed_const_half(0);
3109
3110                 critical_point = dfixed_trunc(crit_point_ff);
3111
3112                 if (rdev->disp_priority == 2) {
3113                         critical_point = 0;
3114                 }
3115
3116                 /*
3117                   The critical point should never be above max_stop_req-4.  Setting
3118                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3119                 */
3120                 if (max_stop_req - critical_point < 4)
3121                         critical_point = 0;
3122
3123                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3124                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3125                         critical_point = 0x10;
3126                 }
3127
3128                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3129                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3130                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3131                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3132                 if ((rdev->family == CHIP_R350) &&
3133                     (stop_req > 0x15)) {
3134                         stop_req -= 0x10;
3135                 }
3136                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3137                 temp |= RADEON_GRPH_BUFFER_SIZE;
3138                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3139                           RADEON_GRPH_CRITICAL_AT_SOF |
3140                           RADEON_GRPH_STOP_CNTL);
3141                 /*
3142                   Write the result into the register.
3143                 */
3144                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3145                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3146
3147 #if 0
3148                 if ((rdev->family == CHIP_RS400) ||
3149                     (rdev->family == CHIP_RS480)) {
3150                         /* attempt to program RS400 disp regs correctly ??? */
3151                         temp = RREG32(RS400_DISP1_REG_CNTL);
3152                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3153                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3154                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3155                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3156                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3157                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3158                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3159                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3160                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3161                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3162                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3163                 }
3164 #endif
3165
3166                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3167                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3168                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3169         }
3170
3171         if (mode2) {
3172                 u32 grph2_cntl;
3173                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3174
3175                 if (stop_req > max_stop_req)
3176                         stop_req = max_stop_req;
3177
3178                 /*
3179                   Find the drain rate of the display buffer.
3180                 */
3181                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3182                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3183
3184                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3185                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3186                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3187                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3188                 if ((rdev->family == CHIP_R350) &&
3189                     (stop_req > 0x15)) {
3190                         stop_req -= 0x10;
3191                 }
3192                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3193                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3194                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3195                           RADEON_GRPH_CRITICAL_AT_SOF |
3196                           RADEON_GRPH_STOP_CNTL);
3197
3198                 if ((rdev->family == CHIP_RS100) ||
3199                     (rdev->family == CHIP_RS200))
3200                         critical_point2 = 0;
3201                 else {
3202                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3203                         temp_ff.full = dfixed_const(temp);
3204                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3205                         if (sclk_ff.full < temp_ff.full)
3206                                 temp_ff.full = sclk_ff.full;
3207
3208                         read_return_rate.full = temp_ff.full;
3209
3210                         if (mode1) {
3211                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3212                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3213                         } else {
3214                                 time_disp1_drop_priority.full = 0;
3215                         }
3216                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3217                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3218                         crit_point_ff.full += dfixed_const_half(0);
3219
3220                         critical_point2 = dfixed_trunc(crit_point_ff);
3221
3222                         if (rdev->disp_priority == 2) {
3223                                 critical_point2 = 0;
3224                         }
3225
3226                         if (max_stop_req - critical_point2 < 4)
3227                                 critical_point2 = 0;
3228
3229                 }
3230
3231                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3232                         /* some R300 cards have problem with this set to 0 */
3233                         critical_point2 = 0x10;
3234                 }
3235
3236                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3237                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3238
3239                 if ((rdev->family == CHIP_RS400) ||
3240                     (rdev->family == CHIP_RS480)) {
3241 #if 0
3242                         /* attempt to program RS400 disp2 regs correctly ??? */
3243                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3244                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3245                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3246                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3247                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3248                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3249                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3250                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3251                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3252                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3253                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3254                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3255 #endif
3256                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3257                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3258                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3259                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3260                 }
3261
3262                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3263                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3264         }
3265 }
3266
3267 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3268 {
3269         DRM_ERROR("pitch                      %d\n", t->pitch);
3270         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3271         DRM_ERROR("width                      %d\n", t->width);
3272         DRM_ERROR("width_11                   %d\n", t->width_11);
3273         DRM_ERROR("height                     %d\n", t->height);
3274         DRM_ERROR("height_11                  %d\n", t->height_11);
3275         DRM_ERROR("num levels                 %d\n", t->num_levels);
3276         DRM_ERROR("depth                      %d\n", t->txdepth);
3277         DRM_ERROR("bpp                        %d\n", t->cpp);
3278         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3279         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3280         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3281         DRM_ERROR("compress format            %d\n", t->compress_format);
3282 }
3283
3284 static int r100_track_compress_size(int compress_format, int w, int h)
3285 {
3286         int block_width, block_height, block_bytes;
3287         int wblocks, hblocks;
3288         int min_wblocks;
3289         int sz;
3290
3291         block_width = 4;
3292         block_height = 4;
3293
3294         switch (compress_format) {
3295         case R100_TRACK_COMP_DXT1:
3296                 block_bytes = 8;
3297                 min_wblocks = 4;
3298                 break;
3299         default:
3300         case R100_TRACK_COMP_DXT35:
3301                 block_bytes = 16;
3302                 min_wblocks = 2;
3303                 break;
3304         }
3305
3306         hblocks = (h + block_height - 1) / block_height;
3307         wblocks = (w + block_width - 1) / block_width;
3308         if (wblocks < min_wblocks)
3309                 wblocks = min_wblocks;
3310         sz = wblocks * hblocks * block_bytes;
3311         return sz;
3312 }
3313
3314 static int r100_cs_track_cube(struct radeon_device *rdev,
3315                               struct r100_cs_track *track, unsigned idx)
3316 {
3317         unsigned face, w, h;
3318         struct radeon_bo *cube_robj;
3319         unsigned long size;
3320         unsigned compress_format = track->textures[idx].compress_format;
3321
3322         for (face = 0; face < 5; face++) {
3323                 cube_robj = track->textures[idx].cube_info[face].robj;
3324                 w = track->textures[idx].cube_info[face].width;
3325                 h = track->textures[idx].cube_info[face].height;
3326
3327                 if (compress_format) {
3328                         size = r100_track_compress_size(compress_format, w, h);
3329                 } else
3330                         size = w * h;
3331                 size *= track->textures[idx].cpp;
3332
3333                 size += track->textures[idx].cube_info[face].offset;
3334
3335                 if (size > radeon_bo_size(cube_robj)) {
3336                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3337                                   size, radeon_bo_size(cube_robj));
3338                         r100_cs_track_texture_print(&track->textures[idx]);
3339                         return -1;
3340                 }
3341         }
3342         return 0;
3343 }
3344
3345 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3346                                        struct r100_cs_track *track)
3347 {
3348         struct radeon_bo *robj;
3349         unsigned long size;
3350         unsigned u, i, w, h, d;
3351         int ret;
3352
3353         for (u = 0; u < track->num_texture; u++) {
3354                 if (!track->textures[u].enabled)
3355                         continue;
3356                 if (track->textures[u].lookup_disable)
3357                         continue;
3358                 robj = track->textures[u].robj;
3359                 if (robj == NULL) {
3360                         DRM_ERROR("No texture bound to unit %u\n", u);
3361                         return -EINVAL;
3362                 }
3363                 size = 0;
3364                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3365                         if (track->textures[u].use_pitch) {
3366                                 if (rdev->family < CHIP_R300)
3367                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3368                                 else
3369                                         w = track->textures[u].pitch / (1 << i);
3370                         } else {
3371                                 w = track->textures[u].width;
3372                                 if (rdev->family >= CHIP_RV515)
3373                                         w |= track->textures[u].width_11;
3374                                 w = w / (1 << i);
3375                                 if (track->textures[u].roundup_w)
3376                                         w = roundup_pow_of_two(w);
3377                         }
3378                         h = track->textures[u].height;
3379                         if (rdev->family >= CHIP_RV515)
3380                                 h |= track->textures[u].height_11;
3381                         h = h / (1 << i);
3382                         if (track->textures[u].roundup_h)
3383                                 h = roundup_pow_of_two(h);
3384                         if (track->textures[u].tex_coord_type == 1) {
3385                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3386                                 if (!d)
3387                                         d = 1;
3388                         } else {
3389                                 d = 1;
3390                         }
3391                         if (track->textures[u].compress_format) {
3392
3393                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3394                                 /* compressed textures are block based */
3395                         } else
3396                                 size += w * h * d;
3397                 }
3398                 size *= track->textures[u].cpp;
3399
3400                 switch (track->textures[u].tex_coord_type) {
3401                 case 0:
3402                 case 1:
3403                         break;
3404                 case 2:
3405                         if (track->separate_cube) {
3406                                 ret = r100_cs_track_cube(rdev, track, u);
3407                                 if (ret)
3408                                         return ret;
3409                         } else
3410                                 size *= 6;
3411                         break;
3412                 default:
3413                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3414                                   "%u\n", track->textures[u].tex_coord_type, u);
3415                         return -EINVAL;
3416                 }
3417                 if (size > radeon_bo_size(robj)) {
3418                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3419                                   "%lu\n", u, size, radeon_bo_size(robj));
3420                         r100_cs_track_texture_print(&track->textures[u]);
3421                         return -EINVAL;
3422                 }
3423         }
3424         return 0;
3425 }
3426
3427 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3428 {
3429         unsigned i;
3430         unsigned long size;
3431         unsigned prim_walk;
3432         unsigned nverts;
3433         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3434
3435         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3436             !track->blend_read_enable)
3437                 num_cb = 0;
3438
3439         for (i = 0; i < num_cb; i++) {
3440                 if (track->cb[i].robj == NULL) {
3441                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3442                         return -EINVAL;
3443                 }
3444                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3445                 size += track->cb[i].offset;
3446                 if (size > radeon_bo_size(track->cb[i].robj)) {
3447                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3448                                   "(need %lu have %lu) !\n", i, size,
3449                                   radeon_bo_size(track->cb[i].robj));
3450                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3451                                   i, track->cb[i].pitch, track->cb[i].cpp,
3452                                   track->cb[i].offset, track->maxy);
3453                         return -EINVAL;
3454                 }
3455         }
3456         track->cb_dirty = false;
3457
3458         if (track->zb_dirty && track->z_enabled) {
3459                 if (track->zb.robj == NULL) {
3460                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3461                         return -EINVAL;
3462                 }
3463                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3464                 size += track->zb.offset;
3465                 if (size > radeon_bo_size(track->zb.robj)) {
3466                         DRM_ERROR("[drm] Buffer too small for z buffer "
3467                                   "(need %lu have %lu) !\n", size,
3468                                   radeon_bo_size(track->zb.robj));
3469                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3470                                   track->zb.pitch, track->zb.cpp,
3471                                   track->zb.offset, track->maxy);
3472                         return -EINVAL;
3473                 }
3474         }
3475         track->zb_dirty = false;
3476
3477         if (track->aa_dirty && track->aaresolve) {
3478                 if (track->aa.robj == NULL) {
3479                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3480                         return -EINVAL;
3481                 }
3482                 /* I believe the format comes from colorbuffer0. */
3483                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3484                 size += track->aa.offset;
3485                 if (size > radeon_bo_size(track->aa.robj)) {
3486                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3487                                   "(need %lu have %lu) !\n", i, size,
3488                                   radeon_bo_size(track->aa.robj));
3489                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3490                                   i, track->aa.pitch, track->cb[0].cpp,
3491                                   track->aa.offset, track->maxy);
3492                         return -EINVAL;
3493                 }
3494         }
3495         track->aa_dirty = false;
3496
3497         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3498         if (track->vap_vf_cntl & (1 << 14)) {
3499                 nverts = track->vap_alt_nverts;
3500         } else {
3501                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3502         }
3503         switch (prim_walk) {
3504         case 1:
3505                 for (i = 0; i < track->num_arrays; i++) {
3506                         size = track->arrays[i].esize * track->max_indx * 4;
3507                         if (track->arrays[i].robj == NULL) {
3508                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3509                                           "bound\n", prim_walk, i);
3510                                 return -EINVAL;
3511                         }
3512                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3513                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3514                                         "need %lu dwords have %lu dwords\n",
3515                                         prim_walk, i, size >> 2,
3516                                         radeon_bo_size(track->arrays[i].robj)
3517                                         >> 2);
3518                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3519                                 return -EINVAL;
3520                         }
3521                 }
3522                 break;
3523         case 2:
3524                 for (i = 0; i < track->num_arrays; i++) {
3525                         size = track->arrays[i].esize * (nverts - 1) * 4;
3526                         if (track->arrays[i].robj == NULL) {
3527                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3528                                           "bound\n", prim_walk, i);
3529                                 return -EINVAL;
3530                         }
3531                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3532                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3533                                         "need %lu dwords have %lu dwords\n",
3534                                         prim_walk, i, size >> 2,
3535                                         radeon_bo_size(track->arrays[i].robj)
3536                                         >> 2);
3537                                 return -EINVAL;
3538                         }
3539                 }
3540                 break;
3541         case 3:
3542                 size = track->vtx_size * nverts;
3543                 if (size != track->immd_dwords) {
3544                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3545                                   track->immd_dwords, size);
3546                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3547                                   nverts, track->vtx_size);
3548                         return -EINVAL;
3549                 }
3550                 break;
3551         default:
3552                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3553                           prim_walk);
3554                 return -EINVAL;
3555         }
3556
3557         if (track->tex_dirty) {
3558                 track->tex_dirty = false;
3559                 return r100_cs_track_texture_check(rdev, track);
3560         }
3561         return 0;
3562 }
3563
3564 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3565 {
3566         unsigned i, face;
3567
3568         track->cb_dirty = true;
3569         track->zb_dirty = true;
3570         track->tex_dirty = true;
3571         track->aa_dirty = true;
3572
3573         if (rdev->family < CHIP_R300) {
3574                 track->num_cb = 1;
3575                 if (rdev->family <= CHIP_RS200)
3576                         track->num_texture = 3;
3577                 else
3578                         track->num_texture = 6;
3579                 track->maxy = 2048;
3580                 track->separate_cube = 1;
3581         } else {
3582                 track->num_cb = 4;
3583                 track->num_texture = 16;
3584                 track->maxy = 4096;
3585                 track->separate_cube = 0;
3586                 track->aaresolve = false;
3587                 track->aa.robj = NULL;
3588         }
3589
3590         for (i = 0; i < track->num_cb; i++) {
3591                 track->cb[i].robj = NULL;
3592                 track->cb[i].pitch = 8192;
3593                 track->cb[i].cpp = 16;
3594                 track->cb[i].offset = 0;
3595         }
3596         track->z_enabled = true;
3597         track->zb.robj = NULL;
3598         track->zb.pitch = 8192;
3599         track->zb.cpp = 4;
3600         track->zb.offset = 0;
3601         track->vtx_size = 0x7F;
3602         track->immd_dwords = 0xFFFFFFFFUL;
3603         track->num_arrays = 11;
3604         track->max_indx = 0x00FFFFFFUL;
3605         for (i = 0; i < track->num_arrays; i++) {
3606                 track->arrays[i].robj = NULL;
3607                 track->arrays[i].esize = 0x7F;
3608         }
3609         for (i = 0; i < track->num_texture; i++) {
3610                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3611                 track->textures[i].pitch = 16536;
3612                 track->textures[i].width = 16536;
3613                 track->textures[i].height = 16536;
3614                 track->textures[i].width_11 = 1 << 11;
3615                 track->textures[i].height_11 = 1 << 11;
3616                 track->textures[i].num_levels = 12;
3617                 if (rdev->family <= CHIP_RS200) {
3618                         track->textures[i].tex_coord_type = 0;
3619                         track->textures[i].txdepth = 0;
3620                 } else {
3621                         track->textures[i].txdepth = 16;
3622                         track->textures[i].tex_coord_type = 1;
3623                 }
3624                 track->textures[i].cpp = 64;
3625                 track->textures[i].robj = NULL;
3626                 /* CS IB emission code makes sure texture unit are disabled */
3627                 track->textures[i].enabled = false;
3628                 track->textures[i].lookup_disable = false;
3629                 track->textures[i].roundup_w = true;
3630                 track->textures[i].roundup_h = true;
3631                 if (track->separate_cube)
3632                         for (face = 0; face < 5; face++) {
3633                                 track->textures[i].cube_info[face].robj = NULL;
3634                                 track->textures[i].cube_info[face].width = 16536;
3635                                 track->textures[i].cube_info[face].height = 16536;
3636                                 track->textures[i].cube_info[face].offset = 0;
3637                         }
3638         }
3639 }
3640
3641 int r100_ring_test(struct radeon_device *rdev)
3642 {
3643         uint32_t scratch;
3644         uint32_t tmp = 0;
3645         unsigned i;
3646         int r;
3647
3648         r = radeon_scratch_get(rdev, &scratch);
3649         if (r) {
3650                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3651                 return r;
3652         }
3653         WREG32(scratch, 0xCAFEDEAD);
3654         r = radeon_ring_lock(rdev, 2);
3655         if (r) {
3656                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3657                 radeon_scratch_free(rdev, scratch);
3658                 return r;
3659         }
3660         radeon_ring_write(rdev, PACKET0(scratch, 0));
3661         radeon_ring_write(rdev, 0xDEADBEEF);
3662         radeon_ring_unlock_commit(rdev);
3663         for (i = 0; i < rdev->usec_timeout; i++) {
3664                 tmp = RREG32(scratch);
3665                 if (tmp == 0xDEADBEEF) {
3666                         break;
3667                 }
3668                 DRM_UDELAY(1);
3669         }
3670         if (i < rdev->usec_timeout) {
3671                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3672         } else {
3673                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3674                           scratch, tmp);
3675                 r = -EINVAL;
3676         }
3677         radeon_scratch_free(rdev, scratch);
3678         return r;
3679 }
3680
3681 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3682 {
3683         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3684         radeon_ring_write(rdev, ib->gpu_addr);
3685         radeon_ring_write(rdev, ib->length_dw);
3686 }
3687
3688 int r100_ib_test(struct radeon_device *rdev)
3689 {
3690         struct radeon_ib *ib;
3691         uint32_t scratch;
3692         uint32_t tmp = 0;
3693         unsigned i;
3694         int r;
3695
3696         r = radeon_scratch_get(rdev, &scratch);
3697         if (r) {
3698                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3699                 return r;
3700         }
3701         WREG32(scratch, 0xCAFEDEAD);
3702         r = radeon_ib_get(rdev, &ib);
3703         if (r) {
3704                 return r;
3705         }
3706         ib->ptr[0] = PACKET0(scratch, 0);
3707         ib->ptr[1] = 0xDEADBEEF;
3708         ib->ptr[2] = PACKET2(0);
3709         ib->ptr[3] = PACKET2(0);
3710         ib->ptr[4] = PACKET2(0);
3711         ib->ptr[5] = PACKET2(0);
3712         ib->ptr[6] = PACKET2(0);
3713         ib->ptr[7] = PACKET2(0);
3714         ib->length_dw = 8;
3715         r = radeon_ib_schedule(rdev, ib);
3716         if (r) {
3717                 radeon_scratch_free(rdev, scratch);
3718                 radeon_ib_free(rdev, &ib);
3719                 return r;
3720         }
3721         r = radeon_fence_wait(ib->fence, false);
3722         if (r) {
3723                 return r;
3724         }
3725         for (i = 0; i < rdev->usec_timeout; i++) {
3726                 tmp = RREG32(scratch);
3727                 if (tmp == 0xDEADBEEF) {
3728                         break;
3729                 }
3730                 DRM_UDELAY(1);
3731         }
3732         if (i < rdev->usec_timeout) {
3733                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3734         } else {
3735                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3736                           scratch, tmp);
3737                 r = -EINVAL;
3738         }
3739         radeon_scratch_free(rdev, scratch);
3740         radeon_ib_free(rdev, &ib);
3741         return r;
3742 }
3743
3744 void r100_ib_fini(struct radeon_device *rdev)
3745 {
3746         radeon_ib_pool_fini(rdev);
3747 }
3748
3749 int r100_ib_init(struct radeon_device *rdev)
3750 {
3751         int r;
3752
3753         r = radeon_ib_pool_init(rdev);
3754         if (r) {
3755                 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
3756                 r100_ib_fini(rdev);
3757                 return r;
3758         }
3759         r = r100_ib_test(rdev);
3760         if (r) {
3761                 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3762                 r100_ib_fini(rdev);
3763                 return r;
3764         }
3765         return 0;
3766 }
3767
3768 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3769 {
3770         /* Shutdown CP we shouldn't need to do that but better be safe than
3771          * sorry
3772          */
3773         rdev->cp.ready = false;
3774         WREG32(R_000740_CP_CSQ_CNTL, 0);
3775
3776         /* Save few CRTC registers */
3777         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3778         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3779         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3780         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3781         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3782                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3783                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3784         }
3785
3786         /* Disable VGA aperture access */
3787         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3788         /* Disable cursor, overlay, crtc */
3789         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3790         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3791                                         S_000054_CRTC_DISPLAY_DIS(1));
3792         WREG32(R_000050_CRTC_GEN_CNTL,
3793                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3794                         S_000050_CRTC_DISP_REQ_EN_B(1));
3795         WREG32(R_000420_OV0_SCALE_CNTL,
3796                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3797         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3798         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3799                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3800                                                 S_000360_CUR2_LOCK(1));
3801                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3802                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3803                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3804                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3805                 WREG32(R_000360_CUR2_OFFSET,
3806                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3807         }
3808 }
3809
3810 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3811 {
3812         /* Update base address for crtc */
3813         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3814         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3815                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3816         }
3817         /* Restore CRTC registers */
3818         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3819         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3820         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3821         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3822                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3823         }
3824 }
3825
3826 void r100_vga_render_disable(struct radeon_device *rdev)
3827 {
3828         u32 tmp;
3829
3830         tmp = RREG8(R_0003C2_GENMO_WT);
3831         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3832 }
3833
3834 static void r100_debugfs(struct radeon_device *rdev)
3835 {
3836         int r;
3837
3838         r = r100_debugfs_mc_info_init(rdev);
3839         if (r)
3840                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3841 }
3842
3843 static void r100_mc_program(struct radeon_device *rdev)
3844 {
3845         struct r100_mc_save save;
3846
3847         /* Stops all mc clients */
3848         r100_mc_stop(rdev, &save);
3849         if (rdev->flags & RADEON_IS_AGP) {
3850                 WREG32(R_00014C_MC_AGP_LOCATION,
3851                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3852                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3853                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3854                 if (rdev->family > CHIP_RV200)
3855                         WREG32(R_00015C_AGP_BASE_2,
3856                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3857         } else {
3858                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3859                 WREG32(R_000170_AGP_BASE, 0);
3860                 if (rdev->family > CHIP_RV200)
3861                         WREG32(R_00015C_AGP_BASE_2, 0);
3862         }
3863         /* Wait for mc idle */
3864         if (r100_mc_wait_for_idle(rdev))
3865                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3866         /* Program MC, should be a 32bits limited address space */
3867         WREG32(R_000148_MC_FB_LOCATION,
3868                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3869                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3870         r100_mc_resume(rdev, &save);
3871 }
3872
3873 void r100_clock_startup(struct radeon_device *rdev)
3874 {
3875         u32 tmp;
3876
3877         if (radeon_dynclks != -1 && radeon_dynclks)
3878                 radeon_legacy_set_clock_gating(rdev, 1);
3879         /* We need to force on some of the block */
3880         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3881         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3882         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3883                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3884         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3885 }
3886
3887 static int r100_startup(struct radeon_device *rdev)
3888 {
3889         int r;
3890
3891         /* set common regs */
3892         r100_set_common_regs(rdev);
3893         /* program mc */
3894         r100_mc_program(rdev);
3895         /* Resume clock */
3896         r100_clock_startup(rdev);
3897         /* Initialize GART (initialize after TTM so we can allocate
3898          * memory through TTM but finalize after TTM) */
3899         r100_enable_bm(rdev);
3900         if (rdev->flags & RADEON_IS_PCI) {
3901                 r = r100_pci_gart_enable(rdev);
3902                 if (r)
3903                         return r;
3904         }
3905
3906         /* allocate wb buffer */
3907         r = radeon_wb_init(rdev);
3908         if (r)
3909                 return r;
3910
3911         /* Enable IRQ */
3912         if (!rdev->irq.installed) {
3913                 r = radeon_irq_kms_init(rdev);
3914                 if (r)
3915                         return r;
3916         }
3917
3918         r100_irq_set(rdev);
3919         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3920         /* 1M ring buffer */
3921         r = r100_cp_init(rdev, 1024 * 1024);
3922         if (r) {
3923                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3924                 return r;
3925         }
3926         r = r100_ib_init(rdev);
3927         if (r) {
3928                 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
3929                 return r;
3930         }
3931         return 0;
3932 }
3933
3934 int r100_resume(struct radeon_device *rdev)
3935 {
3936         /* Make sur GART are not working */
3937         if (rdev->flags & RADEON_IS_PCI)
3938                 r100_pci_gart_disable(rdev);
3939         /* Resume clock before doing reset */
3940         r100_clock_startup(rdev);
3941         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3942         if (radeon_asic_reset(rdev)) {
3943                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3944                         RREG32(R_000E40_RBBM_STATUS),
3945                         RREG32(R_0007C0_CP_STAT));
3946         }
3947         /* post */
3948         radeon_combios_asic_init(rdev->ddev);
3949         /* Resume clock after posting */
3950         r100_clock_startup(rdev);
3951         /* Initialize surface registers */
3952         radeon_surface_init(rdev);
3953         return r100_startup(rdev);
3954 }
3955
3956 int r100_suspend(struct radeon_device *rdev)
3957 {
3958         r100_cp_disable(rdev);
3959         radeon_wb_disable(rdev);
3960         r100_irq_disable(rdev);
3961         if (rdev->flags & RADEON_IS_PCI)
3962                 r100_pci_gart_disable(rdev);
3963         return 0;
3964 }
3965
3966 void r100_fini(struct radeon_device *rdev)
3967 {
3968         r100_cp_fini(rdev);
3969         radeon_wb_fini(rdev);
3970         r100_ib_fini(rdev);
3971         radeon_gem_fini(rdev);
3972         if (rdev->flags & RADEON_IS_PCI)
3973                 r100_pci_gart_fini(rdev);
3974         radeon_agp_fini(rdev);
3975         radeon_irq_kms_fini(rdev);
3976         radeon_fence_driver_fini(rdev);
3977         radeon_bo_fini(rdev);
3978         radeon_atombios_fini(rdev);
3979         kfree(rdev->bios);
3980         rdev->bios = NULL;
3981 }
3982
3983 /*
3984  * Due to how kexec works, it can leave the hw fully initialised when it
3985  * boots the new kernel. However doing our init sequence with the CP and
3986  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3987  * do some quick sanity checks and restore sane values to avoid this
3988  * problem.
3989  */
3990 void r100_restore_sanity(struct radeon_device *rdev)
3991 {
3992         u32 tmp;
3993
3994         tmp = RREG32(RADEON_CP_CSQ_CNTL);
3995         if (tmp) {
3996                 WREG32(RADEON_CP_CSQ_CNTL, 0);
3997         }
3998         tmp = RREG32(RADEON_CP_RB_CNTL);
3999         if (tmp) {
4000                 WREG32(RADEON_CP_RB_CNTL, 0);
4001         }
4002         tmp = RREG32(RADEON_SCRATCH_UMSK);
4003         if (tmp) {
4004                 WREG32(RADEON_SCRATCH_UMSK, 0);
4005         }
4006 }
4007
4008 int r100_init(struct radeon_device *rdev)
4009 {
4010         int r;
4011
4012         /* Register debugfs file specific to this group of asics */
4013         r100_debugfs(rdev);
4014         /* Disable VGA */
4015         r100_vga_render_disable(rdev);
4016         /* Initialize scratch registers */
4017         radeon_scratch_init(rdev);
4018         /* Initialize surface registers */
4019         radeon_surface_init(rdev);
4020         /* sanity check some register to avoid hangs like after kexec */
4021         r100_restore_sanity(rdev);
4022         /* TODO: disable VGA need to use VGA request */
4023         /* BIOS*/
4024         if (!radeon_get_bios(rdev)) {
4025                 if (ASIC_IS_AVIVO(rdev))
4026                         return -EINVAL;
4027         }
4028         if (rdev->is_atom_bios) {
4029                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4030                 return -EINVAL;
4031         } else {
4032                 r = radeon_combios_init(rdev);
4033                 if (r)
4034                         return r;
4035         }
4036         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4037         if (radeon_asic_reset(rdev)) {
4038                 dev_warn(rdev->dev,
4039                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4040                         RREG32(R_000E40_RBBM_STATUS),
4041                         RREG32(R_0007C0_CP_STAT));
4042         }
4043         /* check if cards are posted or not */
4044         if (radeon_boot_test_post_card(rdev) == false)
4045                 return -EINVAL;
4046         /* Set asic errata */
4047         r100_errata(rdev);
4048         /* Initialize clocks */
4049         radeon_get_clock_info(rdev->ddev);
4050         /* initialize AGP */
4051         if (rdev->flags & RADEON_IS_AGP) {
4052                 r = radeon_agp_init(rdev);
4053                 if (r) {
4054                         radeon_agp_disable(rdev);
4055                 }
4056         }
4057         /* initialize VRAM */
4058         r100_mc_init(rdev);
4059         /* Fence driver */
4060         r = radeon_fence_driver_init(rdev);
4061         if (r)
4062                 return r;
4063         /* Memory manager */
4064         r = radeon_bo_init(rdev);
4065         if (r)
4066                 return r;
4067         if (rdev->flags & RADEON_IS_PCI) {
4068                 r = r100_pci_gart_init(rdev);
4069                 if (r)
4070                         return r;
4071         }
4072         r100_set_safe_registers(rdev);
4073         rdev->accel_working = true;
4074         r = r100_startup(rdev);
4075         if (r) {
4076                 /* Somethings want wront with the accel init stop accel */
4077                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4078                 r100_cp_fini(rdev);
4079                 radeon_wb_fini(rdev);
4080                 r100_ib_fini(rdev);
4081                 radeon_irq_kms_fini(rdev);
4082                 if (rdev->flags & RADEON_IS_PCI)
4083                         r100_pci_gart_fini(rdev);
4084                 rdev->accel_working = false;
4085         }
4086         return 0;
4087 }
4088
4089 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4090 {
4091         if (reg < rdev->rmmio_size)
4092                 return readl(((void __iomem *)rdev->rmmio) + reg);
4093         else {
4094                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4095                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4096         }
4097 }
4098
4099 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4100 {
4101         if (reg < rdev->rmmio_size)
4102                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4103         else {
4104                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4105                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4106         }
4107 }
4108
4109 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4110 {
4111         if (reg < rdev->rio_mem_size)
4112                 return ioread32(rdev->rio_mem + reg);
4113         else {
4114                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4115                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4116         }
4117 }
4118
4119 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4120 {
4121         if (reg < rdev->rio_mem_size)
4122                 iowrite32(v, rdev->rio_mem + reg);
4123         else {
4124                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4125                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4126         }
4127 }