drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40
  41 #include <linux/firmware.h>
  42 #include <linux/platform_device.h>
  43
  44 #include "r100_reg_safe.h"
  45 #include "rn50_reg_safe.h"
  46
  47 /* Firmware Names */
  48 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  49 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  50 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  51 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  52 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  53 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  54 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  55
  56 MODULE_FIRMWARE(FIRMWARE_R100);
  57 MODULE_FIRMWARE(FIRMWARE_R200);
  58 MODULE_FIRMWARE(FIRMWARE_R300);
  59 MODULE_FIRMWARE(FIRMWARE_R420);
  60 MODULE_FIRMWARE(FIRMWARE_RS690);
  61 MODULE_FIRMWARE(FIRMWARE_RS600);
  62 MODULE_FIRMWARE(FIRMWARE_R520);
  63
  64 #include "r100_track.h"
  65
  66 /* This files gather functions specifics to:
  67  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  68  */
  69
  70 void r100_get_power_state(struct radeon_device *rdev,
  71                           enum radeon_pm_action action)
  72 {
  73         int i;
  74         rdev->pm.can_upclock = true;
  75         rdev->pm.can_downclock = true;
  76
  77         switch (action) {
  78         case PM_ACTION_MINIMUM:
  79                 rdev->pm.requested_power_state_index = 0;
  80                 rdev->pm.can_downclock = false;
  81                 break;
  82         case PM_ACTION_DOWNCLOCK:
  83                 if (rdev->pm.current_power_state_index == 0) {
  84                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  85                         rdev->pm.can_downclock = false;
  86                 } else {
  87                         if (rdev->pm.active_crtc_count > 1) {
  88                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
  89                                         if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
  90                                                 continue;
  91                                         else if (i >= rdev->pm.current_power_state_index) {
  92                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  93                                                 break;
  94                                         } else {
  95                                                 rdev->pm.requested_power_state_index = i;
  96                                                 break;
  97                                         }
  98                                 }
  99                         } else
 100                                 rdev->pm.requested_power_state_index =
 101                                         rdev->pm.current_power_state_index - 1;
 102                 }
 103                 break;
 104         case PM_ACTION_UPCLOCK:
 105                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 106                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 107                         rdev->pm.can_upclock = false;
 108                 } else {
 109                         if (rdev->pm.active_crtc_count > 1) {
 110                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 111                                         if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
 112                                                 continue;
 113                                         else if (i <= rdev->pm.current_power_state_index) {
 114                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 115                                                 break;
 116                                         } else {
 117                                                 rdev->pm.requested_power_state_index = i;
 118                                                 break;
 119                                         }
 120                                 }
 121                         } else
 122                                 rdev->pm.requested_power_state_index =
 123                                         rdev->pm.current_power_state_index + 1;
 124                 }
 125                 break;
 126         case PM_ACTION_NONE:
 127         default:
 128                 DRM_ERROR("Requested mode for not defined action\n");
 129                 return;
 130         }
 131         /* only one clock mode per power state */
 132         rdev->pm.requested_clock_mode_index = 0;
 133
 134         DRM_INFO("Requested: e: %d m: %d p: %d\n",
 135                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 136                  clock_info[rdev->pm.requested_clock_mode_index].sclk,
 137                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 138                  clock_info[rdev->pm.requested_clock_mode_index].mclk,
 139                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 140                  pcie_lanes);
 141 }
 142
 143 void r100_set_power_state(struct radeon_device *rdev)
 144 {
 145         u32 sclk, mclk;
 146
 147         if (rdev->pm.current_power_state_index == rdev->pm.requested_power_state_index)
 148                 return;
 149
 150         if (radeon_gui_idle(rdev)) {
 151
 152                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 153                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 154                 if (sclk > rdev->clock.default_sclk)
 155                         sclk = rdev->clock.default_sclk;
 156
 157                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 158                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 159                 if (mclk > rdev->clock.default_mclk)
 160                         mclk = rdev->clock.default_mclk;
 161                 /* don't change the mclk with multiple crtcs */
 162                 if (rdev->pm.active_crtc_count > 1)
 163                         mclk = rdev->clock.default_mclk;
 164
 165                 /* set pcie lanes */
 166                 /* TODO */
 167
 168                 /* set voltage */
 169                 /* TODO */
 170
 171                 /* set engine clock */
 172                 if (sclk != rdev->pm.current_sclk) {
 173                         radeon_sync_with_vblank(rdev);
 174                         radeon_pm_debug_check_in_vbl(rdev, false);
 175                         radeon_set_engine_clock(rdev, sclk);
 176                         radeon_pm_debug_check_in_vbl(rdev, true);
 177                         rdev->pm.current_sclk = sclk;
 178                         DRM_INFO("Setting: e: %d\n", sclk);
 179                 }
 180
 181 #if 0
 182                 /* set memory clock */
 183                 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 184                         radeon_sync_with_vblank(rdev);
 185                         radeon_pm_debug_check_in_vbl(rdev, false);
 186                         radeon_set_memory_clock(rdev, mclk);
 187                         radeon_pm_debug_check_in_vbl(rdev, true);
 188                         rdev->pm.current_mclk = mclk;
 189                         DRM_INFO("Setting: m: %d\n", mclk);
 190                 }
 191 #endif
 192
 193                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 194                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 195         } else
 196                 DRM_INFO("GUI not idle!!!\n");
 197 }
 198
 199 bool r100_gui_idle(struct radeon_device *rdev)
 200 {
 201         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 202                 return false;
 203         else
 204                 return true;
 205 }
 206
 207 /* hpd for digital panel detect/disconnect */
 208 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 209 {
 210         bool connected = false;
 211
 212         switch (hpd) {
 213         case RADEON_HPD_1:
 214                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 215                         connected = true;
 216                 break;
 217         case RADEON_HPD_2:
 218                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 219                         connected = true;
 220                 break;
 221         default:
 222                 break;
 223         }
 224         return connected;
 225 }
 226
 227 void r100_hpd_set_polarity(struct radeon_device *rdev,
 228                            enum radeon_hpd_id hpd)
 229 {
 230         u32 tmp;
 231         bool connected = r100_hpd_sense(rdev, hpd);
 232
 233         switch (hpd) {
 234         case RADEON_HPD_1:
 235                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 236                 if (connected)
 237                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 238                 else
 239                         tmp |= RADEON_FP_DETECT_INT_POL;
 240                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 241                 break;
 242         case RADEON_HPD_2:
 243                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 244                 if (connected)
 245                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 246                 else
 247                         tmp |= RADEON_FP2_DETECT_INT_POL;
 248                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 249                 break;
 250         default:
 251                 break;
 252         }
 253 }
 254
 255 void r100_hpd_init(struct radeon_device *rdev)
 256 {
 257         struct drm_device *dev = rdev->ddev;
 258         struct drm_connector *connector;
 259
 260         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 261                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 262                 switch (radeon_connector->hpd.hpd) {
 263                 case RADEON_HPD_1:
 264                         rdev->irq.hpd[0] = true;
 265                         break;
 266                 case RADEON_HPD_2:
 267                         rdev->irq.hpd[1] = true;
 268                         break;
 269                 default:
 270                         break;
 271                 }
 272         }
 273         if (rdev->irq.installed)
 274                 r100_irq_set(rdev);
 275 }
 276
 277 void r100_hpd_fini(struct radeon_device *rdev)
 278 {
 279         struct drm_device *dev = rdev->ddev;
 280         struct drm_connector *connector;
 281
 282         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 283                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 284                 switch (radeon_connector->hpd.hpd) {
 285                 case RADEON_HPD_1:
 286                         rdev->irq.hpd[0] = false;
 287                         break;
 288                 case RADEON_HPD_2:
 289                         rdev->irq.hpd[1] = false;
 290                         break;
 291                 default:
 292                         break;
 293                 }
 294         }
 295 }
 296
 297 /*
 298  * PCI GART
 299  */
 300 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 301 {
 302         /* TODO: can we do somethings here ? */
 303         /* It seems hw only cache one entry so we should discard this
 304          * entry otherwise if first GPU GART read hit this entry it
 305          * could end up in wrong address. */
 306 }
 307
 308 int r100_pci_gart_init(struct radeon_device *rdev)
 309 {
 310         int r;
 311
 312         if (rdev->gart.table.ram.ptr) {
 313                 WARN(1, "R100 PCI GART already initialized.\n");
 314                 return 0;
 315         }
 316         /* Initialize common gart structure */
 317         r = radeon_gart_init(rdev);
 318         if (r)
 319                 return r;
 320         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 321         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 322         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 323         return radeon_gart_table_ram_alloc(rdev);
 324 }
 325
 326 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 327 void r100_enable_bm(struct radeon_device *rdev)
 328 {
 329         uint32_t tmp;
 330         /* Enable bus mastering */
 331         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 332         WREG32(RADEON_BUS_CNTL, tmp);
 333 }
 334
 335 int r100_pci_gart_enable(struct radeon_device *rdev)
 336 {
 337         uint32_t tmp;
 338
 339         radeon_gart_restore(rdev);
 340         /* discard memory request outside of configured range */
 341         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 342         WREG32(RADEON_AIC_CNTL, tmp);
 343         /* set address range for PCI address translate */
 344         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 345         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 346         /* set PCI GART page-table base address */
 347         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 348         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 349         WREG32(RADEON_AIC_CNTL, tmp);
 350         r100_pci_gart_tlb_flush(rdev);
 351         rdev->gart.ready = true;
 352         return 0;
 353 }
 354
 355 void r100_pci_gart_disable(struct radeon_device *rdev)
 356 {
 357         uint32_t tmp;
 358
 359         /* discard memory request outside of configured range */
 360         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 361         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 362         WREG32(RADEON_AIC_LO_ADDR, 0);
 363         WREG32(RADEON_AIC_HI_ADDR, 0);
 364 }
 365
 366 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 367 {
 368         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 369                 return -EINVAL;
 370         }
 371         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 372         return 0;
 373 }
 374
 375 void r100_pci_gart_fini(struct radeon_device *rdev)
 376 {
 377         radeon_gart_fini(rdev);
 378         r100_pci_gart_disable(rdev);
 379         radeon_gart_table_ram_free(rdev);
 380 }
 381
 382 int r100_irq_set(struct radeon_device *rdev)
 383 {
 384         uint32_t tmp = 0;
 385
 386         if (!rdev->irq.installed) {
 387                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
 388                 WREG32(R_000040_GEN_INT_CNTL, 0);
 389                 return -EINVAL;
 390         }
 391         if (rdev->irq.sw_int) {
 392                 tmp |= RADEON_SW_INT_ENABLE;
 393         }
 394         if (rdev->irq.gui_idle) {
 395                 tmp |= RADEON_GUI_IDLE_MASK;
 396         }
 397         if (rdev->irq.crtc_vblank_int[0]) {
 398                 tmp |= RADEON_CRTC_VBLANK_MASK;
 399         }
 400         if (rdev->irq.crtc_vblank_int[1]) {
 401                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 402         }
 403         if (rdev->irq.hpd[0]) {
 404                 tmp |= RADEON_FP_DETECT_MASK;
 405         }
 406         if (rdev->irq.hpd[1]) {
 407                 tmp |= RADEON_FP2_DETECT_MASK;
 408         }
 409         WREG32(RADEON_GEN_INT_CNTL, tmp);
 410         return 0;
 411 }
 412
 413 void r100_irq_disable(struct radeon_device *rdev)
 414 {
 415         u32 tmp;
 416
 417         WREG32(R_000040_GEN_INT_CNTL, 0);
 418         /* Wait and acknowledge irq */
 419         mdelay(1);
 420         tmp = RREG32(R_000044_GEN_INT_STATUS);
 421         WREG32(R_000044_GEN_INT_STATUS, tmp);
 422 }
 423
 424 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 425 {
 426         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 427         uint32_t irq_mask = RADEON_SW_INT_TEST |
 428                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 429                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 430
 431         /* the interrupt works, but the status bit is permanently asserted */
 432         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 433                 if (!rdev->irq.gui_idle_acked)
 434                         irq_mask |= RADEON_GUI_IDLE_STAT;
 435         }
 436
 437         if (irqs) {
 438                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 439         }
 440         return irqs & irq_mask;
 441 }
 442
 443 int r100_irq_process(struct radeon_device *rdev)
 444 {
 445         uint32_t status, msi_rearm;
 446         bool queue_hotplug = false;
 447
 448         /* reset gui idle ack.  the status bit is broken */
 449         rdev->irq.gui_idle_acked = false;
 450
 451         status = r100_irq_ack(rdev);
 452         if (!status) {
 453                 return IRQ_NONE;
 454         }
 455         if (rdev->shutdown) {
 456                 return IRQ_NONE;
 457         }
 458         while (status) {
 459                 /* SW interrupt */
 460                 if (status & RADEON_SW_INT_TEST) {
 461                         radeon_fence_process(rdev);
 462                 }
 463                 /* gui idle interrupt */
 464                 if (status & RADEON_GUI_IDLE_STAT) {
 465                         rdev->irq.gui_idle_acked = true;
 466                         rdev->pm.gui_idle = true;
 467                         wake_up(&rdev->irq.idle_queue);
 468                 }
 469                 /* Vertical blank interrupts */
 470                 if (status & RADEON_CRTC_VBLANK_STAT) {
 471                         drm_handle_vblank(rdev->ddev, 0);
 472                         rdev->pm.vblank_sync = true;
 473                         wake_up(&rdev->irq.vblank_queue);
 474                 }
 475                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 476                         drm_handle_vblank(rdev->ddev, 1);
 477                         rdev->pm.vblank_sync = true;
 478                         wake_up(&rdev->irq.vblank_queue);
 479                 }
 480                 if (status & RADEON_FP_DETECT_STAT) {
 481                         queue_hotplug = true;
 482                         DRM_DEBUG("HPD1\n");
 483                 }
 484                 if (status & RADEON_FP2_DETECT_STAT) {
 485                         queue_hotplug = true;
 486                         DRM_DEBUG("HPD2\n");
 487                 }
 488                 status = r100_irq_ack(rdev);
 489         }
 490         /* reset gui idle ack.  the status bit is broken */
 491         rdev->irq.gui_idle_acked = false;
 492         if (queue_hotplug)
 493                 queue_work(rdev->wq, &rdev->hotplug_work);
 494         if (rdev->msi_enabled) {
 495                 switch (rdev->family) {
 496                 case CHIP_RS400:
 497                 case CHIP_RS480:
 498                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 499                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 500                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 501                         break;
 502                 default:
 503                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 504                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 505                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 506                         break;
 507                 }
 508         }
 509         return IRQ_HANDLED;
 510 }
 511
 512 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 513 {
 514         if (crtc == 0)
 515                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 516         else
 517                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 518 }
 519
 520 /* Who ever call radeon_fence_emit should call ring_lock and ask
 521  * for enough space (today caller are ib schedule and buffer move) */
 522 void r100_fence_ring_emit(struct radeon_device *rdev,
 523                           struct radeon_fence *fence)
 524 {
 525         /* We have to make sure that caches are flushed before
 526          * CPU might read something from VRAM. */
 527         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 528         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 529         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 530         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 531         /* Wait until IDLE & CLEAN */
 532         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 533         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 534         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 535         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 536                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 537         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 538         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 539         /* Emit fence sequence & fire IRQ */
 540         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 541         radeon_ring_write(rdev, fence->seq);
 542         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 543         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 544 }
 545
 546 int r100_wb_init(struct radeon_device *rdev)
 547 {
 548         int r;
 549
 550         if (rdev->wb.wb_obj == NULL) {
 551                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
 552                                         RADEON_GEM_DOMAIN_GTT,
 553                                         &rdev->wb.wb_obj);
 554                 if (r) {
 555                         dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
 556                         return r;
 557                 }
 558                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 559                 if (unlikely(r != 0))
 560                         return r;
 561                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 562                                         &rdev->wb.gpu_addr);
 563                 if (r) {
 564                         dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
 565                         radeon_bo_unreserve(rdev->wb.wb_obj);
 566                         return r;
 567                 }
 568                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 569                 radeon_bo_unreserve(rdev->wb.wb_obj);
 570                 if (r) {
 571                         dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
 572                         return r;
 573                 }
 574         }
 575         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
 576         WREG32(R_00070C_CP_RB_RPTR_ADDR,
 577                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
 578         WREG32(R_000770_SCRATCH_UMSK, 0xff);
 579         return 0;
 580 }
 581
 582 void r100_wb_disable(struct radeon_device *rdev)
 583 {
 584         WREG32(R_000770_SCRATCH_UMSK, 0);
 585 }
 586
 587 void r100_wb_fini(struct radeon_device *rdev)
 588 {
 589         int r;
 590
 591         r100_wb_disable(rdev);
 592         if (rdev->wb.wb_obj) {
 593                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 594                 if (unlikely(r != 0)) {
 595                         dev_err(rdev->dev, "(%d) can't finish WB\n", r);
 596                         return;
 597                 }
 598                 radeon_bo_kunmap(rdev->wb.wb_obj);
 599                 radeon_bo_unpin(rdev->wb.wb_obj);
 600                 radeon_bo_unreserve(rdev->wb.wb_obj);
 601                 radeon_bo_unref(&rdev->wb.wb_obj);
 602                 rdev->wb.wb = NULL;
 603                 rdev->wb.wb_obj = NULL;
 604         }
 605 }
 606
 607 int r100_copy_blit(struct radeon_device *rdev,
 608                    uint64_t src_offset,
 609                    uint64_t dst_offset,
 610                    unsigned num_pages,
 611                    struct radeon_fence *fence)
 612 {
 613         uint32_t cur_pages;
 614         uint32_t stride_bytes = PAGE_SIZE;
 615         uint32_t pitch;
 616         uint32_t stride_pixels;
 617         unsigned ndw;
 618         int num_loops;
 619         int r = 0;
 620
 621         /* radeon limited to 16k stride */
 622         stride_bytes &= 0x3fff;
 623         /* radeon pitch is /64 */
 624         pitch = stride_bytes / 64;
 625         stride_pixels = stride_bytes / 4;
 626         num_loops = DIV_ROUND_UP(num_pages, 8191);
 627
 628         /* Ask for enough room for blit + flush + fence */
 629         ndw = 64 + (10 * num_loops);
 630         r = radeon_ring_lock(rdev, ndw);
 631         if (r) {
 632                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 633                 return -EINVAL;
 634         }
 635         while (num_pages > 0) {
 636                 cur_pages = num_pages;
 637                 if (cur_pages > 8191) {
 638                         cur_pages = 8191;
 639                 }
 640                 num_pages -= cur_pages;
 641
 642                 /* pages are in Y direction - height
 643                    page width in X direction - width */
 644                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 645                 radeon_ring_write(rdev,
 646                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 647                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 648                                   RADEON_GMC_SRC_CLIPPING |
 649                                   RADEON_GMC_DST_CLIPPING |
 650                                   RADEON_GMC_BRUSH_NONE |
 651                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 652                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 653                                   RADEON_ROP3_S |
 654                                   RADEON_DP_SRC_SOURCE_MEMORY |
 655                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 656                                   RADEON_GMC_WR_MSK_DIS);
 657                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 658                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 659                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 660                 radeon_ring_write(rdev, 0);
 661                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 662                 radeon_ring_write(rdev, num_pages);
 663                 radeon_ring_write(rdev, num_pages);
 664                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 665         }
 666         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 667         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 668         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 669         radeon_ring_write(rdev,
 670                           RADEON_WAIT_2D_IDLECLEAN |
 671                           RADEON_WAIT_HOST_IDLECLEAN |
 672                           RADEON_WAIT_DMA_GUI_IDLE);
 673         if (fence) {
 674                 r = radeon_fence_emit(rdev, fence);
 675         }
 676         radeon_ring_unlock_commit(rdev);
 677         return r;
 678 }
 679
 680 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 681 {
 682         unsigned i;
 683         u32 tmp;
 684
 685         for (i = 0; i < rdev->usec_timeout; i++) {
 686                 tmp = RREG32(R_000E40_RBBM_STATUS);
 687                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 688                         return 0;
 689                 }
 690                 udelay(1);
 691         }
 692         return -1;
 693 }
 694
 695 void r100_ring_start(struct radeon_device *rdev)
 696 {
 697         int r;
 698
 699         r = radeon_ring_lock(rdev, 2);
 700         if (r) {
 701                 return;
 702         }
 703         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 704         radeon_ring_write(rdev,
 705                           RADEON_ISYNC_ANY2D_IDLE3D |
 706                           RADEON_ISYNC_ANY3D_IDLE2D |
 707                           RADEON_ISYNC_WAIT_IDLEGUI |
 708                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 709         radeon_ring_unlock_commit(rdev);
 710 }
 711
 712
 713 /* Load the microcode for the CP */
 714 static int r100_cp_init_microcode(struct radeon_device *rdev)
 715 {
 716         struct platform_device *pdev;
 717         const char *fw_name = NULL;
 718         int err;
 719
 720         DRM_DEBUG("\n");
 721
 722         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 723         err = IS_ERR(pdev);
 724         if (err) {
 725                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 726                 return -EINVAL;
 727         }
 728         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 729             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 730             (rdev->family == CHIP_RS200)) {
 731                 DRM_INFO("Loading R100 Microcode\n");
 732                 fw_name = FIRMWARE_R100;
 733         } else if ((rdev->family == CHIP_R200) ||
 734                    (rdev->family == CHIP_RV250) ||
 735                    (rdev->family == CHIP_RV280) ||
 736                    (rdev->family == CHIP_RS300)) {
 737                 DRM_INFO("Loading R200 Microcode\n");
 738                 fw_name = FIRMWARE_R200;
 739         } else if ((rdev->family == CHIP_R300) ||
 740                    (rdev->family == CHIP_R350) ||
 741                    (rdev->family == CHIP_RV350) ||
 742                    (rdev->family == CHIP_RV380) ||
 743                    (rdev->family == CHIP_RS400) ||
 744                    (rdev->family == CHIP_RS480)) {
 745                 DRM_INFO("Loading R300 Microcode\n");
 746                 fw_name = FIRMWARE_R300;
 747         } else if ((rdev->family == CHIP_R420) ||
 748                    (rdev->family == CHIP_R423) ||
 749                    (rdev->family == CHIP_RV410)) {
 750                 DRM_INFO("Loading R400 Microcode\n");
 751                 fw_name = FIRMWARE_R420;
 752         } else if ((rdev->family == CHIP_RS690) ||
 753                    (rdev->family == CHIP_RS740)) {
 754                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 755                 fw_name = FIRMWARE_RS690;
 756         } else if (rdev->family == CHIP_RS600) {
 757                 DRM_INFO("Loading RS600 Microcode\n");
 758                 fw_name = FIRMWARE_RS600;
 759         } else if ((rdev->family == CHIP_RV515) ||
 760                    (rdev->family == CHIP_R520) ||
 761                    (rdev->family == CHIP_RV530) ||
 762                    (rdev->family == CHIP_R580) ||
 763                    (rdev->family == CHIP_RV560) ||
 764                    (rdev->family == CHIP_RV570)) {
 765                 DRM_INFO("Loading R500 Microcode\n");
 766                 fw_name = FIRMWARE_R520;
 767         }
 768
 769         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 770         platform_device_unregister(pdev);
 771         if (err) {
 772                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 773                        fw_name);
 774         } else if (rdev->me_fw->size % 8) {
 775                 printk(KERN_ERR
 776                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 777                        rdev->me_fw->size, fw_name);
 778                 err = -EINVAL;
 779                 release_firmware(rdev->me_fw);
 780                 rdev->me_fw = NULL;
 781         }
 782         return err;
 783 }
 784
 785 static void r100_cp_load_microcode(struct radeon_device *rdev)
 786 {
 787         const __be32 *fw_data;
 788         int i, size;
 789
 790         if (r100_gui_wait_for_idle(rdev)) {
 791                 printk(KERN_WARNING "Failed to wait GUI idle while "
 792                        "programming pipes. Bad things might happen.\n");
 793         }
 794
 795         if (rdev->me_fw) {
 796                 size = rdev->me_fw->size / 4;
 797                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 798                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 799                 for (i = 0; i < size; i += 2) {
 800                         WREG32(RADEON_CP_ME_RAM_DATAH,
 801                                be32_to_cpup(&fw_data[i]));
 802                         WREG32(RADEON_CP_ME_RAM_DATAL,
 803                                be32_to_cpup(&fw_data[i + 1]));
 804                 }
 805         }
 806 }
 807
 808 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 809 {
 810         unsigned rb_bufsz;
 811         unsigned rb_blksz;
 812         unsigned max_fetch;
 813         unsigned pre_write_timer;
 814         unsigned pre_write_limit;
 815         unsigned indirect2_start;
 816         unsigned indirect1_start;
 817         uint32_t tmp;
 818         int r;
 819
 820         if (r100_debugfs_cp_init(rdev)) {
 821                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 822         }
 823         if (!rdev->me_fw) {
 824                 r = r100_cp_init_microcode(rdev);
 825                 if (r) {
 826                         DRM_ERROR("Failed to load firmware!\n");
 827                         return r;
 828                 }
 829         }
 830
 831         /* Align ring size */
 832         rb_bufsz = drm_order(ring_size / 8);
 833         ring_size = (1 << (rb_bufsz + 1)) * 4;
 834         r100_cp_load_microcode(rdev);
 835         r = radeon_ring_init(rdev, ring_size);
 836         if (r) {
 837                 return r;
 838         }
 839         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 840          * the rptr copy in system ram */
 841         rb_blksz = 9;
 842         /* cp will read 128bytes at a time (4 dwords) */
 843         max_fetch = 1;
 844         rdev->cp.align_mask = 16 - 1;
 845         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 846         pre_write_timer = 64;
 847         /* Force CP_RB_WPTR write if written more than one time before the
 848          * delay expire
 849          */
 850         pre_write_limit = 0;
 851         /* Setup the cp cache like this (cache size is 96 dwords) :
 852          *      RING            0  to 15
 853          *      INDIRECT1       16 to 79
 854          *      INDIRECT2       80 to 95
 855          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 856          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 857          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 858          * Idea being that most of the gpu cmd will be through indirect1 buffer
 859          * so it gets the bigger cache.
 860          */
 861         indirect2_start = 80;
 862         indirect1_start = 16;
 863         /* cp setup */
 864         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 865         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 866                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 867                REG_SET(RADEON_MAX_FETCH, max_fetch) |
 868                RADEON_RB_NO_UPDATE);
 869 #ifdef __BIG_ENDIAN
 870         tmp |= RADEON_BUF_SWAP_32BIT;
 871 #endif
 872         WREG32(RADEON_CP_RB_CNTL, tmp);
 873
 874         /* Set ring address */
 875         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
 876         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
 877         /* Force read & write ptr to 0 */
 878         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 879         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 880         WREG32(RADEON_CP_RB_WPTR, 0);
 881         WREG32(RADEON_CP_RB_CNTL, tmp);
 882         udelay(10);
 883         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
 884         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
 885         /* protect against crazy HW on resume */
 886         rdev->cp.wptr &= rdev->cp.ptr_mask;
 887         /* Set cp mode to bus mastering & enable cp*/
 888         WREG32(RADEON_CP_CSQ_MODE,
 889                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
 890                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
 891         WREG32(0x718, 0);
 892         WREG32(0x744, 0x00004D4D);
 893         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
 894         radeon_ring_start(rdev);
 895         r = radeon_ring_test(rdev);
 896         if (r) {
 897                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
 898                 return r;
 899         }
 900         rdev->cp.ready = true;
 901         return 0;
 902 }
 903
 904 void r100_cp_fini(struct radeon_device *rdev)
 905 {
 906         if (r100_cp_wait_for_idle(rdev)) {
 907                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
 908         }
 909         /* Disable ring */
 910         r100_cp_disable(rdev);
 911         radeon_ring_fini(rdev);
 912         DRM_INFO("radeon: cp finalized\n");
 913 }
 914
 915 void r100_cp_disable(struct radeon_device *rdev)
 916 {
 917         /* Disable ring */
 918         rdev->cp.ready = false;
 919         WREG32(RADEON_CP_CSQ_MODE, 0);
 920         WREG32(RADEON_CP_CSQ_CNTL, 0);
 921         if (r100_gui_wait_for_idle(rdev)) {
 922                 printk(KERN_WARNING "Failed to wait GUI idle while "
 923                        "programming pipes. Bad things might happen.\n");
 924         }
 925 }
 926
 927 void r100_cp_commit(struct radeon_device *rdev)
 928 {
 929         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
 930         (void)RREG32(RADEON_CP_RB_WPTR);
 931 }
 932
 933
 934 /*
 935  * CS functions
 936  */
 937 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 938                           struct radeon_cs_packet *pkt,
 939                           const unsigned *auth, unsigned n,
 940                           radeon_packet0_check_t check)
 941 {
 942         unsigned reg;
 943         unsigned i, j, m;
 944         unsigned idx;
 945         int r;
 946
 947         idx = pkt->idx + 1;
 948         reg = pkt->reg;
 949         /* Check that register fall into register range
 950          * determined by the number of entry (n) in the
 951          * safe register bitmap.
 952          */
 953         if (pkt->one_reg_wr) {
 954                 if ((reg >> 7) > n) {
 955                         return -EINVAL;
 956                 }
 957         } else {
 958                 if (((reg + (pkt->count << 2)) >> 7) > n) {
 959                         return -EINVAL;
 960                 }
 961         }
 962         for (i = 0; i <= pkt->count; i++, idx++) {
 963                 j = (reg >> 7);
 964                 m = 1 << ((reg >> 2) & 31);
 965                 if (auth[j] & m) {
 966                         r = check(p, pkt, idx, reg);
 967                         if (r) {
 968                                 return r;
 969                         }
 970                 }
 971                 if (pkt->one_reg_wr) {
 972                         if (!(auth[j] & m)) {
 973                                 break;
 974                         }
 975                 } else {
 976                         reg += 4;
 977                 }
 978         }
 979         return 0;
 980 }
 981
 982 void r100_cs_dump_packet(struct radeon_cs_parser *p,
 983                          struct radeon_cs_packet *pkt)
 984 {
 985         volatile uint32_t *ib;
 986         unsigned i;
 987         unsigned idx;
 988
 989         ib = p->ib->ptr;
 990         idx = pkt->idx;
 991         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
 992                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 993         }
 994 }
 995
 996 /**
 997  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
 998  * @parser:     parser structure holding parsing context.
 999  * @pkt:        where to store packet informations
1000  *
1001  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1002  * if packet is bigger than remaining ib size. or if packets is unknown.
1003  **/
1004 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1005                          struct radeon_cs_packet *pkt,
1006                          unsigned idx)
1007 {
1008         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1009         uint32_t header;
1010
1011         if (idx >= ib_chunk->length_dw) {
1012                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1013                           idx, ib_chunk->length_dw);
1014                 return -EINVAL;
1015         }
1016         header = radeon_get_ib_value(p, idx);
1017         pkt->idx = idx;
1018         pkt->type = CP_PACKET_GET_TYPE(header);
1019         pkt->count = CP_PACKET_GET_COUNT(header);
1020         switch (pkt->type) {
1021         case PACKET_TYPE0:
1022                 pkt->reg = CP_PACKET0_GET_REG(header);
1023                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1024                 break;
1025         case PACKET_TYPE3:
1026                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1027                 break;
1028         case PACKET_TYPE2:
1029                 pkt->count = -1;
1030                 break;
1031         default:
1032                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1033                 return -EINVAL;
1034         }
1035         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1036                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1037                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1038                 return -EINVAL;
1039         }
1040         return 0;
1041 }
1042
1043 /**
1044  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1045  * @parser:             parser structure holding parsing context.
1046  *
1047  * Userspace sends a special sequence for VLINE waits.
1048  * PACKET0 - VLINE_START_END + value
1049  * PACKET0 - WAIT_UNTIL +_value
1050  * RELOC (P3) - crtc_id in reloc.
1051  *
1052  * This function parses this and relocates the VLINE START END
1053  * and WAIT UNTIL packets to the correct crtc.
1054  * It also detects a switched off crtc and nulls out the
1055  * wait in that case.
1056  */
1057 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1058 {
1059         struct drm_mode_object *obj;
1060         struct drm_crtc *crtc;
1061         struct radeon_crtc *radeon_crtc;
1062         struct radeon_cs_packet p3reloc, waitreloc;
1063         int crtc_id;
1064         int r;
1065         uint32_t header, h_idx, reg;
1066         volatile uint32_t *ib;
1067
1068         ib = p->ib->ptr;
1069
1070         /* parse the wait until */
1071         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1072         if (r)
1073                 return r;
1074
1075         /* check its a wait until and only 1 count */
1076         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1077             waitreloc.count != 0) {
1078                 DRM_ERROR("vline wait had illegal wait until segment\n");
1079                 r = -EINVAL;
1080                 return r;
1081         }
1082
1083         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1084                 DRM_ERROR("vline wait had illegal wait until\n");
1085                 r = -EINVAL;
1086                 return r;
1087         }
1088
1089         /* jump over the NOP */
1090         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1091         if (r)
1092                 return r;
1093
1094         h_idx = p->idx - 2;
1095         p->idx += waitreloc.count + 2;
1096         p->idx += p3reloc.count + 2;
1097
1098         header = radeon_get_ib_value(p, h_idx);
1099         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1100         reg = CP_PACKET0_GET_REG(header);
1101         mutex_lock(&p->rdev->ddev->mode_config.mutex);
1102         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1103         if (!obj) {
1104                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1105                 r = -EINVAL;
1106                 goto out;
1107         }
1108         crtc = obj_to_crtc(obj);
1109         radeon_crtc = to_radeon_crtc(crtc);
1110         crtc_id = radeon_crtc->crtc_id;
1111
1112         if (!crtc->enabled) {
1113                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1114                 ib[h_idx + 2] = PACKET2(0);
1115                 ib[h_idx + 3] = PACKET2(0);
1116         } else if (crtc_id == 1) {
1117                 switch (reg) {
1118                 case AVIVO_D1MODE_VLINE_START_END:
1119                         header &= ~R300_CP_PACKET0_REG_MASK;
1120                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1121                         break;
1122                 case RADEON_CRTC_GUI_TRIG_VLINE:
1123                         header &= ~R300_CP_PACKET0_REG_MASK;
1124                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1125                         break;
1126                 default:
1127                         DRM_ERROR("unknown crtc reloc\n");
1128                         r = -EINVAL;
1129                         goto out;
1130                 }
1131                 ib[h_idx] = header;
1132                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1133         }
1134 out:
1135         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1136         return r;
1137 }
1138
1139 /**
1140  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1141  * @parser:             parser structure holding parsing context.
1142  * @data:               pointer to relocation data
1143  * @offset_start:       starting offset
1144  * @offset_mask:        offset mask (to align start offset on)
1145  * @reloc:              reloc informations
1146  *
1147  * Check next packet is relocation packet3, do bo validation and compute
1148  * GPU offset using the provided start.
1149  **/
1150 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1151                               struct radeon_cs_reloc **cs_reloc)
1152 {
1153         struct radeon_cs_chunk *relocs_chunk;
1154         struct radeon_cs_packet p3reloc;
1155         unsigned idx;
1156         int r;
1157
1158         if (p->chunk_relocs_idx == -1) {
1159                 DRM_ERROR("No relocation chunk !\n");
1160                 return -EINVAL;
1161         }
1162         *cs_reloc = NULL;
1163         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1164         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1165         if (r) {
1166                 return r;
1167         }
1168         p->idx += p3reloc.count + 2;
1169         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1170                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1171                           p3reloc.idx);
1172                 r100_cs_dump_packet(p, &p3reloc);
1173                 return -EINVAL;
1174         }
1175         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1176         if (idx >= relocs_chunk->length_dw) {
1177                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1178                           idx, relocs_chunk->length_dw);
1179                 r100_cs_dump_packet(p, &p3reloc);
1180                 return -EINVAL;
1181         }
1182         /* FIXME: we assume reloc size is 4 dwords */
1183         *cs_reloc = p->relocs_ptr[(idx / 4)];
1184         return 0;
1185 }
1186
1187 static int r100_get_vtx_size(uint32_t vtx_fmt)
1188 {
1189         int vtx_size;
1190         vtx_size = 2;
1191         /* ordered according to bits in spec */
1192         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1193                 vtx_size++;
1194         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1195                 vtx_size += 3;
1196         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1197                 vtx_size++;
1198         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1199                 vtx_size++;
1200         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1201                 vtx_size += 3;
1202         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1203                 vtx_size++;
1204         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1205                 vtx_size++;
1206         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1207                 vtx_size += 2;
1208         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1209                 vtx_size += 2;
1210         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1211                 vtx_size++;
1212         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1213                 vtx_size += 2;
1214         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1215                 vtx_size++;
1216         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1217                 vtx_size += 2;
1218         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1219                 vtx_size++;
1220         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1221                 vtx_size++;
1222         /* blend weight */
1223         if (vtx_fmt & (0x7 << 15))
1224                 vtx_size += (vtx_fmt >> 15) & 0x7;
1225         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1226                 vtx_size += 3;
1227         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1228                 vtx_size += 2;
1229         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1230                 vtx_size++;
1231         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1232                 vtx_size++;
1233         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1234                 vtx_size++;
1235         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1236                 vtx_size++;
1237         return vtx_size;
1238 }
1239
1240 static int r100_packet0_check(struct radeon_cs_parser *p,
1241                               struct radeon_cs_packet *pkt,
1242                               unsigned idx, unsigned reg)
1243 {
1244         struct radeon_cs_reloc *reloc;
1245         struct r100_cs_track *track;
1246         volatile uint32_t *ib;
1247         uint32_t tmp;
1248         int r;
1249         int i, face;
1250         u32 tile_flags = 0;
1251         u32 idx_value;
1252
1253         ib = p->ib->ptr;
1254         track = (struct r100_cs_track *)p->track;
1255
1256         idx_value = radeon_get_ib_value(p, idx);
1257
1258         switch (reg) {
1259         case RADEON_CRTC_GUI_TRIG_VLINE:
1260                 r = r100_cs_packet_parse_vline(p);
1261                 if (r) {
1262                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1263                                   idx, reg);
1264                         r100_cs_dump_packet(p, pkt);
1265                         return r;
1266                 }
1267                 break;
1268                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1269                  * range access */
1270         case RADEON_DST_PITCH_OFFSET:
1271         case RADEON_SRC_PITCH_OFFSET:
1272                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1273                 if (r)
1274                         return r;
1275                 break;
1276         case RADEON_RB3D_DEPTHOFFSET:
1277                 r = r100_cs_packet_next_reloc(p, &reloc);
1278                 if (r) {
1279                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1280                                   idx, reg);
1281                         r100_cs_dump_packet(p, pkt);
1282                         return r;
1283                 }
1284                 track->zb.robj = reloc->robj;
1285                 track->zb.offset = idx_value;
1286                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1287                 break;
1288         case RADEON_RB3D_COLOROFFSET:
1289                 r = r100_cs_packet_next_reloc(p, &reloc);
1290                 if (r) {
1291                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1292                                   idx, reg);
1293                         r100_cs_dump_packet(p, pkt);
1294                         return r;
1295                 }
1296                 track->cb[0].robj = reloc->robj;
1297                 track->cb[0].offset = idx_value;
1298                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1299                 break;
1300         case RADEON_PP_TXOFFSET_0:
1301         case RADEON_PP_TXOFFSET_1:
1302         case RADEON_PP_TXOFFSET_2:
1303                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1304                 r = r100_cs_packet_next_reloc(p, &reloc);
1305                 if (r) {
1306                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1307                                   idx, reg);
1308                         r100_cs_dump_packet(p, pkt);
1309                         return r;
1310                 }
1311                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1312                 track->textures[i].robj = reloc->robj;
1313                 break;
1314         case RADEON_PP_CUBIC_OFFSET_T0_0:
1315         case RADEON_PP_CUBIC_OFFSET_T0_1:
1316         case RADEON_PP_CUBIC_OFFSET_T0_2:
1317         case RADEON_PP_CUBIC_OFFSET_T0_3:
1318         case RADEON_PP_CUBIC_OFFSET_T0_4:
1319                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1320                 r = r100_cs_packet_next_reloc(p, &reloc);
1321                 if (r) {
1322                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1323                                   idx, reg);
1324                         r100_cs_dump_packet(p, pkt);
1325                         return r;
1326                 }
1327                 track->textures[0].cube_info[i].offset = idx_value;
1328                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1329                 track->textures[0].cube_info[i].robj = reloc->robj;
1330                 break;
1331         case RADEON_PP_CUBIC_OFFSET_T1_0:
1332         case RADEON_PP_CUBIC_OFFSET_T1_1:
1333         case RADEON_PP_CUBIC_OFFSET_T1_2:
1334         case RADEON_PP_CUBIC_OFFSET_T1_3:
1335         case RADEON_PP_CUBIC_OFFSET_T1_4:
1336                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1337                 r = r100_cs_packet_next_reloc(p, &reloc);
1338                 if (r) {
1339                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1340                                   idx, reg);
1341                         r100_cs_dump_packet(p, pkt);
1342                         return r;
1343                 }
1344                 track->textures[1].cube_info[i].offset = idx_value;
1345                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1346                 track->textures[1].cube_info[i].robj = reloc->robj;
1347                 break;
1348         case RADEON_PP_CUBIC_OFFSET_T2_0:
1349         case RADEON_PP_CUBIC_OFFSET_T2_1:
1350         case RADEON_PP_CUBIC_OFFSET_T2_2:
1351         case RADEON_PP_CUBIC_OFFSET_T2_3:
1352         case RADEON_PP_CUBIC_OFFSET_T2_4:
1353                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1354                 r = r100_cs_packet_next_reloc(p, &reloc);
1355                 if (r) {
1356                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1357                                   idx, reg);
1358                         r100_cs_dump_packet(p, pkt);
1359                         return r;
1360                 }
1361                 track->textures[2].cube_info[i].offset = idx_value;
1362                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1363                 track->textures[2].cube_info[i].robj = reloc->robj;
1364                 break;
1365         case RADEON_RE_WIDTH_HEIGHT:
1366                 track->maxy = ((idx_value >> 16) & 0x7FF);
1367                 break;
1368         case RADEON_RB3D_COLORPITCH:
1369                 r = r100_cs_packet_next_reloc(p, &reloc);
1370                 if (r) {
1371                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1372                                   idx, reg);
1373                         r100_cs_dump_packet(p, pkt);
1374                         return r;
1375                 }
1376
1377                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1378                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1379                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1380                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1381
1382                 tmp = idx_value & ~(0x7 << 16);
1383                 tmp |= tile_flags;
1384                 ib[idx] = tmp;
1385
1386                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1387                 break;
1388         case RADEON_RB3D_DEPTHPITCH:
1389                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1390                 break;
1391         case RADEON_RB3D_CNTL:
1392                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1393                 case 7:
1394                 case 8:
1395                 case 9:
1396                 case 11:
1397                 case 12:
1398                         track->cb[0].cpp = 1;
1399                         break;
1400                 case 3:
1401                 case 4:
1402                 case 15:
1403                         track->cb[0].cpp = 2;
1404                         break;
1405                 case 6:
1406                         track->cb[0].cpp = 4;
1407                         break;
1408                 default:
1409                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1410                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1411                         return -EINVAL;
1412                 }
1413                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1414                 break;
1415         case RADEON_RB3D_ZSTENCILCNTL:
1416                 switch (idx_value & 0xf) {
1417                 case 0:
1418                         track->zb.cpp = 2;
1419                         break;
1420                 case 2:
1421                 case 3:
1422                 case 4:
1423                 case 5:
1424                 case 9:
1425                 case 11:
1426                         track->zb.cpp = 4;
1427                         break;
1428                 default:
1429                         break;
1430                 }
1431                 break;
1432         case RADEON_RB3D_ZPASS_ADDR:
1433                 r = r100_cs_packet_next_reloc(p, &reloc);
1434                 if (r) {
1435                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1436                                   idx, reg);
1437                         r100_cs_dump_packet(p, pkt);
1438                         return r;
1439                 }
1440                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1441                 break;
1442         case RADEON_PP_CNTL:
1443                 {
1444                         uint32_t temp = idx_value >> 4;
1445                         for (i = 0; i < track->num_texture; i++)
1446                                 track->textures[i].enabled = !!(temp & (1 << i));
1447                 }
1448                 break;
1449         case RADEON_SE_VF_CNTL:
1450                 track->vap_vf_cntl = idx_value;
1451                 break;
1452         case RADEON_SE_VTX_FMT:
1453                 track->vtx_size = r100_get_vtx_size(idx_value);
1454                 break;
1455         case RADEON_PP_TEX_SIZE_0:
1456         case RADEON_PP_TEX_SIZE_1:
1457         case RADEON_PP_TEX_SIZE_2:
1458                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1459                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1460                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1461                 break;
1462         case RADEON_PP_TEX_PITCH_0:
1463         case RADEON_PP_TEX_PITCH_1:
1464         case RADEON_PP_TEX_PITCH_2:
1465                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1466                 track->textures[i].pitch = idx_value + 32;
1467                 break;
1468         case RADEON_PP_TXFILTER_0:
1469         case RADEON_PP_TXFILTER_1:
1470         case RADEON_PP_TXFILTER_2:
1471                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1472                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1473                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1474                 tmp = (idx_value >> 23) & 0x7;
1475                 if (tmp == 2 || tmp == 6)
1476                         track->textures[i].roundup_w = false;
1477                 tmp = (idx_value >> 27) & 0x7;
1478                 if (tmp == 2 || tmp == 6)
1479                         track->textures[i].roundup_h = false;
1480                 break;
1481         case RADEON_PP_TXFORMAT_0:
1482         case RADEON_PP_TXFORMAT_1:
1483         case RADEON_PP_TXFORMAT_2:
1484                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1485                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1486                         track->textures[i].use_pitch = 1;
1487                 } else {
1488                         track->textures[i].use_pitch = 0;
1489                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1490                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1491                 }
1492                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1493                         track->textures[i].tex_coord_type = 2;
1494                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1495                 case RADEON_TXFORMAT_I8:
1496                 case RADEON_TXFORMAT_RGB332:
1497                 case RADEON_TXFORMAT_Y8:
1498                         track->textures[i].cpp = 1;
1499                         break;
1500                 case RADEON_TXFORMAT_AI88:
1501                 case RADEON_TXFORMAT_ARGB1555:
1502                 case RADEON_TXFORMAT_RGB565:
1503                 case RADEON_TXFORMAT_ARGB4444:
1504                 case RADEON_TXFORMAT_VYUY422:
1505                 case RADEON_TXFORMAT_YVYU422:
1506                 case RADEON_TXFORMAT_SHADOW16:
1507                 case RADEON_TXFORMAT_LDUDV655:
1508                 case RADEON_TXFORMAT_DUDV88:
1509                         track->textures[i].cpp = 2;
1510                         break;
1511                 case RADEON_TXFORMAT_ARGB8888:
1512                 case RADEON_TXFORMAT_RGBA8888:
1513                 case RADEON_TXFORMAT_SHADOW32:
1514                 case RADEON_TXFORMAT_LDUDUV8888:
1515                         track->textures[i].cpp = 4;
1516                         break;
1517                 case RADEON_TXFORMAT_DXT1:
1518                         track->textures[i].cpp = 1;
1519                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1520                         break;
1521                 case RADEON_TXFORMAT_DXT23:
1522                 case RADEON_TXFORMAT_DXT45:
1523                         track->textures[i].cpp = 1;
1524                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1525                         break;
1526                 }
1527                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1528                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1529                 break;
1530         case RADEON_PP_CUBIC_FACES_0:
1531         case RADEON_PP_CUBIC_FACES_1:
1532         case RADEON_PP_CUBIC_FACES_2:
1533                 tmp = idx_value;
1534                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1535                 for (face = 0; face < 4; face++) {
1536                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1537                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1538                 }
1539                 break;
1540         default:
1541                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1542                        reg, idx);
1543                 return -EINVAL;
1544         }
1545         return 0;
1546 }
1547
1548 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1549                                          struct radeon_cs_packet *pkt,
1550                                          struct radeon_bo *robj)
1551 {
1552         unsigned idx;
1553         u32 value;
1554         idx = pkt->idx + 1;
1555         value = radeon_get_ib_value(p, idx + 2);
1556         if ((value + 1) > radeon_bo_size(robj)) {
1557                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1558                           "(need %u have %lu) !\n",
1559                           value + 1,
1560                           radeon_bo_size(robj));
1561                 return -EINVAL;
1562         }
1563         return 0;
1564 }
1565
1566 static int r100_packet3_check(struct radeon_cs_parser *p,
1567                               struct radeon_cs_packet *pkt)
1568 {
1569         struct radeon_cs_reloc *reloc;
1570         struct r100_cs_track *track;
1571         unsigned idx;
1572         volatile uint32_t *ib;
1573         int r;
1574
1575         ib = p->ib->ptr;
1576         idx = pkt->idx + 1;
1577         track = (struct r100_cs_track *)p->track;
1578         switch (pkt->opcode) {
1579         case PACKET3_3D_LOAD_VBPNTR:
1580                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1581                 if (r)
1582                         return r;
1583                 break;
1584         case PACKET3_INDX_BUFFER:
1585                 r = r100_cs_packet_next_reloc(p, &reloc);
1586                 if (r) {
1587                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1588                         r100_cs_dump_packet(p, pkt);
1589                         return r;
1590                 }
1591                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1592                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1593                 if (r) {
1594                         return r;
1595                 }
1596                 break;
1597         case 0x23:
1598                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1599                 r = r100_cs_packet_next_reloc(p, &reloc);
1600                 if (r) {
1601                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1602                         r100_cs_dump_packet(p, pkt);
1603                         return r;
1604                 }
1605                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1606                 track->num_arrays = 1;
1607                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1608
1609                 track->arrays[0].robj = reloc->robj;
1610                 track->arrays[0].esize = track->vtx_size;
1611
1612                 track->max_indx = radeon_get_ib_value(p, idx+1);
1613
1614                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1615                 track->immd_dwords = pkt->count - 1;
1616                 r = r100_cs_track_check(p->rdev, track);
1617                 if (r)
1618                         return r;
1619                 break;
1620         case PACKET3_3D_DRAW_IMMD:
1621                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1622                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1623                         return -EINVAL;
1624                 }
1625                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1626                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1627                 track->immd_dwords = pkt->count - 1;
1628                 r = r100_cs_track_check(p->rdev, track);
1629                 if (r)
1630                         return r;
1631                 break;
1632                 /* triggers drawing using in-packet vertex data */
1633         case PACKET3_3D_DRAW_IMMD_2:
1634                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1635                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1636                         return -EINVAL;
1637                 }
1638                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1639                 track->immd_dwords = pkt->count;
1640                 r = r100_cs_track_check(p->rdev, track);
1641                 if (r)
1642                         return r;
1643                 break;
1644                 /* triggers drawing using in-packet vertex data */
1645         case PACKET3_3D_DRAW_VBUF_2:
1646                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1647                 r = r100_cs_track_check(p->rdev, track);
1648                 if (r)
1649                         return r;
1650                 break;
1651                 /* triggers drawing of vertex buffers setup elsewhere */
1652         case PACKET3_3D_DRAW_INDX_2:
1653                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1654                 r = r100_cs_track_check(p->rdev, track);
1655                 if (r)
1656                         return r;
1657                 break;
1658                 /* triggers drawing using indices to vertex buffer */
1659         case PACKET3_3D_DRAW_VBUF:
1660                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1661                 r = r100_cs_track_check(p->rdev, track);
1662                 if (r)
1663                         return r;
1664                 break;
1665                 /* triggers drawing of vertex buffers setup elsewhere */
1666         case PACKET3_3D_DRAW_INDX:
1667                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1668                 r = r100_cs_track_check(p->rdev, track);
1669                 if (r)
1670                         return r;
1671                 break;
1672                 /* triggers drawing using indices to vertex buffer */
1673         case PACKET3_NOP:
1674                 break;
1675         default:
1676                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1677                 return -EINVAL;
1678         }
1679         return 0;
1680 }
1681
1682 int r100_cs_parse(struct radeon_cs_parser *p)
1683 {
1684         struct radeon_cs_packet pkt;
1685         struct r100_cs_track *track;
1686         int r;
1687
1688         track = kzalloc(sizeof(*track), GFP_KERNEL);
1689         r100_cs_track_clear(p->rdev, track);
1690         p->track = track;
1691         do {
1692                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1693                 if (r) {
1694                         return r;
1695                 }
1696                 p->idx += pkt.count + 2;
1697                 switch (pkt.type) {
1698                         case PACKET_TYPE0:
1699                                 if (p->rdev->family >= CHIP_R200)
1700                                         r = r100_cs_parse_packet0(p, &pkt,
1701                                                                   p->rdev->config.r100.reg_safe_bm,
1702                                                                   p->rdev->config.r100.reg_safe_bm_size,
1703                                                                   &r200_packet0_check);
1704                                 else
1705                                         r = r100_cs_parse_packet0(p, &pkt,
1706                                                                   p->rdev->config.r100.reg_safe_bm,
1707                                                                   p->rdev->config.r100.reg_safe_bm_size,
1708                                                                   &r100_packet0_check);
1709                                 break;
1710                         case PACKET_TYPE2:
1711                                 break;
1712                         case PACKET_TYPE3:
1713                                 r = r100_packet3_check(p, &pkt);
1714                                 break;
1715                         default:
1716                                 DRM_ERROR("Unknown packet type %d !\n",
1717                                           pkt.type);
1718                                 return -EINVAL;
1719                 }
1720                 if (r) {
1721                         return r;
1722                 }
1723         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1724         return 0;
1725 }
1726
1727
1728 /*
1729  * Global GPU functions
1730  */
1731 void r100_errata(struct radeon_device *rdev)
1732 {
1733         rdev->pll_errata = 0;
1734
1735         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1736                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1737         }
1738
1739         if (rdev->family == CHIP_RV100 ||
1740             rdev->family == CHIP_RS100 ||
1741             rdev->family == CHIP_RS200) {
1742                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1743         }
1744 }
1745
1746 /* Wait for vertical sync on primary CRTC */
1747 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1748 {
1749         uint32_t crtc_gen_cntl, tmp;
1750         int i;
1751
1752         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1753         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1754             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1755                 return;
1756         }
1757         /* Clear the CRTC_VBLANK_SAVE bit */
1758         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1759         for (i = 0; i < rdev->usec_timeout; i++) {
1760                 tmp = RREG32(RADEON_CRTC_STATUS);
1761                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1762                         return;
1763                 }
1764                 DRM_UDELAY(1);
1765         }
1766 }
1767
1768 /* Wait for vertical sync on secondary CRTC */
1769 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1770 {
1771         uint32_t crtc2_gen_cntl, tmp;
1772         int i;
1773
1774         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1775         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1776             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1777                 return;
1778
1779         /* Clear the CRTC_VBLANK_SAVE bit */
1780         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1781         for (i = 0; i < rdev->usec_timeout; i++) {
1782                 tmp = RREG32(RADEON_CRTC2_STATUS);
1783                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1784                         return;
1785                 }
1786                 DRM_UDELAY(1);
1787         }
1788 }
1789
1790 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1791 {
1792         unsigned i;
1793         uint32_t tmp;
1794
1795         for (i = 0; i < rdev->usec_timeout; i++) {
1796                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1797                 if (tmp >= n) {
1798                         return 0;
1799                 }
1800                 DRM_UDELAY(1);
1801         }
1802         return -1;
1803 }
1804
1805 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1806 {
1807         unsigned i;
1808         uint32_t tmp;
1809
1810         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1811                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1812                        " Bad things might happen.\n");
1813         }
1814         for (i = 0; i < rdev->usec_timeout; i++) {
1815                 tmp = RREG32(RADEON_RBBM_STATUS);
1816                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1817                         return 0;
1818                 }
1819                 DRM_UDELAY(1);
1820         }
1821         return -1;
1822 }
1823
1824 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1825 {
1826         unsigned i;
1827         uint32_t tmp;
1828
1829         for (i = 0; i < rdev->usec_timeout; i++) {
1830                 /* read MC_STATUS */
1831                 tmp = RREG32(RADEON_MC_STATUS);
1832                 if (tmp & RADEON_MC_IDLE) {
1833                         return 0;
1834                 }
1835                 DRM_UDELAY(1);
1836         }
1837         return -1;
1838 }
1839
1840 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1841 {
1842         lockup->last_cp_rptr = cp->rptr;
1843         lockup->last_jiffies = jiffies;
1844 }
1845
1846 /**
1847  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1848  * @rdev:       radeon device structure
1849  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
1850  * @cp:         radeon_cp structure holding CP information
1851  *
1852  * We don't need to initialize the lockup tracking information as we will either
1853  * have CP rptr to a different value of jiffies wrap around which will force
1854  * initialization of the lockup tracking informations.
1855  *
1856  * A possible false positivie is if we get call after while and last_cp_rptr ==
1857  * the current CP rptr, even if it's unlikely it might happen. To avoid this
1858  * if the elapsed time since last call is bigger than 2 second than we return
1859  * false and update the tracking information. Due to this the caller must call
1860  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
1861  * the fencing code should be cautious about that.
1862  *
1863  * Caller should write to the ring to force CP to do something so we don't get
1864  * false positive when CP is just gived nothing to do.
1865  *
1866  **/
1867 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1868 {
1869         unsigned long cjiffies, elapsed;
1870
1871         cjiffies = jiffies;
1872         if (!time_after(cjiffies, lockup->last_jiffies)) {
1873                 /* likely a wrap around */
1874                 lockup->last_cp_rptr = cp->rptr;
1875                 lockup->last_jiffies = jiffies;
1876                 return false;
1877         }
1878         if (cp->rptr != lockup->last_cp_rptr) {
1879                 /* CP is still working no lockup */
1880                 lockup->last_cp_rptr = cp->rptr;
1881                 lockup->last_jiffies = jiffies;
1882                 return false;
1883         }
1884         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
1885         if (elapsed >= 3000) {
1886                 /* very likely the improbable case where current
1887                  * rptr is equal to last recorded, a while ago, rptr
1888                  * this is more likely a false positive update tracking
1889                  * information which should force us to be recall at
1890                  * latter point
1891                  */
1892                 lockup->last_cp_rptr = cp->rptr;
1893                 lockup->last_jiffies = jiffies;
1894                 return false;
1895         }
1896         if (elapsed >= 1000) {
1897                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
1898                 return true;
1899         }
1900         /* give a chance to the GPU ... */
1901         return false;
1902 }
1903
1904 bool r100_gpu_is_lockup(struct radeon_device *rdev)
1905 {
1906         u32 rbbm_status;
1907         int r;
1908
1909         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
1910         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
1911                 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
1912                 return false;
1913         }
1914         /* force CP activities */
1915         r = radeon_ring_lock(rdev, 2);
1916         if (!r) {
1917                 /* PACKET2 NOP */
1918                 radeon_ring_write(rdev, 0x80000000);
1919                 radeon_ring_write(rdev, 0x80000000);
1920                 radeon_ring_unlock_commit(rdev);
1921         }
1922         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1923         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
1924 }
1925
1926 void r100_bm_disable(struct radeon_device *rdev)
1927 {
1928         u32 tmp;
1929
1930         /* disable bus mastering */
1931         tmp = RREG32(R_000030_BUS_CNTL);
1932         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
1933         mdelay(1);
1934         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
1935         mdelay(1);
1936         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
1937         tmp = RREG32(RADEON_BUS_CNTL);
1938         mdelay(1);
1939         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
1940         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
1941         mdelay(1);
1942 }
1943
1944 int r100_asic_reset(struct radeon_device *rdev)
1945 {
1946         struct r100_mc_save save;
1947         u32 status, tmp;
1948
1949         r100_mc_stop(rdev, &save);
1950         status = RREG32(R_000E40_RBBM_STATUS);
1951         if (!G_000E40_GUI_ACTIVE(status)) {
1952                 return 0;
1953         }
1954         status = RREG32(R_000E40_RBBM_STATUS);
1955         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1956         /* stop CP */
1957         WREG32(RADEON_CP_CSQ_CNTL, 0);
1958         tmp = RREG32(RADEON_CP_RB_CNTL);
1959         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
1960         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1961         WREG32(RADEON_CP_RB_WPTR, 0);
1962         WREG32(RADEON_CP_RB_CNTL, tmp);
1963         /* save PCI state */
1964         pci_save_state(rdev->pdev);
1965         /* disable bus mastering */
1966         r100_bm_disable(rdev);
1967         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
1968                                         S_0000F0_SOFT_RESET_RE(1) |
1969                                         S_0000F0_SOFT_RESET_PP(1) |
1970                                         S_0000F0_SOFT_RESET_RB(1));
1971         RREG32(R_0000F0_RBBM_SOFT_RESET);
1972         mdelay(500);
1973         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
1974         mdelay(1);
1975         status = RREG32(R_000E40_RBBM_STATUS);
1976         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1977         /* reset CP */
1978         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
1979         RREG32(R_0000F0_RBBM_SOFT_RESET);
1980         mdelay(500);
1981         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
1982         mdelay(1);
1983         status = RREG32(R_000E40_RBBM_STATUS);
1984         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1985         /* restore PCI & busmastering */
1986         pci_restore_state(rdev->pdev);
1987         r100_enable_bm(rdev);
1988         /* Check if GPU is idle */
1989         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
1990                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
1991                 dev_err(rdev->dev, "failed to reset GPU\n");
1992                 rdev->gpu_lockup = true;
1993                 return -1;
1994         }
1995         r100_mc_resume(rdev, &save);
1996         dev_info(rdev->dev, "GPU reset succeed\n");
1997         return 0;
1998 }
1999
2000 void r100_set_common_regs(struct radeon_device *rdev)
2001 {
2002         struct drm_device *dev = rdev->ddev;
2003         bool force_dac2 = false;
2004         u32 tmp;
2005
2006         /* set these so they don't interfere with anything */
2007         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2008         WREG32(RADEON_SUBPIC_CNTL, 0);
2009         WREG32(RADEON_VIPH_CONTROL, 0);
2010         WREG32(RADEON_I2C_CNTL_1, 0);
2011         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2012         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2013         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2014
2015         /* always set up dac2 on rn50 and some rv100 as lots
2016          * of servers seem to wire it up to a VGA port but
2017          * don't report it in the bios connector
2018          * table.
2019          */
2020         switch (dev->pdev->device) {
2021                 /* RN50 */
2022         case 0x515e:
2023         case 0x5969:
2024                 force_dac2 = true;
2025                 break;
2026                 /* RV100*/
2027         case 0x5159:
2028         case 0x515a:
2029                 /* DELL triple head servers */
2030                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2031                     ((dev->pdev->subsystem_device == 0x016c) ||
2032                      (dev->pdev->subsystem_device == 0x016d) ||
2033                      (dev->pdev->subsystem_device == 0x016e) ||
2034                      (dev->pdev->subsystem_device == 0x016f) ||
2035                      (dev->pdev->subsystem_device == 0x0170) ||
2036                      (dev->pdev->subsystem_device == 0x017d) ||
2037                      (dev->pdev->subsystem_device == 0x017e) ||
2038                      (dev->pdev->subsystem_device == 0x0183) ||
2039                      (dev->pdev->subsystem_device == 0x018a) ||
2040                      (dev->pdev->subsystem_device == 0x019a)))
2041                         force_dac2 = true;
2042                 break;
2043         }
2044
2045         if (force_dac2) {
2046                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2047                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2048                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2049
2050                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2051                    enable it, even it's detected.
2052                 */
2053
2054                 /* force it to crtc0 */
2055                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2056                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2057                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2058
2059                 /* set up the TV DAC */
2060                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2061                                  RADEON_TV_DAC_STD_MASK |
2062                                  RADEON_TV_DAC_RDACPD |
2063                                  RADEON_TV_DAC_GDACPD |
2064                                  RADEON_TV_DAC_BDACPD |
2065                                  RADEON_TV_DAC_BGADJ_MASK |
2066                                  RADEON_TV_DAC_DACADJ_MASK);
2067                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2068                                 RADEON_TV_DAC_NHOLD |
2069                                 RADEON_TV_DAC_STD_PS2 |
2070                                 (0x58 << 16));
2071
2072                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2073                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2074                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2075         }
2076
2077         /* switch PM block to ACPI mode */
2078         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2079         tmp &= ~RADEON_PM_MODE_SEL;
2080         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2081
2082 }
2083
2084 /*
2085  * VRAM info
2086  */
2087 static void r100_vram_get_type(struct radeon_device *rdev)
2088 {
2089         uint32_t tmp;
2090
2091         rdev->mc.vram_is_ddr = false;
2092         if (rdev->flags & RADEON_IS_IGP)
2093                 rdev->mc.vram_is_ddr = true;
2094         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2095                 rdev->mc.vram_is_ddr = true;
2096         if ((rdev->family == CHIP_RV100) ||
2097             (rdev->family == CHIP_RS100) ||
2098             (rdev->family == CHIP_RS200)) {
2099                 tmp = RREG32(RADEON_MEM_CNTL);
2100                 if (tmp & RV100_HALF_MODE) {
2101                         rdev->mc.vram_width = 32;
2102                 } else {
2103                         rdev->mc.vram_width = 64;
2104                 }
2105                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2106                         rdev->mc.vram_width /= 4;
2107                         rdev->mc.vram_is_ddr = true;
2108                 }
2109         } else if (rdev->family <= CHIP_RV280) {
2110                 tmp = RREG32(RADEON_MEM_CNTL);
2111                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2112                         rdev->mc.vram_width = 128;
2113                 } else {
2114                         rdev->mc.vram_width = 64;
2115                 }
2116         } else {
2117                 /* newer IGPs */
2118                 rdev->mc.vram_width = 128;
2119         }
2120 }
2121
2122 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2123 {
2124         u32 aper_size;
2125         u8 byte;
2126
2127         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2128
2129         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2130          * that is has the 2nd generation multifunction PCI interface
2131          */
2132         if (rdev->family == CHIP_RV280 ||
2133             rdev->family >= CHIP_RV350) {
2134                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2135                        ~RADEON_HDP_APER_CNTL);
2136                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2137                 return aper_size * 2;
2138         }
2139
2140         /* Older cards have all sorts of funny issues to deal with. First
2141          * check if it's a multifunction card by reading the PCI config
2142          * header type... Limit those to one aperture size
2143          */
2144         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2145         if (byte & 0x80) {
2146                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2147                 DRM_INFO("Limiting VRAM to one aperture\n");
2148                 return aper_size;
2149         }
2150
2151         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2152          * have set it up. We don't write this as it's broken on some ASICs but
2153          * we expect the BIOS to have done the right thing (might be too optimistic...)
2154          */
2155         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2156                 return aper_size * 2;
2157         return aper_size;
2158 }
2159
2160 void r100_vram_init_sizes(struct radeon_device *rdev)
2161 {
2162         u64 config_aper_size;
2163
2164         /* work out accessible VRAM */
2165         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
2166         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2167         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2168         /* FIXME we don't use the second aperture yet when we could use it */
2169         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2170                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2171         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2172         if (rdev->flags & RADEON_IS_IGP) {
2173                 uint32_t tom;
2174                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2175                 tom = RREG32(RADEON_NB_TOM);
2176                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2177                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2178                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2179         } else {
2180                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2181                 /* Some production boards of m6 will report 0
2182                  * if it's 8 MB
2183                  */
2184                 if (rdev->mc.real_vram_size == 0) {
2185                         rdev->mc.real_vram_size = 8192 * 1024;
2186                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2187                 }
2188                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2189                  * Novell bug 204882 + along with lots of ubuntu ones
2190                  */
2191                 if (config_aper_size > rdev->mc.real_vram_size)
2192                         rdev->mc.mc_vram_size = config_aper_size;
2193                 else
2194                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2195         }
2196 }
2197
2198 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2199 {
2200         uint32_t temp;
2201
2202         temp = RREG32(RADEON_CONFIG_CNTL);
2203         if (state == false) {
2204                 temp &= ~(1<<8);
2205                 temp |= (1<<9);
2206         } else {
2207                 temp &= ~(1<<9);
2208         }
2209         WREG32(RADEON_CONFIG_CNTL, temp);
2210 }
2211
2212 void r100_mc_init(struct radeon_device *rdev)
2213 {
2214         u64 base;
2215
2216         r100_vram_get_type(rdev);
2217         r100_vram_init_sizes(rdev);
2218         base = rdev->mc.aper_base;
2219         if (rdev->flags & RADEON_IS_IGP)
2220                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2221         radeon_vram_location(rdev, &rdev->mc, base);
2222         if (!(rdev->flags & RADEON_IS_AGP))
2223                 radeon_gtt_location(rdev, &rdev->mc);
2224         radeon_update_bandwidth_info(rdev);
2225 }
2226
2227
2228 /*
2229  * Indirect registers accessor
2230  */
2231 void r100_pll_errata_after_index(struct radeon_device *rdev)
2232 {
2233         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2234                 return;
2235         }
2236         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2237         (void)RREG32(RADEON_CRTC_GEN_CNTL);
2238 }
2239
2240 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2241 {
2242         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2243          * or the chip could hang on a subsequent access
2244          */
2245         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2246                 udelay(5000);
2247         }
2248
2249         /* This function is required to workaround a hardware bug in some (all?)
2250          * revisions of the R300.  This workaround should be called after every
2251          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2252          * may not be correct.
2253          */
2254         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2255                 uint32_t save, tmp;
2256
2257                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2258                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2259                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2260                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2261                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2262         }
2263 }
2264
2265 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2266 {
2267         uint32_t data;
2268
2269         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2270         r100_pll_errata_after_index(rdev);
2271         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2272         r100_pll_errata_after_data(rdev);
2273         return data;
2274 }
2275
2276 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2277 {
2278         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2279         r100_pll_errata_after_index(rdev);
2280         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2281         r100_pll_errata_after_data(rdev);
2282 }
2283
2284 void r100_set_safe_registers(struct radeon_device *rdev)
2285 {
2286         if (ASIC_IS_RN50(rdev)) {
2287                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2288                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2289         } else if (rdev->family < CHIP_R200) {
2290                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2291                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2292         } else {
2293                 r200_set_safe_registers(rdev);
2294         }
2295 }
2296
2297 /*
2298  * Debugfs info
2299  */
2300 #if defined(CONFIG_DEBUG_FS)
2301 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2302 {
2303         struct drm_info_node *node = (struct drm_info_node *) m->private;
2304         struct drm_device *dev = node->minor->dev;
2305         struct radeon_device *rdev = dev->dev_private;
2306         uint32_t reg, value;
2307         unsigned i;
2308
2309         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2310         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2311         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2312         for (i = 0; i < 64; i++) {
2313                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2314                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2315                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2316                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2317                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2318         }
2319         return 0;
2320 }
2321
2322 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2323 {
2324         struct drm_info_node *node = (struct drm_info_node *) m->private;
2325         struct drm_device *dev = node->minor->dev;
2326         struct radeon_device *rdev = dev->dev_private;
2327         uint32_t rdp, wdp;
2328         unsigned count, i, j;
2329
2330         radeon_ring_free_size(rdev);
2331         rdp = RREG32(RADEON_CP_RB_RPTR);
2332         wdp = RREG32(RADEON_CP_RB_WPTR);
2333         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2334         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2335         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2336         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2337         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2338         seq_printf(m, "%u dwords in ring\n", count);
2339         for (j = 0; j <= count; j++) {
2340                 i = (rdp + j) & rdev->cp.ptr_mask;
2341                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2342         }
2343         return 0;
2344 }
2345
2346
2347 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2348 {
2349         struct drm_info_node *node = (struct drm_info_node *) m->private;
2350         struct drm_device *dev = node->minor->dev;
2351         struct radeon_device *rdev = dev->dev_private;
2352         uint32_t csq_stat, csq2_stat, tmp;
2353         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2354         unsigned i;
2355
2356         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2357         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2358         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2359         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2360         r_rptr = (csq_stat >> 0) & 0x3ff;
2361         r_wptr = (csq_stat >> 10) & 0x3ff;
2362         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2363         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2364         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2365         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2366         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2367         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2368         seq_printf(m, "Ring rptr %u\n", r_rptr);
2369         seq_printf(m, "Ring wptr %u\n", r_wptr);
2370         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2371         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2372         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2373         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2374         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2375          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2376         seq_printf(m, "Ring fifo:\n");
2377         for (i = 0; i < 256; i++) {
2378                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2379                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2380                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2381         }
2382         seq_printf(m, "Indirect1 fifo:\n");
2383         for (i = 256; i <= 512; i++) {
2384                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2385                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2386                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2387         }
2388         seq_printf(m, "Indirect2 fifo:\n");
2389         for (i = 640; i < ib1_wptr; i++) {
2390                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2391                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2392                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2393         }
2394         return 0;
2395 }
2396
2397 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2398 {
2399         struct drm_info_node *node = (struct drm_info_node *) m->private;
2400         struct drm_device *dev = node->minor->dev;
2401         struct radeon_device *rdev = dev->dev_private;
2402         uint32_t tmp;
2403
2404         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2405         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2406         tmp = RREG32(RADEON_MC_FB_LOCATION);
2407         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2408         tmp = RREG32(RADEON_BUS_CNTL);
2409         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2410         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2411         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2412         tmp = RREG32(RADEON_AGP_BASE);
2413         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2414         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2415         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2416         tmp = RREG32(0x01D0);
2417         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2418         tmp = RREG32(RADEON_AIC_LO_ADDR);
2419         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2420         tmp = RREG32(RADEON_AIC_HI_ADDR);
2421         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2422         tmp = RREG32(0x01E4);
2423         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2424         return 0;
2425 }
2426
2427 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2428         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2429 };
2430
2431 static struct drm_info_list r100_debugfs_cp_list[] = {
2432         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2433         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2434 };
2435
2436 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2437         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2438 };
2439 #endif
2440
2441 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2442 {
2443 #if defined(CONFIG_DEBUG_FS)
2444         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2445 #else
2446         return 0;
2447 #endif
2448 }
2449
2450 int r100_debugfs_cp_init(struct radeon_device *rdev)
2451 {
2452 #if defined(CONFIG_DEBUG_FS)
2453         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2454 #else
2455         return 0;
2456 #endif
2457 }
2458
2459 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2460 {
2461 #if defined(CONFIG_DEBUG_FS)
2462         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2463 #else
2464         return 0;
2465 #endif
2466 }
2467
2468 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2469                          uint32_t tiling_flags, uint32_t pitch,
2470                          uint32_t offset, uint32_t obj_size)
2471 {
2472         int surf_index = reg * 16;
2473         int flags = 0;
2474
2475         /* r100/r200 divide by 16 */
2476         if (rdev->family < CHIP_R300)
2477                 flags = pitch / 16;
2478         else
2479                 flags = pitch / 8;
2480
2481         if (rdev->family <= CHIP_RS200) {
2482                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2483                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2484                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2485                 if (tiling_flags & RADEON_TILING_MACRO)
2486                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2487         } else if (rdev->family <= CHIP_RV280) {
2488                 if (tiling_flags & (RADEON_TILING_MACRO))
2489                         flags |= R200_SURF_TILE_COLOR_MACRO;
2490                 if (tiling_flags & RADEON_TILING_MICRO)
2491                         flags |= R200_SURF_TILE_COLOR_MICRO;
2492         } else {
2493                 if (tiling_flags & RADEON_TILING_MACRO)
2494                         flags |= R300_SURF_TILE_MACRO;
2495                 if (tiling_flags & RADEON_TILING_MICRO)
2496                         flags |= R300_SURF_TILE_MICRO;
2497         }
2498
2499         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2500                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2501         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2502                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2503
2504         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2505         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2506         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2507         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2508         return 0;
2509 }
2510
2511 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2512 {
2513         int surf_index = reg * 16;
2514         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2515 }
2516
2517 void r100_bandwidth_update(struct radeon_device *rdev)
2518 {
2519         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2520         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2521         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2522         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2523         fixed20_12 memtcas_ff[8] = {
2524                 fixed_init(1),
2525                 fixed_init(2),
2526                 fixed_init(3),
2527                 fixed_init(0),
2528                 fixed_init_half(1),
2529                 fixed_init_half(2),
2530                 fixed_init(0),
2531         };
2532         fixed20_12 memtcas_rs480_ff[8] = {
2533                 fixed_init(0),
2534                 fixed_init(1),
2535                 fixed_init(2),
2536                 fixed_init(3),
2537                 fixed_init(0),
2538                 fixed_init_half(1),
2539                 fixed_init_half(2),
2540                 fixed_init_half(3),
2541         };
2542         fixed20_12 memtcas2_ff[8] = {
2543                 fixed_init(0),
2544                 fixed_init(1),
2545                 fixed_init(2),
2546                 fixed_init(3),
2547                 fixed_init(4),
2548                 fixed_init(5),
2549                 fixed_init(6),
2550                 fixed_init(7),
2551         };
2552         fixed20_12 memtrbs[8] = {
2553                 fixed_init(1),
2554                 fixed_init_half(1),
2555                 fixed_init(2),
2556                 fixed_init_half(2),
2557                 fixed_init(3),
2558                 fixed_init_half(3),
2559                 fixed_init(4),
2560                 fixed_init_half(4)
2561         };
2562         fixed20_12 memtrbs_r4xx[8] = {
2563                 fixed_init(4),
2564                 fixed_init(5),
2565                 fixed_init(6),
2566                 fixed_init(7),
2567                 fixed_init(8),
2568                 fixed_init(9),
2569                 fixed_init(10),
2570                 fixed_init(11)
2571         };
2572         fixed20_12 min_mem_eff;
2573         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2574         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2575         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2576                 disp_drain_rate2, read_return_rate;
2577         fixed20_12 time_disp1_drop_priority;
2578         int c;
2579         int cur_size = 16;       /* in octawords */
2580         int critical_point = 0, critical_point2;
2581 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2582         int stop_req, max_stop_req;
2583         struct drm_display_mode *mode1 = NULL;
2584         struct drm_display_mode *mode2 = NULL;
2585         uint32_t pixel_bytes1 = 0;
2586         uint32_t pixel_bytes2 = 0;
2587
2588         radeon_update_display_priority(rdev);
2589
2590         if (rdev->mode_info.crtcs[0]->base.enabled) {
2591                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2592                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2593         }
2594         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2595                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2596                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2597                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2598                 }
2599         }
2600
2601         min_mem_eff.full = rfixed_const_8(0);
2602         /* get modes */
2603         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2604                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2605                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2606                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2607                 /* check crtc enables */
2608                 if (mode2)
2609                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2610                 if (mode1)
2611                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2612                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2613         }
2614
2615         /*
2616          * determine is there is enough bw for current mode
2617          */
2618         sclk_ff = rdev->pm.sclk;
2619         mclk_ff = rdev->pm.mclk;
2620
2621         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2622         temp_ff.full = rfixed_const(temp);
2623         mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2624
2625         pix_clk.full = 0;
2626         pix_clk2.full = 0;
2627         peak_disp_bw.full = 0;
2628         if (mode1) {
2629                 temp_ff.full = rfixed_const(1000);
2630                 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2631                 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2632                 temp_ff.full = rfixed_const(pixel_bytes1);
2633                 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2634         }
2635         if (mode2) {
2636                 temp_ff.full = rfixed_const(1000);
2637                 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2638                 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2639                 temp_ff.full = rfixed_const(pixel_bytes2);
2640                 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2641         }
2642
2643         mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2644         if (peak_disp_bw.full >= mem_bw.full) {
2645                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2646                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2647         }
2648
2649         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2650         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2651         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2652                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2653                 mem_trp  = ((temp & 0x3)) + 1;
2654                 mem_tras = ((temp & 0x70) >> 4) + 1;
2655         } else if (rdev->family == CHIP_R300 ||
2656                    rdev->family == CHIP_R350) { /* r300, r350 */
2657                 mem_trcd = (temp & 0x7) + 1;
2658                 mem_trp = ((temp >> 8) & 0x7) + 1;
2659                 mem_tras = ((temp >> 11) & 0xf) + 4;
2660         } else if (rdev->family == CHIP_RV350 ||
2661                    rdev->family <= CHIP_RV380) {
2662                 /* rv3x0 */
2663                 mem_trcd = (temp & 0x7) + 3;
2664                 mem_trp = ((temp >> 8) & 0x7) + 3;
2665                 mem_tras = ((temp >> 11) & 0xf) + 6;
2666         } else if (rdev->family == CHIP_R420 ||
2667                    rdev->family == CHIP_R423 ||
2668                    rdev->family == CHIP_RV410) {
2669                 /* r4xx */
2670                 mem_trcd = (temp & 0xf) + 3;
2671                 if (mem_trcd > 15)
2672                         mem_trcd = 15;
2673                 mem_trp = ((temp >> 8) & 0xf) + 3;
2674                 if (mem_trp > 15)
2675                         mem_trp = 15;
2676                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2677                 if (mem_tras > 31)
2678                         mem_tras = 31;
2679         } else { /* RV200, R200 */
2680                 mem_trcd = (temp & 0x7) + 1;
2681                 mem_trp = ((temp >> 8) & 0x7) + 1;
2682                 mem_tras = ((temp >> 12) & 0xf) + 4;
2683         }
2684         /* convert to FF */
2685         trcd_ff.full = rfixed_const(mem_trcd);
2686         trp_ff.full = rfixed_const(mem_trp);
2687         tras_ff.full = rfixed_const(mem_tras);
2688
2689         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2690         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2691         data = (temp & (7 << 20)) >> 20;
2692         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2693                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2694                         tcas_ff = memtcas_rs480_ff[data];
2695                 else
2696                         tcas_ff = memtcas_ff[data];
2697         } else
2698                 tcas_ff = memtcas2_ff[data];
2699
2700         if (rdev->family == CHIP_RS400 ||
2701             rdev->family == CHIP_RS480) {
2702                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2703                 data = (temp >> 23) & 0x7;
2704                 if (data < 5)
2705                         tcas_ff.full += rfixed_const(data);
2706         }
2707
2708         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2709                 /* on the R300, Tcas is included in Trbs.
2710                  */
2711                 temp = RREG32(RADEON_MEM_CNTL);
2712                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2713                 if (data == 1) {
2714                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2715                                 temp = RREG32(R300_MC_IND_INDEX);
2716                                 temp &= ~R300_MC_IND_ADDR_MASK;
2717                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2718                                 WREG32(R300_MC_IND_INDEX, temp);
2719                                 temp = RREG32(R300_MC_IND_DATA);
2720                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2721                         } else {
2722                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2723                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2724                         }
2725                 } else {
2726                         temp = RREG32(R300_MC_READ_CNTL_AB);
2727                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2728                 }
2729                 if (rdev->family == CHIP_RV410 ||
2730                     rdev->family == CHIP_R420 ||
2731                     rdev->family == CHIP_R423)
2732                         trbs_ff = memtrbs_r4xx[data];
2733                 else
2734                         trbs_ff = memtrbs[data];
2735                 tcas_ff.full += trbs_ff.full;
2736         }
2737
2738         sclk_eff_ff.full = sclk_ff.full;
2739
2740         if (rdev->flags & RADEON_IS_AGP) {
2741                 fixed20_12 agpmode_ff;
2742                 agpmode_ff.full = rfixed_const(radeon_agpmode);
2743                 temp_ff.full = rfixed_const_666(16);
2744                 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2745         }
2746         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2747
2748         if (ASIC_IS_R300(rdev)) {
2749                 sclk_delay_ff.full = rfixed_const(250);
2750         } else {
2751                 if ((rdev->family == CHIP_RV100) ||
2752                     rdev->flags & RADEON_IS_IGP) {
2753                         if (rdev->mc.vram_is_ddr)
2754                                 sclk_delay_ff.full = rfixed_const(41);
2755                         else
2756                                 sclk_delay_ff.full = rfixed_const(33);
2757                 } else {
2758                         if (rdev->mc.vram_width == 128)
2759                                 sclk_delay_ff.full = rfixed_const(57);
2760                         else
2761                                 sclk_delay_ff.full = rfixed_const(41);
2762                 }
2763         }
2764
2765         mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2766
2767         if (rdev->mc.vram_is_ddr) {
2768                 if (rdev->mc.vram_width == 32) {
2769                         k1.full = rfixed_const(40);
2770                         c  = 3;
2771                 } else {
2772                         k1.full = rfixed_const(20);
2773                         c  = 1;
2774                 }
2775         } else {
2776                 k1.full = rfixed_const(40);
2777                 c  = 3;
2778         }
2779
2780         temp_ff.full = rfixed_const(2);
2781         mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2782         temp_ff.full = rfixed_const(c);
2783         mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2784         temp_ff.full = rfixed_const(4);
2785         mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2786         mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2787         mc_latency_mclk.full += k1.full;
2788
2789         mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2790         mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2791
2792         /*
2793           HW cursor time assuming worst case of full size colour cursor.
2794         */
2795         temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2796         temp_ff.full += trcd_ff.full;
2797         if (temp_ff.full < tras_ff.full)
2798                 temp_ff.full = tras_ff.full;
2799         cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2800
2801         temp_ff.full = rfixed_const(cur_size);
2802         cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2803         /*
2804           Find the total latency for the display data.
2805         */
2806         disp_latency_overhead.full = rfixed_const(8);
2807         disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2808         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2809         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2810
2811         if (mc_latency_mclk.full > mc_latency_sclk.full)
2812                 disp_latency.full = mc_latency_mclk.full;
2813         else
2814                 disp_latency.full = mc_latency_sclk.full;
2815
2816         /* setup Max GRPH_STOP_REQ default value */
2817         if (ASIC_IS_RV100(rdev))
2818                 max_stop_req = 0x5c;
2819         else
2820                 max_stop_req = 0x7c;
2821
2822         if (mode1) {
2823                 /*  CRTC1
2824                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2825                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2826                 */
2827                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2828
2829                 if (stop_req > max_stop_req)
2830                         stop_req = max_stop_req;
2831
2832                 /*
2833                   Find the drain rate of the display buffer.
2834                 */
2835                 temp_ff.full = rfixed_const((16/pixel_bytes1));
2836                 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2837
2838                 /*
2839                   Find the critical point of the display buffer.
2840                 */
2841                 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2842                 crit_point_ff.full += rfixed_const_half(0);
2843
2844                 critical_point = rfixed_trunc(crit_point_ff);
2845
2846                 if (rdev->disp_priority == 2) {
2847                         critical_point = 0;
2848                 }
2849
2850                 /*
2851                   The critical point should never be above max_stop_req-4.  Setting
2852                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2853                 */
2854                 if (max_stop_req - critical_point < 4)
2855                         critical_point = 0;
2856
2857                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2858                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2859                         critical_point = 0x10;
2860                 }
2861
2862                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2863                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2864                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2865                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2866                 if ((rdev->family == CHIP_R350) &&
2867                     (stop_req > 0x15)) {
2868                         stop_req -= 0x10;
2869                 }
2870                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2871                 temp |= RADEON_GRPH_BUFFER_SIZE;
2872                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2873                           RADEON_GRPH_CRITICAL_AT_SOF |
2874                           RADEON_GRPH_STOP_CNTL);
2875                 /*
2876                   Write the result into the register.
2877                 */
2878                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2879                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2880
2881 #if 0
2882                 if ((rdev->family == CHIP_RS400) ||
2883                     (rdev->family == CHIP_RS480)) {
2884                         /* attempt to program RS400 disp regs correctly ??? */
2885                         temp = RREG32(RS400_DISP1_REG_CNTL);
2886                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2887                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
2888                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2889                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2890                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2891                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
2892                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2893                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2894                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2895                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2896                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2897                 }
2898 #endif
2899
2900                 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2901                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
2902                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2903         }
2904
2905         if (mode2) {
2906                 u32 grph2_cntl;
2907                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2908
2909                 if (stop_req > max_stop_req)
2910                         stop_req = max_stop_req;
2911
2912                 /*
2913                   Find the drain rate of the display buffer.
2914                 */
2915                 temp_ff.full = rfixed_const((16/pixel_bytes2));
2916                 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2917
2918                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2919                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2920                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2921                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2922                 if ((rdev->family == CHIP_R350) &&
2923                     (stop_req > 0x15)) {
2924                         stop_req -= 0x10;
2925                 }
2926                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2927                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2928                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2929                           RADEON_GRPH_CRITICAL_AT_SOF |
2930                           RADEON_GRPH_STOP_CNTL);
2931
2932                 if ((rdev->family == CHIP_RS100) ||
2933                     (rdev->family == CHIP_RS200))
2934                         critical_point2 = 0;
2935                 else {
2936                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2937                         temp_ff.full = rfixed_const(temp);
2938                         temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2939                         if (sclk_ff.full < temp_ff.full)
2940                                 temp_ff.full = sclk_ff.full;
2941
2942                         read_return_rate.full = temp_ff.full;
2943
2944                         if (mode1) {
2945                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2946                                 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2947                         } else {
2948                                 time_disp1_drop_priority.full = 0;
2949                         }
2950                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2951                         crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2952                         crit_point_ff.full += rfixed_const_half(0);
2953
2954                         critical_point2 = rfixed_trunc(crit_point_ff);
2955
2956                         if (rdev->disp_priority == 2) {
2957                                 critical_point2 = 0;
2958                         }
2959
2960                         if (max_stop_req - critical_point2 < 4)
2961                                 critical_point2 = 0;
2962
2963                 }
2964
2965                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2966                         /* some R300 cards have problem with this set to 0 */
2967                         critical_point2 = 0x10;
2968                 }
2969
2970                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2971                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2972
2973                 if ((rdev->family == CHIP_RS400) ||
2974                     (rdev->family == CHIP_RS480)) {
2975 #if 0
2976                         /* attempt to program RS400 disp2 regs correctly ??? */
2977                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
2978                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2979                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
2980                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2981                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2982                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2983                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
2984                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2985                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2986                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2987                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2988                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2989 #endif
2990                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2991                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2992                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
2993                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2994                 }
2995
2996                 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2997                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2998         }
2999 }
3000
3001 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3002 {
3003         DRM_ERROR("pitch                      %d\n", t->pitch);
3004         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3005         DRM_ERROR("width                      %d\n", t->width);
3006         DRM_ERROR("width_11                   %d\n", t->width_11);
3007         DRM_ERROR("height                     %d\n", t->height);
3008         DRM_ERROR("height_11                  %d\n", t->height_11);
3009         DRM_ERROR("num levels                 %d\n", t->num_levels);
3010         DRM_ERROR("depth                      %d\n", t->txdepth);
3011         DRM_ERROR("bpp                        %d\n", t->cpp);
3012         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3013         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3014         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3015         DRM_ERROR("compress format            %d\n", t->compress_format);
3016 }
3017
3018 static int r100_cs_track_cube(struct radeon_device *rdev,
3019                               struct r100_cs_track *track, unsigned idx)
3020 {
3021         unsigned face, w, h;
3022         struct radeon_bo *cube_robj;
3023         unsigned long size;
3024
3025         for (face = 0; face < 5; face++) {
3026                 cube_robj = track->textures[idx].cube_info[face].robj;
3027                 w = track->textures[idx].cube_info[face].width;
3028                 h = track->textures[idx].cube_info[face].height;
3029
3030                 size = w * h;
3031                 size *= track->textures[idx].cpp;
3032
3033                 size += track->textures[idx].cube_info[face].offset;
3034
3035                 if (size > radeon_bo_size(cube_robj)) {
3036                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3037                                   size, radeon_bo_size(cube_robj));
3038                         r100_cs_track_texture_print(&track->textures[idx]);
3039                         return -1;
3040                 }
3041         }
3042         return 0;
3043 }
3044
3045 static int r100_track_compress_size(int compress_format, int w, int h)
3046 {
3047         int block_width, block_height, block_bytes;
3048         int wblocks, hblocks;
3049         int min_wblocks;
3050         int sz;
3051
3052         block_width = 4;
3053         block_height = 4;
3054
3055         switch (compress_format) {
3056         case R100_TRACK_COMP_DXT1:
3057                 block_bytes = 8;
3058                 min_wblocks = 4;
3059                 break;
3060         default:
3061         case R100_TRACK_COMP_DXT35:
3062                 block_bytes = 16;
3063                 min_wblocks = 2;
3064                 break;
3065         }
3066
3067         hblocks = (h + block_height - 1) / block_height;
3068         wblocks = (w + block_width - 1) / block_width;
3069         if (wblocks < min_wblocks)
3070                 wblocks = min_wblocks;
3071         sz = wblocks * hblocks * block_bytes;
3072         return sz;
3073 }
3074
3075 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3076                                        struct r100_cs_track *track)
3077 {
3078         struct radeon_bo *robj;
3079         unsigned long size;
3080         unsigned u, i, w, h, d;
3081         int ret;
3082
3083         for (u = 0; u < track->num_texture; u++) {
3084                 if (!track->textures[u].enabled)
3085                         continue;
3086                 robj = track->textures[u].robj;
3087                 if (robj == NULL) {
3088                         DRM_ERROR("No texture bound to unit %u\n", u);
3089                         return -EINVAL;
3090                 }
3091                 size = 0;
3092                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3093                         if (track->textures[u].use_pitch) {
3094                                 if (rdev->family < CHIP_R300)
3095                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3096                                 else
3097                                         w = track->textures[u].pitch / (1 << i);
3098                         } else {
3099                                 w = track->textures[u].width;
3100                                 if (rdev->family >= CHIP_RV515)
3101                                         w |= track->textures[u].width_11;
3102                                 w = w / (1 << i);
3103                                 if (track->textures[u].roundup_w)
3104                                         w = roundup_pow_of_two(w);
3105                         }
3106                         h = track->textures[u].height;
3107                         if (rdev->family >= CHIP_RV515)
3108                                 h |= track->textures[u].height_11;
3109                         h = h / (1 << i);
3110                         if (track->textures[u].roundup_h)
3111                                 h = roundup_pow_of_two(h);
3112                         if (track->textures[u].tex_coord_type == 1) {
3113                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3114                                 if (!d)
3115                                         d = 1;
3116                         } else {
3117                                 d = 1;
3118                         }
3119                         if (track->textures[u].compress_format) {
3120
3121                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3122                                 /* compressed textures are block based */
3123                         } else
3124                                 size += w * h * d;
3125                 }
3126                 size *= track->textures[u].cpp;
3127
3128                 switch (track->textures[u].tex_coord_type) {
3129                 case 0:
3130                 case 1:
3131                         break;
3132                 case 2:
3133                         if (track->separate_cube) {
3134                                 ret = r100_cs_track_cube(rdev, track, u);
3135                                 if (ret)
3136                                         return ret;
3137                         } else
3138                                 size *= 6;
3139                         break;
3140                 default:
3141                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3142                                   "%u\n", track->textures[u].tex_coord_type, u);
3143                         return -EINVAL;
3144                 }
3145                 if (size > radeon_bo_size(robj)) {
3146                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3147                                   "%lu\n", u, size, radeon_bo_size(robj));
3148                         r100_cs_track_texture_print(&track->textures[u]);
3149                         return -EINVAL;
3150                 }
3151         }
3152         return 0;
3153 }
3154
3155 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3156 {
3157         unsigned i;
3158         unsigned long size;
3159         unsigned prim_walk;
3160         unsigned nverts;
3161
3162         for (i = 0; i < track->num_cb; i++) {
3163                 if (track->cb[i].robj == NULL) {
3164                         if (!(track->fastfill || track->color_channel_mask ||
3165                               track->blend_read_enable)) {
3166                                 continue;
3167                         }
3168                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3169                         return -EINVAL;
3170                 }
3171                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3172                 size += track->cb[i].offset;
3173                 if (size > radeon_bo_size(track->cb[i].robj)) {
3174                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3175                                   "(need %lu have %lu) !\n", i, size,
3176                                   radeon_bo_size(track->cb[i].robj));
3177                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3178                                   i, track->cb[i].pitch, track->cb[i].cpp,
3179                                   track->cb[i].offset, track->maxy);
3180                         return -EINVAL;
3181                 }
3182         }
3183         if (track->z_enabled) {
3184                 if (track->zb.robj == NULL) {
3185                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3186                         return -EINVAL;
3187                 }
3188                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3189                 size += track->zb.offset;
3190                 if (size > radeon_bo_size(track->zb.robj)) {
3191                         DRM_ERROR("[drm] Buffer too small for z buffer "
3192                                   "(need %lu have %lu) !\n", size,
3193                                   radeon_bo_size(track->zb.robj));
3194                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3195                                   track->zb.pitch, track->zb.cpp,
3196                                   track->zb.offset, track->maxy);
3197                         return -EINVAL;
3198                 }
3199         }
3200         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3201         if (track->vap_vf_cntl & (1 << 14)) {
3202                 nverts = track->vap_alt_nverts;
3203         } else {
3204                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3205         }
3206         switch (prim_walk) {
3207         case 1:
3208                 for (i = 0; i < track->num_arrays; i++) {
3209                         size = track->arrays[i].esize * track->max_indx * 4;
3210                         if (track->arrays[i].robj == NULL) {
3211                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3212                                           "bound\n", prim_walk, i);
3213                                 return -EINVAL;
3214                         }
3215                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3216                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3217                                         "need %lu dwords have %lu dwords\n",
3218                                         prim_walk, i, size >> 2,
3219                                         radeon_bo_size(track->arrays[i].robj)
3220                                         >> 2);
3221                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3222                                 return -EINVAL;
3223                         }
3224                 }
3225                 break;
3226         case 2:
3227                 for (i = 0; i < track->num_arrays; i++) {
3228                         size = track->arrays[i].esize * (nverts - 1) * 4;
3229                         if (track->arrays[i].robj == NULL) {
3230                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3231                                           "bound\n", prim_walk, i);
3232                                 return -EINVAL;
3233                         }
3234                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3235                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3236                                         "need %lu dwords have %lu dwords\n",
3237                                         prim_walk, i, size >> 2,
3238                                         radeon_bo_size(track->arrays[i].robj)
3239                                         >> 2);
3240                                 return -EINVAL;
3241                         }
3242                 }
3243                 break;
3244         case 3:
3245                 size = track->vtx_size * nverts;
3246                 if (size != track->immd_dwords) {
3247                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3248                                   track->immd_dwords, size);
3249                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3250                                   nverts, track->vtx_size);
3251                         return -EINVAL;
3252                 }
3253                 break;
3254         default:
3255                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3256                           prim_walk);
3257                 return -EINVAL;
3258         }
3259         return r100_cs_track_texture_check(rdev, track);
3260 }
3261
3262 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3263 {
3264         unsigned i, face;
3265
3266         if (rdev->family < CHIP_R300) {
3267                 track->num_cb = 1;
3268                 if (rdev->family <= CHIP_RS200)
3269                         track->num_texture = 3;
3270                 else
3271                         track->num_texture = 6;
3272                 track->maxy = 2048;
3273                 track->separate_cube = 1;
3274         } else {
3275                 track->num_cb = 4;
3276                 track->num_texture = 16;
3277                 track->maxy = 4096;
3278                 track->separate_cube = 0;
3279         }
3280
3281         for (i = 0; i < track->num_cb; i++) {
3282                 track->cb[i].robj = NULL;
3283                 track->cb[i].pitch = 8192;
3284                 track->cb[i].cpp = 16;
3285                 track->cb[i].offset = 0;
3286         }
3287         track->z_enabled = true;
3288         track->zb.robj = NULL;
3289         track->zb.pitch = 8192;
3290         track->zb.cpp = 4;
3291         track->zb.offset = 0;
3292         track->vtx_size = 0x7F;
3293         track->immd_dwords = 0xFFFFFFFFUL;
3294         track->num_arrays = 11;
3295         track->max_indx = 0x00FFFFFFUL;
3296         for (i = 0; i < track->num_arrays; i++) {
3297                 track->arrays[i].robj = NULL;
3298                 track->arrays[i].esize = 0x7F;
3299         }
3300         for (i = 0; i < track->num_texture; i++) {
3301                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3302                 track->textures[i].pitch = 16536;
3303                 track->textures[i].width = 16536;
3304                 track->textures[i].height = 16536;
3305                 track->textures[i].width_11 = 1 << 11;
3306                 track->textures[i].height_11 = 1 << 11;
3307                 track->textures[i].num_levels = 12;
3308                 if (rdev->family <= CHIP_RS200) {
3309                         track->textures[i].tex_coord_type = 0;
3310                         track->textures[i].txdepth = 0;
3311                 } else {
3312                         track->textures[i].txdepth = 16;
3313                         track->textures[i].tex_coord_type = 1;
3314                 }
3315                 track->textures[i].cpp = 64;
3316                 track->textures[i].robj = NULL;
3317                 /* CS IB emission code makes sure texture unit are disabled */
3318                 track->textures[i].enabled = false;
3319                 track->textures[i].roundup_w = true;
3320                 track->textures[i].roundup_h = true;
3321                 if (track->separate_cube)
3322                         for (face = 0; face < 5; face++) {
3323                                 track->textures[i].cube_info[face].robj = NULL;
3324                                 track->textures[i].cube_info[face].width = 16536;
3325                                 track->textures[i].cube_info[face].height = 16536;
3326                                 track->textures[i].cube_info[face].offset = 0;
3327                         }
3328         }
3329 }
3330
3331 int r100_ring_test(struct radeon_device *rdev)
3332 {
3333         uint32_t scratch;
3334         uint32_t tmp = 0;
3335         unsigned i;
3336         int r;
3337
3338         r = radeon_scratch_get(rdev, &scratch);
3339         if (r) {
3340                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3341                 return r;
3342         }
3343         WREG32(scratch, 0xCAFEDEAD);
3344         r = radeon_ring_lock(rdev, 2);
3345         if (r) {
3346                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3347                 radeon_scratch_free(rdev, scratch);
3348                 return r;
3349         }
3350         radeon_ring_write(rdev, PACKET0(scratch, 0));
3351         radeon_ring_write(rdev, 0xDEADBEEF);
3352         radeon_ring_unlock_commit(rdev);
3353         for (i = 0; i < rdev->usec_timeout; i++) {
3354                 tmp = RREG32(scratch);
3355                 if (tmp == 0xDEADBEEF) {
3356                         break;
3357                 }
3358                 DRM_UDELAY(1);
3359         }
3360         if (i < rdev->usec_timeout) {
3361                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3362         } else {
3363                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3364                           scratch, tmp);
3365                 r = -EINVAL;
3366         }
3367         radeon_scratch_free(rdev, scratch);
3368         return r;
3369 }
3370
3371 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3372 {
3373         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3374         radeon_ring_write(rdev, ib->gpu_addr);
3375         radeon_ring_write(rdev, ib->length_dw);
3376 }
3377
3378 int r100_ib_test(struct radeon_device *rdev)
3379 {
3380         struct radeon_ib *ib;
3381         uint32_t scratch;
3382         uint32_t tmp = 0;
3383         unsigned i;
3384         int r;
3385
3386         r = radeon_scratch_get(rdev, &scratch);
3387         if (r) {
3388                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3389                 return r;
3390         }
3391         WREG32(scratch, 0xCAFEDEAD);
3392         r = radeon_ib_get(rdev, &ib);
3393         if (r) {
3394                 return r;
3395         }
3396         ib->ptr[0] = PACKET0(scratch, 0);
3397         ib->ptr[1] = 0xDEADBEEF;
3398         ib->ptr[2] = PACKET2(0);
3399         ib->ptr[3] = PACKET2(0);
3400         ib->ptr[4] = PACKET2(0);
3401         ib->ptr[5] = PACKET2(0);
3402         ib->ptr[6] = PACKET2(0);
3403         ib->ptr[7] = PACKET2(0);
3404         ib->length_dw = 8;
3405         r = radeon_ib_schedule(rdev, ib);
3406         if (r) {
3407                 radeon_scratch_free(rdev, scratch);
3408                 radeon_ib_free(rdev, &ib);
3409                 return r;
3410         }
3411         r = radeon_fence_wait(ib->fence, false);
3412         if (r) {
3413                 return r;
3414         }
3415         for (i = 0; i < rdev->usec_timeout; i++) {
3416                 tmp = RREG32(scratch);
3417                 if (tmp == 0xDEADBEEF) {
3418                         break;
3419                 }
3420                 DRM_UDELAY(1);
3421         }
3422         if (i < rdev->usec_timeout) {
3423                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3424         } else {
3425                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3426                           scratch, tmp);
3427                 r = -EINVAL;
3428         }
3429         radeon_scratch_free(rdev, scratch);
3430         radeon_ib_free(rdev, &ib);
3431         return r;
3432 }
3433
3434 void r100_ib_fini(struct radeon_device *rdev)
3435 {
3436         radeon_ib_pool_fini(rdev);
3437 }
3438
3439 int r100_ib_init(struct radeon_device *rdev)
3440 {
3441         int r;
3442
3443         r = radeon_ib_pool_init(rdev);
3444         if (r) {
3445                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3446                 r100_ib_fini(rdev);
3447                 return r;
3448         }
3449         r = r100_ib_test(rdev);
3450         if (r) {
3451                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3452                 r100_ib_fini(rdev);
3453                 return r;
3454         }
3455         return 0;
3456 }
3457
3458 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3459 {
3460         /* Shutdown CP we shouldn't need to do that but better be safe than
3461          * sorry
3462          */
3463         rdev->cp.ready = false;
3464         WREG32(R_000740_CP_CSQ_CNTL, 0);
3465
3466         /* Save few CRTC registers */
3467         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3468         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3469         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3470         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3471         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3472                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3473                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3474         }
3475
3476         /* Disable VGA aperture access */
3477         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3478         /* Disable cursor, overlay, crtc */
3479         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3480         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3481                                         S_000054_CRTC_DISPLAY_DIS(1));
3482         WREG32(R_000050_CRTC_GEN_CNTL,
3483                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3484                         S_000050_CRTC_DISP_REQ_EN_B(1));
3485         WREG32(R_000420_OV0_SCALE_CNTL,
3486                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3487         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3488         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3489                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3490                                                 S_000360_CUR2_LOCK(1));
3491                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3492                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3493                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3494                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3495                 WREG32(R_000360_CUR2_OFFSET,
3496                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3497         }
3498 }
3499
3500 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3501 {
3502         /* Update base address for crtc */
3503         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3504         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3505                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3506         }
3507         /* Restore CRTC registers */
3508         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3509         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3510         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3511         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3512                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3513         }
3514 }
3515
3516 void r100_vga_render_disable(struct radeon_device *rdev)
3517 {
3518         u32 tmp;
3519
3520         tmp = RREG8(R_0003C2_GENMO_WT);
3521         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3522 }
3523
3524 static void r100_debugfs(struct radeon_device *rdev)
3525 {
3526         int r;
3527
3528         r = r100_debugfs_mc_info_init(rdev);
3529         if (r)
3530                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3531 }
3532
3533 static void r100_mc_program(struct radeon_device *rdev)
3534 {
3535         struct r100_mc_save save;
3536
3537         /* Stops all mc clients */
3538         r100_mc_stop(rdev, &save);
3539         if (rdev->flags & RADEON_IS_AGP) {
3540                 WREG32(R_00014C_MC_AGP_LOCATION,
3541                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3542                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3543                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3544                 if (rdev->family > CHIP_RV200)
3545                         WREG32(R_00015C_AGP_BASE_2,
3546                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3547         } else {
3548                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3549                 WREG32(R_000170_AGP_BASE, 0);
3550                 if (rdev->family > CHIP_RV200)
3551                         WREG32(R_00015C_AGP_BASE_2, 0);
3552         }
3553         /* Wait for mc idle */
3554         if (r100_mc_wait_for_idle(rdev))
3555                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3556         /* Program MC, should be a 32bits limited address space */
3557         WREG32(R_000148_MC_FB_LOCATION,
3558                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3559                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3560         r100_mc_resume(rdev, &save);
3561 }
3562
3563 void r100_clock_startup(struct radeon_device *rdev)
3564 {
3565         u32 tmp;
3566
3567         if (radeon_dynclks != -1 && radeon_dynclks)
3568                 radeon_legacy_set_clock_gating(rdev, 1);
3569         /* We need to force on some of the block */
3570         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3571         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3572         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3573                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3574         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3575 }
3576
3577 static int r100_startup(struct radeon_device *rdev)
3578 {
3579         int r;
3580
3581         /* set common regs */
3582         r100_set_common_regs(rdev);
3583         /* program mc */
3584         r100_mc_program(rdev);
3585         /* Resume clock */
3586         r100_clock_startup(rdev);
3587         /* Initialize GPU configuration (# pipes, ...) */
3588 //      r100_gpu_init(rdev);
3589         /* Initialize GART (initialize after TTM so we can allocate
3590          * memory through TTM but finalize after TTM) */
3591         r100_enable_bm(rdev);
3592         if (rdev->flags & RADEON_IS_PCI) {
3593                 r = r100_pci_gart_enable(rdev);
3594                 if (r)
3595                         return r;
3596         }
3597         /* Enable IRQ */
3598         r100_irq_set(rdev);
3599         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3600         /* 1M ring buffer */
3601         r = r100_cp_init(rdev, 1024 * 1024);
3602         if (r) {
3603                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3604                 return r;
3605         }
3606         r = r100_wb_init(rdev);
3607         if (r)
3608                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3609         r = r100_ib_init(rdev);
3610         if (r) {
3611                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3612                 return r;
3613         }
3614         return 0;
3615 }
3616
3617 int r100_resume(struct radeon_device *rdev)
3618 {
3619         /* Make sur GART are not working */
3620         if (rdev->flags & RADEON_IS_PCI)
3621                 r100_pci_gart_disable(rdev);
3622         /* Resume clock before doing reset */
3623         r100_clock_startup(rdev);
3624         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3625         if (radeon_asic_reset(rdev)) {
3626                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3627                         RREG32(R_000E40_RBBM_STATUS),
3628                         RREG32(R_0007C0_CP_STAT));
3629         }
3630         /* post */
3631         radeon_combios_asic_init(rdev->ddev);
3632         /* Resume clock after posting */
3633         r100_clock_startup(rdev);
3634         /* Initialize surface registers */
3635         radeon_surface_init(rdev);
3636         return r100_startup(rdev);
3637 }
3638
3639 int r100_suspend(struct radeon_device *rdev)
3640 {
3641         r100_cp_disable(rdev);
3642         r100_wb_disable(rdev);
3643         r100_irq_disable(rdev);
3644         if (rdev->flags & RADEON_IS_PCI)
3645                 r100_pci_gart_disable(rdev);
3646         return 0;
3647 }
3648
3649 void r100_fini(struct radeon_device *rdev)
3650 {
3651         radeon_pm_fini(rdev);
3652         r100_cp_fini(rdev);
3653         r100_wb_fini(rdev);
3654         r100_ib_fini(rdev);
3655         radeon_gem_fini(rdev);
3656         if (rdev->flags & RADEON_IS_PCI)
3657                 r100_pci_gart_fini(rdev);
3658         radeon_agp_fini(rdev);
3659         radeon_irq_kms_fini(rdev);
3660         radeon_fence_driver_fini(rdev);
3661         radeon_bo_fini(rdev);
3662         radeon_atombios_fini(rdev);
3663         kfree(rdev->bios);
3664         rdev->bios = NULL;
3665 }
3666
3667 int r100_init(struct radeon_device *rdev)
3668 {
3669         int r;
3670
3671         /* Register debugfs file specific to this group of asics */
3672         r100_debugfs(rdev);
3673         /* Disable VGA */
3674         r100_vga_render_disable(rdev);
3675         /* Initialize scratch registers */
3676         radeon_scratch_init(rdev);
3677         /* Initialize surface registers */
3678         radeon_surface_init(rdev);
3679         /* TODO: disable VGA need to use VGA request */
3680         /* BIOS*/
3681         if (!radeon_get_bios(rdev)) {
3682                 if (ASIC_IS_AVIVO(rdev))
3683                         return -EINVAL;
3684         }
3685         if (rdev->is_atom_bios) {
3686                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3687                 return -EINVAL;
3688         } else {
3689                 r = radeon_combios_init(rdev);
3690                 if (r)
3691                         return r;
3692         }
3693         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3694         if (radeon_asic_reset(rdev)) {
3695                 dev_warn(rdev->dev,
3696                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3697                         RREG32(R_000E40_RBBM_STATUS),
3698                         RREG32(R_0007C0_CP_STAT));
3699         }
3700         /* check if cards are posted or not */
3701         if (radeon_boot_test_post_card(rdev) == false)
3702                 return -EINVAL;
3703         /* Set asic errata */
3704         r100_errata(rdev);
3705         /* Initialize clocks */
3706         radeon_get_clock_info(rdev->ddev);
3707         /* Initialize power management */
3708         radeon_pm_init(rdev);
3709         /* initialize AGP */
3710         if (rdev->flags & RADEON_IS_AGP) {
3711                 r = radeon_agp_init(rdev);
3712                 if (r) {
3713                         radeon_agp_disable(rdev);
3714                 }
3715         }
3716         /* initialize VRAM */
3717         r100_mc_init(rdev);
3718         /* Fence driver */
3719         r = radeon_fence_driver_init(rdev);
3720         if (r)
3721                 return r;
3722         r = radeon_irq_kms_init(rdev);
3723         if (r)
3724                 return r;
3725         /* Memory manager */
3726         r = radeon_bo_init(rdev);
3727         if (r)
3728                 return r;
3729         if (rdev->flags & RADEON_IS_PCI) {
3730                 r = r100_pci_gart_init(rdev);
3731                 if (r)
3732                         return r;
3733         }
3734         r100_set_safe_registers(rdev);
3735         rdev->accel_working = true;
3736         r = r100_startup(rdev);
3737         if (r) {
3738                 /* Somethings want wront with the accel init stop accel */
3739                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3740                 r100_cp_fini(rdev);
3741                 r100_wb_fini(rdev);
3742                 r100_ib_fini(rdev);
3743                 radeon_irq_kms_fini(rdev);
3744                 if (rdev->flags & RADEON_IS_PCI)
3745                         r100_pci_gart_fini(rdev);
3746                 rdev->accel_working = false;
3747         }
3748         return 0;
3749 }