drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44
  45 #include "r100_reg_safe.h"
  46 #include "rn50_reg_safe.h"
  47
  48 /* Firmware Names */
  49 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  50 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  51 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  52 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  53 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  54 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  55 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  56
  57 MODULE_FIRMWARE(FIRMWARE_R100);
  58 MODULE_FIRMWARE(FIRMWARE_R200);
  59 MODULE_FIRMWARE(FIRMWARE_R300);
  60 MODULE_FIRMWARE(FIRMWARE_R420);
  61 MODULE_FIRMWARE(FIRMWARE_RS690);
  62 MODULE_FIRMWARE(FIRMWARE_RS600);
  63 MODULE_FIRMWARE(FIRMWARE_R520);
  64
  65 #include "r100_track.h"
  66
  67 /* This files gather functions specifics to:
  68  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  69  */
  70
  71 void r100_get_power_state(struct radeon_device *rdev,
  72                           enum radeon_pm_action action)
  73 {
  74         int i;
  75         rdev->pm.can_upclock = true;
  76         rdev->pm.can_downclock = true;
  77
  78         switch (action) {
  79         case PM_ACTION_MINIMUM:
  80                 rdev->pm.requested_power_state_index = 0;
  81                 rdev->pm.can_downclock = false;
  82                 break;
  83         case PM_ACTION_DOWNCLOCK:
  84                 if (rdev->pm.current_power_state_index == 0) {
  85                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  86                         rdev->pm.can_downclock = false;
  87                 } else {
  88                         if (rdev->pm.active_crtc_count > 1) {
  89                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
  90                                         if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
  91                                                 continue;
  92                                         else if (i >= rdev->pm.current_power_state_index) {
  93                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  94                                                 break;
  95                                         } else {
  96                                                 rdev->pm.requested_power_state_index = i;
  97                                                 break;
  98                                         }
  99                                 }
 100                         } else
 101                                 rdev->pm.requested_power_state_index =
 102                                         rdev->pm.current_power_state_index - 1;
 103                 }
 104                 break;
 105         case PM_ACTION_UPCLOCK:
 106                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 107                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 108                         rdev->pm.can_upclock = false;
 109                 } else {
 110                         if (rdev->pm.active_crtc_count > 1) {
 111                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 112                                         if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
 113                                                 continue;
 114                                         else if (i <= rdev->pm.current_power_state_index) {
 115                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 116                                                 break;
 117                                         } else {
 118                                                 rdev->pm.requested_power_state_index = i;
 119                                                 break;
 120                                         }
 121                                 }
 122                         } else
 123                                 rdev->pm.requested_power_state_index =
 124                                         rdev->pm.current_power_state_index + 1;
 125                 }
 126                 break;
 127         case PM_ACTION_DEFAULT:
 128                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 129                 rdev->pm.can_upclock = false;
 130                 break;
 131         case PM_ACTION_NONE:
 132         default:
 133                 DRM_ERROR("Requested mode for not defined action\n");
 134                 return;
 135         }
 136         /* only one clock mode per power state */
 137         rdev->pm.requested_clock_mode_index = 0;
 138
 139         DRM_INFO("Requested: e: %d m: %d p: %d\n",
 140                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 141                  clock_info[rdev->pm.requested_clock_mode_index].sclk,
 142                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 143                  clock_info[rdev->pm.requested_clock_mode_index].mclk,
 144                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 145                  pcie_lanes);
 146 }
 147
 148 void r100_set_power_state(struct radeon_device *rdev, bool static_switch)
 149 {
 150         u32 sclk, mclk;
 151
 152         if (rdev->pm.current_power_state_index == rdev->pm.requested_power_state_index)
 153                 return;
 154
 155         if (radeon_gui_idle(rdev)) {
 156
 157                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 158                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 159                 if (sclk > rdev->clock.default_sclk)
 160                         sclk = rdev->clock.default_sclk;
 161
 162                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 163                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 164                 if (mclk > rdev->clock.default_mclk)
 165                         mclk = rdev->clock.default_mclk;
 166                 /* don't change the mclk with multiple crtcs */
 167                 if (rdev->pm.active_crtc_count > 1)
 168                         mclk = rdev->clock.default_mclk;
 169
 170                 /* voltage, pcie lanes, etc.*/
 171                 radeon_pm_misc(rdev);
 172
 173                 if (static_switch) {
 174                         radeon_pm_prepare(rdev);
 175                         /* set engine clock */
 176                         if (sclk != rdev->pm.current_sclk) {
 177                                 radeon_set_engine_clock(rdev, sclk);
 178                                 rdev->pm.current_sclk = sclk;
 179                                 DRM_INFO("Setting: e: %d\n", sclk);
 180                         }
 181                         /* set memory clock */
 182                         if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 183                                 radeon_set_memory_clock(rdev, mclk);
 184                                 rdev->pm.current_mclk = mclk;
 185                                 DRM_INFO("Setting: m: %d\n", mclk);
 186                         }
 187                         radeon_pm_finish(rdev);
 188                 } else {
 189                         radeon_sync_with_vblank(rdev);
 190
 191                         if (!radeon_pm_in_vbl(rdev))
 192                                 return;
 193
 194                         radeon_pm_prepare(rdev);
 195                         /* set engine clock */
 196                         if (sclk != rdev->pm.current_sclk) {
 197                                 radeon_pm_debug_check_in_vbl(rdev, false);
 198                                 radeon_set_engine_clock(rdev, sclk);
 199                                 radeon_pm_debug_check_in_vbl(rdev, true);
 200                                 rdev->pm.current_sclk = sclk;
 201                                 DRM_INFO("Setting: e: %d\n", sclk);
 202                         }
 203
 204                         /* set memory clock */
 205                         if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 206                                 radeon_pm_debug_check_in_vbl(rdev, false);
 207                                 radeon_set_memory_clock(rdev, mclk);
 208                                 radeon_pm_debug_check_in_vbl(rdev, true);
 209                                 rdev->pm.current_mclk = mclk;
 210                                 DRM_INFO("Setting: m: %d\n", mclk);
 211                         }
 212                         radeon_pm_finish(rdev);
 213                 }
 214
 215                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 216                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 217         } else
 218                 DRM_INFO("GUI not idle!!!\n");
 219 }
 220
 221 void r100_pm_misc(struct radeon_device *rdev)
 222 {
 223         int requested_index = rdev->pm.requested_power_state_index;
 224         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 225         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 226         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 227
 228         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 229                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 230                         tmp = RREG32(voltage->gpio.reg);
 231                         if (voltage->active_high)
 232                                 tmp |= voltage->gpio.mask;
 233                         else
 234                                 tmp &= ~(voltage->gpio.mask);
 235                         WREG32(voltage->gpio.reg, tmp);
 236                         if (voltage->delay)
 237                                 udelay(voltage->delay);
 238                 } else {
 239                         tmp = RREG32(voltage->gpio.reg);
 240                         if (voltage->active_high)
 241                                 tmp &= ~voltage->gpio.mask;
 242                         else
 243                                 tmp |= voltage->gpio.mask;
 244                         WREG32(voltage->gpio.reg, tmp);
 245                         if (voltage->delay)
 246                                 udelay(voltage->delay);
 247                 }
 248         }
 249
 250         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 251         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 252         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 253         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 254         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 255         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 256                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 257                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 258                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 259                 else
 260                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 261                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 262                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 263                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 264                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 265         } else
 266                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 267
 268         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 269                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 270                 if (voltage->delay) {
 271                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 272                         switch (voltage->delay) {
 273                         case 33:
 274                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 275                                 break;
 276                         case 66:
 277                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 278                                 break;
 279                         case 99:
 280                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 281                                 break;
 282                         case 132:
 283                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 284                                 break;
 285                         }
 286                 } else
 287                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 288         } else
 289                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 290
 291         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 292                 sclk_cntl &= ~FORCE_HDP;
 293         else
 294                 sclk_cntl |= FORCE_HDP;
 295
 296         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 297         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 298         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 299
 300         /* set pcie lanes */
 301         if ((rdev->flags & RADEON_IS_PCIE) &&
 302             !(rdev->flags & RADEON_IS_IGP) &&
 303             rdev->asic->set_pcie_lanes &&
 304             (ps->pcie_lanes !=
 305              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 306                 radeon_set_pcie_lanes(rdev,
 307                                       ps->pcie_lanes);
 308                 DRM_INFO("Setting: p: %d\n", ps->pcie_lanes);
 309         }
 310 }
 311
 312 void r100_pm_prepare(struct radeon_device *rdev)
 313 {
 314         struct drm_device *ddev = rdev->ddev;
 315         struct drm_crtc *crtc;
 316         struct radeon_crtc *radeon_crtc;
 317         u32 tmp;
 318
 319         /* disable any active CRTCs */
 320         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 321                 radeon_crtc = to_radeon_crtc(crtc);
 322                 if (radeon_crtc->enabled) {
 323                         if (radeon_crtc->crtc_id) {
 324                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 325                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 326                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 327                         } else {
 328                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 329                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 330                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 331                         }
 332                 }
 333         }
 334 }
 335
 336 void r100_pm_finish(struct radeon_device *rdev)
 337 {
 338         struct drm_device *ddev = rdev->ddev;
 339         struct drm_crtc *crtc;
 340         struct radeon_crtc *radeon_crtc;
 341         u32 tmp;
 342
 343         /* enable any active CRTCs */
 344         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 345                 radeon_crtc = to_radeon_crtc(crtc);
 346                 if (radeon_crtc->enabled) {
 347                         if (radeon_crtc->crtc_id) {
 348                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 349                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 350                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 351                         } else {
 352                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 353                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 354                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 355                         }
 356                 }
 357         }
 358 }
 359
 360 bool r100_gui_idle(struct radeon_device *rdev)
 361 {
 362         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 363                 return false;
 364         else
 365                 return true;
 366 }
 367
 368 /* hpd for digital panel detect/disconnect */
 369 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 370 {
 371         bool connected = false;
 372
 373         switch (hpd) {
 374         case RADEON_HPD_1:
 375                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 376                         connected = true;
 377                 break;
 378         case RADEON_HPD_2:
 379                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 380                         connected = true;
 381                 break;
 382         default:
 383                 break;
 384         }
 385         return connected;
 386 }
 387
 388 void r100_hpd_set_polarity(struct radeon_device *rdev,
 389                            enum radeon_hpd_id hpd)
 390 {
 391         u32 tmp;
 392         bool connected = r100_hpd_sense(rdev, hpd);
 393
 394         switch (hpd) {
 395         case RADEON_HPD_1:
 396                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 397                 if (connected)
 398                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 399                 else
 400                         tmp |= RADEON_FP_DETECT_INT_POL;
 401                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 402                 break;
 403         case RADEON_HPD_2:
 404                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 405                 if (connected)
 406                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 407                 else
 408                         tmp |= RADEON_FP2_DETECT_INT_POL;
 409                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 410                 break;
 411         default:
 412                 break;
 413         }
 414 }
 415
 416 void r100_hpd_init(struct radeon_device *rdev)
 417 {
 418         struct drm_device *dev = rdev->ddev;
 419         struct drm_connector *connector;
 420
 421         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 422                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 423                 switch (radeon_connector->hpd.hpd) {
 424                 case RADEON_HPD_1:
 425                         rdev->irq.hpd[0] = true;
 426                         break;
 427                 case RADEON_HPD_2:
 428                         rdev->irq.hpd[1] = true;
 429                         break;
 430                 default:
 431                         break;
 432                 }
 433         }
 434         if (rdev->irq.installed)
 435                 r100_irq_set(rdev);
 436 }
 437
 438 void r100_hpd_fini(struct radeon_device *rdev)
 439 {
 440         struct drm_device *dev = rdev->ddev;
 441         struct drm_connector *connector;
 442
 443         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 444                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 445                 switch (radeon_connector->hpd.hpd) {
 446                 case RADEON_HPD_1:
 447                         rdev->irq.hpd[0] = false;
 448                         break;
 449                 case RADEON_HPD_2:
 450                         rdev->irq.hpd[1] = false;
 451                         break;
 452                 default:
 453                         break;
 454                 }
 455         }
 456 }
 457
 458 /*
 459  * PCI GART
 460  */
 461 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 462 {
 463         /* TODO: can we do somethings here ? */
 464         /* It seems hw only cache one entry so we should discard this
 465          * entry otherwise if first GPU GART read hit this entry it
 466          * could end up in wrong address. */
 467 }
 468
 469 int r100_pci_gart_init(struct radeon_device *rdev)
 470 {
 471         int r;
 472
 473         if (rdev->gart.table.ram.ptr) {
 474                 WARN(1, "R100 PCI GART already initialized.\n");
 475                 return 0;
 476         }
 477         /* Initialize common gart structure */
 478         r = radeon_gart_init(rdev);
 479         if (r)
 480                 return r;
 481         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 482         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 483         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 484         return radeon_gart_table_ram_alloc(rdev);
 485 }
 486
 487 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 488 void r100_enable_bm(struct radeon_device *rdev)
 489 {
 490         uint32_t tmp;
 491         /* Enable bus mastering */
 492         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 493         WREG32(RADEON_BUS_CNTL, tmp);
 494 }
 495
 496 int r100_pci_gart_enable(struct radeon_device *rdev)
 497 {
 498         uint32_t tmp;
 499
 500         radeon_gart_restore(rdev);
 501         /* discard memory request outside of configured range */
 502         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 503         WREG32(RADEON_AIC_CNTL, tmp);
 504         /* set address range for PCI address translate */
 505         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 506         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 507         /* set PCI GART page-table base address */
 508         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 509         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 510         WREG32(RADEON_AIC_CNTL, tmp);
 511         r100_pci_gart_tlb_flush(rdev);
 512         rdev->gart.ready = true;
 513         return 0;
 514 }
 515
 516 void r100_pci_gart_disable(struct radeon_device *rdev)
 517 {
 518         uint32_t tmp;
 519
 520         /* discard memory request outside of configured range */
 521         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 522         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 523         WREG32(RADEON_AIC_LO_ADDR, 0);
 524         WREG32(RADEON_AIC_HI_ADDR, 0);
 525 }
 526
 527 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 528 {
 529         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 530                 return -EINVAL;
 531         }
 532         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 533         return 0;
 534 }
 535
 536 void r100_pci_gart_fini(struct radeon_device *rdev)
 537 {
 538         radeon_gart_fini(rdev);
 539         r100_pci_gart_disable(rdev);
 540         radeon_gart_table_ram_free(rdev);
 541 }
 542
 543 int r100_irq_set(struct radeon_device *rdev)
 544 {
 545         uint32_t tmp = 0;
 546
 547         if (!rdev->irq.installed) {
 548                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
 549                 WREG32(R_000040_GEN_INT_CNTL, 0);
 550                 return -EINVAL;
 551         }
 552         if (rdev->irq.sw_int) {
 553                 tmp |= RADEON_SW_INT_ENABLE;
 554         }
 555         if (rdev->irq.gui_idle) {
 556                 tmp |= RADEON_GUI_IDLE_MASK;
 557         }
 558         if (rdev->irq.crtc_vblank_int[0]) {
 559                 tmp |= RADEON_CRTC_VBLANK_MASK;
 560         }
 561         if (rdev->irq.crtc_vblank_int[1]) {
 562                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 563         }
 564         if (rdev->irq.hpd[0]) {
 565                 tmp |= RADEON_FP_DETECT_MASK;
 566         }
 567         if (rdev->irq.hpd[1]) {
 568                 tmp |= RADEON_FP2_DETECT_MASK;
 569         }
 570         WREG32(RADEON_GEN_INT_CNTL, tmp);
 571         return 0;
 572 }
 573
 574 void r100_irq_disable(struct radeon_device *rdev)
 575 {
 576         u32 tmp;
 577
 578         WREG32(R_000040_GEN_INT_CNTL, 0);
 579         /* Wait and acknowledge irq */
 580         mdelay(1);
 581         tmp = RREG32(R_000044_GEN_INT_STATUS);
 582         WREG32(R_000044_GEN_INT_STATUS, tmp);
 583 }
 584
 585 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 586 {
 587         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 588         uint32_t irq_mask = RADEON_SW_INT_TEST |
 589                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 590                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 591
 592         /* the interrupt works, but the status bit is permanently asserted */
 593         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 594                 if (!rdev->irq.gui_idle_acked)
 595                         irq_mask |= RADEON_GUI_IDLE_STAT;
 596         }
 597
 598         if (irqs) {
 599                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 600         }
 601         return irqs & irq_mask;
 602 }
 603
 604 int r100_irq_process(struct radeon_device *rdev)
 605 {
 606         uint32_t status, msi_rearm;
 607         bool queue_hotplug = false;
 608
 609         /* reset gui idle ack.  the status bit is broken */
 610         rdev->irq.gui_idle_acked = false;
 611
 612         status = r100_irq_ack(rdev);
 613         if (!status) {
 614                 return IRQ_NONE;
 615         }
 616         if (rdev->shutdown) {
 617                 return IRQ_NONE;
 618         }
 619         while (status) {
 620                 /* SW interrupt */
 621                 if (status & RADEON_SW_INT_TEST) {
 622                         radeon_fence_process(rdev);
 623                 }
 624                 /* gui idle interrupt */
 625                 if (status & RADEON_GUI_IDLE_STAT) {
 626                         rdev->irq.gui_idle_acked = true;
 627                         rdev->pm.gui_idle = true;
 628                         wake_up(&rdev->irq.idle_queue);
 629                 }
 630                 /* Vertical blank interrupts */
 631                 if (status & RADEON_CRTC_VBLANK_STAT) {
 632                         drm_handle_vblank(rdev->ddev, 0);
 633                         rdev->pm.vblank_sync = true;
 634                         wake_up(&rdev->irq.vblank_queue);
 635                 }
 636                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 637                         drm_handle_vblank(rdev->ddev, 1);
 638                         rdev->pm.vblank_sync = true;
 639                         wake_up(&rdev->irq.vblank_queue);
 640                 }
 641                 if (status & RADEON_FP_DETECT_STAT) {
 642                         queue_hotplug = true;
 643                         DRM_DEBUG("HPD1\n");
 644                 }
 645                 if (status & RADEON_FP2_DETECT_STAT) {
 646                         queue_hotplug = true;
 647                         DRM_DEBUG("HPD2\n");
 648                 }
 649                 status = r100_irq_ack(rdev);
 650         }
 651         /* reset gui idle ack.  the status bit is broken */
 652         rdev->irq.gui_idle_acked = false;
 653         if (queue_hotplug)
 654                 queue_work(rdev->wq, &rdev->hotplug_work);
 655         if (rdev->msi_enabled) {
 656                 switch (rdev->family) {
 657                 case CHIP_RS400:
 658                 case CHIP_RS480:
 659                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 660                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 661                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 662                         break;
 663                 default:
 664                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 665                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 666                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 667                         break;
 668                 }
 669         }
 670         return IRQ_HANDLED;
 671 }
 672
 673 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 674 {
 675         if (crtc == 0)
 676                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 677         else
 678                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 679 }
 680
 681 /* Who ever call radeon_fence_emit should call ring_lock and ask
 682  * for enough space (today caller are ib schedule and buffer move) */
 683 void r100_fence_ring_emit(struct radeon_device *rdev,
 684                           struct radeon_fence *fence)
 685 {
 686         /* We have to make sure that caches are flushed before
 687          * CPU might read something from VRAM. */
 688         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 689         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 690         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 691         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 692         /* Wait until IDLE & CLEAN */
 693         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 694         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 695         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 696         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 697                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 698         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 699         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 700         /* Emit fence sequence & fire IRQ */
 701         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 702         radeon_ring_write(rdev, fence->seq);
 703         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 704         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 705 }
 706
 707 int r100_wb_init(struct radeon_device *rdev)
 708 {
 709         int r;
 710
 711         if (rdev->wb.wb_obj == NULL) {
 712                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
 713                                         RADEON_GEM_DOMAIN_GTT,
 714                                         &rdev->wb.wb_obj);
 715                 if (r) {
 716                         dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
 717                         return r;
 718                 }
 719                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 720                 if (unlikely(r != 0))
 721                         return r;
 722                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 723                                         &rdev->wb.gpu_addr);
 724                 if (r) {
 725                         dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
 726                         radeon_bo_unreserve(rdev->wb.wb_obj);
 727                         return r;
 728                 }
 729                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 730                 radeon_bo_unreserve(rdev->wb.wb_obj);
 731                 if (r) {
 732                         dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
 733                         return r;
 734                 }
 735         }
 736         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
 737         WREG32(R_00070C_CP_RB_RPTR_ADDR,
 738                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
 739         WREG32(R_000770_SCRATCH_UMSK, 0xff);
 740         return 0;
 741 }
 742
 743 void r100_wb_disable(struct radeon_device *rdev)
 744 {
 745         WREG32(R_000770_SCRATCH_UMSK, 0);
 746 }
 747
 748 void r100_wb_fini(struct radeon_device *rdev)
 749 {
 750         int r;
 751
 752         r100_wb_disable(rdev);
 753         if (rdev->wb.wb_obj) {
 754                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 755                 if (unlikely(r != 0)) {
 756                         dev_err(rdev->dev, "(%d) can't finish WB\n", r);
 757                         return;
 758                 }
 759                 radeon_bo_kunmap(rdev->wb.wb_obj);
 760                 radeon_bo_unpin(rdev->wb.wb_obj);
 761                 radeon_bo_unreserve(rdev->wb.wb_obj);
 762                 radeon_bo_unref(&rdev->wb.wb_obj);
 763                 rdev->wb.wb = NULL;
 764                 rdev->wb.wb_obj = NULL;
 765         }
 766 }
 767
 768 int r100_copy_blit(struct radeon_device *rdev,
 769                    uint64_t src_offset,
 770                    uint64_t dst_offset,
 771                    unsigned num_pages,
 772                    struct radeon_fence *fence)
 773 {
 774         uint32_t cur_pages;
 775         uint32_t stride_bytes = PAGE_SIZE;
 776         uint32_t pitch;
 777         uint32_t stride_pixels;
 778         unsigned ndw;
 779         int num_loops;
 780         int r = 0;
 781
 782         /* radeon limited to 16k stride */
 783         stride_bytes &= 0x3fff;
 784         /* radeon pitch is /64 */
 785         pitch = stride_bytes / 64;
 786         stride_pixels = stride_bytes / 4;
 787         num_loops = DIV_ROUND_UP(num_pages, 8191);
 788
 789         /* Ask for enough room for blit + flush + fence */
 790         ndw = 64 + (10 * num_loops);
 791         r = radeon_ring_lock(rdev, ndw);
 792         if (r) {
 793                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 794                 return -EINVAL;
 795         }
 796         while (num_pages > 0) {
 797                 cur_pages = num_pages;
 798                 if (cur_pages > 8191) {
 799                         cur_pages = 8191;
 800                 }
 801                 num_pages -= cur_pages;
 802
 803                 /* pages are in Y direction - height
 804                    page width in X direction - width */
 805                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 806                 radeon_ring_write(rdev,
 807                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 808                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 809                                   RADEON_GMC_SRC_CLIPPING |
 810                                   RADEON_GMC_DST_CLIPPING |
 811                                   RADEON_GMC_BRUSH_NONE |
 812                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 813                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 814                                   RADEON_ROP3_S |
 815                                   RADEON_DP_SRC_SOURCE_MEMORY |
 816                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 817                                   RADEON_GMC_WR_MSK_DIS);
 818                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 819                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 820                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 821                 radeon_ring_write(rdev, 0);
 822                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 823                 radeon_ring_write(rdev, num_pages);
 824                 radeon_ring_write(rdev, num_pages);
 825                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 826         }
 827         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 828         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 829         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 830         radeon_ring_write(rdev,
 831                           RADEON_WAIT_2D_IDLECLEAN |
 832                           RADEON_WAIT_HOST_IDLECLEAN |
 833                           RADEON_WAIT_DMA_GUI_IDLE);
 834         if (fence) {
 835                 r = radeon_fence_emit(rdev, fence);
 836         }
 837         radeon_ring_unlock_commit(rdev);
 838         return r;
 839 }
 840
 841 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 842 {
 843         unsigned i;
 844         u32 tmp;
 845
 846         for (i = 0; i < rdev->usec_timeout; i++) {
 847                 tmp = RREG32(R_000E40_RBBM_STATUS);
 848                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 849                         return 0;
 850                 }
 851                 udelay(1);
 852         }
 853         return -1;
 854 }
 855
 856 void r100_ring_start(struct radeon_device *rdev)
 857 {
 858         int r;
 859
 860         r = radeon_ring_lock(rdev, 2);
 861         if (r) {
 862                 return;
 863         }
 864         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 865         radeon_ring_write(rdev,
 866                           RADEON_ISYNC_ANY2D_IDLE3D |
 867                           RADEON_ISYNC_ANY3D_IDLE2D |
 868                           RADEON_ISYNC_WAIT_IDLEGUI |
 869                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 870         radeon_ring_unlock_commit(rdev);
 871 }
 872
 873
 874 /* Load the microcode for the CP */
 875 static int r100_cp_init_microcode(struct radeon_device *rdev)
 876 {
 877         struct platform_device *pdev;
 878         const char *fw_name = NULL;
 879         int err;
 880
 881         DRM_DEBUG("\n");
 882
 883         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 884         err = IS_ERR(pdev);
 885         if (err) {
 886                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 887                 return -EINVAL;
 888         }
 889         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 890             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 891             (rdev->family == CHIP_RS200)) {
 892                 DRM_INFO("Loading R100 Microcode\n");
 893                 fw_name = FIRMWARE_R100;
 894         } else if ((rdev->family == CHIP_R200) ||
 895                    (rdev->family == CHIP_RV250) ||
 896                    (rdev->family == CHIP_RV280) ||
 897                    (rdev->family == CHIP_RS300)) {
 898                 DRM_INFO("Loading R200 Microcode\n");
 899                 fw_name = FIRMWARE_R200;
 900         } else if ((rdev->family == CHIP_R300) ||
 901                    (rdev->family == CHIP_R350) ||
 902                    (rdev->family == CHIP_RV350) ||
 903                    (rdev->family == CHIP_RV380) ||
 904                    (rdev->family == CHIP_RS400) ||
 905                    (rdev->family == CHIP_RS480)) {
 906                 DRM_INFO("Loading R300 Microcode\n");
 907                 fw_name = FIRMWARE_R300;
 908         } else if ((rdev->family == CHIP_R420) ||
 909                    (rdev->family == CHIP_R423) ||
 910                    (rdev->family == CHIP_RV410)) {
 911                 DRM_INFO("Loading R400 Microcode\n");
 912                 fw_name = FIRMWARE_R420;
 913         } else if ((rdev->family == CHIP_RS690) ||
 914                    (rdev->family == CHIP_RS740)) {
 915                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 916                 fw_name = FIRMWARE_RS690;
 917         } else if (rdev->family == CHIP_RS600) {
 918                 DRM_INFO("Loading RS600 Microcode\n");
 919                 fw_name = FIRMWARE_RS600;
 920         } else if ((rdev->family == CHIP_RV515) ||
 921                    (rdev->family == CHIP_R520) ||
 922                    (rdev->family == CHIP_RV530) ||
 923                    (rdev->family == CHIP_R580) ||
 924                    (rdev->family == CHIP_RV560) ||
 925                    (rdev->family == CHIP_RV570)) {
 926                 DRM_INFO("Loading R500 Microcode\n");
 927                 fw_name = FIRMWARE_R520;
 928         }
 929
 930         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 931         platform_device_unregister(pdev);
 932         if (err) {
 933                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 934                        fw_name);
 935         } else if (rdev->me_fw->size % 8) {
 936                 printk(KERN_ERR
 937                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 938                        rdev->me_fw->size, fw_name);
 939                 err = -EINVAL;
 940                 release_firmware(rdev->me_fw);
 941                 rdev->me_fw = NULL;
 942         }
 943         return err;
 944 }
 945
 946 static void r100_cp_load_microcode(struct radeon_device *rdev)
 947 {
 948         const __be32 *fw_data;
 949         int i, size;
 950
 951         if (r100_gui_wait_for_idle(rdev)) {
 952                 printk(KERN_WARNING "Failed to wait GUI idle while "
 953                        "programming pipes. Bad things might happen.\n");
 954         }
 955
 956         if (rdev->me_fw) {
 957                 size = rdev->me_fw->size / 4;
 958                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 959                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 960                 for (i = 0; i < size; i += 2) {
 961                         WREG32(RADEON_CP_ME_RAM_DATAH,
 962                                be32_to_cpup(&fw_data[i]));
 963                         WREG32(RADEON_CP_ME_RAM_DATAL,
 964                                be32_to_cpup(&fw_data[i + 1]));
 965                 }
 966         }
 967 }
 968
 969 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 970 {
 971         unsigned rb_bufsz;
 972         unsigned rb_blksz;
 973         unsigned max_fetch;
 974         unsigned pre_write_timer;
 975         unsigned pre_write_limit;
 976         unsigned indirect2_start;
 977         unsigned indirect1_start;
 978         uint32_t tmp;
 979         int r;
 980
 981         if (r100_debugfs_cp_init(rdev)) {
 982                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 983         }
 984         if (!rdev->me_fw) {
 985                 r = r100_cp_init_microcode(rdev);
 986                 if (r) {
 987                         DRM_ERROR("Failed to load firmware!\n");
 988                         return r;
 989                 }
 990         }
 991
 992         /* Align ring size */
 993         rb_bufsz = drm_order(ring_size / 8);
 994         ring_size = (1 << (rb_bufsz + 1)) * 4;
 995         r100_cp_load_microcode(rdev);
 996         r = radeon_ring_init(rdev, ring_size);
 997         if (r) {
 998                 return r;
 999         }
1000         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1001          * the rptr copy in system ram */
1002         rb_blksz = 9;
1003         /* cp will read 128bytes at a time (4 dwords) */
1004         max_fetch = 1;
1005         rdev->cp.align_mask = 16 - 1;
1006         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1007         pre_write_timer = 64;
1008         /* Force CP_RB_WPTR write if written more than one time before the
1009          * delay expire
1010          */
1011         pre_write_limit = 0;
1012         /* Setup the cp cache like this (cache size is 96 dwords) :
1013          *      RING            0  to 15
1014          *      INDIRECT1       16 to 79
1015          *      INDIRECT2       80 to 95
1016          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1017          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1018          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1019          * Idea being that most of the gpu cmd will be through indirect1 buffer
1020          * so it gets the bigger cache.
1021          */
1022         indirect2_start = 80;
1023         indirect1_start = 16;
1024         /* cp setup */
1025         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1026         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1027                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1028                REG_SET(RADEON_MAX_FETCH, max_fetch) |
1029                RADEON_RB_NO_UPDATE);
1030 #ifdef __BIG_ENDIAN
1031         tmp |= RADEON_BUF_SWAP_32BIT;
1032 #endif
1033         WREG32(RADEON_CP_RB_CNTL, tmp);
1034
1035         /* Set ring address */
1036         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1037         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1038         /* Force read & write ptr to 0 */
1039         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
1040         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1041         WREG32(RADEON_CP_RB_WPTR, 0);
1042         WREG32(RADEON_CP_RB_CNTL, tmp);
1043         udelay(10);
1044         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1045         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
1046         /* protect against crazy HW on resume */
1047         rdev->cp.wptr &= rdev->cp.ptr_mask;
1048         /* Set cp mode to bus mastering & enable cp*/
1049         WREG32(RADEON_CP_CSQ_MODE,
1050                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1051                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1052         WREG32(0x718, 0);
1053         WREG32(0x744, 0x00004D4D);
1054         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1055         radeon_ring_start(rdev);
1056         r = radeon_ring_test(rdev);
1057         if (r) {
1058                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1059                 return r;
1060         }
1061         rdev->cp.ready = true;
1062         return 0;
1063 }
1064
1065 void r100_cp_fini(struct radeon_device *rdev)
1066 {
1067         if (r100_cp_wait_for_idle(rdev)) {
1068                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1069         }
1070         /* Disable ring */
1071         r100_cp_disable(rdev);
1072         radeon_ring_fini(rdev);
1073         DRM_INFO("radeon: cp finalized\n");
1074 }
1075
1076 void r100_cp_disable(struct radeon_device *rdev)
1077 {
1078         /* Disable ring */
1079         rdev->cp.ready = false;
1080         WREG32(RADEON_CP_CSQ_MODE, 0);
1081         WREG32(RADEON_CP_CSQ_CNTL, 0);
1082         if (r100_gui_wait_for_idle(rdev)) {
1083                 printk(KERN_WARNING "Failed to wait GUI idle while "
1084                        "programming pipes. Bad things might happen.\n");
1085         }
1086 }
1087
1088 void r100_cp_commit(struct radeon_device *rdev)
1089 {
1090         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1091         (void)RREG32(RADEON_CP_RB_WPTR);
1092 }
1093
1094
1095 /*
1096  * CS functions
1097  */
1098 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1099                           struct radeon_cs_packet *pkt,
1100                           const unsigned *auth, unsigned n,
1101                           radeon_packet0_check_t check)
1102 {
1103         unsigned reg;
1104         unsigned i, j, m;
1105         unsigned idx;
1106         int r;
1107
1108         idx = pkt->idx + 1;
1109         reg = pkt->reg;
1110         /* Check that register fall into register range
1111          * determined by the number of entry (n) in the
1112          * safe register bitmap.
1113          */
1114         if (pkt->one_reg_wr) {
1115                 if ((reg >> 7) > n) {
1116                         return -EINVAL;
1117                 }
1118         } else {
1119                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1120                         return -EINVAL;
1121                 }
1122         }
1123         for (i = 0; i <= pkt->count; i++, idx++) {
1124                 j = (reg >> 7);
1125                 m = 1 << ((reg >> 2) & 31);
1126                 if (auth[j] & m) {
1127                         r = check(p, pkt, idx, reg);
1128                         if (r) {
1129                                 return r;
1130                         }
1131                 }
1132                 if (pkt->one_reg_wr) {
1133                         if (!(auth[j] & m)) {
1134                                 break;
1135                         }
1136                 } else {
1137                         reg += 4;
1138                 }
1139         }
1140         return 0;
1141 }
1142
1143 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1144                          struct radeon_cs_packet *pkt)
1145 {
1146         volatile uint32_t *ib;
1147         unsigned i;
1148         unsigned idx;
1149
1150         ib = p->ib->ptr;
1151         idx = pkt->idx;
1152         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1153                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1154         }
1155 }
1156
1157 /**
1158  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1159  * @parser:     parser structure holding parsing context.
1160  * @pkt:        where to store packet informations
1161  *
1162  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1163  * if packet is bigger than remaining ib size. or if packets is unknown.
1164  **/
1165 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1166                          struct radeon_cs_packet *pkt,
1167                          unsigned idx)
1168 {
1169         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1170         uint32_t header;
1171
1172         if (idx >= ib_chunk->length_dw) {
1173                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1174                           idx, ib_chunk->length_dw);
1175                 return -EINVAL;
1176         }
1177         header = radeon_get_ib_value(p, idx);
1178         pkt->idx = idx;
1179         pkt->type = CP_PACKET_GET_TYPE(header);
1180         pkt->count = CP_PACKET_GET_COUNT(header);
1181         switch (pkt->type) {
1182         case PACKET_TYPE0:
1183                 pkt->reg = CP_PACKET0_GET_REG(header);
1184                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1185                 break;
1186         case PACKET_TYPE3:
1187                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1188                 break;
1189         case PACKET_TYPE2:
1190                 pkt->count = -1;
1191                 break;
1192         default:
1193                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1194                 return -EINVAL;
1195         }
1196         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1197                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1198                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1199                 return -EINVAL;
1200         }
1201         return 0;
1202 }
1203
1204 /**
1205  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1206  * @parser:             parser structure holding parsing context.
1207  *
1208  * Userspace sends a special sequence for VLINE waits.
1209  * PACKET0 - VLINE_START_END + value
1210  * PACKET0 - WAIT_UNTIL +_value
1211  * RELOC (P3) - crtc_id in reloc.
1212  *
1213  * This function parses this and relocates the VLINE START END
1214  * and WAIT UNTIL packets to the correct crtc.
1215  * It also detects a switched off crtc and nulls out the
1216  * wait in that case.
1217  */
1218 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1219 {
1220         struct drm_mode_object *obj;
1221         struct drm_crtc *crtc;
1222         struct radeon_crtc *radeon_crtc;
1223         struct radeon_cs_packet p3reloc, waitreloc;
1224         int crtc_id;
1225         int r;
1226         uint32_t header, h_idx, reg;
1227         volatile uint32_t *ib;
1228
1229         ib = p->ib->ptr;
1230
1231         /* parse the wait until */
1232         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1233         if (r)
1234                 return r;
1235
1236         /* check its a wait until and only 1 count */
1237         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1238             waitreloc.count != 0) {
1239                 DRM_ERROR("vline wait had illegal wait until segment\n");
1240                 r = -EINVAL;
1241                 return r;
1242         }
1243
1244         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1245                 DRM_ERROR("vline wait had illegal wait until\n");
1246                 r = -EINVAL;
1247                 return r;
1248         }
1249
1250         /* jump over the NOP */
1251         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1252         if (r)
1253                 return r;
1254
1255         h_idx = p->idx - 2;
1256         p->idx += waitreloc.count + 2;
1257         p->idx += p3reloc.count + 2;
1258
1259         header = radeon_get_ib_value(p, h_idx);
1260         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1261         reg = CP_PACKET0_GET_REG(header);
1262         mutex_lock(&p->rdev->ddev->mode_config.mutex);
1263         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1264         if (!obj) {
1265                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1266                 r = -EINVAL;
1267                 goto out;
1268         }
1269         crtc = obj_to_crtc(obj);
1270         radeon_crtc = to_radeon_crtc(crtc);
1271         crtc_id = radeon_crtc->crtc_id;
1272
1273         if (!crtc->enabled) {
1274                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1275                 ib[h_idx + 2] = PACKET2(0);
1276                 ib[h_idx + 3] = PACKET2(0);
1277         } else if (crtc_id == 1) {
1278                 switch (reg) {
1279                 case AVIVO_D1MODE_VLINE_START_END:
1280                         header &= ~R300_CP_PACKET0_REG_MASK;
1281                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1282                         break;
1283                 case RADEON_CRTC_GUI_TRIG_VLINE:
1284                         header &= ~R300_CP_PACKET0_REG_MASK;
1285                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1286                         break;
1287                 default:
1288                         DRM_ERROR("unknown crtc reloc\n");
1289                         r = -EINVAL;
1290                         goto out;
1291                 }
1292                 ib[h_idx] = header;
1293                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1294         }
1295 out:
1296         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1297         return r;
1298 }
1299
1300 /**
1301  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1302  * @parser:             parser structure holding parsing context.
1303  * @data:               pointer to relocation data
1304  * @offset_start:       starting offset
1305  * @offset_mask:        offset mask (to align start offset on)
1306  * @reloc:              reloc informations
1307  *
1308  * Check next packet is relocation packet3, do bo validation and compute
1309  * GPU offset using the provided start.
1310  **/
1311 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1312                               struct radeon_cs_reloc **cs_reloc)
1313 {
1314         struct radeon_cs_chunk *relocs_chunk;
1315         struct radeon_cs_packet p3reloc;
1316         unsigned idx;
1317         int r;
1318
1319         if (p->chunk_relocs_idx == -1) {
1320                 DRM_ERROR("No relocation chunk !\n");
1321                 return -EINVAL;
1322         }
1323         *cs_reloc = NULL;
1324         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1325         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1326         if (r) {
1327                 return r;
1328         }
1329         p->idx += p3reloc.count + 2;
1330         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1331                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1332                           p3reloc.idx);
1333                 r100_cs_dump_packet(p, &p3reloc);
1334                 return -EINVAL;
1335         }
1336         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1337         if (idx >= relocs_chunk->length_dw) {
1338                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1339                           idx, relocs_chunk->length_dw);
1340                 r100_cs_dump_packet(p, &p3reloc);
1341                 return -EINVAL;
1342         }
1343         /* FIXME: we assume reloc size is 4 dwords */
1344         *cs_reloc = p->relocs_ptr[(idx / 4)];
1345         return 0;
1346 }
1347
1348 static int r100_get_vtx_size(uint32_t vtx_fmt)
1349 {
1350         int vtx_size;
1351         vtx_size = 2;
1352         /* ordered according to bits in spec */
1353         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1354                 vtx_size++;
1355         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1356                 vtx_size += 3;
1357         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1358                 vtx_size++;
1359         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1360                 vtx_size++;
1361         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1362                 vtx_size += 3;
1363         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1364                 vtx_size++;
1365         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1366                 vtx_size++;
1367         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1368                 vtx_size += 2;
1369         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1370                 vtx_size += 2;
1371         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1372                 vtx_size++;
1373         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1374                 vtx_size += 2;
1375         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1376                 vtx_size++;
1377         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1378                 vtx_size += 2;
1379         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1380                 vtx_size++;
1381         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1382                 vtx_size++;
1383         /* blend weight */
1384         if (vtx_fmt & (0x7 << 15))
1385                 vtx_size += (vtx_fmt >> 15) & 0x7;
1386         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1387                 vtx_size += 3;
1388         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1389                 vtx_size += 2;
1390         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1391                 vtx_size++;
1392         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1393                 vtx_size++;
1394         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1395                 vtx_size++;
1396         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1397                 vtx_size++;
1398         return vtx_size;
1399 }
1400
1401 static int r100_packet0_check(struct radeon_cs_parser *p,
1402                               struct radeon_cs_packet *pkt,
1403                               unsigned idx, unsigned reg)
1404 {
1405         struct radeon_cs_reloc *reloc;
1406         struct r100_cs_track *track;
1407         volatile uint32_t *ib;
1408         uint32_t tmp;
1409         int r;
1410         int i, face;
1411         u32 tile_flags = 0;
1412         u32 idx_value;
1413
1414         ib = p->ib->ptr;
1415         track = (struct r100_cs_track *)p->track;
1416
1417         idx_value = radeon_get_ib_value(p, idx);
1418
1419         switch (reg) {
1420         case RADEON_CRTC_GUI_TRIG_VLINE:
1421                 r = r100_cs_packet_parse_vline(p);
1422                 if (r) {
1423                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1424                                   idx, reg);
1425                         r100_cs_dump_packet(p, pkt);
1426                         return r;
1427                 }
1428                 break;
1429                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1430                  * range access */
1431         case RADEON_DST_PITCH_OFFSET:
1432         case RADEON_SRC_PITCH_OFFSET:
1433                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1434                 if (r)
1435                         return r;
1436                 break;
1437         case RADEON_RB3D_DEPTHOFFSET:
1438                 r = r100_cs_packet_next_reloc(p, &reloc);
1439                 if (r) {
1440                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1441                                   idx, reg);
1442                         r100_cs_dump_packet(p, pkt);
1443                         return r;
1444                 }
1445                 track->zb.robj = reloc->robj;
1446                 track->zb.offset = idx_value;
1447                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1448                 break;
1449         case RADEON_RB3D_COLOROFFSET:
1450                 r = r100_cs_packet_next_reloc(p, &reloc);
1451                 if (r) {
1452                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1453                                   idx, reg);
1454                         r100_cs_dump_packet(p, pkt);
1455                         return r;
1456                 }
1457                 track->cb[0].robj = reloc->robj;
1458                 track->cb[0].offset = idx_value;
1459                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1460                 break;
1461         case RADEON_PP_TXOFFSET_0:
1462         case RADEON_PP_TXOFFSET_1:
1463         case RADEON_PP_TXOFFSET_2:
1464                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1465                 r = r100_cs_packet_next_reloc(p, &reloc);
1466                 if (r) {
1467                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1468                                   idx, reg);
1469                         r100_cs_dump_packet(p, pkt);
1470                         return r;
1471                 }
1472                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1473                 track->textures[i].robj = reloc->robj;
1474                 break;
1475         case RADEON_PP_CUBIC_OFFSET_T0_0:
1476         case RADEON_PP_CUBIC_OFFSET_T0_1:
1477         case RADEON_PP_CUBIC_OFFSET_T0_2:
1478         case RADEON_PP_CUBIC_OFFSET_T0_3:
1479         case RADEON_PP_CUBIC_OFFSET_T0_4:
1480                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1481                 r = r100_cs_packet_next_reloc(p, &reloc);
1482                 if (r) {
1483                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1484                                   idx, reg);
1485                         r100_cs_dump_packet(p, pkt);
1486                         return r;
1487                 }
1488                 track->textures[0].cube_info[i].offset = idx_value;
1489                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1490                 track->textures[0].cube_info[i].robj = reloc->robj;
1491                 break;
1492         case RADEON_PP_CUBIC_OFFSET_T1_0:
1493         case RADEON_PP_CUBIC_OFFSET_T1_1:
1494         case RADEON_PP_CUBIC_OFFSET_T1_2:
1495         case RADEON_PP_CUBIC_OFFSET_T1_3:
1496         case RADEON_PP_CUBIC_OFFSET_T1_4:
1497                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1498                 r = r100_cs_packet_next_reloc(p, &reloc);
1499                 if (r) {
1500                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1501                                   idx, reg);
1502                         r100_cs_dump_packet(p, pkt);
1503                         return r;
1504                 }
1505                 track->textures[1].cube_info[i].offset = idx_value;
1506                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1507                 track->textures[1].cube_info[i].robj = reloc->robj;
1508                 break;
1509         case RADEON_PP_CUBIC_OFFSET_T2_0:
1510         case RADEON_PP_CUBIC_OFFSET_T2_1:
1511         case RADEON_PP_CUBIC_OFFSET_T2_2:
1512         case RADEON_PP_CUBIC_OFFSET_T2_3:
1513         case RADEON_PP_CUBIC_OFFSET_T2_4:
1514                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1515                 r = r100_cs_packet_next_reloc(p, &reloc);
1516                 if (r) {
1517                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1518                                   idx, reg);
1519                         r100_cs_dump_packet(p, pkt);
1520                         return r;
1521                 }
1522                 track->textures[2].cube_info[i].offset = idx_value;
1523                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1524                 track->textures[2].cube_info[i].robj = reloc->robj;
1525                 break;
1526         case RADEON_RE_WIDTH_HEIGHT:
1527                 track->maxy = ((idx_value >> 16) & 0x7FF);
1528                 break;
1529         case RADEON_RB3D_COLORPITCH:
1530                 r = r100_cs_packet_next_reloc(p, &reloc);
1531                 if (r) {
1532                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1533                                   idx, reg);
1534                         r100_cs_dump_packet(p, pkt);
1535                         return r;
1536                 }
1537
1538                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1539                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1540                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1541                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1542
1543                 tmp = idx_value & ~(0x7 << 16);
1544                 tmp |= tile_flags;
1545                 ib[idx] = tmp;
1546
1547                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1548                 break;
1549         case RADEON_RB3D_DEPTHPITCH:
1550                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1551                 break;
1552         case RADEON_RB3D_CNTL:
1553                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1554                 case 7:
1555                 case 8:
1556                 case 9:
1557                 case 11:
1558                 case 12:
1559                         track->cb[0].cpp = 1;
1560                         break;
1561                 case 3:
1562                 case 4:
1563                 case 15:
1564                         track->cb[0].cpp = 2;
1565                         break;
1566                 case 6:
1567                         track->cb[0].cpp = 4;
1568                         break;
1569                 default:
1570                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1571                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1572                         return -EINVAL;
1573                 }
1574                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1575                 break;
1576         case RADEON_RB3D_ZSTENCILCNTL:
1577                 switch (idx_value & 0xf) {
1578                 case 0:
1579                         track->zb.cpp = 2;
1580                         break;
1581                 case 2:
1582                 case 3:
1583                 case 4:
1584                 case 5:
1585                 case 9:
1586                 case 11:
1587                         track->zb.cpp = 4;
1588                         break;
1589                 default:
1590                         break;
1591                 }
1592                 break;
1593         case RADEON_RB3D_ZPASS_ADDR:
1594                 r = r100_cs_packet_next_reloc(p, &reloc);
1595                 if (r) {
1596                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1597                                   idx, reg);
1598                         r100_cs_dump_packet(p, pkt);
1599                         return r;
1600                 }
1601                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1602                 break;
1603         case RADEON_PP_CNTL:
1604                 {
1605                         uint32_t temp = idx_value >> 4;
1606                         for (i = 0; i < track->num_texture; i++)
1607                                 track->textures[i].enabled = !!(temp & (1 << i));
1608                 }
1609                 break;
1610         case RADEON_SE_VF_CNTL:
1611                 track->vap_vf_cntl = idx_value;
1612                 break;
1613         case RADEON_SE_VTX_FMT:
1614                 track->vtx_size = r100_get_vtx_size(idx_value);
1615                 break;
1616         case RADEON_PP_TEX_SIZE_0:
1617         case RADEON_PP_TEX_SIZE_1:
1618         case RADEON_PP_TEX_SIZE_2:
1619                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1620                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1621                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1622                 break;
1623         case RADEON_PP_TEX_PITCH_0:
1624         case RADEON_PP_TEX_PITCH_1:
1625         case RADEON_PP_TEX_PITCH_2:
1626                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1627                 track->textures[i].pitch = idx_value + 32;
1628                 break;
1629         case RADEON_PP_TXFILTER_0:
1630         case RADEON_PP_TXFILTER_1:
1631         case RADEON_PP_TXFILTER_2:
1632                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1633                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1634                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1635                 tmp = (idx_value >> 23) & 0x7;
1636                 if (tmp == 2 || tmp == 6)
1637                         track->textures[i].roundup_w = false;
1638                 tmp = (idx_value >> 27) & 0x7;
1639                 if (tmp == 2 || tmp == 6)
1640                         track->textures[i].roundup_h = false;
1641                 break;
1642         case RADEON_PP_TXFORMAT_0:
1643         case RADEON_PP_TXFORMAT_1:
1644         case RADEON_PP_TXFORMAT_2:
1645                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1646                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1647                         track->textures[i].use_pitch = 1;
1648                 } else {
1649                         track->textures[i].use_pitch = 0;
1650                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1651                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1652                 }
1653                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1654                         track->textures[i].tex_coord_type = 2;
1655                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1656                 case RADEON_TXFORMAT_I8:
1657                 case RADEON_TXFORMAT_RGB332:
1658                 case RADEON_TXFORMAT_Y8:
1659                         track->textures[i].cpp = 1;
1660                         break;
1661                 case RADEON_TXFORMAT_AI88:
1662                 case RADEON_TXFORMAT_ARGB1555:
1663                 case RADEON_TXFORMAT_RGB565:
1664                 case RADEON_TXFORMAT_ARGB4444:
1665                 case RADEON_TXFORMAT_VYUY422:
1666                 case RADEON_TXFORMAT_YVYU422:
1667                 case RADEON_TXFORMAT_SHADOW16:
1668                 case RADEON_TXFORMAT_LDUDV655:
1669                 case RADEON_TXFORMAT_DUDV88:
1670                         track->textures[i].cpp = 2;
1671                         break;
1672                 case RADEON_TXFORMAT_ARGB8888:
1673                 case RADEON_TXFORMAT_RGBA8888:
1674                 case RADEON_TXFORMAT_SHADOW32:
1675                 case RADEON_TXFORMAT_LDUDUV8888:
1676                         track->textures[i].cpp = 4;
1677                         break;
1678                 case RADEON_TXFORMAT_DXT1:
1679                         track->textures[i].cpp = 1;
1680                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1681                         break;
1682                 case RADEON_TXFORMAT_DXT23:
1683                 case RADEON_TXFORMAT_DXT45:
1684                         track->textures[i].cpp = 1;
1685                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1686                         break;
1687                 }
1688                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1689                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1690                 break;
1691         case RADEON_PP_CUBIC_FACES_0:
1692         case RADEON_PP_CUBIC_FACES_1:
1693         case RADEON_PP_CUBIC_FACES_2:
1694                 tmp = idx_value;
1695                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1696                 for (face = 0; face < 4; face++) {
1697                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1698                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1699                 }
1700                 break;
1701         default:
1702                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1703                        reg, idx);
1704                 return -EINVAL;
1705         }
1706         return 0;
1707 }
1708
1709 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1710                                          struct radeon_cs_packet *pkt,
1711                                          struct radeon_bo *robj)
1712 {
1713         unsigned idx;
1714         u32 value;
1715         idx = pkt->idx + 1;
1716         value = radeon_get_ib_value(p, idx + 2);
1717         if ((value + 1) > radeon_bo_size(robj)) {
1718                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1719                           "(need %u have %lu) !\n",
1720                           value + 1,
1721                           radeon_bo_size(robj));
1722                 return -EINVAL;
1723         }
1724         return 0;
1725 }
1726
1727 static int r100_packet3_check(struct radeon_cs_parser *p,
1728                               struct radeon_cs_packet *pkt)
1729 {
1730         struct radeon_cs_reloc *reloc;
1731         struct r100_cs_track *track;
1732         unsigned idx;
1733         volatile uint32_t *ib;
1734         int r;
1735
1736         ib = p->ib->ptr;
1737         idx = pkt->idx + 1;
1738         track = (struct r100_cs_track *)p->track;
1739         switch (pkt->opcode) {
1740         case PACKET3_3D_LOAD_VBPNTR:
1741                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1742                 if (r)
1743                         return r;
1744                 break;
1745         case PACKET3_INDX_BUFFER:
1746                 r = r100_cs_packet_next_reloc(p, &reloc);
1747                 if (r) {
1748                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1749                         r100_cs_dump_packet(p, pkt);
1750                         return r;
1751                 }
1752                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1753                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1754                 if (r) {
1755                         return r;
1756                 }
1757                 break;
1758         case 0x23:
1759                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1760                 r = r100_cs_packet_next_reloc(p, &reloc);
1761                 if (r) {
1762                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1763                         r100_cs_dump_packet(p, pkt);
1764                         return r;
1765                 }
1766                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1767                 track->num_arrays = 1;
1768                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1769
1770                 track->arrays[0].robj = reloc->robj;
1771                 track->arrays[0].esize = track->vtx_size;
1772
1773                 track->max_indx = radeon_get_ib_value(p, idx+1);
1774
1775                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1776                 track->immd_dwords = pkt->count - 1;
1777                 r = r100_cs_track_check(p->rdev, track);
1778                 if (r)
1779                         return r;
1780                 break;
1781         case PACKET3_3D_DRAW_IMMD:
1782                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1783                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1784                         return -EINVAL;
1785                 }
1786                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1787                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1788                 track->immd_dwords = pkt->count - 1;
1789                 r = r100_cs_track_check(p->rdev, track);
1790                 if (r)
1791                         return r;
1792                 break;
1793                 /* triggers drawing using in-packet vertex data */
1794         case PACKET3_3D_DRAW_IMMD_2:
1795                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1796                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1797                         return -EINVAL;
1798                 }
1799                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1800                 track->immd_dwords = pkt->count;
1801                 r = r100_cs_track_check(p->rdev, track);
1802                 if (r)
1803                         return r;
1804                 break;
1805                 /* triggers drawing using in-packet vertex data */
1806         case PACKET3_3D_DRAW_VBUF_2:
1807                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1808                 r = r100_cs_track_check(p->rdev, track);
1809                 if (r)
1810                         return r;
1811                 break;
1812                 /* triggers drawing of vertex buffers setup elsewhere */
1813         case PACKET3_3D_DRAW_INDX_2:
1814                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1815                 r = r100_cs_track_check(p->rdev, track);
1816                 if (r)
1817                         return r;
1818                 break;
1819                 /* triggers drawing using indices to vertex buffer */
1820         case PACKET3_3D_DRAW_VBUF:
1821                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1822                 r = r100_cs_track_check(p->rdev, track);
1823                 if (r)
1824                         return r;
1825                 break;
1826                 /* triggers drawing of vertex buffers setup elsewhere */
1827         case PACKET3_3D_DRAW_INDX:
1828                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1829                 r = r100_cs_track_check(p->rdev, track);
1830                 if (r)
1831                         return r;
1832                 break;
1833                 /* triggers drawing using indices to vertex buffer */
1834         case PACKET3_NOP:
1835                 break;
1836         default:
1837                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1838                 return -EINVAL;
1839         }
1840         return 0;
1841 }
1842
1843 int r100_cs_parse(struct radeon_cs_parser *p)
1844 {
1845         struct radeon_cs_packet pkt;
1846         struct r100_cs_track *track;
1847         int r;
1848
1849         track = kzalloc(sizeof(*track), GFP_KERNEL);
1850         r100_cs_track_clear(p->rdev, track);
1851         p->track = track;
1852         do {
1853                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1854                 if (r) {
1855                         return r;
1856                 }
1857                 p->idx += pkt.count + 2;
1858                 switch (pkt.type) {
1859                         case PACKET_TYPE0:
1860                                 if (p->rdev->family >= CHIP_R200)
1861                                         r = r100_cs_parse_packet0(p, &pkt,
1862                                                                   p->rdev->config.r100.reg_safe_bm,
1863                                                                   p->rdev->config.r100.reg_safe_bm_size,
1864                                                                   &r200_packet0_check);
1865                                 else
1866                                         r = r100_cs_parse_packet0(p, &pkt,
1867                                                                   p->rdev->config.r100.reg_safe_bm,
1868                                                                   p->rdev->config.r100.reg_safe_bm_size,
1869                                                                   &r100_packet0_check);
1870                                 break;
1871                         case PACKET_TYPE2:
1872                                 break;
1873                         case PACKET_TYPE3:
1874                                 r = r100_packet3_check(p, &pkt);
1875                                 break;
1876                         default:
1877                                 DRM_ERROR("Unknown packet type %d !\n",
1878                                           pkt.type);
1879                                 return -EINVAL;
1880                 }
1881                 if (r) {
1882                         return r;
1883                 }
1884         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1885         return 0;
1886 }
1887
1888
1889 /*
1890  * Global GPU functions
1891  */
1892 void r100_errata(struct radeon_device *rdev)
1893 {
1894         rdev->pll_errata = 0;
1895
1896         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1897                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1898         }
1899
1900         if (rdev->family == CHIP_RV100 ||
1901             rdev->family == CHIP_RS100 ||
1902             rdev->family == CHIP_RS200) {
1903                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1904         }
1905 }
1906
1907 /* Wait for vertical sync on primary CRTC */
1908 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1909 {
1910         uint32_t crtc_gen_cntl, tmp;
1911         int i;
1912
1913         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1914         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1915             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1916                 return;
1917         }
1918         /* Clear the CRTC_VBLANK_SAVE bit */
1919         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1920         for (i = 0; i < rdev->usec_timeout; i++) {
1921                 tmp = RREG32(RADEON_CRTC_STATUS);
1922                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1923                         return;
1924                 }
1925                 DRM_UDELAY(1);
1926         }
1927 }
1928
1929 /* Wait for vertical sync on secondary CRTC */
1930 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1931 {
1932         uint32_t crtc2_gen_cntl, tmp;
1933         int i;
1934
1935         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1936         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1937             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1938                 return;
1939
1940         /* Clear the CRTC_VBLANK_SAVE bit */
1941         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1942         for (i = 0; i < rdev->usec_timeout; i++) {
1943                 tmp = RREG32(RADEON_CRTC2_STATUS);
1944                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1945                         return;
1946                 }
1947                 DRM_UDELAY(1);
1948         }
1949 }
1950
1951 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1952 {
1953         unsigned i;
1954         uint32_t tmp;
1955
1956         for (i = 0; i < rdev->usec_timeout; i++) {
1957                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1958                 if (tmp >= n) {
1959                         return 0;
1960                 }
1961                 DRM_UDELAY(1);
1962         }
1963         return -1;
1964 }
1965
1966 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1967 {
1968         unsigned i;
1969         uint32_t tmp;
1970
1971         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1972                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1973                        " Bad things might happen.\n");
1974         }
1975         for (i = 0; i < rdev->usec_timeout; i++) {
1976                 tmp = RREG32(RADEON_RBBM_STATUS);
1977                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1978                         return 0;
1979                 }
1980                 DRM_UDELAY(1);
1981         }
1982         return -1;
1983 }
1984
1985 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1986 {
1987         unsigned i;
1988         uint32_t tmp;
1989
1990         for (i = 0; i < rdev->usec_timeout; i++) {
1991                 /* read MC_STATUS */
1992                 tmp = RREG32(RADEON_MC_STATUS);
1993                 if (tmp & RADEON_MC_IDLE) {
1994                         return 0;
1995                 }
1996                 DRM_UDELAY(1);
1997         }
1998         return -1;
1999 }
2000
2001 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2002 {
2003         lockup->last_cp_rptr = cp->rptr;
2004         lockup->last_jiffies = jiffies;
2005 }
2006
2007 /**
2008  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2009  * @rdev:       radeon device structure
2010  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
2011  * @cp:         radeon_cp structure holding CP information
2012  *
2013  * We don't need to initialize the lockup tracking information as we will either
2014  * have CP rptr to a different value of jiffies wrap around which will force
2015  * initialization of the lockup tracking informations.
2016  *
2017  * A possible false positivie is if we get call after while and last_cp_rptr ==
2018  * the current CP rptr, even if it's unlikely it might happen. To avoid this
2019  * if the elapsed time since last call is bigger than 2 second than we return
2020  * false and update the tracking information. Due to this the caller must call
2021  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2022  * the fencing code should be cautious about that.
2023  *
2024  * Caller should write to the ring to force CP to do something so we don't get
2025  * false positive when CP is just gived nothing to do.
2026  *
2027  **/
2028 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2029 {
2030         unsigned long cjiffies, elapsed;
2031
2032         cjiffies = jiffies;
2033         if (!time_after(cjiffies, lockup->last_jiffies)) {
2034                 /* likely a wrap around */
2035                 lockup->last_cp_rptr = cp->rptr;
2036                 lockup->last_jiffies = jiffies;
2037                 return false;
2038         }
2039         if (cp->rptr != lockup->last_cp_rptr) {
2040                 /* CP is still working no lockup */
2041                 lockup->last_cp_rptr = cp->rptr;
2042                 lockup->last_jiffies = jiffies;
2043                 return false;
2044         }
2045         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2046         if (elapsed >= 3000) {
2047                 /* very likely the improbable case where current
2048                  * rptr is equal to last recorded, a while ago, rptr
2049                  * this is more likely a false positive update tracking
2050                  * information which should force us to be recall at
2051                  * latter point
2052                  */
2053                 lockup->last_cp_rptr = cp->rptr;
2054                 lockup->last_jiffies = jiffies;
2055                 return false;
2056         }
2057         if (elapsed >= 1000) {
2058                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2059                 return true;
2060         }
2061         /* give a chance to the GPU ... */
2062         return false;
2063 }
2064
2065 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2066 {
2067         u32 rbbm_status;
2068         int r;
2069
2070         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2071         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2072                 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2073                 return false;
2074         }
2075         /* force CP activities */
2076         r = radeon_ring_lock(rdev, 2);
2077         if (!r) {
2078                 /* PACKET2 NOP */
2079                 radeon_ring_write(rdev, 0x80000000);
2080                 radeon_ring_write(rdev, 0x80000000);
2081                 radeon_ring_unlock_commit(rdev);
2082         }
2083         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2084         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2085 }
2086
2087 void r100_bm_disable(struct radeon_device *rdev)
2088 {
2089         u32 tmp;
2090
2091         /* disable bus mastering */
2092         tmp = RREG32(R_000030_BUS_CNTL);
2093         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2094         mdelay(1);
2095         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2096         mdelay(1);
2097         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2098         tmp = RREG32(RADEON_BUS_CNTL);
2099         mdelay(1);
2100         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2101         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2102         mdelay(1);
2103 }
2104
2105 int r100_asic_reset(struct radeon_device *rdev)
2106 {
2107         struct r100_mc_save save;
2108         u32 status, tmp;
2109
2110         r100_mc_stop(rdev, &save);
2111         status = RREG32(R_000E40_RBBM_STATUS);
2112         if (!G_000E40_GUI_ACTIVE(status)) {
2113                 return 0;
2114         }
2115         status = RREG32(R_000E40_RBBM_STATUS);
2116         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2117         /* stop CP */
2118         WREG32(RADEON_CP_CSQ_CNTL, 0);
2119         tmp = RREG32(RADEON_CP_RB_CNTL);
2120         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2121         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2122         WREG32(RADEON_CP_RB_WPTR, 0);
2123         WREG32(RADEON_CP_RB_CNTL, tmp);
2124         /* save PCI state */
2125         pci_save_state(rdev->pdev);
2126         /* disable bus mastering */
2127         r100_bm_disable(rdev);
2128         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2129                                         S_0000F0_SOFT_RESET_RE(1) |
2130                                         S_0000F0_SOFT_RESET_PP(1) |
2131                                         S_0000F0_SOFT_RESET_RB(1));
2132         RREG32(R_0000F0_RBBM_SOFT_RESET);
2133         mdelay(500);
2134         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2135         mdelay(1);
2136         status = RREG32(R_000E40_RBBM_STATUS);
2137         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2138         /* reset CP */
2139         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2140         RREG32(R_0000F0_RBBM_SOFT_RESET);
2141         mdelay(500);
2142         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2143         mdelay(1);
2144         status = RREG32(R_000E40_RBBM_STATUS);
2145         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2146         /* restore PCI & busmastering */
2147         pci_restore_state(rdev->pdev);
2148         r100_enable_bm(rdev);
2149         /* Check if GPU is idle */
2150         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2151                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2152                 dev_err(rdev->dev, "failed to reset GPU\n");
2153                 rdev->gpu_lockup = true;
2154                 return -1;
2155         }
2156         r100_mc_resume(rdev, &save);
2157         dev_info(rdev->dev, "GPU reset succeed\n");
2158         return 0;
2159 }
2160
2161 void r100_set_common_regs(struct radeon_device *rdev)
2162 {
2163         struct drm_device *dev = rdev->ddev;
2164         bool force_dac2 = false;
2165         u32 tmp;
2166
2167         /* set these so they don't interfere with anything */
2168         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2169         WREG32(RADEON_SUBPIC_CNTL, 0);
2170         WREG32(RADEON_VIPH_CONTROL, 0);
2171         WREG32(RADEON_I2C_CNTL_1, 0);
2172         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2173         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2174         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2175
2176         /* always set up dac2 on rn50 and some rv100 as lots
2177          * of servers seem to wire it up to a VGA port but
2178          * don't report it in the bios connector
2179          * table.
2180          */
2181         switch (dev->pdev->device) {
2182                 /* RN50 */
2183         case 0x515e:
2184         case 0x5969:
2185                 force_dac2 = true;
2186                 break;
2187                 /* RV100*/
2188         case 0x5159:
2189         case 0x515a:
2190                 /* DELL triple head servers */
2191                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2192                     ((dev->pdev->subsystem_device == 0x016c) ||
2193                      (dev->pdev->subsystem_device == 0x016d) ||
2194                      (dev->pdev->subsystem_device == 0x016e) ||
2195                      (dev->pdev->subsystem_device == 0x016f) ||
2196                      (dev->pdev->subsystem_device == 0x0170) ||
2197                      (dev->pdev->subsystem_device == 0x017d) ||
2198                      (dev->pdev->subsystem_device == 0x017e) ||
2199                      (dev->pdev->subsystem_device == 0x0183) ||
2200                      (dev->pdev->subsystem_device == 0x018a) ||
2201                      (dev->pdev->subsystem_device == 0x019a)))
2202                         force_dac2 = true;
2203                 break;
2204         }
2205
2206         if (force_dac2) {
2207                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2208                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2209                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2210
2211                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2212                    enable it, even it's detected.
2213                 */
2214
2215                 /* force it to crtc0 */
2216                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2217                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2218                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2219
2220                 /* set up the TV DAC */
2221                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2222                                  RADEON_TV_DAC_STD_MASK |
2223                                  RADEON_TV_DAC_RDACPD |
2224                                  RADEON_TV_DAC_GDACPD |
2225                                  RADEON_TV_DAC_BDACPD |
2226                                  RADEON_TV_DAC_BGADJ_MASK |
2227                                  RADEON_TV_DAC_DACADJ_MASK);
2228                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2229                                 RADEON_TV_DAC_NHOLD |
2230                                 RADEON_TV_DAC_STD_PS2 |
2231                                 (0x58 << 16));
2232
2233                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2234                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2235                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2236         }
2237
2238         /* switch PM block to ACPI mode */
2239         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2240         tmp &= ~RADEON_PM_MODE_SEL;
2241         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2242
2243 }
2244
2245 /*
2246  * VRAM info
2247  */
2248 static void r100_vram_get_type(struct radeon_device *rdev)
2249 {
2250         uint32_t tmp;
2251
2252         rdev->mc.vram_is_ddr = false;
2253         if (rdev->flags & RADEON_IS_IGP)
2254                 rdev->mc.vram_is_ddr = true;
2255         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2256                 rdev->mc.vram_is_ddr = true;
2257         if ((rdev->family == CHIP_RV100) ||
2258             (rdev->family == CHIP_RS100) ||
2259             (rdev->family == CHIP_RS200)) {
2260                 tmp = RREG32(RADEON_MEM_CNTL);
2261                 if (tmp & RV100_HALF_MODE) {
2262                         rdev->mc.vram_width = 32;
2263                 } else {
2264                         rdev->mc.vram_width = 64;
2265                 }
2266                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2267                         rdev->mc.vram_width /= 4;
2268                         rdev->mc.vram_is_ddr = true;
2269                 }
2270         } else if (rdev->family <= CHIP_RV280) {
2271                 tmp = RREG32(RADEON_MEM_CNTL);
2272                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2273                         rdev->mc.vram_width = 128;
2274                 } else {
2275                         rdev->mc.vram_width = 64;
2276                 }
2277         } else {
2278                 /* newer IGPs */
2279                 rdev->mc.vram_width = 128;
2280         }
2281 }
2282
2283 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2284 {
2285         u32 aper_size;
2286         u8 byte;
2287
2288         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2289
2290         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2291          * that is has the 2nd generation multifunction PCI interface
2292          */
2293         if (rdev->family == CHIP_RV280 ||
2294             rdev->family >= CHIP_RV350) {
2295                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2296                        ~RADEON_HDP_APER_CNTL);
2297                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2298                 return aper_size * 2;
2299         }
2300
2301         /* Older cards have all sorts of funny issues to deal with. First
2302          * check if it's a multifunction card by reading the PCI config
2303          * header type... Limit those to one aperture size
2304          */
2305         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2306         if (byte & 0x80) {
2307                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2308                 DRM_INFO("Limiting VRAM to one aperture\n");
2309                 return aper_size;
2310         }
2311
2312         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2313          * have set it up. We don't write this as it's broken on some ASICs but
2314          * we expect the BIOS to have done the right thing (might be too optimistic...)
2315          */
2316         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2317                 return aper_size * 2;
2318         return aper_size;
2319 }
2320
2321 void r100_vram_init_sizes(struct radeon_device *rdev)
2322 {
2323         u64 config_aper_size;
2324
2325         /* work out accessible VRAM */
2326         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
2327         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2328         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2329         /* FIXME we don't use the second aperture yet when we could use it */
2330         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2331                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2332         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2333         if (rdev->flags & RADEON_IS_IGP) {
2334                 uint32_t tom;
2335                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2336                 tom = RREG32(RADEON_NB_TOM);
2337                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2338                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2339                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2340         } else {
2341                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2342                 /* Some production boards of m6 will report 0
2343                  * if it's 8 MB
2344                  */
2345                 if (rdev->mc.real_vram_size == 0) {
2346                         rdev->mc.real_vram_size = 8192 * 1024;
2347                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2348                 }
2349                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2350                  * Novell bug 204882 + along with lots of ubuntu ones
2351                  */
2352                 if (config_aper_size > rdev->mc.real_vram_size)
2353                         rdev->mc.mc_vram_size = config_aper_size;
2354                 else
2355                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2356         }
2357 }
2358
2359 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2360 {
2361         uint32_t temp;
2362
2363         temp = RREG32(RADEON_CONFIG_CNTL);
2364         if (state == false) {
2365                 temp &= ~(1<<8);
2366                 temp |= (1<<9);
2367         } else {
2368                 temp &= ~(1<<9);
2369         }
2370         WREG32(RADEON_CONFIG_CNTL, temp);
2371 }
2372
2373 void r100_mc_init(struct radeon_device *rdev)
2374 {
2375         u64 base;
2376
2377         r100_vram_get_type(rdev);
2378         r100_vram_init_sizes(rdev);
2379         base = rdev->mc.aper_base;
2380         if (rdev->flags & RADEON_IS_IGP)
2381                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2382         radeon_vram_location(rdev, &rdev->mc, base);
2383         if (!(rdev->flags & RADEON_IS_AGP))
2384                 radeon_gtt_location(rdev, &rdev->mc);
2385         radeon_update_bandwidth_info(rdev);
2386 }
2387
2388
2389 /*
2390  * Indirect registers accessor
2391  */
2392 void r100_pll_errata_after_index(struct radeon_device *rdev)
2393 {
2394         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2395                 return;
2396         }
2397         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2398         (void)RREG32(RADEON_CRTC_GEN_CNTL);
2399 }
2400
2401 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2402 {
2403         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2404          * or the chip could hang on a subsequent access
2405          */
2406         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2407                 udelay(5000);
2408         }
2409
2410         /* This function is required to workaround a hardware bug in some (all?)
2411          * revisions of the R300.  This workaround should be called after every
2412          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2413          * may not be correct.
2414          */
2415         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2416                 uint32_t save, tmp;
2417
2418                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2419                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2420                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2421                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2422                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2423         }
2424 }
2425
2426 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2427 {
2428         uint32_t data;
2429
2430         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2431         r100_pll_errata_after_index(rdev);
2432         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2433         r100_pll_errata_after_data(rdev);
2434         return data;
2435 }
2436
2437 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2438 {
2439         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2440         r100_pll_errata_after_index(rdev);
2441         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2442         r100_pll_errata_after_data(rdev);
2443 }
2444
2445 void r100_set_safe_registers(struct radeon_device *rdev)
2446 {
2447         if (ASIC_IS_RN50(rdev)) {
2448                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2449                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2450         } else if (rdev->family < CHIP_R200) {
2451                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2452                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2453         } else {
2454                 r200_set_safe_registers(rdev);
2455         }
2456 }
2457
2458 /*
2459  * Debugfs info
2460  */
2461 #if defined(CONFIG_DEBUG_FS)
2462 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2463 {
2464         struct drm_info_node *node = (struct drm_info_node *) m->private;
2465         struct drm_device *dev = node->minor->dev;
2466         struct radeon_device *rdev = dev->dev_private;
2467         uint32_t reg, value;
2468         unsigned i;
2469
2470         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2471         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2472         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2473         for (i = 0; i < 64; i++) {
2474                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2475                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2476                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2477                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2478                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2479         }
2480         return 0;
2481 }
2482
2483 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2484 {
2485         struct drm_info_node *node = (struct drm_info_node *) m->private;
2486         struct drm_device *dev = node->minor->dev;
2487         struct radeon_device *rdev = dev->dev_private;
2488         uint32_t rdp, wdp;
2489         unsigned count, i, j;
2490
2491         radeon_ring_free_size(rdev);
2492         rdp = RREG32(RADEON_CP_RB_RPTR);
2493         wdp = RREG32(RADEON_CP_RB_WPTR);
2494         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2495         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2496         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2497         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2498         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2499         seq_printf(m, "%u dwords in ring\n", count);
2500         for (j = 0; j <= count; j++) {
2501                 i = (rdp + j) & rdev->cp.ptr_mask;
2502                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2503         }
2504         return 0;
2505 }
2506
2507
2508 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2509 {
2510         struct drm_info_node *node = (struct drm_info_node *) m->private;
2511         struct drm_device *dev = node->minor->dev;
2512         struct radeon_device *rdev = dev->dev_private;
2513         uint32_t csq_stat, csq2_stat, tmp;
2514         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2515         unsigned i;
2516
2517         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2518         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2519         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2520         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2521         r_rptr = (csq_stat >> 0) & 0x3ff;
2522         r_wptr = (csq_stat >> 10) & 0x3ff;
2523         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2524         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2525         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2526         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2527         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2528         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2529         seq_printf(m, "Ring rptr %u\n", r_rptr);
2530         seq_printf(m, "Ring wptr %u\n", r_wptr);
2531         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2532         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2533         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2534         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2535         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2536          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2537         seq_printf(m, "Ring fifo:\n");
2538         for (i = 0; i < 256; i++) {
2539                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2540                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2541                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2542         }
2543         seq_printf(m, "Indirect1 fifo:\n");
2544         for (i = 256; i <= 512; i++) {
2545                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2546                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2547                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2548         }
2549         seq_printf(m, "Indirect2 fifo:\n");
2550         for (i = 640; i < ib1_wptr; i++) {
2551                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2552                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2553                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2554         }
2555         return 0;
2556 }
2557
2558 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2559 {
2560         struct drm_info_node *node = (struct drm_info_node *) m->private;
2561         struct drm_device *dev = node->minor->dev;
2562         struct radeon_device *rdev = dev->dev_private;
2563         uint32_t tmp;
2564
2565         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2566         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2567         tmp = RREG32(RADEON_MC_FB_LOCATION);
2568         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2569         tmp = RREG32(RADEON_BUS_CNTL);
2570         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2571         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2572         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2573         tmp = RREG32(RADEON_AGP_BASE);
2574         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2575         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2576         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2577         tmp = RREG32(0x01D0);
2578         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2579         tmp = RREG32(RADEON_AIC_LO_ADDR);
2580         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2581         tmp = RREG32(RADEON_AIC_HI_ADDR);
2582         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2583         tmp = RREG32(0x01E4);
2584         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2585         return 0;
2586 }
2587
2588 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2589         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2590 };
2591
2592 static struct drm_info_list r100_debugfs_cp_list[] = {
2593         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2594         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2595 };
2596
2597 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2598         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2599 };
2600 #endif
2601
2602 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2603 {
2604 #if defined(CONFIG_DEBUG_FS)
2605         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2606 #else
2607         return 0;
2608 #endif
2609 }
2610
2611 int r100_debugfs_cp_init(struct radeon_device *rdev)
2612 {
2613 #if defined(CONFIG_DEBUG_FS)
2614         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2615 #else
2616         return 0;
2617 #endif
2618 }
2619
2620 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2621 {
2622 #if defined(CONFIG_DEBUG_FS)
2623         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2624 #else
2625         return 0;
2626 #endif
2627 }
2628
2629 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2630                          uint32_t tiling_flags, uint32_t pitch,
2631                          uint32_t offset, uint32_t obj_size)
2632 {
2633         int surf_index = reg * 16;
2634         int flags = 0;
2635
2636         /* r100/r200 divide by 16 */
2637         if (rdev->family < CHIP_R300)
2638                 flags = pitch / 16;
2639         else
2640                 flags = pitch / 8;
2641
2642         if (rdev->family <= CHIP_RS200) {
2643                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2644                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2645                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2646                 if (tiling_flags & RADEON_TILING_MACRO)
2647                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2648         } else if (rdev->family <= CHIP_RV280) {
2649                 if (tiling_flags & (RADEON_TILING_MACRO))
2650                         flags |= R200_SURF_TILE_COLOR_MACRO;
2651                 if (tiling_flags & RADEON_TILING_MICRO)
2652                         flags |= R200_SURF_TILE_COLOR_MICRO;
2653         } else {
2654                 if (tiling_flags & RADEON_TILING_MACRO)
2655                         flags |= R300_SURF_TILE_MACRO;
2656                 if (tiling_flags & RADEON_TILING_MICRO)
2657                         flags |= R300_SURF_TILE_MICRO;
2658         }
2659
2660         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2661                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2662         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2663                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2664
2665         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2666         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2667         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2668         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2669         return 0;
2670 }
2671
2672 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2673 {
2674         int surf_index = reg * 16;
2675         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2676 }
2677
2678 void r100_bandwidth_update(struct radeon_device *rdev)
2679 {
2680         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2681         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2682         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2683         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2684         fixed20_12 memtcas_ff[8] = {
2685                 dfixed_init(1),
2686                 dfixed_init(2),
2687                 dfixed_init(3),
2688                 dfixed_init(0),
2689                 dfixed_init_half(1),
2690                 dfixed_init_half(2),
2691                 dfixed_init(0),
2692         };
2693         fixed20_12 memtcas_rs480_ff[8] = {
2694                 dfixed_init(0),
2695                 dfixed_init(1),
2696                 dfixed_init(2),
2697                 dfixed_init(3),
2698                 dfixed_init(0),
2699                 dfixed_init_half(1),
2700                 dfixed_init_half(2),
2701                 dfixed_init_half(3),
2702         };
2703         fixed20_12 memtcas2_ff[8] = {
2704                 dfixed_init(0),
2705                 dfixed_init(1),
2706                 dfixed_init(2),
2707                 dfixed_init(3),
2708                 dfixed_init(4),
2709                 dfixed_init(5),
2710                 dfixed_init(6),
2711                 dfixed_init(7),
2712         };
2713         fixed20_12 memtrbs[8] = {
2714                 dfixed_init(1),
2715                 dfixed_init_half(1),
2716                 dfixed_init(2),
2717                 dfixed_init_half(2),
2718                 dfixed_init(3),
2719                 dfixed_init_half(3),
2720                 dfixed_init(4),
2721                 dfixed_init_half(4)
2722         };
2723         fixed20_12 memtrbs_r4xx[8] = {
2724                 dfixed_init(4),
2725                 dfixed_init(5),
2726                 dfixed_init(6),
2727                 dfixed_init(7),
2728                 dfixed_init(8),
2729                 dfixed_init(9),
2730                 dfixed_init(10),
2731                 dfixed_init(11)
2732         };
2733         fixed20_12 min_mem_eff;
2734         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2735         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2736         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2737                 disp_drain_rate2, read_return_rate;
2738         fixed20_12 time_disp1_drop_priority;
2739         int c;
2740         int cur_size = 16;       /* in octawords */
2741         int critical_point = 0, critical_point2;
2742 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2743         int stop_req, max_stop_req;
2744         struct drm_display_mode *mode1 = NULL;
2745         struct drm_display_mode *mode2 = NULL;
2746         uint32_t pixel_bytes1 = 0;
2747         uint32_t pixel_bytes2 = 0;
2748
2749         radeon_update_display_priority(rdev);
2750
2751         if (rdev->mode_info.crtcs[0]->base.enabled) {
2752                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2753                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2754         }
2755         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2756                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2757                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2758                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2759                 }
2760         }
2761
2762         min_mem_eff.full = dfixed_const_8(0);
2763         /* get modes */
2764         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2765                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2766                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2767                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2768                 /* check crtc enables */
2769                 if (mode2)
2770                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2771                 if (mode1)
2772                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2773                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2774         }
2775
2776         /*
2777          * determine is there is enough bw for current mode
2778          */
2779         sclk_ff = rdev->pm.sclk;
2780         mclk_ff = rdev->pm.mclk;
2781
2782         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2783         temp_ff.full = dfixed_const(temp);
2784         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2785
2786         pix_clk.full = 0;
2787         pix_clk2.full = 0;
2788         peak_disp_bw.full = 0;
2789         if (mode1) {
2790                 temp_ff.full = dfixed_const(1000);
2791                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2792                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2793                 temp_ff.full = dfixed_const(pixel_bytes1);
2794                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2795         }
2796         if (mode2) {
2797                 temp_ff.full = dfixed_const(1000);
2798                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2799                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2800                 temp_ff.full = dfixed_const(pixel_bytes2);
2801                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2802         }
2803
2804         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2805         if (peak_disp_bw.full >= mem_bw.full) {
2806                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2807                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2808         }
2809
2810         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2811         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2812         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2813                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2814                 mem_trp  = ((temp & 0x3)) + 1;
2815                 mem_tras = ((temp & 0x70) >> 4) + 1;
2816         } else if (rdev->family == CHIP_R300 ||
2817                    rdev->family == CHIP_R350) { /* r300, r350 */
2818                 mem_trcd = (temp & 0x7) + 1;
2819                 mem_trp = ((temp >> 8) & 0x7) + 1;
2820                 mem_tras = ((temp >> 11) & 0xf) + 4;
2821         } else if (rdev->family == CHIP_RV350 ||
2822                    rdev->family <= CHIP_RV380) {
2823                 /* rv3x0 */
2824                 mem_trcd = (temp & 0x7) + 3;
2825                 mem_trp = ((temp >> 8) & 0x7) + 3;
2826                 mem_tras = ((temp >> 11) & 0xf) + 6;
2827         } else if (rdev->family == CHIP_R420 ||
2828                    rdev->family == CHIP_R423 ||
2829                    rdev->family == CHIP_RV410) {
2830                 /* r4xx */
2831                 mem_trcd = (temp & 0xf) + 3;
2832                 if (mem_trcd > 15)
2833                         mem_trcd = 15;
2834                 mem_trp = ((temp >> 8) & 0xf) + 3;
2835                 if (mem_trp > 15)
2836                         mem_trp = 15;
2837                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2838                 if (mem_tras > 31)
2839                         mem_tras = 31;
2840         } else { /* RV200, R200 */
2841                 mem_trcd = (temp & 0x7) + 1;
2842                 mem_trp = ((temp >> 8) & 0x7) + 1;
2843                 mem_tras = ((temp >> 12) & 0xf) + 4;
2844         }
2845         /* convert to FF */
2846         trcd_ff.full = dfixed_const(mem_trcd);
2847         trp_ff.full = dfixed_const(mem_trp);
2848         tras_ff.full = dfixed_const(mem_tras);
2849
2850         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2851         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2852         data = (temp & (7 << 20)) >> 20;
2853         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2854                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2855                         tcas_ff = memtcas_rs480_ff[data];
2856                 else
2857                         tcas_ff = memtcas_ff[data];
2858         } else
2859                 tcas_ff = memtcas2_ff[data];
2860
2861         if (rdev->family == CHIP_RS400 ||
2862             rdev->family == CHIP_RS480) {
2863                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2864                 data = (temp >> 23) & 0x7;
2865                 if (data < 5)
2866                         tcas_ff.full += dfixed_const(data);
2867         }
2868
2869         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2870                 /* on the R300, Tcas is included in Trbs.
2871                  */
2872                 temp = RREG32(RADEON_MEM_CNTL);
2873                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2874                 if (data == 1) {
2875                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2876                                 temp = RREG32(R300_MC_IND_INDEX);
2877                                 temp &= ~R300_MC_IND_ADDR_MASK;
2878                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2879                                 WREG32(R300_MC_IND_INDEX, temp);
2880                                 temp = RREG32(R300_MC_IND_DATA);
2881                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2882                         } else {
2883                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2884                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2885                         }
2886                 } else {
2887                         temp = RREG32(R300_MC_READ_CNTL_AB);
2888                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2889                 }
2890                 if (rdev->family == CHIP_RV410 ||
2891                     rdev->family == CHIP_R420 ||
2892                     rdev->family == CHIP_R423)
2893                         trbs_ff = memtrbs_r4xx[data];
2894                 else
2895                         trbs_ff = memtrbs[data];
2896                 tcas_ff.full += trbs_ff.full;
2897         }
2898
2899         sclk_eff_ff.full = sclk_ff.full;
2900
2901         if (rdev->flags & RADEON_IS_AGP) {
2902                 fixed20_12 agpmode_ff;
2903                 agpmode_ff.full = dfixed_const(radeon_agpmode);
2904                 temp_ff.full = dfixed_const_666(16);
2905                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2906         }
2907         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2908
2909         if (ASIC_IS_R300(rdev)) {
2910                 sclk_delay_ff.full = dfixed_const(250);
2911         } else {
2912                 if ((rdev->family == CHIP_RV100) ||
2913                     rdev->flags & RADEON_IS_IGP) {
2914                         if (rdev->mc.vram_is_ddr)
2915                                 sclk_delay_ff.full = dfixed_const(41);
2916                         else
2917                                 sclk_delay_ff.full = dfixed_const(33);
2918                 } else {
2919                         if (rdev->mc.vram_width == 128)
2920                                 sclk_delay_ff.full = dfixed_const(57);
2921                         else
2922                                 sclk_delay_ff.full = dfixed_const(41);
2923                 }
2924         }
2925
2926         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
2927
2928         if (rdev->mc.vram_is_ddr) {
2929                 if (rdev->mc.vram_width == 32) {
2930                         k1.full = dfixed_const(40);
2931                         c  = 3;
2932                 } else {
2933                         k1.full = dfixed_const(20);
2934                         c  = 1;
2935                 }
2936         } else {
2937                 k1.full = dfixed_const(40);
2938                 c  = 3;
2939         }
2940
2941         temp_ff.full = dfixed_const(2);
2942         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2943         temp_ff.full = dfixed_const(c);
2944         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2945         temp_ff.full = dfixed_const(4);
2946         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2947         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
2948         mc_latency_mclk.full += k1.full;
2949
2950         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2951         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
2952
2953         /*
2954           HW cursor time assuming worst case of full size colour cursor.
2955         */
2956         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2957         temp_ff.full += trcd_ff.full;
2958         if (temp_ff.full < tras_ff.full)
2959                 temp_ff.full = tras_ff.full;
2960         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
2961
2962         temp_ff.full = dfixed_const(cur_size);
2963         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
2964         /*
2965           Find the total latency for the display data.
2966         */
2967         disp_latency_overhead.full = dfixed_const(8);
2968         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
2969         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2970         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2971
2972         if (mc_latency_mclk.full > mc_latency_sclk.full)
2973                 disp_latency.full = mc_latency_mclk.full;
2974         else
2975                 disp_latency.full = mc_latency_sclk.full;
2976
2977         /* setup Max GRPH_STOP_REQ default value */
2978         if (ASIC_IS_RV100(rdev))
2979                 max_stop_req = 0x5c;
2980         else
2981                 max_stop_req = 0x7c;
2982
2983         if (mode1) {
2984                 /*  CRTC1
2985                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2986                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2987                 */
2988                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2989
2990                 if (stop_req > max_stop_req)
2991                         stop_req = max_stop_req;
2992
2993                 /*
2994                   Find the drain rate of the display buffer.
2995                 */
2996                 temp_ff.full = dfixed_const((16/pixel_bytes1));
2997                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
2998
2999                 /*
3000                   Find the critical point of the display buffer.
3001                 */
3002                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3003                 crit_point_ff.full += dfixed_const_half(0);
3004
3005                 critical_point = dfixed_trunc(crit_point_ff);
3006
3007                 if (rdev->disp_priority == 2) {
3008                         critical_point = 0;
3009                 }
3010
3011                 /*
3012                   The critical point should never be above max_stop_req-4.  Setting
3013                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3014                 */
3015                 if (max_stop_req - critical_point < 4)
3016                         critical_point = 0;
3017
3018                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3019                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3020                         critical_point = 0x10;
3021                 }
3022
3023                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3024                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3025                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3026                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3027                 if ((rdev->family == CHIP_R350) &&
3028                     (stop_req > 0x15)) {
3029                         stop_req -= 0x10;
3030                 }
3031                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3032                 temp |= RADEON_GRPH_BUFFER_SIZE;
3033                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3034                           RADEON_GRPH_CRITICAL_AT_SOF |
3035                           RADEON_GRPH_STOP_CNTL);
3036                 /*
3037                   Write the result into the register.
3038                 */
3039                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3040                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3041
3042 #if 0
3043                 if ((rdev->family == CHIP_RS400) ||
3044                     (rdev->family == CHIP_RS480)) {
3045                         /* attempt to program RS400 disp regs correctly ??? */
3046                         temp = RREG32(RS400_DISP1_REG_CNTL);
3047                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3048                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3049                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3050                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3051                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3052                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3053                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3054                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3055                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3056                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3057                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3058                 }
3059 #endif
3060
3061                 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
3062                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3063                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3064         }
3065
3066         if (mode2) {
3067                 u32 grph2_cntl;
3068                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3069
3070                 if (stop_req > max_stop_req)
3071                         stop_req = max_stop_req;
3072
3073                 /*
3074                   Find the drain rate of the display buffer.
3075                 */
3076                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3077                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3078
3079                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3080                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3081                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3082                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3083                 if ((rdev->family == CHIP_R350) &&
3084                     (stop_req > 0x15)) {
3085                         stop_req -= 0x10;
3086                 }
3087                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3088                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3089                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3090                           RADEON_GRPH_CRITICAL_AT_SOF |
3091                           RADEON_GRPH_STOP_CNTL);
3092
3093                 if ((rdev->family == CHIP_RS100) ||
3094                     (rdev->family == CHIP_RS200))
3095                         critical_point2 = 0;
3096                 else {
3097                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3098                         temp_ff.full = dfixed_const(temp);
3099                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3100                         if (sclk_ff.full < temp_ff.full)
3101                                 temp_ff.full = sclk_ff.full;
3102
3103                         read_return_rate.full = temp_ff.full;
3104
3105                         if (mode1) {
3106                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3107                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3108                         } else {
3109                                 time_disp1_drop_priority.full = 0;
3110                         }
3111                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3112                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3113                         crit_point_ff.full += dfixed_const_half(0);
3114
3115                         critical_point2 = dfixed_trunc(crit_point_ff);
3116
3117                         if (rdev->disp_priority == 2) {
3118                                 critical_point2 = 0;
3119                         }
3120
3121                         if (max_stop_req - critical_point2 < 4)
3122                                 critical_point2 = 0;
3123
3124                 }
3125
3126                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3127                         /* some R300 cards have problem with this set to 0 */
3128                         critical_point2 = 0x10;
3129                 }
3130
3131                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3132                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3133
3134                 if ((rdev->family == CHIP_RS400) ||
3135                     (rdev->family == CHIP_RS480)) {
3136 #if 0
3137                         /* attempt to program RS400 disp2 regs correctly ??? */
3138                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3139                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3140                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3141                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3142                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3143                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3144                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3145                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3146                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3147                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3148                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3149                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3150 #endif
3151                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3152                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3153                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3154                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3155                 }
3156
3157                 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
3158                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3159         }
3160 }
3161
3162 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3163 {
3164         DRM_ERROR("pitch                      %d\n", t->pitch);
3165         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3166         DRM_ERROR("width                      %d\n", t->width);
3167         DRM_ERROR("width_11                   %d\n", t->width_11);
3168         DRM_ERROR("height                     %d\n", t->height);
3169         DRM_ERROR("height_11                  %d\n", t->height_11);
3170         DRM_ERROR("num levels                 %d\n", t->num_levels);
3171         DRM_ERROR("depth                      %d\n", t->txdepth);
3172         DRM_ERROR("bpp                        %d\n", t->cpp);
3173         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3174         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3175         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3176         DRM_ERROR("compress format            %d\n", t->compress_format);
3177 }
3178
3179 static int r100_cs_track_cube(struct radeon_device *rdev,
3180                               struct r100_cs_track *track, unsigned idx)
3181 {
3182         unsigned face, w, h;
3183         struct radeon_bo *cube_robj;
3184         unsigned long size;
3185
3186         for (face = 0; face < 5; face++) {
3187                 cube_robj = track->textures[idx].cube_info[face].robj;
3188                 w = track->textures[idx].cube_info[face].width;
3189                 h = track->textures[idx].cube_info[face].height;
3190
3191                 size = w * h;
3192                 size *= track->textures[idx].cpp;
3193
3194                 size += track->textures[idx].cube_info[face].offset;
3195
3196                 if (size > radeon_bo_size(cube_robj)) {
3197                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3198                                   size, radeon_bo_size(cube_robj));
3199                         r100_cs_track_texture_print(&track->textures[idx]);
3200                         return -1;
3201                 }
3202         }
3203         return 0;
3204 }
3205
3206 static int r100_track_compress_size(int compress_format, int w, int h)
3207 {
3208         int block_width, block_height, block_bytes;
3209         int wblocks, hblocks;
3210         int min_wblocks;
3211         int sz;
3212
3213         block_width = 4;
3214         block_height = 4;
3215
3216         switch (compress_format) {
3217         case R100_TRACK_COMP_DXT1:
3218                 block_bytes = 8;
3219                 min_wblocks = 4;
3220                 break;
3221         default:
3222         case R100_TRACK_COMP_DXT35:
3223                 block_bytes = 16;
3224                 min_wblocks = 2;
3225                 break;
3226         }
3227
3228         hblocks = (h + block_height - 1) / block_height;
3229         wblocks = (w + block_width - 1) / block_width;
3230         if (wblocks < min_wblocks)
3231                 wblocks = min_wblocks;
3232         sz = wblocks * hblocks * block_bytes;
3233         return sz;
3234 }
3235
3236 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3237                                        struct r100_cs_track *track)
3238 {
3239         struct radeon_bo *robj;
3240         unsigned long size;
3241         unsigned u, i, w, h, d;
3242         int ret;
3243
3244         for (u = 0; u < track->num_texture; u++) {
3245                 if (!track->textures[u].enabled)
3246                         continue;
3247                 robj = track->textures[u].robj;
3248                 if (robj == NULL) {
3249                         DRM_ERROR("No texture bound to unit %u\n", u);
3250                         return -EINVAL;
3251                 }
3252                 size = 0;
3253                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3254                         if (track->textures[u].use_pitch) {
3255                                 if (rdev->family < CHIP_R300)
3256                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3257                                 else
3258                                         w = track->textures[u].pitch / (1 << i);
3259                         } else {
3260                                 w = track->textures[u].width;
3261                                 if (rdev->family >= CHIP_RV515)
3262                                         w |= track->textures[u].width_11;
3263                                 w = w / (1 << i);
3264                                 if (track->textures[u].roundup_w)
3265                                         w = roundup_pow_of_two(w);
3266                         }
3267                         h = track->textures[u].height;
3268                         if (rdev->family >= CHIP_RV515)
3269                                 h |= track->textures[u].height_11;
3270                         h = h / (1 << i);
3271                         if (track->textures[u].roundup_h)
3272                                 h = roundup_pow_of_two(h);
3273                         if (track->textures[u].tex_coord_type == 1) {
3274                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3275                                 if (!d)
3276                                         d = 1;
3277                         } else {
3278                                 d = 1;
3279                         }
3280                         if (track->textures[u].compress_format) {
3281
3282                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3283                                 /* compressed textures are block based */
3284                         } else
3285                                 size += w * h * d;
3286                 }
3287                 size *= track->textures[u].cpp;
3288
3289                 switch (track->textures[u].tex_coord_type) {
3290                 case 0:
3291                 case 1:
3292                         break;
3293                 case 2:
3294                         if (track->separate_cube) {
3295                                 ret = r100_cs_track_cube(rdev, track, u);
3296                                 if (ret)
3297                                         return ret;
3298                         } else
3299                                 size *= 6;
3300                         break;
3301                 default:
3302                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3303                                   "%u\n", track->textures[u].tex_coord_type, u);
3304                         return -EINVAL;
3305                 }
3306                 if (size > radeon_bo_size(robj)) {
3307                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3308                                   "%lu\n", u, size, radeon_bo_size(robj));
3309                         r100_cs_track_texture_print(&track->textures[u]);
3310                         return -EINVAL;
3311                 }
3312         }
3313         return 0;
3314 }
3315
3316 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3317 {
3318         unsigned i;
3319         unsigned long size;
3320         unsigned prim_walk;
3321         unsigned nverts;
3322
3323         for (i = 0; i < track->num_cb; i++) {
3324                 if (track->cb[i].robj == NULL) {
3325                         if (!(track->fastfill || track->color_channel_mask ||
3326                               track->blend_read_enable)) {
3327                                 continue;
3328                         }
3329                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3330                         return -EINVAL;
3331                 }
3332                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3333                 size += track->cb[i].offset;
3334                 if (size > radeon_bo_size(track->cb[i].robj)) {
3335                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3336                                   "(need %lu have %lu) !\n", i, size,
3337                                   radeon_bo_size(track->cb[i].robj));
3338                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3339                                   i, track->cb[i].pitch, track->cb[i].cpp,
3340                                   track->cb[i].offset, track->maxy);
3341                         return -EINVAL;
3342                 }
3343         }
3344         if (track->z_enabled) {
3345                 if (track->zb.robj == NULL) {
3346                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3347                         return -EINVAL;
3348                 }
3349                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3350                 size += track->zb.offset;
3351                 if (size > radeon_bo_size(track->zb.robj)) {
3352                         DRM_ERROR("[drm] Buffer too small for z buffer "
3353                                   "(need %lu have %lu) !\n", size,
3354                                   radeon_bo_size(track->zb.robj));
3355                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3356                                   track->zb.pitch, track->zb.cpp,
3357                                   track->zb.offset, track->maxy);
3358                         return -EINVAL;
3359                 }
3360         }
3361         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3362         if (track->vap_vf_cntl & (1 << 14)) {
3363                 nverts = track->vap_alt_nverts;
3364         } else {
3365                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3366         }
3367         switch (prim_walk) {
3368         case 1:
3369                 for (i = 0; i < track->num_arrays; i++) {
3370                         size = track->arrays[i].esize * track->max_indx * 4;
3371                         if (track->arrays[i].robj == NULL) {
3372                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3373                                           "bound\n", prim_walk, i);
3374                                 return -EINVAL;
3375                         }
3376                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3377                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3378                                         "need %lu dwords have %lu dwords\n",
3379                                         prim_walk, i, size >> 2,
3380                                         radeon_bo_size(track->arrays[i].robj)
3381                                         >> 2);
3382                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3383                                 return -EINVAL;
3384                         }
3385                 }
3386                 break;
3387         case 2:
3388                 for (i = 0; i < track->num_arrays; i++) {
3389                         size = track->arrays[i].esize * (nverts - 1) * 4;
3390                         if (track->arrays[i].robj == NULL) {
3391                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3392                                           "bound\n", prim_walk, i);
3393                                 return -EINVAL;
3394                         }
3395                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3396                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3397                                         "need %lu dwords have %lu dwords\n",
3398                                         prim_walk, i, size >> 2,
3399                                         radeon_bo_size(track->arrays[i].robj)
3400                                         >> 2);
3401                                 return -EINVAL;
3402                         }
3403                 }
3404                 break;
3405         case 3:
3406                 size = track->vtx_size * nverts;
3407                 if (size != track->immd_dwords) {
3408                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3409                                   track->immd_dwords, size);
3410                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3411                                   nverts, track->vtx_size);
3412                         return -EINVAL;
3413                 }
3414                 break;
3415         default:
3416                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3417                           prim_walk);
3418                 return -EINVAL;
3419         }
3420         return r100_cs_track_texture_check(rdev, track);
3421 }
3422
3423 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3424 {
3425         unsigned i, face;
3426
3427         if (rdev->family < CHIP_R300) {
3428                 track->num_cb = 1;
3429                 if (rdev->family <= CHIP_RS200)
3430                         track->num_texture = 3;
3431                 else
3432                         track->num_texture = 6;
3433                 track->maxy = 2048;
3434                 track->separate_cube = 1;
3435         } else {
3436                 track->num_cb = 4;
3437                 track->num_texture = 16;
3438                 track->maxy = 4096;
3439                 track->separate_cube = 0;
3440         }
3441
3442         for (i = 0; i < track->num_cb; i++) {
3443                 track->cb[i].robj = NULL;
3444                 track->cb[i].pitch = 8192;
3445                 track->cb[i].cpp = 16;
3446                 track->cb[i].offset = 0;
3447         }
3448         track->z_enabled = true;
3449         track->zb.robj = NULL;
3450         track->zb.pitch = 8192;
3451         track->zb.cpp = 4;
3452         track->zb.offset = 0;
3453         track->vtx_size = 0x7F;
3454         track->immd_dwords = 0xFFFFFFFFUL;
3455         track->num_arrays = 11;
3456         track->max_indx = 0x00FFFFFFUL;
3457         for (i = 0; i < track->num_arrays; i++) {
3458                 track->arrays[i].robj = NULL;
3459                 track->arrays[i].esize = 0x7F;
3460         }
3461         for (i = 0; i < track->num_texture; i++) {
3462                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3463                 track->textures[i].pitch = 16536;
3464                 track->textures[i].width = 16536;
3465                 track->textures[i].height = 16536;
3466                 track->textures[i].width_11 = 1 << 11;
3467                 track->textures[i].height_11 = 1 << 11;
3468                 track->textures[i].num_levels = 12;
3469                 if (rdev->family <= CHIP_RS200) {
3470                         track->textures[i].tex_coord_type = 0;
3471                         track->textures[i].txdepth = 0;
3472                 } else {
3473                         track->textures[i].txdepth = 16;
3474                         track->textures[i].tex_coord_type = 1;
3475                 }
3476                 track->textures[i].cpp = 64;
3477                 track->textures[i].robj = NULL;
3478                 /* CS IB emission code makes sure texture unit are disabled */
3479                 track->textures[i].enabled = false;
3480                 track->textures[i].roundup_w = true;
3481                 track->textures[i].roundup_h = true;
3482                 if (track->separate_cube)
3483                         for (face = 0; face < 5; face++) {
3484                                 track->textures[i].cube_info[face].robj = NULL;
3485                                 track->textures[i].cube_info[face].width = 16536;
3486                                 track->textures[i].cube_info[face].height = 16536;
3487                                 track->textures[i].cube_info[face].offset = 0;
3488                         }
3489         }
3490 }
3491
3492 int r100_ring_test(struct radeon_device *rdev)
3493 {
3494         uint32_t scratch;
3495         uint32_t tmp = 0;
3496         unsigned i;
3497         int r;
3498
3499         r = radeon_scratch_get(rdev, &scratch);
3500         if (r) {
3501                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3502                 return r;
3503         }
3504         WREG32(scratch, 0xCAFEDEAD);
3505         r = radeon_ring_lock(rdev, 2);
3506         if (r) {
3507                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3508                 radeon_scratch_free(rdev, scratch);
3509                 return r;
3510         }
3511         radeon_ring_write(rdev, PACKET0(scratch, 0));
3512         radeon_ring_write(rdev, 0xDEADBEEF);
3513         radeon_ring_unlock_commit(rdev);
3514         for (i = 0; i < rdev->usec_timeout; i++) {
3515                 tmp = RREG32(scratch);
3516                 if (tmp == 0xDEADBEEF) {
3517                         break;
3518                 }
3519                 DRM_UDELAY(1);
3520         }
3521         if (i < rdev->usec_timeout) {
3522                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3523         } else {
3524                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3525                           scratch, tmp);
3526                 r = -EINVAL;
3527         }
3528         radeon_scratch_free(rdev, scratch);
3529         return r;
3530 }
3531
3532 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3533 {
3534         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3535         radeon_ring_write(rdev, ib->gpu_addr);
3536         radeon_ring_write(rdev, ib->length_dw);
3537 }
3538
3539 int r100_ib_test(struct radeon_device *rdev)
3540 {
3541         struct radeon_ib *ib;
3542         uint32_t scratch;
3543         uint32_t tmp = 0;
3544         unsigned i;
3545         int r;
3546
3547         r = radeon_scratch_get(rdev, &scratch);
3548         if (r) {
3549                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3550                 return r;
3551         }
3552         WREG32(scratch, 0xCAFEDEAD);
3553         r = radeon_ib_get(rdev, &ib);
3554         if (r) {
3555                 return r;
3556         }
3557         ib->ptr[0] = PACKET0(scratch, 0);
3558         ib->ptr[1] = 0xDEADBEEF;
3559         ib->ptr[2] = PACKET2(0);
3560         ib->ptr[3] = PACKET2(0);
3561         ib->ptr[4] = PACKET2(0);
3562         ib->ptr[5] = PACKET2(0);
3563         ib->ptr[6] = PACKET2(0);
3564         ib->ptr[7] = PACKET2(0);
3565         ib->length_dw = 8;
3566         r = radeon_ib_schedule(rdev, ib);
3567         if (r) {
3568                 radeon_scratch_free(rdev, scratch);
3569                 radeon_ib_free(rdev, &ib);
3570                 return r;
3571         }
3572         r = radeon_fence_wait(ib->fence, false);
3573         if (r) {
3574                 return r;
3575         }
3576         for (i = 0; i < rdev->usec_timeout; i++) {
3577                 tmp = RREG32(scratch);
3578                 if (tmp == 0xDEADBEEF) {
3579                         break;
3580                 }
3581                 DRM_UDELAY(1);
3582         }
3583         if (i < rdev->usec_timeout) {
3584                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3585         } else {
3586                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3587                           scratch, tmp);
3588                 r = -EINVAL;
3589         }
3590         radeon_scratch_free(rdev, scratch);
3591         radeon_ib_free(rdev, &ib);
3592         return r;
3593 }
3594
3595 void r100_ib_fini(struct radeon_device *rdev)
3596 {
3597         radeon_ib_pool_fini(rdev);
3598 }
3599
3600 int r100_ib_init(struct radeon_device *rdev)
3601 {
3602         int r;
3603
3604         r = radeon_ib_pool_init(rdev);
3605         if (r) {
3606                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3607                 r100_ib_fini(rdev);
3608                 return r;
3609         }
3610         r = r100_ib_test(rdev);
3611         if (r) {
3612                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3613                 r100_ib_fini(rdev);
3614                 return r;
3615         }
3616         return 0;
3617 }
3618
3619 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3620 {
3621         /* Shutdown CP we shouldn't need to do that but better be safe than
3622          * sorry
3623          */
3624         rdev->cp.ready = false;
3625         WREG32(R_000740_CP_CSQ_CNTL, 0);
3626
3627         /* Save few CRTC registers */
3628         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3629         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3630         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3631         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3632         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3633                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3634                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3635         }
3636
3637         /* Disable VGA aperture access */
3638         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3639         /* Disable cursor, overlay, crtc */
3640         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3641         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3642                                         S_000054_CRTC_DISPLAY_DIS(1));
3643         WREG32(R_000050_CRTC_GEN_CNTL,
3644                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3645                         S_000050_CRTC_DISP_REQ_EN_B(1));
3646         WREG32(R_000420_OV0_SCALE_CNTL,
3647                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3648         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3649         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3650                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3651                                                 S_000360_CUR2_LOCK(1));
3652                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3653                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3654                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3655                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3656                 WREG32(R_000360_CUR2_OFFSET,
3657                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3658         }
3659 }
3660
3661 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3662 {
3663         /* Update base address for crtc */
3664         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3665         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3666                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3667         }
3668         /* Restore CRTC registers */
3669         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3670         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3671         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3672         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3673                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3674         }
3675 }
3676
3677 void r100_vga_render_disable(struct radeon_device *rdev)
3678 {
3679         u32 tmp;
3680
3681         tmp = RREG8(R_0003C2_GENMO_WT);
3682         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3683 }
3684
3685 static void r100_debugfs(struct radeon_device *rdev)
3686 {
3687         int r;
3688
3689         r = r100_debugfs_mc_info_init(rdev);
3690         if (r)
3691                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3692 }
3693
3694 static void r100_mc_program(struct radeon_device *rdev)
3695 {
3696         struct r100_mc_save save;
3697
3698         /* Stops all mc clients */
3699         r100_mc_stop(rdev, &save);
3700         if (rdev->flags & RADEON_IS_AGP) {
3701                 WREG32(R_00014C_MC_AGP_LOCATION,
3702                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3703                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3704                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3705                 if (rdev->family > CHIP_RV200)
3706                         WREG32(R_00015C_AGP_BASE_2,
3707                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3708         } else {
3709                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3710                 WREG32(R_000170_AGP_BASE, 0);
3711                 if (rdev->family > CHIP_RV200)
3712                         WREG32(R_00015C_AGP_BASE_2, 0);
3713         }
3714         /* Wait for mc idle */
3715         if (r100_mc_wait_for_idle(rdev))
3716                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3717         /* Program MC, should be a 32bits limited address space */
3718         WREG32(R_000148_MC_FB_LOCATION,
3719                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3720                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3721         r100_mc_resume(rdev, &save);
3722 }
3723
3724 void r100_clock_startup(struct radeon_device *rdev)
3725 {
3726         u32 tmp;
3727
3728         if (radeon_dynclks != -1 && radeon_dynclks)
3729                 radeon_legacy_set_clock_gating(rdev, 1);
3730         /* We need to force on some of the block */
3731         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3732         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3733         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3734                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3735         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3736 }
3737
3738 static int r100_startup(struct radeon_device *rdev)
3739 {
3740         int r;
3741
3742         /* set common regs */
3743         r100_set_common_regs(rdev);
3744         /* program mc */
3745         r100_mc_program(rdev);
3746         /* Resume clock */
3747         r100_clock_startup(rdev);
3748         /* Initialize GPU configuration (# pipes, ...) */
3749 //      r100_gpu_init(rdev);
3750         /* Initialize GART (initialize after TTM so we can allocate
3751          * memory through TTM but finalize after TTM) */
3752         r100_enable_bm(rdev);
3753         if (rdev->flags & RADEON_IS_PCI) {
3754                 r = r100_pci_gart_enable(rdev);
3755                 if (r)
3756                         return r;
3757         }
3758         /* Enable IRQ */
3759         r100_irq_set(rdev);
3760         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3761         /* 1M ring buffer */
3762         r = r100_cp_init(rdev, 1024 * 1024);
3763         if (r) {
3764                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3765                 return r;
3766         }
3767         r = r100_wb_init(rdev);
3768         if (r)
3769                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3770         r = r100_ib_init(rdev);
3771         if (r) {
3772                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3773                 return r;
3774         }
3775         return 0;
3776 }
3777
3778 int r100_resume(struct radeon_device *rdev)
3779 {
3780         /* Make sur GART are not working */
3781         if (rdev->flags & RADEON_IS_PCI)
3782                 r100_pci_gart_disable(rdev);
3783         /* Resume clock before doing reset */
3784         r100_clock_startup(rdev);
3785         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3786         if (radeon_asic_reset(rdev)) {
3787                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3788                         RREG32(R_000E40_RBBM_STATUS),
3789                         RREG32(R_0007C0_CP_STAT));
3790         }
3791         /* post */
3792         radeon_combios_asic_init(rdev->ddev);
3793         /* Resume clock after posting */
3794         r100_clock_startup(rdev);
3795         /* Initialize surface registers */
3796         radeon_surface_init(rdev);
3797         return r100_startup(rdev);
3798 }
3799
3800 int r100_suspend(struct radeon_device *rdev)
3801 {
3802         r100_cp_disable(rdev);
3803         r100_wb_disable(rdev);
3804         r100_irq_disable(rdev);
3805         if (rdev->flags & RADEON_IS_PCI)
3806                 r100_pci_gart_disable(rdev);
3807         return 0;
3808 }
3809
3810 void r100_fini(struct radeon_device *rdev)
3811 {
3812         radeon_pm_fini(rdev);
3813         r100_cp_fini(rdev);
3814         r100_wb_fini(rdev);
3815         r100_ib_fini(rdev);
3816         radeon_gem_fini(rdev);
3817         if (rdev->flags & RADEON_IS_PCI)
3818                 r100_pci_gart_fini(rdev);
3819         radeon_agp_fini(rdev);
3820         radeon_irq_kms_fini(rdev);
3821         radeon_fence_driver_fini(rdev);
3822         radeon_bo_fini(rdev);
3823         radeon_atombios_fini(rdev);
3824         kfree(rdev->bios);
3825         rdev->bios = NULL;
3826 }
3827
3828 int r100_init(struct radeon_device *rdev)
3829 {
3830         int r;
3831
3832         /* Register debugfs file specific to this group of asics */
3833         r100_debugfs(rdev);
3834         /* Disable VGA */
3835         r100_vga_render_disable(rdev);
3836         /* Initialize scratch registers */
3837         radeon_scratch_init(rdev);
3838         /* Initialize surface registers */
3839         radeon_surface_init(rdev);
3840         /* TODO: disable VGA need to use VGA request */
3841         /* BIOS*/
3842         if (!radeon_get_bios(rdev)) {
3843                 if (ASIC_IS_AVIVO(rdev))
3844                         return -EINVAL;
3845         }
3846         if (rdev->is_atom_bios) {
3847                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3848                 return -EINVAL;
3849         } else {
3850                 r = radeon_combios_init(rdev);
3851                 if (r)
3852                         return r;
3853         }
3854         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3855         if (radeon_asic_reset(rdev)) {
3856                 dev_warn(rdev->dev,
3857                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3858                         RREG32(R_000E40_RBBM_STATUS),
3859                         RREG32(R_0007C0_CP_STAT));
3860         }
3861         /* check if cards are posted or not */
3862         if (radeon_boot_test_post_card(rdev) == false)
3863                 return -EINVAL;
3864         /* Set asic errata */
3865         r100_errata(rdev);
3866         /* Initialize clocks */
3867         radeon_get_clock_info(rdev->ddev);
3868         /* Initialize power management */
3869         radeon_pm_init(rdev);
3870         /* initialize AGP */
3871         if (rdev->flags & RADEON_IS_AGP) {
3872                 r = radeon_agp_init(rdev);
3873                 if (r) {
3874                         radeon_agp_disable(rdev);
3875                 }
3876         }
3877         /* initialize VRAM */
3878         r100_mc_init(rdev);
3879         /* Fence driver */
3880         r = radeon_fence_driver_init(rdev);
3881         if (r)
3882                 return r;
3883         r = radeon_irq_kms_init(rdev);
3884         if (r)
3885                 return r;
3886         /* Memory manager */
3887         r = radeon_bo_init(rdev);
3888         if (r)
3889                 return r;
3890         if (rdev->flags & RADEON_IS_PCI) {
3891                 r = r100_pci_gart_init(rdev);
3892                 if (r)
3893                         return r;
3894         }
3895         r100_set_safe_registers(rdev);
3896         rdev->accel_working = true;
3897         r = r100_startup(rdev);
3898         if (r) {
3899                 /* Somethings want wront with the accel init stop accel */
3900                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3901                 r100_cp_fini(rdev);
3902                 r100_wb_fini(rdev);
3903                 r100_ib_fini(rdev);
3904                 radeon_irq_kms_fini(rdev);
3905                 if (rdev->flags & RADEON_IS_PCI)
3906                         r100_pci_gart_fini(rdev);
3907                 rdev->accel_working = false;
3908         }
3909         return 0;
3910 }