drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44
  45 #include "r100_reg_safe.h"
  46 #include "rn50_reg_safe.h"
  47
  48 /* Firmware Names */
  49 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  50 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  51 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  52 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  53 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  54 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  55 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  56
  57 MODULE_FIRMWARE(FIRMWARE_R100);
  58 MODULE_FIRMWARE(FIRMWARE_R200);
  59 MODULE_FIRMWARE(FIRMWARE_R300);
  60 MODULE_FIRMWARE(FIRMWARE_R420);
  61 MODULE_FIRMWARE(FIRMWARE_RS690);
  62 MODULE_FIRMWARE(FIRMWARE_RS600);
  63 MODULE_FIRMWARE(FIRMWARE_R520);
  64
  65 #include "r100_track.h"
  66
  67 /* This files gather functions specifics to:
  68  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  69  */
  70
  71 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
  72 {
  73         int i;
  74         rdev->pm.dynpm_can_upclock = true;
  75         rdev->pm.dynpm_can_downclock = true;
  76
  77         switch (rdev->pm.dynpm_planned_action) {
  78         case DYNPM_ACTION_MINIMUM:
  79                 rdev->pm.requested_power_state_index = 0;
  80                 rdev->pm.dynpm_can_downclock = false;
  81                 break;
  82         case DYNPM_ACTION_DOWNCLOCK:
  83                 if (rdev->pm.current_power_state_index == 0) {
  84                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  85                         rdev->pm.dynpm_can_downclock = false;
  86                 } else {
  87                         if (rdev->pm.active_crtc_count > 1) {
  88                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
  89                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
  90                                                 continue;
  91                                         else if (i >= rdev->pm.current_power_state_index) {
  92                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  93                                                 break;
  94                                         } else {
  95                                                 rdev->pm.requested_power_state_index = i;
  96                                                 break;
  97                                         }
  98                                 }
  99                         } else
 100                                 rdev->pm.requested_power_state_index =
 101                                         rdev->pm.current_power_state_index - 1;
 102                 }
 103                 /* don't use the power state if crtcs are active and no display flag is set */
 104                 if ((rdev->pm.active_crtc_count > 0) &&
 105                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 106                      RADEON_PM_MODE_NO_DISPLAY)) {
 107                         rdev->pm.requested_power_state_index++;
 108                 }
 109                 break;
 110         case DYNPM_ACTION_UPCLOCK:
 111                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 112                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 113                         rdev->pm.dynpm_can_upclock = false;
 114                 } else {
 115                         if (rdev->pm.active_crtc_count > 1) {
 116                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 117                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 118                                                 continue;
 119                                         else if (i <= rdev->pm.current_power_state_index) {
 120                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 121                                                 break;
 122                                         } else {
 123                                                 rdev->pm.requested_power_state_index = i;
 124                                                 break;
 125                                         }
 126                                 }
 127                         } else
 128                                 rdev->pm.requested_power_state_index =
 129                                         rdev->pm.current_power_state_index + 1;
 130                 }
 131                 break;
 132         case DYNPM_ACTION_DEFAULT:
 133                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 134                 rdev->pm.dynpm_can_upclock = false;
 135                 break;
 136         case DYNPM_ACTION_NONE:
 137         default:
 138                 DRM_ERROR("Requested mode for not defined action\n");
 139                 return;
 140         }
 141         /* only one clock mode per power state */
 142         rdev->pm.requested_clock_mode_index = 0;
 143
 144         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 145                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 146                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 147                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 148                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 149                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 150                   pcie_lanes);
 151 }
 152
 153 void r100_pm_init_profile(struct radeon_device *rdev)
 154 {
 155         /* default */
 156         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 157         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 158         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 159         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 160         /* low sh */
 161         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 162         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 163         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 164         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 165         /* mid sh */
 166         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 167         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 168         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 169         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 170         /* high sh */
 171         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 172         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 173         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 174         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 175         /* low mh */
 176         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 177         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 178         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 179         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 180         /* mid mh */
 181         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 182         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 183         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 184         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 185         /* high mh */
 186         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 187         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 188         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 189         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 190 }
 191
 192 void r100_pm_misc(struct radeon_device *rdev)
 193 {
 194         int requested_index = rdev->pm.requested_power_state_index;
 195         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 196         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 197         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 198
 199         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 200                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 201                         tmp = RREG32(voltage->gpio.reg);
 202                         if (voltage->active_high)
 203                                 tmp |= voltage->gpio.mask;
 204                         else
 205                                 tmp &= ~(voltage->gpio.mask);
 206                         WREG32(voltage->gpio.reg, tmp);
 207                         if (voltage->delay)
 208                                 udelay(voltage->delay);
 209                 } else {
 210                         tmp = RREG32(voltage->gpio.reg);
 211                         if (voltage->active_high)
 212                                 tmp &= ~voltage->gpio.mask;
 213                         else
 214                                 tmp |= voltage->gpio.mask;
 215                         WREG32(voltage->gpio.reg, tmp);
 216                         if (voltage->delay)
 217                                 udelay(voltage->delay);
 218                 }
 219         }
 220
 221         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 222         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 223         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 224         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 225         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 226         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 227                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 228                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 229                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 230                 else
 231                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 232                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 233                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 234                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 235                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 236         } else
 237                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 238
 239         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 240                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 241                 if (voltage->delay) {
 242                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 243                         switch (voltage->delay) {
 244                         case 33:
 245                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 246                                 break;
 247                         case 66:
 248                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 249                                 break;
 250                         case 99:
 251                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 252                                 break;
 253                         case 132:
 254                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 255                                 break;
 256                         }
 257                 } else
 258                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 259         } else
 260                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 261
 262         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 263                 sclk_cntl &= ~FORCE_HDP;
 264         else
 265                 sclk_cntl |= FORCE_HDP;
 266
 267         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 268         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 269         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 270
 271         /* set pcie lanes */
 272         if ((rdev->flags & RADEON_IS_PCIE) &&
 273             !(rdev->flags & RADEON_IS_IGP) &&
 274             rdev->asic->set_pcie_lanes &&
 275             (ps->pcie_lanes !=
 276              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 277                 radeon_set_pcie_lanes(rdev,
 278                                       ps->pcie_lanes);
 279                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 280         }
 281 }
 282
 283 void r100_pm_prepare(struct radeon_device *rdev)
 284 {
 285         struct drm_device *ddev = rdev->ddev;
 286         struct drm_crtc *crtc;
 287         struct radeon_crtc *radeon_crtc;
 288         u32 tmp;
 289
 290         /* disable any active CRTCs */
 291         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 292                 radeon_crtc = to_radeon_crtc(crtc);
 293                 if (radeon_crtc->enabled) {
 294                         if (radeon_crtc->crtc_id) {
 295                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 296                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 297                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 298                         } else {
 299                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 300                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 301                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 302                         }
 303                 }
 304         }
 305 }
 306
 307 void r100_pm_finish(struct radeon_device *rdev)
 308 {
 309         struct drm_device *ddev = rdev->ddev;
 310         struct drm_crtc *crtc;
 311         struct radeon_crtc *radeon_crtc;
 312         u32 tmp;
 313
 314         /* enable any active CRTCs */
 315         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 316                 radeon_crtc = to_radeon_crtc(crtc);
 317                 if (radeon_crtc->enabled) {
 318                         if (radeon_crtc->crtc_id) {
 319                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 320                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 321                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 322                         } else {
 323                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 324                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 325                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 326                         }
 327                 }
 328         }
 329 }
 330
 331 bool r100_gui_idle(struct radeon_device *rdev)
 332 {
 333         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 334                 return false;
 335         else
 336                 return true;
 337 }
 338
 339 /* hpd for digital panel detect/disconnect */
 340 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 341 {
 342         bool connected = false;
 343
 344         switch (hpd) {
 345         case RADEON_HPD_1:
 346                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 347                         connected = true;
 348                 break;
 349         case RADEON_HPD_2:
 350                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 351                         connected = true;
 352                 break;
 353         default:
 354                 break;
 355         }
 356         return connected;
 357 }
 358
 359 void r100_hpd_set_polarity(struct radeon_device *rdev,
 360                            enum radeon_hpd_id hpd)
 361 {
 362         u32 tmp;
 363         bool connected = r100_hpd_sense(rdev, hpd);
 364
 365         switch (hpd) {
 366         case RADEON_HPD_1:
 367                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 368                 if (connected)
 369                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 370                 else
 371                         tmp |= RADEON_FP_DETECT_INT_POL;
 372                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 373                 break;
 374         case RADEON_HPD_2:
 375                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 376                 if (connected)
 377                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 378                 else
 379                         tmp |= RADEON_FP2_DETECT_INT_POL;
 380                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 381                 break;
 382         default:
 383                 break;
 384         }
 385 }
 386
 387 void r100_hpd_init(struct radeon_device *rdev)
 388 {
 389         struct drm_device *dev = rdev->ddev;
 390         struct drm_connector *connector;
 391
 392         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 393                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 394                 switch (radeon_connector->hpd.hpd) {
 395                 case RADEON_HPD_1:
 396                         rdev->irq.hpd[0] = true;
 397                         break;
 398                 case RADEON_HPD_2:
 399                         rdev->irq.hpd[1] = true;
 400                         break;
 401                 default:
 402                         break;
 403                 }
 404         }
 405         if (rdev->irq.installed)
 406                 r100_irq_set(rdev);
 407 }
 408
 409 void r100_hpd_fini(struct radeon_device *rdev)
 410 {
 411         struct drm_device *dev = rdev->ddev;
 412         struct drm_connector *connector;
 413
 414         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 415                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 416                 switch (radeon_connector->hpd.hpd) {
 417                 case RADEON_HPD_1:
 418                         rdev->irq.hpd[0] = false;
 419                         break;
 420                 case RADEON_HPD_2:
 421                         rdev->irq.hpd[1] = false;
 422                         break;
 423                 default:
 424                         break;
 425                 }
 426         }
 427 }
 428
 429 /*
 430  * PCI GART
 431  */
 432 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 433 {
 434         /* TODO: can we do somethings here ? */
 435         /* It seems hw only cache one entry so we should discard this
 436          * entry otherwise if first GPU GART read hit this entry it
 437          * could end up in wrong address. */
 438 }
 439
 440 int r100_pci_gart_init(struct radeon_device *rdev)
 441 {
 442         int r;
 443
 444         if (rdev->gart.table.ram.ptr) {
 445                 WARN(1, "R100 PCI GART already initialized.\n");
 446                 return 0;
 447         }
 448         /* Initialize common gart structure */
 449         r = radeon_gart_init(rdev);
 450         if (r)
 451                 return r;
 452         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 453         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 454         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 455         return radeon_gart_table_ram_alloc(rdev);
 456 }
 457
 458 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 459 void r100_enable_bm(struct radeon_device *rdev)
 460 {
 461         uint32_t tmp;
 462         /* Enable bus mastering */
 463         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 464         WREG32(RADEON_BUS_CNTL, tmp);
 465 }
 466
 467 int r100_pci_gart_enable(struct radeon_device *rdev)
 468 {
 469         uint32_t tmp;
 470
 471         radeon_gart_restore(rdev);
 472         /* discard memory request outside of configured range */
 473         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 474         WREG32(RADEON_AIC_CNTL, tmp);
 475         /* set address range for PCI address translate */
 476         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 477         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 478         /* set PCI GART page-table base address */
 479         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 480         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 481         WREG32(RADEON_AIC_CNTL, tmp);
 482         r100_pci_gart_tlb_flush(rdev);
 483         rdev->gart.ready = true;
 484         return 0;
 485 }
 486
 487 void r100_pci_gart_disable(struct radeon_device *rdev)
 488 {
 489         uint32_t tmp;
 490
 491         /* discard memory request outside of configured range */
 492         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 493         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 494         WREG32(RADEON_AIC_LO_ADDR, 0);
 495         WREG32(RADEON_AIC_HI_ADDR, 0);
 496 }
 497
 498 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 499 {
 500         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 501                 return -EINVAL;
 502         }
 503         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 504         return 0;
 505 }
 506
 507 void r100_pci_gart_fini(struct radeon_device *rdev)
 508 {
 509         radeon_gart_fini(rdev);
 510         r100_pci_gart_disable(rdev);
 511         radeon_gart_table_ram_free(rdev);
 512 }
 513
 514 int r100_irq_set(struct radeon_device *rdev)
 515 {
 516         uint32_t tmp = 0;
 517
 518         if (!rdev->irq.installed) {
 519                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
 520                 WREG32(R_000040_GEN_INT_CNTL, 0);
 521                 return -EINVAL;
 522         }
 523         if (rdev->irq.sw_int) {
 524                 tmp |= RADEON_SW_INT_ENABLE;
 525         }
 526         if (rdev->irq.gui_idle) {
 527                 tmp |= RADEON_GUI_IDLE_MASK;
 528         }
 529         if (rdev->irq.crtc_vblank_int[0]) {
 530                 tmp |= RADEON_CRTC_VBLANK_MASK;
 531         }
 532         if (rdev->irq.crtc_vblank_int[1]) {
 533                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 534         }
 535         if (rdev->irq.hpd[0]) {
 536                 tmp |= RADEON_FP_DETECT_MASK;
 537         }
 538         if (rdev->irq.hpd[1]) {
 539                 tmp |= RADEON_FP2_DETECT_MASK;
 540         }
 541         WREG32(RADEON_GEN_INT_CNTL, tmp);
 542         return 0;
 543 }
 544
 545 void r100_irq_disable(struct radeon_device *rdev)
 546 {
 547         u32 tmp;
 548
 549         WREG32(R_000040_GEN_INT_CNTL, 0);
 550         /* Wait and acknowledge irq */
 551         mdelay(1);
 552         tmp = RREG32(R_000044_GEN_INT_STATUS);
 553         WREG32(R_000044_GEN_INT_STATUS, tmp);
 554 }
 555
 556 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 557 {
 558         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 559         uint32_t irq_mask = RADEON_SW_INT_TEST |
 560                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 561                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 562
 563         /* the interrupt works, but the status bit is permanently asserted */
 564         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 565                 if (!rdev->irq.gui_idle_acked)
 566                         irq_mask |= RADEON_GUI_IDLE_STAT;
 567         }
 568
 569         if (irqs) {
 570                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 571         }
 572         return irqs & irq_mask;
 573 }
 574
 575 int r100_irq_process(struct radeon_device *rdev)
 576 {
 577         uint32_t status, msi_rearm;
 578         bool queue_hotplug = false;
 579
 580         /* reset gui idle ack.  the status bit is broken */
 581         rdev->irq.gui_idle_acked = false;
 582
 583         status = r100_irq_ack(rdev);
 584         if (!status) {
 585                 return IRQ_NONE;
 586         }
 587         if (rdev->shutdown) {
 588                 return IRQ_NONE;
 589         }
 590         while (status) {
 591                 /* SW interrupt */
 592                 if (status & RADEON_SW_INT_TEST) {
 593                         radeon_fence_process(rdev);
 594                 }
 595                 /* gui idle interrupt */
 596                 if (status & RADEON_GUI_IDLE_STAT) {
 597                         rdev->irq.gui_idle_acked = true;
 598                         rdev->pm.gui_idle = true;
 599                         wake_up(&rdev->irq.idle_queue);
 600                 }
 601                 /* Vertical blank interrupts */
 602                 if (status & RADEON_CRTC_VBLANK_STAT) {
 603                         drm_handle_vblank(rdev->ddev, 0);
 604                         rdev->pm.vblank_sync = true;
 605                         wake_up(&rdev->irq.vblank_queue);
 606                 }
 607                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 608                         drm_handle_vblank(rdev->ddev, 1);
 609                         rdev->pm.vblank_sync = true;
 610                         wake_up(&rdev->irq.vblank_queue);
 611                 }
 612                 if (status & RADEON_FP_DETECT_STAT) {
 613                         queue_hotplug = true;
 614                         DRM_DEBUG("HPD1\n");
 615                 }
 616                 if (status & RADEON_FP2_DETECT_STAT) {
 617                         queue_hotplug = true;
 618                         DRM_DEBUG("HPD2\n");
 619                 }
 620                 status = r100_irq_ack(rdev);
 621         }
 622         /* reset gui idle ack.  the status bit is broken */
 623         rdev->irq.gui_idle_acked = false;
 624         if (queue_hotplug)
 625                 queue_work(rdev->wq, &rdev->hotplug_work);
 626         if (rdev->msi_enabled) {
 627                 switch (rdev->family) {
 628                 case CHIP_RS400:
 629                 case CHIP_RS480:
 630                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 631                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 632                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 633                         break;
 634                 default:
 635                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 636                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 637                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 638                         break;
 639                 }
 640         }
 641         return IRQ_HANDLED;
 642 }
 643
 644 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 645 {
 646         if (crtc == 0)
 647                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 648         else
 649                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 650 }
 651
 652 /* Who ever call radeon_fence_emit should call ring_lock and ask
 653  * for enough space (today caller are ib schedule and buffer move) */
 654 void r100_fence_ring_emit(struct radeon_device *rdev,
 655                           struct radeon_fence *fence)
 656 {
 657         /* We have to make sure that caches are flushed before
 658          * CPU might read something from VRAM. */
 659         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 660         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 661         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 662         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 663         /* Wait until IDLE & CLEAN */
 664         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 665         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 666         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 667         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 668                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 669         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 670         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 671         /* Emit fence sequence & fire IRQ */
 672         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 673         radeon_ring_write(rdev, fence->seq);
 674         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 675         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 676 }
 677
 678 int r100_copy_blit(struct radeon_device *rdev,
 679                    uint64_t src_offset,
 680                    uint64_t dst_offset,
 681                    unsigned num_pages,
 682                    struct radeon_fence *fence)
 683 {
 684         uint32_t cur_pages;
 685         uint32_t stride_bytes = PAGE_SIZE;
 686         uint32_t pitch;
 687         uint32_t stride_pixels;
 688         unsigned ndw;
 689         int num_loops;
 690         int r = 0;
 691
 692         /* radeon limited to 16k stride */
 693         stride_bytes &= 0x3fff;
 694         /* radeon pitch is /64 */
 695         pitch = stride_bytes / 64;
 696         stride_pixels = stride_bytes / 4;
 697         num_loops = DIV_ROUND_UP(num_pages, 8191);
 698
 699         /* Ask for enough room for blit + flush + fence */
 700         ndw = 64 + (10 * num_loops);
 701         r = radeon_ring_lock(rdev, ndw);
 702         if (r) {
 703                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 704                 return -EINVAL;
 705         }
 706         while (num_pages > 0) {
 707                 cur_pages = num_pages;
 708                 if (cur_pages > 8191) {
 709                         cur_pages = 8191;
 710                 }
 711                 num_pages -= cur_pages;
 712
 713                 /* pages are in Y direction - height
 714                    page width in X direction - width */
 715                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 716                 radeon_ring_write(rdev,
 717                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 718                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 719                                   RADEON_GMC_SRC_CLIPPING |
 720                                   RADEON_GMC_DST_CLIPPING |
 721                                   RADEON_GMC_BRUSH_NONE |
 722                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 723                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 724                                   RADEON_ROP3_S |
 725                                   RADEON_DP_SRC_SOURCE_MEMORY |
 726                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 727                                   RADEON_GMC_WR_MSK_DIS);
 728                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 729                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 730                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 731                 radeon_ring_write(rdev, 0);
 732                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 733                 radeon_ring_write(rdev, num_pages);
 734                 radeon_ring_write(rdev, num_pages);
 735                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 736         }
 737         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 738         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 739         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 740         radeon_ring_write(rdev,
 741                           RADEON_WAIT_2D_IDLECLEAN |
 742                           RADEON_WAIT_HOST_IDLECLEAN |
 743                           RADEON_WAIT_DMA_GUI_IDLE);
 744         if (fence) {
 745                 r = radeon_fence_emit(rdev, fence);
 746         }
 747         radeon_ring_unlock_commit(rdev);
 748         return r;
 749 }
 750
 751 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 752 {
 753         unsigned i;
 754         u32 tmp;
 755
 756         for (i = 0; i < rdev->usec_timeout; i++) {
 757                 tmp = RREG32(R_000E40_RBBM_STATUS);
 758                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 759                         return 0;
 760                 }
 761                 udelay(1);
 762         }
 763         return -1;
 764 }
 765
 766 void r100_ring_start(struct radeon_device *rdev)
 767 {
 768         int r;
 769
 770         r = radeon_ring_lock(rdev, 2);
 771         if (r) {
 772                 return;
 773         }
 774         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 775         radeon_ring_write(rdev,
 776                           RADEON_ISYNC_ANY2D_IDLE3D |
 777                           RADEON_ISYNC_ANY3D_IDLE2D |
 778                           RADEON_ISYNC_WAIT_IDLEGUI |
 779                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 780         radeon_ring_unlock_commit(rdev);
 781 }
 782
 783
 784 /* Load the microcode for the CP */
 785 static int r100_cp_init_microcode(struct radeon_device *rdev)
 786 {
 787         struct platform_device *pdev;
 788         const char *fw_name = NULL;
 789         int err;
 790
 791         DRM_DEBUG_KMS("\n");
 792
 793         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 794         err = IS_ERR(pdev);
 795         if (err) {
 796                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 797                 return -EINVAL;
 798         }
 799         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 800             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 801             (rdev->family == CHIP_RS200)) {
 802                 DRM_INFO("Loading R100 Microcode\n");
 803                 fw_name = FIRMWARE_R100;
 804         } else if ((rdev->family == CHIP_R200) ||
 805                    (rdev->family == CHIP_RV250) ||
 806                    (rdev->family == CHIP_RV280) ||
 807                    (rdev->family == CHIP_RS300)) {
 808                 DRM_INFO("Loading R200 Microcode\n");
 809                 fw_name = FIRMWARE_R200;
 810         } else if ((rdev->family == CHIP_R300) ||
 811                    (rdev->family == CHIP_R350) ||
 812                    (rdev->family == CHIP_RV350) ||
 813                    (rdev->family == CHIP_RV380) ||
 814                    (rdev->family == CHIP_RS400) ||
 815                    (rdev->family == CHIP_RS480)) {
 816                 DRM_INFO("Loading R300 Microcode\n");
 817                 fw_name = FIRMWARE_R300;
 818         } else if ((rdev->family == CHIP_R420) ||
 819                    (rdev->family == CHIP_R423) ||
 820                    (rdev->family == CHIP_RV410)) {
 821                 DRM_INFO("Loading R400 Microcode\n");
 822                 fw_name = FIRMWARE_R420;
 823         } else if ((rdev->family == CHIP_RS690) ||
 824                    (rdev->family == CHIP_RS740)) {
 825                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 826                 fw_name = FIRMWARE_RS690;
 827         } else if (rdev->family == CHIP_RS600) {
 828                 DRM_INFO("Loading RS600 Microcode\n");
 829                 fw_name = FIRMWARE_RS600;
 830         } else if ((rdev->family == CHIP_RV515) ||
 831                    (rdev->family == CHIP_R520) ||
 832                    (rdev->family == CHIP_RV530) ||
 833                    (rdev->family == CHIP_R580) ||
 834                    (rdev->family == CHIP_RV560) ||
 835                    (rdev->family == CHIP_RV570)) {
 836                 DRM_INFO("Loading R500 Microcode\n");
 837                 fw_name = FIRMWARE_R520;
 838         }
 839
 840         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 841         platform_device_unregister(pdev);
 842         if (err) {
 843                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 844                        fw_name);
 845         } else if (rdev->me_fw->size % 8) {
 846                 printk(KERN_ERR
 847                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 848                        rdev->me_fw->size, fw_name);
 849                 err = -EINVAL;
 850                 release_firmware(rdev->me_fw);
 851                 rdev->me_fw = NULL;
 852         }
 853         return err;
 854 }
 855
 856 static void r100_cp_load_microcode(struct radeon_device *rdev)
 857 {
 858         const __be32 *fw_data;
 859         int i, size;
 860
 861         if (r100_gui_wait_for_idle(rdev)) {
 862                 printk(KERN_WARNING "Failed to wait GUI idle while "
 863                        "programming pipes. Bad things might happen.\n");
 864         }
 865
 866         if (rdev->me_fw) {
 867                 size = rdev->me_fw->size / 4;
 868                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 869                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 870                 for (i = 0; i < size; i += 2) {
 871                         WREG32(RADEON_CP_ME_RAM_DATAH,
 872                                be32_to_cpup(&fw_data[i]));
 873                         WREG32(RADEON_CP_ME_RAM_DATAL,
 874                                be32_to_cpup(&fw_data[i + 1]));
 875                 }
 876         }
 877 }
 878
 879 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 880 {
 881         unsigned rb_bufsz;
 882         unsigned rb_blksz;
 883         unsigned max_fetch;
 884         unsigned pre_write_timer;
 885         unsigned pre_write_limit;
 886         unsigned indirect2_start;
 887         unsigned indirect1_start;
 888         uint32_t tmp;
 889         int r;
 890
 891         if (r100_debugfs_cp_init(rdev)) {
 892                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 893         }
 894         if (!rdev->me_fw) {
 895                 r = r100_cp_init_microcode(rdev);
 896                 if (r) {
 897                         DRM_ERROR("Failed to load firmware!\n");
 898                         return r;
 899                 }
 900         }
 901
 902         /* Align ring size */
 903         rb_bufsz = drm_order(ring_size / 8);
 904         ring_size = (1 << (rb_bufsz + 1)) * 4;
 905         r100_cp_load_microcode(rdev);
 906         r = radeon_ring_init(rdev, ring_size);
 907         if (r) {
 908                 return r;
 909         }
 910         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 911          * the rptr copy in system ram */
 912         rb_blksz = 9;
 913         /* cp will read 128bytes at a time (4 dwords) */
 914         max_fetch = 1;
 915         rdev->cp.align_mask = 16 - 1;
 916         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 917         pre_write_timer = 64;
 918         /* Force CP_RB_WPTR write if written more than one time before the
 919          * delay expire
 920          */
 921         pre_write_limit = 0;
 922         /* Setup the cp cache like this (cache size is 96 dwords) :
 923          *      RING            0  to 15
 924          *      INDIRECT1       16 to 79
 925          *      INDIRECT2       80 to 95
 926          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 927          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 928          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 929          * Idea being that most of the gpu cmd will be through indirect1 buffer
 930          * so it gets the bigger cache.
 931          */
 932         indirect2_start = 80;
 933         indirect1_start = 16;
 934         /* cp setup */
 935         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 936         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 937                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 938                REG_SET(RADEON_MAX_FETCH, max_fetch));
 939 #ifdef __BIG_ENDIAN
 940         tmp |= RADEON_BUF_SWAP_32BIT;
 941 #endif
 942         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
 943
 944         /* Set ring address */
 945         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
 946         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
 947         /* Force read & write ptr to 0 */
 948         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
 949         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 950         WREG32(RADEON_CP_RB_WPTR, 0);
 951
 952         /* set the wb address whether it's enabled or not */
 953         WREG32(R_00070C_CP_RB_RPTR_ADDR,
 954                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
 955         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
 956
 957         if (rdev->wb.enabled)
 958                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
 959         else {
 960                 tmp |= RADEON_RB_NO_UPDATE;
 961                 WREG32(R_000770_SCRATCH_UMSK, 0);
 962         }
 963
 964         WREG32(RADEON_CP_RB_CNTL, tmp);
 965         udelay(10);
 966         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
 967         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
 968         /* protect against crazy HW on resume */
 969         rdev->cp.wptr &= rdev->cp.ptr_mask;
 970         /* Set cp mode to bus mastering & enable cp*/
 971         WREG32(RADEON_CP_CSQ_MODE,
 972                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
 973                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
 974         WREG32(0x718, 0);
 975         WREG32(0x744, 0x00004D4D);
 976         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
 977         radeon_ring_start(rdev);
 978         r = radeon_ring_test(rdev);
 979         if (r) {
 980                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
 981                 return r;
 982         }
 983         rdev->cp.ready = true;
 984         return 0;
 985 }
 986
 987 void r100_cp_fini(struct radeon_device *rdev)
 988 {
 989         if (r100_cp_wait_for_idle(rdev)) {
 990                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
 991         }
 992         /* Disable ring */
 993         r100_cp_disable(rdev);
 994         radeon_ring_fini(rdev);
 995         DRM_INFO("radeon: cp finalized\n");
 996 }
 997
 998 void r100_cp_disable(struct radeon_device *rdev)
 999 {
1000         /* Disable ring */
1001         rdev->cp.ready = false;
1002         WREG32(RADEON_CP_CSQ_MODE, 0);
1003         WREG32(RADEON_CP_CSQ_CNTL, 0);
1004         WREG32(R_000770_SCRATCH_UMSK, 0);
1005         if (r100_gui_wait_for_idle(rdev)) {
1006                 printk(KERN_WARNING "Failed to wait GUI idle while "
1007                        "programming pipes. Bad things might happen.\n");
1008         }
1009 }
1010
1011 void r100_cp_commit(struct radeon_device *rdev)
1012 {
1013         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1014         (void)RREG32(RADEON_CP_RB_WPTR);
1015 }
1016
1017
1018 /*
1019  * CS functions
1020  */
1021 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1022                           struct radeon_cs_packet *pkt,
1023                           const unsigned *auth, unsigned n,
1024                           radeon_packet0_check_t check)
1025 {
1026         unsigned reg;
1027         unsigned i, j, m;
1028         unsigned idx;
1029         int r;
1030
1031         idx = pkt->idx + 1;
1032         reg = pkt->reg;
1033         /* Check that register fall into register range
1034          * determined by the number of entry (n) in the
1035          * safe register bitmap.
1036          */
1037         if (pkt->one_reg_wr) {
1038                 if ((reg >> 7) > n) {
1039                         return -EINVAL;
1040                 }
1041         } else {
1042                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1043                         return -EINVAL;
1044                 }
1045         }
1046         for (i = 0; i <= pkt->count; i++, idx++) {
1047                 j = (reg >> 7);
1048                 m = 1 << ((reg >> 2) & 31);
1049                 if (auth[j] & m) {
1050                         r = check(p, pkt, idx, reg);
1051                         if (r) {
1052                                 return r;
1053                         }
1054                 }
1055                 if (pkt->one_reg_wr) {
1056                         if (!(auth[j] & m)) {
1057                                 break;
1058                         }
1059                 } else {
1060                         reg += 4;
1061                 }
1062         }
1063         return 0;
1064 }
1065
1066 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1067                          struct radeon_cs_packet *pkt)
1068 {
1069         volatile uint32_t *ib;
1070         unsigned i;
1071         unsigned idx;
1072
1073         ib = p->ib->ptr;
1074         idx = pkt->idx;
1075         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1076                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1077         }
1078 }
1079
1080 /**
1081  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1082  * @parser:     parser structure holding parsing context.
1083  * @pkt:        where to store packet informations
1084  *
1085  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1086  * if packet is bigger than remaining ib size. or if packets is unknown.
1087  **/
1088 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1089                          struct radeon_cs_packet *pkt,
1090                          unsigned idx)
1091 {
1092         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1093         uint32_t header;
1094
1095         if (idx >= ib_chunk->length_dw) {
1096                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1097                           idx, ib_chunk->length_dw);
1098                 return -EINVAL;
1099         }
1100         header = radeon_get_ib_value(p, idx);
1101         pkt->idx = idx;
1102         pkt->type = CP_PACKET_GET_TYPE(header);
1103         pkt->count = CP_PACKET_GET_COUNT(header);
1104         switch (pkt->type) {
1105         case PACKET_TYPE0:
1106                 pkt->reg = CP_PACKET0_GET_REG(header);
1107                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1108                 break;
1109         case PACKET_TYPE3:
1110                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1111                 break;
1112         case PACKET_TYPE2:
1113                 pkt->count = -1;
1114                 break;
1115         default:
1116                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1117                 return -EINVAL;
1118         }
1119         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1120                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1121                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1122                 return -EINVAL;
1123         }
1124         return 0;
1125 }
1126
1127 /**
1128  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1129  * @parser:             parser structure holding parsing context.
1130  *
1131  * Userspace sends a special sequence for VLINE waits.
1132  * PACKET0 - VLINE_START_END + value
1133  * PACKET0 - WAIT_UNTIL +_value
1134  * RELOC (P3) - crtc_id in reloc.
1135  *
1136  * This function parses this and relocates the VLINE START END
1137  * and WAIT UNTIL packets to the correct crtc.
1138  * It also detects a switched off crtc and nulls out the
1139  * wait in that case.
1140  */
1141 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1142 {
1143         struct drm_mode_object *obj;
1144         struct drm_crtc *crtc;
1145         struct radeon_crtc *radeon_crtc;
1146         struct radeon_cs_packet p3reloc, waitreloc;
1147         int crtc_id;
1148         int r;
1149         uint32_t header, h_idx, reg;
1150         volatile uint32_t *ib;
1151
1152         ib = p->ib->ptr;
1153
1154         /* parse the wait until */
1155         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1156         if (r)
1157                 return r;
1158
1159         /* check its a wait until and only 1 count */
1160         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1161             waitreloc.count != 0) {
1162                 DRM_ERROR("vline wait had illegal wait until segment\n");
1163                 r = -EINVAL;
1164                 return r;
1165         }
1166
1167         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1168                 DRM_ERROR("vline wait had illegal wait until\n");
1169                 r = -EINVAL;
1170                 return r;
1171         }
1172
1173         /* jump over the NOP */
1174         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1175         if (r)
1176                 return r;
1177
1178         h_idx = p->idx - 2;
1179         p->idx += waitreloc.count + 2;
1180         p->idx += p3reloc.count + 2;
1181
1182         header = radeon_get_ib_value(p, h_idx);
1183         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1184         reg = CP_PACKET0_GET_REG(header);
1185         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1186         if (!obj) {
1187                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1188                 r = -EINVAL;
1189                 goto out;
1190         }
1191         crtc = obj_to_crtc(obj);
1192         radeon_crtc = to_radeon_crtc(crtc);
1193         crtc_id = radeon_crtc->crtc_id;
1194
1195         if (!crtc->enabled) {
1196                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1197                 ib[h_idx + 2] = PACKET2(0);
1198                 ib[h_idx + 3] = PACKET2(0);
1199         } else if (crtc_id == 1) {
1200                 switch (reg) {
1201                 case AVIVO_D1MODE_VLINE_START_END:
1202                         header &= ~R300_CP_PACKET0_REG_MASK;
1203                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1204                         break;
1205                 case RADEON_CRTC_GUI_TRIG_VLINE:
1206                         header &= ~R300_CP_PACKET0_REG_MASK;
1207                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1208                         break;
1209                 default:
1210                         DRM_ERROR("unknown crtc reloc\n");
1211                         r = -EINVAL;
1212                         goto out;
1213                 }
1214                 ib[h_idx] = header;
1215                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1216         }
1217 out:
1218         return r;
1219 }
1220
1221 /**
1222  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1223  * @parser:             parser structure holding parsing context.
1224  * @data:               pointer to relocation data
1225  * @offset_start:       starting offset
1226  * @offset_mask:        offset mask (to align start offset on)
1227  * @reloc:              reloc informations
1228  *
1229  * Check next packet is relocation packet3, do bo validation and compute
1230  * GPU offset using the provided start.
1231  **/
1232 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1233                               struct radeon_cs_reloc **cs_reloc)
1234 {
1235         struct radeon_cs_chunk *relocs_chunk;
1236         struct radeon_cs_packet p3reloc;
1237         unsigned idx;
1238         int r;
1239
1240         if (p->chunk_relocs_idx == -1) {
1241                 DRM_ERROR("No relocation chunk !\n");
1242                 return -EINVAL;
1243         }
1244         *cs_reloc = NULL;
1245         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1246         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1247         if (r) {
1248                 return r;
1249         }
1250         p->idx += p3reloc.count + 2;
1251         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1252                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1253                           p3reloc.idx);
1254                 r100_cs_dump_packet(p, &p3reloc);
1255                 return -EINVAL;
1256         }
1257         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1258         if (idx >= relocs_chunk->length_dw) {
1259                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1260                           idx, relocs_chunk->length_dw);
1261                 r100_cs_dump_packet(p, &p3reloc);
1262                 return -EINVAL;
1263         }
1264         /* FIXME: we assume reloc size is 4 dwords */
1265         *cs_reloc = p->relocs_ptr[(idx / 4)];
1266         return 0;
1267 }
1268
1269 static int r100_get_vtx_size(uint32_t vtx_fmt)
1270 {
1271         int vtx_size;
1272         vtx_size = 2;
1273         /* ordered according to bits in spec */
1274         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1275                 vtx_size++;
1276         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1277                 vtx_size += 3;
1278         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1279                 vtx_size++;
1280         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1281                 vtx_size++;
1282         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1283                 vtx_size += 3;
1284         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1285                 vtx_size++;
1286         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1287                 vtx_size++;
1288         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1289                 vtx_size += 2;
1290         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1291                 vtx_size += 2;
1292         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1293                 vtx_size++;
1294         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1295                 vtx_size += 2;
1296         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1297                 vtx_size++;
1298         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1299                 vtx_size += 2;
1300         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1301                 vtx_size++;
1302         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1303                 vtx_size++;
1304         /* blend weight */
1305         if (vtx_fmt & (0x7 << 15))
1306                 vtx_size += (vtx_fmt >> 15) & 0x7;
1307         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1308                 vtx_size += 3;
1309         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1310                 vtx_size += 2;
1311         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1312                 vtx_size++;
1313         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1314                 vtx_size++;
1315         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1316                 vtx_size++;
1317         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1318                 vtx_size++;
1319         return vtx_size;
1320 }
1321
1322 static int r100_packet0_check(struct radeon_cs_parser *p,
1323                               struct radeon_cs_packet *pkt,
1324                               unsigned idx, unsigned reg)
1325 {
1326         struct radeon_cs_reloc *reloc;
1327         struct r100_cs_track *track;
1328         volatile uint32_t *ib;
1329         uint32_t tmp;
1330         int r;
1331         int i, face;
1332         u32 tile_flags = 0;
1333         u32 idx_value;
1334
1335         ib = p->ib->ptr;
1336         track = (struct r100_cs_track *)p->track;
1337
1338         idx_value = radeon_get_ib_value(p, idx);
1339
1340         switch (reg) {
1341         case RADEON_CRTC_GUI_TRIG_VLINE:
1342                 r = r100_cs_packet_parse_vline(p);
1343                 if (r) {
1344                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1345                                   idx, reg);
1346                         r100_cs_dump_packet(p, pkt);
1347                         return r;
1348                 }
1349                 break;
1350                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1351                  * range access */
1352         case RADEON_DST_PITCH_OFFSET:
1353         case RADEON_SRC_PITCH_OFFSET:
1354                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1355                 if (r)
1356                         return r;
1357                 break;
1358         case RADEON_RB3D_DEPTHOFFSET:
1359                 r = r100_cs_packet_next_reloc(p, &reloc);
1360                 if (r) {
1361                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1362                                   idx, reg);
1363                         r100_cs_dump_packet(p, pkt);
1364                         return r;
1365                 }
1366                 track->zb.robj = reloc->robj;
1367                 track->zb.offset = idx_value;
1368                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1369                 break;
1370         case RADEON_RB3D_COLOROFFSET:
1371                 r = r100_cs_packet_next_reloc(p, &reloc);
1372                 if (r) {
1373                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1374                                   idx, reg);
1375                         r100_cs_dump_packet(p, pkt);
1376                         return r;
1377                 }
1378                 track->cb[0].robj = reloc->robj;
1379                 track->cb[0].offset = idx_value;
1380                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1381                 break;
1382         case RADEON_PP_TXOFFSET_0:
1383         case RADEON_PP_TXOFFSET_1:
1384         case RADEON_PP_TXOFFSET_2:
1385                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1386                 r = r100_cs_packet_next_reloc(p, &reloc);
1387                 if (r) {
1388                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1389                                   idx, reg);
1390                         r100_cs_dump_packet(p, pkt);
1391                         return r;
1392                 }
1393                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1394                 track->textures[i].robj = reloc->robj;
1395                 break;
1396         case RADEON_PP_CUBIC_OFFSET_T0_0:
1397         case RADEON_PP_CUBIC_OFFSET_T0_1:
1398         case RADEON_PP_CUBIC_OFFSET_T0_2:
1399         case RADEON_PP_CUBIC_OFFSET_T0_3:
1400         case RADEON_PP_CUBIC_OFFSET_T0_4:
1401                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1402                 r = r100_cs_packet_next_reloc(p, &reloc);
1403                 if (r) {
1404                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1405                                   idx, reg);
1406                         r100_cs_dump_packet(p, pkt);
1407                         return r;
1408                 }
1409                 track->textures[0].cube_info[i].offset = idx_value;
1410                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1411                 track->textures[0].cube_info[i].robj = reloc->robj;
1412                 break;
1413         case RADEON_PP_CUBIC_OFFSET_T1_0:
1414         case RADEON_PP_CUBIC_OFFSET_T1_1:
1415         case RADEON_PP_CUBIC_OFFSET_T1_2:
1416         case RADEON_PP_CUBIC_OFFSET_T1_3:
1417         case RADEON_PP_CUBIC_OFFSET_T1_4:
1418                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1419                 r = r100_cs_packet_next_reloc(p, &reloc);
1420                 if (r) {
1421                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1422                                   idx, reg);
1423                         r100_cs_dump_packet(p, pkt);
1424                         return r;
1425                 }
1426                 track->textures[1].cube_info[i].offset = idx_value;
1427                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1428                 track->textures[1].cube_info[i].robj = reloc->robj;
1429                 break;
1430         case RADEON_PP_CUBIC_OFFSET_T2_0:
1431         case RADEON_PP_CUBIC_OFFSET_T2_1:
1432         case RADEON_PP_CUBIC_OFFSET_T2_2:
1433         case RADEON_PP_CUBIC_OFFSET_T2_3:
1434         case RADEON_PP_CUBIC_OFFSET_T2_4:
1435                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1436                 r = r100_cs_packet_next_reloc(p, &reloc);
1437                 if (r) {
1438                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1439                                   idx, reg);
1440                         r100_cs_dump_packet(p, pkt);
1441                         return r;
1442                 }
1443                 track->textures[2].cube_info[i].offset = idx_value;
1444                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1445                 track->textures[2].cube_info[i].robj = reloc->robj;
1446                 break;
1447         case RADEON_RE_WIDTH_HEIGHT:
1448                 track->maxy = ((idx_value >> 16) & 0x7FF);
1449                 break;
1450         case RADEON_RB3D_COLORPITCH:
1451                 r = r100_cs_packet_next_reloc(p, &reloc);
1452                 if (r) {
1453                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1454                                   idx, reg);
1455                         r100_cs_dump_packet(p, pkt);
1456                         return r;
1457                 }
1458
1459                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1460                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1461                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1462                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1463
1464                 tmp = idx_value & ~(0x7 << 16);
1465                 tmp |= tile_flags;
1466                 ib[idx] = tmp;
1467
1468                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1469                 break;
1470         case RADEON_RB3D_DEPTHPITCH:
1471                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1472                 break;
1473         case RADEON_RB3D_CNTL:
1474                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1475                 case 7:
1476                 case 8:
1477                 case 9:
1478                 case 11:
1479                 case 12:
1480                         track->cb[0].cpp = 1;
1481                         break;
1482                 case 3:
1483                 case 4:
1484                 case 15:
1485                         track->cb[0].cpp = 2;
1486                         break;
1487                 case 6:
1488                         track->cb[0].cpp = 4;
1489                         break;
1490                 default:
1491                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1492                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1493                         return -EINVAL;
1494                 }
1495                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1496                 break;
1497         case RADEON_RB3D_ZSTENCILCNTL:
1498                 switch (idx_value & 0xf) {
1499                 case 0:
1500                         track->zb.cpp = 2;
1501                         break;
1502                 case 2:
1503                 case 3:
1504                 case 4:
1505                 case 5:
1506                 case 9:
1507                 case 11:
1508                         track->zb.cpp = 4;
1509                         break;
1510                 default:
1511                         break;
1512                 }
1513                 break;
1514         case RADEON_RB3D_ZPASS_ADDR:
1515                 r = r100_cs_packet_next_reloc(p, &reloc);
1516                 if (r) {
1517                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1518                                   idx, reg);
1519                         r100_cs_dump_packet(p, pkt);
1520                         return r;
1521                 }
1522                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1523                 break;
1524         case RADEON_PP_CNTL:
1525                 {
1526                         uint32_t temp = idx_value >> 4;
1527                         for (i = 0; i < track->num_texture; i++)
1528                                 track->textures[i].enabled = !!(temp & (1 << i));
1529                 }
1530                 break;
1531         case RADEON_SE_VF_CNTL:
1532                 track->vap_vf_cntl = idx_value;
1533                 break;
1534         case RADEON_SE_VTX_FMT:
1535                 track->vtx_size = r100_get_vtx_size(idx_value);
1536                 break;
1537         case RADEON_PP_TEX_SIZE_0:
1538         case RADEON_PP_TEX_SIZE_1:
1539         case RADEON_PP_TEX_SIZE_2:
1540                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1541                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1542                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1543                 break;
1544         case RADEON_PP_TEX_PITCH_0:
1545         case RADEON_PP_TEX_PITCH_1:
1546         case RADEON_PP_TEX_PITCH_2:
1547                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1548                 track->textures[i].pitch = idx_value + 32;
1549                 break;
1550         case RADEON_PP_TXFILTER_0:
1551         case RADEON_PP_TXFILTER_1:
1552         case RADEON_PP_TXFILTER_2:
1553                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1554                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1555                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1556                 tmp = (idx_value >> 23) & 0x7;
1557                 if (tmp == 2 || tmp == 6)
1558                         track->textures[i].roundup_w = false;
1559                 tmp = (idx_value >> 27) & 0x7;
1560                 if (tmp == 2 || tmp == 6)
1561                         track->textures[i].roundup_h = false;
1562                 break;
1563         case RADEON_PP_TXFORMAT_0:
1564         case RADEON_PP_TXFORMAT_1:
1565         case RADEON_PP_TXFORMAT_2:
1566                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1567                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1568                         track->textures[i].use_pitch = 1;
1569                 } else {
1570                         track->textures[i].use_pitch = 0;
1571                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1572                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1573                 }
1574                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1575                         track->textures[i].tex_coord_type = 2;
1576                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1577                 case RADEON_TXFORMAT_I8:
1578                 case RADEON_TXFORMAT_RGB332:
1579                 case RADEON_TXFORMAT_Y8:
1580                         track->textures[i].cpp = 1;
1581                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1582                         break;
1583                 case RADEON_TXFORMAT_AI88:
1584                 case RADEON_TXFORMAT_ARGB1555:
1585                 case RADEON_TXFORMAT_RGB565:
1586                 case RADEON_TXFORMAT_ARGB4444:
1587                 case RADEON_TXFORMAT_VYUY422:
1588                 case RADEON_TXFORMAT_YVYU422:
1589                 case RADEON_TXFORMAT_SHADOW16:
1590                 case RADEON_TXFORMAT_LDUDV655:
1591                 case RADEON_TXFORMAT_DUDV88:
1592                         track->textures[i].cpp = 2;
1593                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1594                         break;
1595                 case RADEON_TXFORMAT_ARGB8888:
1596                 case RADEON_TXFORMAT_RGBA8888:
1597                 case RADEON_TXFORMAT_SHADOW32:
1598                 case RADEON_TXFORMAT_LDUDUV8888:
1599                         track->textures[i].cpp = 4;
1600                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1601                         break;
1602                 case RADEON_TXFORMAT_DXT1:
1603                         track->textures[i].cpp = 1;
1604                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1605                         break;
1606                 case RADEON_TXFORMAT_DXT23:
1607                 case RADEON_TXFORMAT_DXT45:
1608                         track->textures[i].cpp = 1;
1609                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1610                         break;
1611                 }
1612                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1613                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1614                 break;
1615         case RADEON_PP_CUBIC_FACES_0:
1616         case RADEON_PP_CUBIC_FACES_1:
1617         case RADEON_PP_CUBIC_FACES_2:
1618                 tmp = idx_value;
1619                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1620                 for (face = 0; face < 4; face++) {
1621                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1622                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1623                 }
1624                 break;
1625         default:
1626                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1627                        reg, idx);
1628                 return -EINVAL;
1629         }
1630         return 0;
1631 }
1632
1633 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1634                                          struct radeon_cs_packet *pkt,
1635                                          struct radeon_bo *robj)
1636 {
1637         unsigned idx;
1638         u32 value;
1639         idx = pkt->idx + 1;
1640         value = radeon_get_ib_value(p, idx + 2);
1641         if ((value + 1) > radeon_bo_size(robj)) {
1642                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1643                           "(need %u have %lu) !\n",
1644                           value + 1,
1645                           radeon_bo_size(robj));
1646                 return -EINVAL;
1647         }
1648         return 0;
1649 }
1650
1651 static int r100_packet3_check(struct radeon_cs_parser *p,
1652                               struct radeon_cs_packet *pkt)
1653 {
1654         struct radeon_cs_reloc *reloc;
1655         struct r100_cs_track *track;
1656         unsigned idx;
1657         volatile uint32_t *ib;
1658         int r;
1659
1660         ib = p->ib->ptr;
1661         idx = pkt->idx + 1;
1662         track = (struct r100_cs_track *)p->track;
1663         switch (pkt->opcode) {
1664         case PACKET3_3D_LOAD_VBPNTR:
1665                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1666                 if (r)
1667                         return r;
1668                 break;
1669         case PACKET3_INDX_BUFFER:
1670                 r = r100_cs_packet_next_reloc(p, &reloc);
1671                 if (r) {
1672                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1673                         r100_cs_dump_packet(p, pkt);
1674                         return r;
1675                 }
1676                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1677                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1678                 if (r) {
1679                         return r;
1680                 }
1681                 break;
1682         case 0x23:
1683                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1684                 r = r100_cs_packet_next_reloc(p, &reloc);
1685                 if (r) {
1686                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1687                         r100_cs_dump_packet(p, pkt);
1688                         return r;
1689                 }
1690                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1691                 track->num_arrays = 1;
1692                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1693
1694                 track->arrays[0].robj = reloc->robj;
1695                 track->arrays[0].esize = track->vtx_size;
1696
1697                 track->max_indx = radeon_get_ib_value(p, idx+1);
1698
1699                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1700                 track->immd_dwords = pkt->count - 1;
1701                 r = r100_cs_track_check(p->rdev, track);
1702                 if (r)
1703                         return r;
1704                 break;
1705         case PACKET3_3D_DRAW_IMMD:
1706                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1707                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1708                         return -EINVAL;
1709                 }
1710                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1711                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1712                 track->immd_dwords = pkt->count - 1;
1713                 r = r100_cs_track_check(p->rdev, track);
1714                 if (r)
1715                         return r;
1716                 break;
1717                 /* triggers drawing using in-packet vertex data */
1718         case PACKET3_3D_DRAW_IMMD_2:
1719                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1720                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1721                         return -EINVAL;
1722                 }
1723                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1724                 track->immd_dwords = pkt->count;
1725                 r = r100_cs_track_check(p->rdev, track);
1726                 if (r)
1727                         return r;
1728                 break;
1729                 /* triggers drawing using in-packet vertex data */
1730         case PACKET3_3D_DRAW_VBUF_2:
1731                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1732                 r = r100_cs_track_check(p->rdev, track);
1733                 if (r)
1734                         return r;
1735                 break;
1736                 /* triggers drawing of vertex buffers setup elsewhere */
1737         case PACKET3_3D_DRAW_INDX_2:
1738                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1739                 r = r100_cs_track_check(p->rdev, track);
1740                 if (r)
1741                         return r;
1742                 break;
1743                 /* triggers drawing using indices to vertex buffer */
1744         case PACKET3_3D_DRAW_VBUF:
1745                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1746                 r = r100_cs_track_check(p->rdev, track);
1747                 if (r)
1748                         return r;
1749                 break;
1750                 /* triggers drawing of vertex buffers setup elsewhere */
1751         case PACKET3_3D_DRAW_INDX:
1752                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1753                 r = r100_cs_track_check(p->rdev, track);
1754                 if (r)
1755                         return r;
1756                 break;
1757                 /* triggers drawing using indices to vertex buffer */
1758         case PACKET3_3D_CLEAR_HIZ:
1759         case PACKET3_3D_CLEAR_ZMASK:
1760                 if (p->rdev->hyperz_filp != p->filp)
1761                         return -EINVAL;
1762                 break;
1763         case PACKET3_NOP:
1764                 break;
1765         default:
1766                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1767                 return -EINVAL;
1768         }
1769         return 0;
1770 }
1771
1772 int r100_cs_parse(struct radeon_cs_parser *p)
1773 {
1774         struct radeon_cs_packet pkt;
1775         struct r100_cs_track *track;
1776         int r;
1777
1778         track = kzalloc(sizeof(*track), GFP_KERNEL);
1779         r100_cs_track_clear(p->rdev, track);
1780         p->track = track;
1781         do {
1782                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1783                 if (r) {
1784                         return r;
1785                 }
1786                 p->idx += pkt.count + 2;
1787                 switch (pkt.type) {
1788                         case PACKET_TYPE0:
1789                                 if (p->rdev->family >= CHIP_R200)
1790                                         r = r100_cs_parse_packet0(p, &pkt,
1791                                                                   p->rdev->config.r100.reg_safe_bm,
1792                                                                   p->rdev->config.r100.reg_safe_bm_size,
1793                                                                   &r200_packet0_check);
1794                                 else
1795                                         r = r100_cs_parse_packet0(p, &pkt,
1796                                                                   p->rdev->config.r100.reg_safe_bm,
1797                                                                   p->rdev->config.r100.reg_safe_bm_size,
1798                                                                   &r100_packet0_check);
1799                                 break;
1800                         case PACKET_TYPE2:
1801                                 break;
1802                         case PACKET_TYPE3:
1803                                 r = r100_packet3_check(p, &pkt);
1804                                 break;
1805                         default:
1806                                 DRM_ERROR("Unknown packet type %d !\n",
1807                                           pkt.type);
1808                                 return -EINVAL;
1809                 }
1810                 if (r) {
1811                         return r;
1812                 }
1813         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1814         return 0;
1815 }
1816
1817
1818 /*
1819  * Global GPU functions
1820  */
1821 void r100_errata(struct radeon_device *rdev)
1822 {
1823         rdev->pll_errata = 0;
1824
1825         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1826                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1827         }
1828
1829         if (rdev->family == CHIP_RV100 ||
1830             rdev->family == CHIP_RS100 ||
1831             rdev->family == CHIP_RS200) {
1832                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1833         }
1834 }
1835
1836 /* Wait for vertical sync on primary CRTC */
1837 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1838 {
1839         uint32_t crtc_gen_cntl, tmp;
1840         int i;
1841
1842         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1843         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1844             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1845                 return;
1846         }
1847         /* Clear the CRTC_VBLANK_SAVE bit */
1848         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1849         for (i = 0; i < rdev->usec_timeout; i++) {
1850                 tmp = RREG32(RADEON_CRTC_STATUS);
1851                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1852                         return;
1853                 }
1854                 DRM_UDELAY(1);
1855         }
1856 }
1857
1858 /* Wait for vertical sync on secondary CRTC */
1859 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1860 {
1861         uint32_t crtc2_gen_cntl, tmp;
1862         int i;
1863
1864         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1865         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1866             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1867                 return;
1868
1869         /* Clear the CRTC_VBLANK_SAVE bit */
1870         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1871         for (i = 0; i < rdev->usec_timeout; i++) {
1872                 tmp = RREG32(RADEON_CRTC2_STATUS);
1873                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1874                         return;
1875                 }
1876                 DRM_UDELAY(1);
1877         }
1878 }
1879
1880 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1881 {
1882         unsigned i;
1883         uint32_t tmp;
1884
1885         for (i = 0; i < rdev->usec_timeout; i++) {
1886                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1887                 if (tmp >= n) {
1888                         return 0;
1889                 }
1890                 DRM_UDELAY(1);
1891         }
1892         return -1;
1893 }
1894
1895 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1896 {
1897         unsigned i;
1898         uint32_t tmp;
1899
1900         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1901                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1902                        " Bad things might happen.\n");
1903         }
1904         for (i = 0; i < rdev->usec_timeout; i++) {
1905                 tmp = RREG32(RADEON_RBBM_STATUS);
1906                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1907                         return 0;
1908                 }
1909                 DRM_UDELAY(1);
1910         }
1911         return -1;
1912 }
1913
1914 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1915 {
1916         unsigned i;
1917         uint32_t tmp;
1918
1919         for (i = 0; i < rdev->usec_timeout; i++) {
1920                 /* read MC_STATUS */
1921                 tmp = RREG32(RADEON_MC_STATUS);
1922                 if (tmp & RADEON_MC_IDLE) {
1923                         return 0;
1924                 }
1925                 DRM_UDELAY(1);
1926         }
1927         return -1;
1928 }
1929
1930 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1931 {
1932         lockup->last_cp_rptr = cp->rptr;
1933         lockup->last_jiffies = jiffies;
1934 }
1935
1936 /**
1937  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1938  * @rdev:       radeon device structure
1939  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
1940  * @cp:         radeon_cp structure holding CP information
1941  *
1942  * We don't need to initialize the lockup tracking information as we will either
1943  * have CP rptr to a different value of jiffies wrap around which will force
1944  * initialization of the lockup tracking informations.
1945  *
1946  * A possible false positivie is if we get call after while and last_cp_rptr ==
1947  * the current CP rptr, even if it's unlikely it might happen. To avoid this
1948  * if the elapsed time since last call is bigger than 2 second than we return
1949  * false and update the tracking information. Due to this the caller must call
1950  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
1951  * the fencing code should be cautious about that.
1952  *
1953  * Caller should write to the ring to force CP to do something so we don't get
1954  * false positive when CP is just gived nothing to do.
1955  *
1956  **/
1957 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1958 {
1959         unsigned long cjiffies, elapsed;
1960
1961         cjiffies = jiffies;
1962         if (!time_after(cjiffies, lockup->last_jiffies)) {
1963                 /* likely a wrap around */
1964                 lockup->last_cp_rptr = cp->rptr;
1965                 lockup->last_jiffies = jiffies;
1966                 return false;
1967         }
1968         if (cp->rptr != lockup->last_cp_rptr) {
1969                 /* CP is still working no lockup */
1970                 lockup->last_cp_rptr = cp->rptr;
1971                 lockup->last_jiffies = jiffies;
1972                 return false;
1973         }
1974         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
1975         if (elapsed >= 10000) {
1976                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
1977                 return true;
1978         }
1979         /* give a chance to the GPU ... */
1980         return false;
1981 }
1982
1983 bool r100_gpu_is_lockup(struct radeon_device *rdev)
1984 {
1985         u32 rbbm_status;
1986         int r;
1987
1988         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
1989         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
1990                 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
1991                 return false;
1992         }
1993         /* force CP activities */
1994         r = radeon_ring_lock(rdev, 2);
1995         if (!r) {
1996                 /* PACKET2 NOP */
1997                 radeon_ring_write(rdev, 0x80000000);
1998                 radeon_ring_write(rdev, 0x80000000);
1999                 radeon_ring_unlock_commit(rdev);
2000         }
2001         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2002         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2003 }
2004
2005 void r100_bm_disable(struct radeon_device *rdev)
2006 {
2007         u32 tmp;
2008
2009         /* disable bus mastering */
2010         tmp = RREG32(R_000030_BUS_CNTL);
2011         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2012         mdelay(1);
2013         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2014         mdelay(1);
2015         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2016         tmp = RREG32(RADEON_BUS_CNTL);
2017         mdelay(1);
2018         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2019         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2020         mdelay(1);
2021 }
2022
2023 int r100_asic_reset(struct radeon_device *rdev)
2024 {
2025         struct r100_mc_save save;
2026         u32 status, tmp;
2027
2028         r100_mc_stop(rdev, &save);
2029         status = RREG32(R_000E40_RBBM_STATUS);
2030         if (!G_000E40_GUI_ACTIVE(status)) {
2031                 return 0;
2032         }
2033         status = RREG32(R_000E40_RBBM_STATUS);
2034         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2035         /* stop CP */
2036         WREG32(RADEON_CP_CSQ_CNTL, 0);
2037         tmp = RREG32(RADEON_CP_RB_CNTL);
2038         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2039         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2040         WREG32(RADEON_CP_RB_WPTR, 0);
2041         WREG32(RADEON_CP_RB_CNTL, tmp);
2042         /* save PCI state */
2043         pci_save_state(rdev->pdev);
2044         /* disable bus mastering */
2045         r100_bm_disable(rdev);
2046         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2047                                         S_0000F0_SOFT_RESET_RE(1) |
2048                                         S_0000F0_SOFT_RESET_PP(1) |
2049                                         S_0000F0_SOFT_RESET_RB(1));
2050         RREG32(R_0000F0_RBBM_SOFT_RESET);
2051         mdelay(500);
2052         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2053         mdelay(1);
2054         status = RREG32(R_000E40_RBBM_STATUS);
2055         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2056         /* reset CP */
2057         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2058         RREG32(R_0000F0_RBBM_SOFT_RESET);
2059         mdelay(500);
2060         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2061         mdelay(1);
2062         status = RREG32(R_000E40_RBBM_STATUS);
2063         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2064         /* restore PCI & busmastering */
2065         pci_restore_state(rdev->pdev);
2066         r100_enable_bm(rdev);
2067         /* Check if GPU is idle */
2068         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2069                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2070                 dev_err(rdev->dev, "failed to reset GPU\n");
2071                 rdev->gpu_lockup = true;
2072                 return -1;
2073         }
2074         r100_mc_resume(rdev, &save);
2075         dev_info(rdev->dev, "GPU reset succeed\n");
2076         return 0;
2077 }
2078
2079 void r100_set_common_regs(struct radeon_device *rdev)
2080 {
2081         struct drm_device *dev = rdev->ddev;
2082         bool force_dac2 = false;
2083         u32 tmp;
2084
2085         /* set these so they don't interfere with anything */
2086         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2087         WREG32(RADEON_SUBPIC_CNTL, 0);
2088         WREG32(RADEON_VIPH_CONTROL, 0);
2089         WREG32(RADEON_I2C_CNTL_1, 0);
2090         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2091         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2092         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2093
2094         /* always set up dac2 on rn50 and some rv100 as lots
2095          * of servers seem to wire it up to a VGA port but
2096          * don't report it in the bios connector
2097          * table.
2098          */
2099         switch (dev->pdev->device) {
2100                 /* RN50 */
2101         case 0x515e:
2102         case 0x5969:
2103                 force_dac2 = true;
2104                 break;
2105                 /* RV100*/
2106         case 0x5159:
2107         case 0x515a:
2108                 /* DELL triple head servers */
2109                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2110                     ((dev->pdev->subsystem_device == 0x016c) ||
2111                      (dev->pdev->subsystem_device == 0x016d) ||
2112                      (dev->pdev->subsystem_device == 0x016e) ||
2113                      (dev->pdev->subsystem_device == 0x016f) ||
2114                      (dev->pdev->subsystem_device == 0x0170) ||
2115                      (dev->pdev->subsystem_device == 0x017d) ||
2116                      (dev->pdev->subsystem_device == 0x017e) ||
2117                      (dev->pdev->subsystem_device == 0x0183) ||
2118                      (dev->pdev->subsystem_device == 0x018a) ||
2119                      (dev->pdev->subsystem_device == 0x019a)))
2120                         force_dac2 = true;
2121                 break;
2122         }
2123
2124         if (force_dac2) {
2125                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2126                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2127                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2128
2129                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2130                    enable it, even it's detected.
2131                 */
2132
2133                 /* force it to crtc0 */
2134                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2135                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2136                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2137
2138                 /* set up the TV DAC */
2139                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2140                                  RADEON_TV_DAC_STD_MASK |
2141                                  RADEON_TV_DAC_RDACPD |
2142                                  RADEON_TV_DAC_GDACPD |
2143                                  RADEON_TV_DAC_BDACPD |
2144                                  RADEON_TV_DAC_BGADJ_MASK |
2145                                  RADEON_TV_DAC_DACADJ_MASK);
2146                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2147                                 RADEON_TV_DAC_NHOLD |
2148                                 RADEON_TV_DAC_STD_PS2 |
2149                                 (0x58 << 16));
2150
2151                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2152                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2153                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2154         }
2155
2156         /* switch PM block to ACPI mode */
2157         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2158         tmp &= ~RADEON_PM_MODE_SEL;
2159         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2160
2161 }
2162
2163 /*
2164  * VRAM info
2165  */
2166 static void r100_vram_get_type(struct radeon_device *rdev)
2167 {
2168         uint32_t tmp;
2169
2170         rdev->mc.vram_is_ddr = false;
2171         if (rdev->flags & RADEON_IS_IGP)
2172                 rdev->mc.vram_is_ddr = true;
2173         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2174                 rdev->mc.vram_is_ddr = true;
2175         if ((rdev->family == CHIP_RV100) ||
2176             (rdev->family == CHIP_RS100) ||
2177             (rdev->family == CHIP_RS200)) {
2178                 tmp = RREG32(RADEON_MEM_CNTL);
2179                 if (tmp & RV100_HALF_MODE) {
2180                         rdev->mc.vram_width = 32;
2181                 } else {
2182                         rdev->mc.vram_width = 64;
2183                 }
2184                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2185                         rdev->mc.vram_width /= 4;
2186                         rdev->mc.vram_is_ddr = true;
2187                 }
2188         } else if (rdev->family <= CHIP_RV280) {
2189                 tmp = RREG32(RADEON_MEM_CNTL);
2190                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2191                         rdev->mc.vram_width = 128;
2192                 } else {
2193                         rdev->mc.vram_width = 64;
2194                 }
2195         } else {
2196                 /* newer IGPs */
2197                 rdev->mc.vram_width = 128;
2198         }
2199 }
2200
2201 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2202 {
2203         u32 aper_size;
2204         u8 byte;
2205
2206         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2207
2208         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2209          * that is has the 2nd generation multifunction PCI interface
2210          */
2211         if (rdev->family == CHIP_RV280 ||
2212             rdev->family >= CHIP_RV350) {
2213                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2214                        ~RADEON_HDP_APER_CNTL);
2215                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2216                 return aper_size * 2;
2217         }
2218
2219         /* Older cards have all sorts of funny issues to deal with. First
2220          * check if it's a multifunction card by reading the PCI config
2221          * header type... Limit those to one aperture size
2222          */
2223         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2224         if (byte & 0x80) {
2225                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2226                 DRM_INFO("Limiting VRAM to one aperture\n");
2227                 return aper_size;
2228         }
2229
2230         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2231          * have set it up. We don't write this as it's broken on some ASICs but
2232          * we expect the BIOS to have done the right thing (might be too optimistic...)
2233          */
2234         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2235                 return aper_size * 2;
2236         return aper_size;
2237 }
2238
2239 void r100_vram_init_sizes(struct radeon_device *rdev)
2240 {
2241         u64 config_aper_size;
2242
2243         /* work out accessible VRAM */
2244         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2245         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2246         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2247         /* FIXME we don't use the second aperture yet when we could use it */
2248         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2249                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2250         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2251         if (rdev->flags & RADEON_IS_IGP) {
2252                 uint32_t tom;
2253                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2254                 tom = RREG32(RADEON_NB_TOM);
2255                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2256                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2257                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2258         } else {
2259                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2260                 /* Some production boards of m6 will report 0
2261                  * if it's 8 MB
2262                  */
2263                 if (rdev->mc.real_vram_size == 0) {
2264                         rdev->mc.real_vram_size = 8192 * 1024;
2265                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2266                 }
2267                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2268                  * Novell bug 204882 + along with lots of ubuntu ones
2269                  */
2270                 if (config_aper_size > rdev->mc.real_vram_size)
2271                         rdev->mc.mc_vram_size = config_aper_size;
2272                 else
2273                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2274         }
2275 }
2276
2277 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2278 {
2279         uint32_t temp;
2280
2281         temp = RREG32(RADEON_CONFIG_CNTL);
2282         if (state == false) {
2283                 temp &= ~(1<<8);
2284                 temp |= (1<<9);
2285         } else {
2286                 temp &= ~(1<<9);
2287         }
2288         WREG32(RADEON_CONFIG_CNTL, temp);
2289 }
2290
2291 void r100_mc_init(struct radeon_device *rdev)
2292 {
2293         u64 base;
2294
2295         r100_vram_get_type(rdev);
2296         r100_vram_init_sizes(rdev);
2297         base = rdev->mc.aper_base;
2298         if (rdev->flags & RADEON_IS_IGP)
2299                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2300         radeon_vram_location(rdev, &rdev->mc, base);
2301         rdev->mc.gtt_base_align = 0;
2302         if (!(rdev->flags & RADEON_IS_AGP))
2303                 radeon_gtt_location(rdev, &rdev->mc);
2304         radeon_update_bandwidth_info(rdev);
2305 }
2306
2307
2308 /*
2309  * Indirect registers accessor
2310  */
2311 void r100_pll_errata_after_index(struct radeon_device *rdev)
2312 {
2313         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2314                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2315                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2316         }
2317 }
2318
2319 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2320 {
2321         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2322          * or the chip could hang on a subsequent access
2323          */
2324         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2325                 udelay(5000);
2326         }
2327
2328         /* This function is required to workaround a hardware bug in some (all?)
2329          * revisions of the R300.  This workaround should be called after every
2330          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2331          * may not be correct.
2332          */
2333         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2334                 uint32_t save, tmp;
2335
2336                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2337                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2338                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2339                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2340                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2341         }
2342 }
2343
2344 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2345 {
2346         uint32_t data;
2347
2348         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2349         r100_pll_errata_after_index(rdev);
2350         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2351         r100_pll_errata_after_data(rdev);
2352         return data;
2353 }
2354
2355 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2356 {
2357         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2358         r100_pll_errata_after_index(rdev);
2359         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2360         r100_pll_errata_after_data(rdev);
2361 }
2362
2363 void r100_set_safe_registers(struct radeon_device *rdev)
2364 {
2365         if (ASIC_IS_RN50(rdev)) {
2366                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2367                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2368         } else if (rdev->family < CHIP_R200) {
2369                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2370                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2371         } else {
2372                 r200_set_safe_registers(rdev);
2373         }
2374 }
2375
2376 /*
2377  * Debugfs info
2378  */
2379 #if defined(CONFIG_DEBUG_FS)
2380 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2381 {
2382         struct drm_info_node *node = (struct drm_info_node *) m->private;
2383         struct drm_device *dev = node->minor->dev;
2384         struct radeon_device *rdev = dev->dev_private;
2385         uint32_t reg, value;
2386         unsigned i;
2387
2388         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2389         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2390         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2391         for (i = 0; i < 64; i++) {
2392                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2393                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2394                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2395                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2396                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2397         }
2398         return 0;
2399 }
2400
2401 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2402 {
2403         struct drm_info_node *node = (struct drm_info_node *) m->private;
2404         struct drm_device *dev = node->minor->dev;
2405         struct radeon_device *rdev = dev->dev_private;
2406         uint32_t rdp, wdp;
2407         unsigned count, i, j;
2408
2409         radeon_ring_free_size(rdev);
2410         rdp = RREG32(RADEON_CP_RB_RPTR);
2411         wdp = RREG32(RADEON_CP_RB_WPTR);
2412         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2413         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2414         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2415         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2416         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2417         seq_printf(m, "%u dwords in ring\n", count);
2418         for (j = 0; j <= count; j++) {
2419                 i = (rdp + j) & rdev->cp.ptr_mask;
2420                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2421         }
2422         return 0;
2423 }
2424
2425
2426 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2427 {
2428         struct drm_info_node *node = (struct drm_info_node *) m->private;
2429         struct drm_device *dev = node->minor->dev;
2430         struct radeon_device *rdev = dev->dev_private;
2431         uint32_t csq_stat, csq2_stat, tmp;
2432         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2433         unsigned i;
2434
2435         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2436         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2437         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2438         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2439         r_rptr = (csq_stat >> 0) & 0x3ff;
2440         r_wptr = (csq_stat >> 10) & 0x3ff;
2441         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2442         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2443         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2444         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2445         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2446         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2447         seq_printf(m, "Ring rptr %u\n", r_rptr);
2448         seq_printf(m, "Ring wptr %u\n", r_wptr);
2449         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2450         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2451         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2452         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2453         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2454          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2455         seq_printf(m, "Ring fifo:\n");
2456         for (i = 0; i < 256; i++) {
2457                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2458                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2459                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2460         }
2461         seq_printf(m, "Indirect1 fifo:\n");
2462         for (i = 256; i <= 512; i++) {
2463                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2464                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2465                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2466         }
2467         seq_printf(m, "Indirect2 fifo:\n");
2468         for (i = 640; i < ib1_wptr; i++) {
2469                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2470                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2471                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2472         }
2473         return 0;
2474 }
2475
2476 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2477 {
2478         struct drm_info_node *node = (struct drm_info_node *) m->private;
2479         struct drm_device *dev = node->minor->dev;
2480         struct radeon_device *rdev = dev->dev_private;
2481         uint32_t tmp;
2482
2483         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2484         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2485         tmp = RREG32(RADEON_MC_FB_LOCATION);
2486         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2487         tmp = RREG32(RADEON_BUS_CNTL);
2488         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2489         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2490         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2491         tmp = RREG32(RADEON_AGP_BASE);
2492         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2493         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2494         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2495         tmp = RREG32(0x01D0);
2496         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2497         tmp = RREG32(RADEON_AIC_LO_ADDR);
2498         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2499         tmp = RREG32(RADEON_AIC_HI_ADDR);
2500         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2501         tmp = RREG32(0x01E4);
2502         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2503         return 0;
2504 }
2505
2506 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2507         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2508 };
2509
2510 static struct drm_info_list r100_debugfs_cp_list[] = {
2511         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2512         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2513 };
2514
2515 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2516         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2517 };
2518 #endif
2519
2520 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2521 {
2522 #if defined(CONFIG_DEBUG_FS)
2523         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2524 #else
2525         return 0;
2526 #endif
2527 }
2528
2529 int r100_debugfs_cp_init(struct radeon_device *rdev)
2530 {
2531 #if defined(CONFIG_DEBUG_FS)
2532         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2533 #else
2534         return 0;
2535 #endif
2536 }
2537
2538 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2539 {
2540 #if defined(CONFIG_DEBUG_FS)
2541         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2542 #else
2543         return 0;
2544 #endif
2545 }
2546
2547 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2548                          uint32_t tiling_flags, uint32_t pitch,
2549                          uint32_t offset, uint32_t obj_size)
2550 {
2551         int surf_index = reg * 16;
2552         int flags = 0;
2553
2554         if (rdev->family <= CHIP_RS200) {
2555                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2556                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2557                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2558                 if (tiling_flags & RADEON_TILING_MACRO)
2559                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2560         } else if (rdev->family <= CHIP_RV280) {
2561                 if (tiling_flags & (RADEON_TILING_MACRO))
2562                         flags |= R200_SURF_TILE_COLOR_MACRO;
2563                 if (tiling_flags & RADEON_TILING_MICRO)
2564                         flags |= R200_SURF_TILE_COLOR_MICRO;
2565         } else {
2566                 if (tiling_flags & RADEON_TILING_MACRO)
2567                         flags |= R300_SURF_TILE_MACRO;
2568                 if (tiling_flags & RADEON_TILING_MICRO)
2569                         flags |= R300_SURF_TILE_MICRO;
2570         }
2571
2572         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2573                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2574         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2575                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2576
2577         /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2578         if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2579                 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2580                         if (ASIC_IS_RN50(rdev))
2581                                 pitch /= 16;
2582         }
2583
2584         /* r100/r200 divide by 16 */
2585         if (rdev->family < CHIP_R300)
2586                 flags |= pitch / 16;
2587         else
2588                 flags |= pitch / 8;
2589
2590
2591         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2592         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2593         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2594         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2595         return 0;
2596 }
2597
2598 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2599 {
2600         int surf_index = reg * 16;
2601         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2602 }
2603
2604 void r100_bandwidth_update(struct radeon_device *rdev)
2605 {
2606         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2607         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2608         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2609         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2610         fixed20_12 memtcas_ff[8] = {
2611                 dfixed_init(1),
2612                 dfixed_init(2),
2613                 dfixed_init(3),
2614                 dfixed_init(0),
2615                 dfixed_init_half(1),
2616                 dfixed_init_half(2),
2617                 dfixed_init(0),
2618         };
2619         fixed20_12 memtcas_rs480_ff[8] = {
2620                 dfixed_init(0),
2621                 dfixed_init(1),
2622                 dfixed_init(2),
2623                 dfixed_init(3),
2624                 dfixed_init(0),
2625                 dfixed_init_half(1),
2626                 dfixed_init_half(2),
2627                 dfixed_init_half(3),
2628         };
2629         fixed20_12 memtcas2_ff[8] = {
2630                 dfixed_init(0),
2631                 dfixed_init(1),
2632                 dfixed_init(2),
2633                 dfixed_init(3),
2634                 dfixed_init(4),
2635                 dfixed_init(5),
2636                 dfixed_init(6),
2637                 dfixed_init(7),
2638         };
2639         fixed20_12 memtrbs[8] = {
2640                 dfixed_init(1),
2641                 dfixed_init_half(1),
2642                 dfixed_init(2),
2643                 dfixed_init_half(2),
2644                 dfixed_init(3),
2645                 dfixed_init_half(3),
2646                 dfixed_init(4),
2647                 dfixed_init_half(4)
2648         };
2649         fixed20_12 memtrbs_r4xx[8] = {
2650                 dfixed_init(4),
2651                 dfixed_init(5),
2652                 dfixed_init(6),
2653                 dfixed_init(7),
2654                 dfixed_init(8),
2655                 dfixed_init(9),
2656                 dfixed_init(10),
2657                 dfixed_init(11)
2658         };
2659         fixed20_12 min_mem_eff;
2660         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2661         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2662         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2663                 disp_drain_rate2, read_return_rate;
2664         fixed20_12 time_disp1_drop_priority;
2665         int c;
2666         int cur_size = 16;       /* in octawords */
2667         int critical_point = 0, critical_point2;
2668 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2669         int stop_req, max_stop_req;
2670         struct drm_display_mode *mode1 = NULL;
2671         struct drm_display_mode *mode2 = NULL;
2672         uint32_t pixel_bytes1 = 0;
2673         uint32_t pixel_bytes2 = 0;
2674
2675         radeon_update_display_priority(rdev);
2676
2677         if (rdev->mode_info.crtcs[0]->base.enabled) {
2678                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2679                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2680         }
2681         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2682                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2683                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2684                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2685                 }
2686         }
2687
2688         min_mem_eff.full = dfixed_const_8(0);
2689         /* get modes */
2690         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2691                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2692                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2693                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2694                 /* check crtc enables */
2695                 if (mode2)
2696                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2697                 if (mode1)
2698                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2699                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2700         }
2701
2702         /*
2703          * determine is there is enough bw for current mode
2704          */
2705         sclk_ff = rdev->pm.sclk;
2706         mclk_ff = rdev->pm.mclk;
2707
2708         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2709         temp_ff.full = dfixed_const(temp);
2710         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2711
2712         pix_clk.full = 0;
2713         pix_clk2.full = 0;
2714         peak_disp_bw.full = 0;
2715         if (mode1) {
2716                 temp_ff.full = dfixed_const(1000);
2717                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2718                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2719                 temp_ff.full = dfixed_const(pixel_bytes1);
2720                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2721         }
2722         if (mode2) {
2723                 temp_ff.full = dfixed_const(1000);
2724                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2725                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2726                 temp_ff.full = dfixed_const(pixel_bytes2);
2727                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2728         }
2729
2730         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2731         if (peak_disp_bw.full >= mem_bw.full) {
2732                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2733                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2734         }
2735
2736         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2737         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2738         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2739                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2740                 mem_trp  = ((temp & 0x3)) + 1;
2741                 mem_tras = ((temp & 0x70) >> 4) + 1;
2742         } else if (rdev->family == CHIP_R300 ||
2743                    rdev->family == CHIP_R350) { /* r300, r350 */
2744                 mem_trcd = (temp & 0x7) + 1;
2745                 mem_trp = ((temp >> 8) & 0x7) + 1;
2746                 mem_tras = ((temp >> 11) & 0xf) + 4;
2747         } else if (rdev->family == CHIP_RV350 ||
2748                    rdev->family <= CHIP_RV380) {
2749                 /* rv3x0 */
2750                 mem_trcd = (temp & 0x7) + 3;
2751                 mem_trp = ((temp >> 8) & 0x7) + 3;
2752                 mem_tras = ((temp >> 11) & 0xf) + 6;
2753         } else if (rdev->family == CHIP_R420 ||
2754                    rdev->family == CHIP_R423 ||
2755                    rdev->family == CHIP_RV410) {
2756                 /* r4xx */
2757                 mem_trcd = (temp & 0xf) + 3;
2758                 if (mem_trcd > 15)
2759                         mem_trcd = 15;
2760                 mem_trp = ((temp >> 8) & 0xf) + 3;
2761                 if (mem_trp > 15)
2762                         mem_trp = 15;
2763                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2764                 if (mem_tras > 31)
2765                         mem_tras = 31;
2766         } else { /* RV200, R200 */
2767                 mem_trcd = (temp & 0x7) + 1;
2768                 mem_trp = ((temp >> 8) & 0x7) + 1;
2769                 mem_tras = ((temp >> 12) & 0xf) + 4;
2770         }
2771         /* convert to FF */
2772         trcd_ff.full = dfixed_const(mem_trcd);
2773         trp_ff.full = dfixed_const(mem_trp);
2774         tras_ff.full = dfixed_const(mem_tras);
2775
2776         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2777         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2778         data = (temp & (7 << 20)) >> 20;
2779         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2780                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2781                         tcas_ff = memtcas_rs480_ff[data];
2782                 else
2783                         tcas_ff = memtcas_ff[data];
2784         } else
2785                 tcas_ff = memtcas2_ff[data];
2786
2787         if (rdev->family == CHIP_RS400 ||
2788             rdev->family == CHIP_RS480) {
2789                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2790                 data = (temp >> 23) & 0x7;
2791                 if (data < 5)
2792                         tcas_ff.full += dfixed_const(data);
2793         }
2794
2795         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2796                 /* on the R300, Tcas is included in Trbs.
2797                  */
2798                 temp = RREG32(RADEON_MEM_CNTL);
2799                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2800                 if (data == 1) {
2801                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2802                                 temp = RREG32(R300_MC_IND_INDEX);
2803                                 temp &= ~R300_MC_IND_ADDR_MASK;
2804                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2805                                 WREG32(R300_MC_IND_INDEX, temp);
2806                                 temp = RREG32(R300_MC_IND_DATA);
2807                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2808                         } else {
2809                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2810                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2811                         }
2812                 } else {
2813                         temp = RREG32(R300_MC_READ_CNTL_AB);
2814                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2815                 }
2816                 if (rdev->family == CHIP_RV410 ||
2817                     rdev->family == CHIP_R420 ||
2818                     rdev->family == CHIP_R423)
2819                         trbs_ff = memtrbs_r4xx[data];
2820                 else
2821                         trbs_ff = memtrbs[data];
2822                 tcas_ff.full += trbs_ff.full;
2823         }
2824
2825         sclk_eff_ff.full = sclk_ff.full;
2826
2827         if (rdev->flags & RADEON_IS_AGP) {
2828                 fixed20_12 agpmode_ff;
2829                 agpmode_ff.full = dfixed_const(radeon_agpmode);
2830                 temp_ff.full = dfixed_const_666(16);
2831                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2832         }
2833         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2834
2835         if (ASIC_IS_R300(rdev)) {
2836                 sclk_delay_ff.full = dfixed_const(250);
2837         } else {
2838                 if ((rdev->family == CHIP_RV100) ||
2839                     rdev->flags & RADEON_IS_IGP) {
2840                         if (rdev->mc.vram_is_ddr)
2841                                 sclk_delay_ff.full = dfixed_const(41);
2842                         else
2843                                 sclk_delay_ff.full = dfixed_const(33);
2844                 } else {
2845                         if (rdev->mc.vram_width == 128)
2846                                 sclk_delay_ff.full = dfixed_const(57);
2847                         else
2848                                 sclk_delay_ff.full = dfixed_const(41);
2849                 }
2850         }
2851
2852         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
2853
2854         if (rdev->mc.vram_is_ddr) {
2855                 if (rdev->mc.vram_width == 32) {
2856                         k1.full = dfixed_const(40);
2857                         c  = 3;
2858                 } else {
2859                         k1.full = dfixed_const(20);
2860                         c  = 1;
2861                 }
2862         } else {
2863                 k1.full = dfixed_const(40);
2864                 c  = 3;
2865         }
2866
2867         temp_ff.full = dfixed_const(2);
2868         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2869         temp_ff.full = dfixed_const(c);
2870         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2871         temp_ff.full = dfixed_const(4);
2872         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2873         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
2874         mc_latency_mclk.full += k1.full;
2875
2876         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2877         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
2878
2879         /*
2880           HW cursor time assuming worst case of full size colour cursor.
2881         */
2882         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2883         temp_ff.full += trcd_ff.full;
2884         if (temp_ff.full < tras_ff.full)
2885                 temp_ff.full = tras_ff.full;
2886         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
2887
2888         temp_ff.full = dfixed_const(cur_size);
2889         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
2890         /*
2891           Find the total latency for the display data.
2892         */
2893         disp_latency_overhead.full = dfixed_const(8);
2894         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
2895         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2896         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2897
2898         if (mc_latency_mclk.full > mc_latency_sclk.full)
2899                 disp_latency.full = mc_latency_mclk.full;
2900         else
2901                 disp_latency.full = mc_latency_sclk.full;
2902
2903         /* setup Max GRPH_STOP_REQ default value */
2904         if (ASIC_IS_RV100(rdev))
2905                 max_stop_req = 0x5c;
2906         else
2907                 max_stop_req = 0x7c;
2908
2909         if (mode1) {
2910                 /*  CRTC1
2911                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2912                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2913                 */
2914                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2915
2916                 if (stop_req > max_stop_req)
2917                         stop_req = max_stop_req;
2918
2919                 /*
2920                   Find the drain rate of the display buffer.
2921                 */
2922                 temp_ff.full = dfixed_const((16/pixel_bytes1));
2923                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
2924
2925                 /*
2926                   Find the critical point of the display buffer.
2927                 */
2928                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
2929                 crit_point_ff.full += dfixed_const_half(0);
2930
2931                 critical_point = dfixed_trunc(crit_point_ff);
2932
2933                 if (rdev->disp_priority == 2) {
2934                         critical_point = 0;
2935                 }
2936
2937                 /*
2938                   The critical point should never be above max_stop_req-4.  Setting
2939                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2940                 */
2941                 if (max_stop_req - critical_point < 4)
2942                         critical_point = 0;
2943
2944                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2945                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2946                         critical_point = 0x10;
2947                 }
2948
2949                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2950                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2951                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2952                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2953                 if ((rdev->family == CHIP_R350) &&
2954                     (stop_req > 0x15)) {
2955                         stop_req -= 0x10;
2956                 }
2957                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2958                 temp |= RADEON_GRPH_BUFFER_SIZE;
2959                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2960                           RADEON_GRPH_CRITICAL_AT_SOF |
2961                           RADEON_GRPH_STOP_CNTL);
2962                 /*
2963                   Write the result into the register.
2964                 */
2965                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2966                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2967
2968 #if 0
2969                 if ((rdev->family == CHIP_RS400) ||
2970                     (rdev->family == CHIP_RS480)) {
2971                         /* attempt to program RS400 disp regs correctly ??? */
2972                         temp = RREG32(RS400_DISP1_REG_CNTL);
2973                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2974                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
2975                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2976                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2977                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2978                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
2979                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2980                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2981                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2982                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2983                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2984                 }
2985 #endif
2986
2987                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
2988                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
2989                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2990         }
2991
2992         if (mode2) {
2993                 u32 grph2_cntl;
2994                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2995
2996                 if (stop_req > max_stop_req)
2997                         stop_req = max_stop_req;
2998
2999                 /*
3000                   Find the drain rate of the display buffer.
3001                 */
3002                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3003                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3004
3005                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3006                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3007                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3008                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3009                 if ((rdev->family == CHIP_R350) &&
3010                     (stop_req > 0x15)) {
3011                         stop_req -= 0x10;
3012                 }
3013                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3014                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3015                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3016                           RADEON_GRPH_CRITICAL_AT_SOF |
3017                           RADEON_GRPH_STOP_CNTL);
3018
3019                 if ((rdev->family == CHIP_RS100) ||
3020                     (rdev->family == CHIP_RS200))
3021                         critical_point2 = 0;
3022                 else {
3023                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3024                         temp_ff.full = dfixed_const(temp);
3025                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3026                         if (sclk_ff.full < temp_ff.full)
3027                                 temp_ff.full = sclk_ff.full;
3028
3029                         read_return_rate.full = temp_ff.full;
3030
3031                         if (mode1) {
3032                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3033                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3034                         } else {
3035                                 time_disp1_drop_priority.full = 0;
3036                         }
3037                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3038                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3039                         crit_point_ff.full += dfixed_const_half(0);
3040
3041                         critical_point2 = dfixed_trunc(crit_point_ff);
3042
3043                         if (rdev->disp_priority == 2) {
3044                                 critical_point2 = 0;
3045                         }
3046
3047                         if (max_stop_req - critical_point2 < 4)
3048                                 critical_point2 = 0;
3049
3050                 }
3051
3052                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3053                         /* some R300 cards have problem with this set to 0 */
3054                         critical_point2 = 0x10;
3055                 }
3056
3057                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3058                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3059
3060                 if ((rdev->family == CHIP_RS400) ||
3061                     (rdev->family == CHIP_RS480)) {
3062 #if 0
3063                         /* attempt to program RS400 disp2 regs correctly ??? */
3064                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3065                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3066                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3067                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3068                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3069                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3070                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3071                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3072                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3073                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3074                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3075                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3076 #endif
3077                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3078                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3079                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3080                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3081                 }
3082
3083                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3084                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3085         }
3086 }
3087
3088 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3089 {
3090         DRM_ERROR("pitch                      %d\n", t->pitch);
3091         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3092         DRM_ERROR("width                      %d\n", t->width);
3093         DRM_ERROR("width_11                   %d\n", t->width_11);
3094         DRM_ERROR("height                     %d\n", t->height);
3095         DRM_ERROR("height_11                  %d\n", t->height_11);
3096         DRM_ERROR("num levels                 %d\n", t->num_levels);
3097         DRM_ERROR("depth                      %d\n", t->txdepth);
3098         DRM_ERROR("bpp                        %d\n", t->cpp);
3099         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3100         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3101         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3102         DRM_ERROR("compress format            %d\n", t->compress_format);
3103 }
3104
3105 static int r100_track_compress_size(int compress_format, int w, int h)
3106 {
3107         int block_width, block_height, block_bytes;
3108         int wblocks, hblocks;
3109         int min_wblocks;
3110         int sz;
3111
3112         block_width = 4;
3113         block_height = 4;
3114
3115         switch (compress_format) {
3116         case R100_TRACK_COMP_DXT1:
3117                 block_bytes = 8;
3118                 min_wblocks = 4;
3119                 break;
3120         default:
3121         case R100_TRACK_COMP_DXT35:
3122                 block_bytes = 16;
3123                 min_wblocks = 2;
3124                 break;
3125         }
3126
3127         hblocks = (h + block_height - 1) / block_height;
3128         wblocks = (w + block_width - 1) / block_width;
3129         if (wblocks < min_wblocks)
3130                 wblocks = min_wblocks;
3131         sz = wblocks * hblocks * block_bytes;
3132         return sz;
3133 }
3134
3135 static int r100_cs_track_cube(struct radeon_device *rdev,
3136                               struct r100_cs_track *track, unsigned idx)
3137 {
3138         unsigned face, w, h;
3139         struct radeon_bo *cube_robj;
3140         unsigned long size;
3141         unsigned compress_format = track->textures[idx].compress_format;
3142
3143         for (face = 0; face < 5; face++) {
3144                 cube_robj = track->textures[idx].cube_info[face].robj;
3145                 w = track->textures[idx].cube_info[face].width;
3146                 h = track->textures[idx].cube_info[face].height;
3147
3148                 if (compress_format) {
3149                         size = r100_track_compress_size(compress_format, w, h);
3150                 } else
3151                         size = w * h;
3152                 size *= track->textures[idx].cpp;
3153
3154                 size += track->textures[idx].cube_info[face].offset;
3155
3156                 if (size > radeon_bo_size(cube_robj)) {
3157                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3158                                   size, radeon_bo_size(cube_robj));
3159                         r100_cs_track_texture_print(&track->textures[idx]);
3160                         return -1;
3161                 }
3162         }
3163         return 0;
3164 }
3165
3166 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3167                                        struct r100_cs_track *track)
3168 {
3169         struct radeon_bo *robj;
3170         unsigned long size;
3171         unsigned u, i, w, h, d;
3172         int ret;
3173
3174         for (u = 0; u < track->num_texture; u++) {
3175                 if (!track->textures[u].enabled)
3176                         continue;
3177                 robj = track->textures[u].robj;
3178                 if (robj == NULL) {
3179                         DRM_ERROR("No texture bound to unit %u\n", u);
3180                         return -EINVAL;
3181                 }
3182                 size = 0;
3183                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3184                         if (track->textures[u].use_pitch) {
3185                                 if (rdev->family < CHIP_R300)
3186                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3187                                 else
3188                                         w = track->textures[u].pitch / (1 << i);
3189                         } else {
3190                                 w = track->textures[u].width;
3191                                 if (rdev->family >= CHIP_RV515)
3192                                         w |= track->textures[u].width_11;
3193                                 w = w / (1 << i);
3194                                 if (track->textures[u].roundup_w)
3195                                         w = roundup_pow_of_two(w);
3196                         }
3197                         h = track->textures[u].height;
3198                         if (rdev->family >= CHIP_RV515)
3199                                 h |= track->textures[u].height_11;
3200                         h = h / (1 << i);
3201                         if (track->textures[u].roundup_h)
3202                                 h = roundup_pow_of_two(h);
3203                         if (track->textures[u].tex_coord_type == 1) {
3204                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3205                                 if (!d)
3206                                         d = 1;
3207                         } else {
3208                                 d = 1;
3209                         }
3210                         if (track->textures[u].compress_format) {
3211
3212                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3213                                 /* compressed textures are block based */
3214                         } else
3215                                 size += w * h * d;
3216                 }
3217                 size *= track->textures[u].cpp;
3218
3219                 switch (track->textures[u].tex_coord_type) {
3220                 case 0:
3221                 case 1:
3222                         break;
3223                 case 2:
3224                         if (track->separate_cube) {
3225                                 ret = r100_cs_track_cube(rdev, track, u);
3226                                 if (ret)
3227                                         return ret;
3228                         } else
3229                                 size *= 6;
3230                         break;
3231                 default:
3232                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3233                                   "%u\n", track->textures[u].tex_coord_type, u);
3234                         return -EINVAL;
3235                 }
3236                 if (size > radeon_bo_size(robj)) {
3237                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3238                                   "%lu\n", u, size, radeon_bo_size(robj));
3239                         r100_cs_track_texture_print(&track->textures[u]);
3240                         return -EINVAL;
3241                 }
3242         }
3243         return 0;
3244 }
3245
3246 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3247 {
3248         unsigned i;
3249         unsigned long size;
3250         unsigned prim_walk;
3251         unsigned nverts;
3252         unsigned num_cb = track->num_cb;
3253
3254         if (!track->zb_cb_clear && !track->color_channel_mask &&
3255             !track->blend_read_enable)
3256                 num_cb = 0;
3257
3258         for (i = 0; i < num_cb; i++) {
3259                 if (track->cb[i].robj == NULL) {
3260                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3261                         return -EINVAL;
3262                 }
3263                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3264                 size += track->cb[i].offset;
3265                 if (size > radeon_bo_size(track->cb[i].robj)) {
3266                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3267                                   "(need %lu have %lu) !\n", i, size,
3268                                   radeon_bo_size(track->cb[i].robj));
3269                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3270                                   i, track->cb[i].pitch, track->cb[i].cpp,
3271                                   track->cb[i].offset, track->maxy);
3272                         return -EINVAL;
3273                 }
3274         }
3275         if (track->z_enabled) {
3276                 if (track->zb.robj == NULL) {
3277                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3278                         return -EINVAL;
3279                 }
3280                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3281                 size += track->zb.offset;
3282                 if (size > radeon_bo_size(track->zb.robj)) {
3283                         DRM_ERROR("[drm] Buffer too small for z buffer "
3284                                   "(need %lu have %lu) !\n", size,
3285                                   radeon_bo_size(track->zb.robj));
3286                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3287                                   track->zb.pitch, track->zb.cpp,
3288                                   track->zb.offset, track->maxy);
3289                         return -EINVAL;
3290                 }
3291         }
3292         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3293         if (track->vap_vf_cntl & (1 << 14)) {
3294                 nverts = track->vap_alt_nverts;
3295         } else {
3296                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3297         }
3298         switch (prim_walk) {
3299         case 1:
3300                 for (i = 0; i < track->num_arrays; i++) {
3301                         size = track->arrays[i].esize * track->max_indx * 4;
3302                         if (track->arrays[i].robj == NULL) {
3303                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3304                                           "bound\n", prim_walk, i);
3305                                 return -EINVAL;
3306                         }
3307                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3308                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3309                                         "need %lu dwords have %lu dwords\n",
3310                                         prim_walk, i, size >> 2,
3311                                         radeon_bo_size(track->arrays[i].robj)
3312                                         >> 2);
3313                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3314                                 return -EINVAL;
3315                         }
3316                 }
3317                 break;
3318         case 2:
3319                 for (i = 0; i < track->num_arrays; i++) {
3320                         size = track->arrays[i].esize * (nverts - 1) * 4;
3321                         if (track->arrays[i].robj == NULL) {
3322                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3323                                           "bound\n", prim_walk, i);
3324                                 return -EINVAL;
3325                         }
3326                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3327                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3328                                         "need %lu dwords have %lu dwords\n",
3329                                         prim_walk, i, size >> 2,
3330                                         radeon_bo_size(track->arrays[i].robj)
3331                                         >> 2);
3332                                 return -EINVAL;
3333                         }
3334                 }
3335                 break;
3336         case 3:
3337                 size = track->vtx_size * nverts;
3338                 if (size != track->immd_dwords) {
3339                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3340                                   track->immd_dwords, size);
3341                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3342                                   nverts, track->vtx_size);
3343                         return -EINVAL;
3344                 }
3345                 break;
3346         default:
3347                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3348                           prim_walk);
3349                 return -EINVAL;
3350         }
3351         return r100_cs_track_texture_check(rdev, track);
3352 }
3353
3354 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3355 {
3356         unsigned i, face;
3357
3358         if (rdev->family < CHIP_R300) {
3359                 track->num_cb = 1;
3360                 if (rdev->family <= CHIP_RS200)
3361                         track->num_texture = 3;
3362                 else
3363                         track->num_texture = 6;
3364                 track->maxy = 2048;
3365                 track->separate_cube = 1;
3366         } else {
3367                 track->num_cb = 4;
3368                 track->num_texture = 16;
3369                 track->maxy = 4096;
3370                 track->separate_cube = 0;
3371         }
3372
3373         for (i = 0; i < track->num_cb; i++) {
3374                 track->cb[i].robj = NULL;
3375                 track->cb[i].pitch = 8192;
3376                 track->cb[i].cpp = 16;
3377                 track->cb[i].offset = 0;
3378         }
3379         track->z_enabled = true;
3380         track->zb.robj = NULL;
3381         track->zb.pitch = 8192;
3382         track->zb.cpp = 4;
3383         track->zb.offset = 0;
3384         track->vtx_size = 0x7F;
3385         track->immd_dwords = 0xFFFFFFFFUL;
3386         track->num_arrays = 11;
3387         track->max_indx = 0x00FFFFFFUL;
3388         for (i = 0; i < track->num_arrays; i++) {
3389                 track->arrays[i].robj = NULL;
3390                 track->arrays[i].esize = 0x7F;
3391         }
3392         for (i = 0; i < track->num_texture; i++) {
3393                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3394                 track->textures[i].pitch = 16536;
3395                 track->textures[i].width = 16536;
3396                 track->textures[i].height = 16536;
3397                 track->textures[i].width_11 = 1 << 11;
3398                 track->textures[i].height_11 = 1 << 11;
3399                 track->textures[i].num_levels = 12;
3400                 if (rdev->family <= CHIP_RS200) {
3401                         track->textures[i].tex_coord_type = 0;
3402                         track->textures[i].txdepth = 0;
3403                 } else {
3404                         track->textures[i].txdepth = 16;
3405                         track->textures[i].tex_coord_type = 1;
3406                 }
3407                 track->textures[i].cpp = 64;
3408                 track->textures[i].robj = NULL;
3409                 /* CS IB emission code makes sure texture unit are disabled */
3410                 track->textures[i].enabled = false;
3411                 track->textures[i].roundup_w = true;
3412                 track->textures[i].roundup_h = true;
3413                 if (track->separate_cube)
3414                         for (face = 0; face < 5; face++) {
3415                                 track->textures[i].cube_info[face].robj = NULL;
3416                                 track->textures[i].cube_info[face].width = 16536;
3417                                 track->textures[i].cube_info[face].height = 16536;
3418                                 track->textures[i].cube_info[face].offset = 0;
3419                         }
3420         }
3421 }
3422
3423 int r100_ring_test(struct radeon_device *rdev)
3424 {
3425         uint32_t scratch;
3426         uint32_t tmp = 0;
3427         unsigned i;
3428         int r;
3429
3430         r = radeon_scratch_get(rdev, &scratch);
3431         if (r) {
3432                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3433                 return r;
3434         }
3435         WREG32(scratch, 0xCAFEDEAD);
3436         r = radeon_ring_lock(rdev, 2);
3437         if (r) {
3438                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3439                 radeon_scratch_free(rdev, scratch);
3440                 return r;
3441         }
3442         radeon_ring_write(rdev, PACKET0(scratch, 0));
3443         radeon_ring_write(rdev, 0xDEADBEEF);
3444         radeon_ring_unlock_commit(rdev);
3445         for (i = 0; i < rdev->usec_timeout; i++) {
3446                 tmp = RREG32(scratch);
3447                 if (tmp == 0xDEADBEEF) {
3448                         break;
3449                 }
3450                 DRM_UDELAY(1);
3451         }
3452         if (i < rdev->usec_timeout) {
3453                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3454         } else {
3455                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3456                           scratch, tmp);
3457                 r = -EINVAL;
3458         }
3459         radeon_scratch_free(rdev, scratch);
3460         return r;
3461 }
3462
3463 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3464 {
3465         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3466         radeon_ring_write(rdev, ib->gpu_addr);
3467         radeon_ring_write(rdev, ib->length_dw);
3468 }
3469
3470 int r100_ib_test(struct radeon_device *rdev)
3471 {
3472         struct radeon_ib *ib;
3473         uint32_t scratch;
3474         uint32_t tmp = 0;
3475         unsigned i;
3476         int r;
3477
3478         r = radeon_scratch_get(rdev, &scratch);
3479         if (r) {
3480                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3481                 return r;
3482         }
3483         WREG32(scratch, 0xCAFEDEAD);
3484         r = radeon_ib_get(rdev, &ib);
3485         if (r) {
3486                 return r;
3487         }
3488         ib->ptr[0] = PACKET0(scratch, 0);
3489         ib->ptr[1] = 0xDEADBEEF;
3490         ib->ptr[2] = PACKET2(0);
3491         ib->ptr[3] = PACKET2(0);
3492         ib->ptr[4] = PACKET2(0);
3493         ib->ptr[5] = PACKET2(0);
3494         ib->ptr[6] = PACKET2(0);
3495         ib->ptr[7] = PACKET2(0);
3496         ib->length_dw = 8;
3497         r = radeon_ib_schedule(rdev, ib);
3498         if (r) {
3499                 radeon_scratch_free(rdev, scratch);
3500                 radeon_ib_free(rdev, &ib);
3501                 return r;
3502         }
3503         r = radeon_fence_wait(ib->fence, false);
3504         if (r) {
3505                 return r;
3506         }
3507         for (i = 0; i < rdev->usec_timeout; i++) {
3508                 tmp = RREG32(scratch);
3509                 if (tmp == 0xDEADBEEF) {
3510                         break;
3511                 }
3512                 DRM_UDELAY(1);
3513         }
3514         if (i < rdev->usec_timeout) {
3515                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3516         } else {
3517                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3518                           scratch, tmp);
3519                 r = -EINVAL;
3520         }
3521         radeon_scratch_free(rdev, scratch);
3522         radeon_ib_free(rdev, &ib);
3523         return r;
3524 }
3525
3526 void r100_ib_fini(struct radeon_device *rdev)
3527 {
3528         radeon_ib_pool_fini(rdev);
3529 }
3530
3531 int r100_ib_init(struct radeon_device *rdev)
3532 {
3533         int r;
3534
3535         r = radeon_ib_pool_init(rdev);
3536         if (r) {
3537                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3538                 r100_ib_fini(rdev);
3539                 return r;
3540         }
3541         r = r100_ib_test(rdev);
3542         if (r) {
3543                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3544                 r100_ib_fini(rdev);
3545                 return r;
3546         }
3547         return 0;
3548 }
3549
3550 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3551 {
3552         /* Shutdown CP we shouldn't need to do that but better be safe than
3553          * sorry
3554          */
3555         rdev->cp.ready = false;
3556         WREG32(R_000740_CP_CSQ_CNTL, 0);
3557
3558         /* Save few CRTC registers */
3559         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3560         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3561         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3562         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3563         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3564                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3565                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3566         }
3567
3568         /* Disable VGA aperture access */
3569         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3570         /* Disable cursor, overlay, crtc */
3571         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3572         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3573                                         S_000054_CRTC_DISPLAY_DIS(1));
3574         WREG32(R_000050_CRTC_GEN_CNTL,
3575                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3576                         S_000050_CRTC_DISP_REQ_EN_B(1));
3577         WREG32(R_000420_OV0_SCALE_CNTL,
3578                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3579         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3580         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3581                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3582                                                 S_000360_CUR2_LOCK(1));
3583                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3584                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3585                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3586                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3587                 WREG32(R_000360_CUR2_OFFSET,
3588                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3589         }
3590 }
3591
3592 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3593 {
3594         /* Update base address for crtc */
3595         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3596         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3597                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3598         }
3599         /* Restore CRTC registers */
3600         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3601         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3602         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3603         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3604                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3605         }
3606 }
3607
3608 void r100_vga_render_disable(struct radeon_device *rdev)
3609 {
3610         u32 tmp;
3611
3612         tmp = RREG8(R_0003C2_GENMO_WT);
3613         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3614 }
3615
3616 static void r100_debugfs(struct radeon_device *rdev)
3617 {
3618         int r;
3619
3620         r = r100_debugfs_mc_info_init(rdev);
3621         if (r)
3622                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3623 }
3624
3625 static void r100_mc_program(struct radeon_device *rdev)
3626 {
3627         struct r100_mc_save save;
3628
3629         /* Stops all mc clients */
3630         r100_mc_stop(rdev, &save);
3631         if (rdev->flags & RADEON_IS_AGP) {
3632                 WREG32(R_00014C_MC_AGP_LOCATION,
3633                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3634                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3635                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3636                 if (rdev->family > CHIP_RV200)
3637                         WREG32(R_00015C_AGP_BASE_2,
3638                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3639         } else {
3640                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3641                 WREG32(R_000170_AGP_BASE, 0);
3642                 if (rdev->family > CHIP_RV200)
3643                         WREG32(R_00015C_AGP_BASE_2, 0);
3644         }
3645         /* Wait for mc idle */
3646         if (r100_mc_wait_for_idle(rdev))
3647                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3648         /* Program MC, should be a 32bits limited address space */
3649         WREG32(R_000148_MC_FB_LOCATION,
3650                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3651                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3652         r100_mc_resume(rdev, &save);
3653 }
3654
3655 void r100_clock_startup(struct radeon_device *rdev)
3656 {
3657         u32 tmp;
3658
3659         if (radeon_dynclks != -1 && radeon_dynclks)
3660                 radeon_legacy_set_clock_gating(rdev, 1);
3661         /* We need to force on some of the block */
3662         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3663         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3664         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3665                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3666         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3667 }
3668
3669 static int r100_startup(struct radeon_device *rdev)
3670 {
3671         int r;
3672
3673         /* set common regs */
3674         r100_set_common_regs(rdev);
3675         /* program mc */
3676         r100_mc_program(rdev);
3677         /* Resume clock */
3678         r100_clock_startup(rdev);
3679         /* Initialize GPU configuration (# pipes, ...) */
3680 //      r100_gpu_init(rdev);
3681         /* Initialize GART (initialize after TTM so we can allocate
3682          * memory through TTM but finalize after TTM) */
3683         r100_enable_bm(rdev);
3684         if (rdev->flags & RADEON_IS_PCI) {
3685                 r = r100_pci_gart_enable(rdev);
3686                 if (r)
3687                         return r;
3688         }
3689
3690         /* allocate wb buffer */
3691         r = radeon_wb_init(rdev);
3692         if (r)
3693                 return r;
3694
3695         /* Enable IRQ */
3696         r100_irq_set(rdev);
3697         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3698         /* 1M ring buffer */
3699         r = r100_cp_init(rdev, 1024 * 1024);
3700         if (r) {
3701                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3702                 return r;
3703         }
3704         r = r100_ib_init(rdev);
3705         if (r) {
3706                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3707                 return r;
3708         }
3709         return 0;
3710 }
3711
3712 int r100_resume(struct radeon_device *rdev)
3713 {
3714         /* Make sur GART are not working */
3715         if (rdev->flags & RADEON_IS_PCI)
3716                 r100_pci_gart_disable(rdev);
3717         /* Resume clock before doing reset */
3718         r100_clock_startup(rdev);
3719         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3720         if (radeon_asic_reset(rdev)) {
3721                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3722                         RREG32(R_000E40_RBBM_STATUS),
3723                         RREG32(R_0007C0_CP_STAT));
3724         }
3725         /* post */
3726         radeon_combios_asic_init(rdev->ddev);
3727         /* Resume clock after posting */
3728         r100_clock_startup(rdev);
3729         /* Initialize surface registers */
3730         radeon_surface_init(rdev);
3731         return r100_startup(rdev);
3732 }
3733
3734 int r100_suspend(struct radeon_device *rdev)
3735 {
3736         r100_cp_disable(rdev);
3737         radeon_wb_disable(rdev);
3738         r100_irq_disable(rdev);
3739         if (rdev->flags & RADEON_IS_PCI)
3740                 r100_pci_gart_disable(rdev);
3741         return 0;
3742 }
3743
3744 void r100_fini(struct radeon_device *rdev)
3745 {
3746         r100_cp_fini(rdev);
3747         radeon_wb_fini(rdev);
3748         r100_ib_fini(rdev);
3749         radeon_gem_fini(rdev);
3750         if (rdev->flags & RADEON_IS_PCI)
3751                 r100_pci_gart_fini(rdev);
3752         radeon_agp_fini(rdev);
3753         radeon_irq_kms_fini(rdev);
3754         radeon_fence_driver_fini(rdev);
3755         radeon_bo_fini(rdev);
3756         radeon_atombios_fini(rdev);
3757         kfree(rdev->bios);
3758         rdev->bios = NULL;
3759 }
3760
3761 /*
3762  * Due to how kexec works, it can leave the hw fully initialised when it
3763  * boots the new kernel. However doing our init sequence with the CP and
3764  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3765  * do some quick sanity checks and restore sane values to avoid this
3766  * problem.
3767  */
3768 void r100_restore_sanity(struct radeon_device *rdev)
3769 {
3770         u32 tmp;
3771
3772         tmp = RREG32(RADEON_CP_CSQ_CNTL);
3773         if (tmp) {
3774                 WREG32(RADEON_CP_CSQ_CNTL, 0);
3775         }
3776         tmp = RREG32(RADEON_CP_RB_CNTL);
3777         if (tmp) {
3778                 WREG32(RADEON_CP_RB_CNTL, 0);
3779         }
3780         tmp = RREG32(RADEON_SCRATCH_UMSK);
3781         if (tmp) {
3782                 WREG32(RADEON_SCRATCH_UMSK, 0);
3783         }
3784 }
3785
3786 int r100_init(struct radeon_device *rdev)
3787 {
3788         int r;
3789
3790         /* Register debugfs file specific to this group of asics */
3791         r100_debugfs(rdev);
3792         /* Disable VGA */
3793         r100_vga_render_disable(rdev);
3794         /* Initialize scratch registers */
3795         radeon_scratch_init(rdev);
3796         /* Initialize surface registers */
3797         radeon_surface_init(rdev);
3798         /* sanity check some register to avoid hangs like after kexec */
3799         r100_restore_sanity(rdev);
3800         /* TODO: disable VGA need to use VGA request */
3801         /* BIOS*/
3802         if (!radeon_get_bios(rdev)) {
3803                 if (ASIC_IS_AVIVO(rdev))
3804                         return -EINVAL;
3805         }
3806         if (rdev->is_atom_bios) {
3807                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3808                 return -EINVAL;
3809         } else {
3810                 r = radeon_combios_init(rdev);
3811                 if (r)
3812                         return r;
3813         }
3814         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3815         if (radeon_asic_reset(rdev)) {
3816                 dev_warn(rdev->dev,
3817                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3818                         RREG32(R_000E40_RBBM_STATUS),
3819                         RREG32(R_0007C0_CP_STAT));
3820         }
3821         /* check if cards are posted or not */
3822         if (radeon_boot_test_post_card(rdev) == false)
3823                 return -EINVAL;
3824         /* Set asic errata */
3825         r100_errata(rdev);
3826         /* Initialize clocks */
3827         radeon_get_clock_info(rdev->ddev);
3828         /* initialize AGP */
3829         if (rdev->flags & RADEON_IS_AGP) {
3830                 r = radeon_agp_init(rdev);
3831                 if (r) {
3832                         radeon_agp_disable(rdev);
3833                 }
3834         }
3835         /* initialize VRAM */
3836         r100_mc_init(rdev);
3837         /* Fence driver */
3838         r = radeon_fence_driver_init(rdev);
3839         if (r)
3840                 return r;
3841         r = radeon_irq_kms_init(rdev);
3842         if (r)
3843                 return r;
3844         /* Memory manager */
3845         r = radeon_bo_init(rdev);
3846         if (r)
3847                 return r;
3848         if (rdev->flags & RADEON_IS_PCI) {
3849                 r = r100_pci_gart_init(rdev);
3850                 if (r)
3851                         return r;
3852         }
3853         r100_set_safe_registers(rdev);
3854         rdev->accel_working = true;
3855         r = r100_startup(rdev);
3856         if (r) {
3857                 /* Somethings want wront with the accel init stop accel */
3858                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3859                 r100_cp_fini(rdev);
3860                 radeon_wb_fini(rdev);
3861                 r100_ib_fini(rdev);
3862                 radeon_irq_kms_fini(rdev);
3863                 if (rdev->flags & RADEON_IS_PCI)
3864                         r100_pci_gart_fini(rdev);
3865                 rdev->accel_working = false;
3866         }
3867         return 0;
3868 }