2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
35 #include "radeon_asic.h"
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
44 #include <linux/module.h>
46 #include "r100_reg_safe.h"
47 #include "rn50_reg_safe.h"
50 #define FIRMWARE_R100 "radeon/R100_cp.bin"
51 #define FIRMWARE_R200 "radeon/R200_cp.bin"
52 #define FIRMWARE_R300 "radeon/R300_cp.bin"
53 #define FIRMWARE_R420 "radeon/R420_cp.bin"
54 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
55 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
56 #define FIRMWARE_R520 "radeon/R520_cp.bin"
58 MODULE_FIRMWARE(FIRMWARE_R100);
59 MODULE_FIRMWARE(FIRMWARE_R200);
60 MODULE_FIRMWARE(FIRMWARE_R300);
61 MODULE_FIRMWARE(FIRMWARE_R420);
62 MODULE_FIRMWARE(FIRMWARE_RS690);
63 MODULE_FIRMWARE(FIRMWARE_RS600);
64 MODULE_FIRMWARE(FIRMWARE_R520);
66 #include "r100_track.h"
68 /* This files gather functions specifics to:
69 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
70 * and others in some cases.
74 * r100_wait_for_vblank - vblank wait asic callback.
76 * @rdev: radeon_device pointer
77 * @crtc: crtc to wait for vblank on
79 * Wait for vblank on the requested crtc (r1xx-r4xx).
81 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
85 if (crtc >= rdev->num_crtc)
89 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
90 for (i = 0; i < rdev->usec_timeout; i++) {
91 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
95 for (i = 0; i < rdev->usec_timeout; i++) {
96 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
102 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
103 for (i = 0; i < rdev->usec_timeout; i++) {
104 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
108 for (i = 0; i < rdev->usec_timeout; i++) {
109 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
118 * r100_pre_page_flip - pre-pageflip callback.
120 * @rdev: radeon_device pointer
121 * @crtc: crtc to prepare for pageflip on
123 * Pre-pageflip callback (r1xx-r4xx).
124 * Enables the pageflip irq (vblank irq).
126 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
128 /* enable the pflip int */
129 radeon_irq_kms_pflip_irq_get(rdev, crtc);
133 * r100_post_page_flip - pos-pageflip callback.
135 * @rdev: radeon_device pointer
136 * @crtc: crtc to cleanup pageflip on
138 * Post-pageflip callback (r1xx-r4xx).
139 * Disables the pageflip irq (vblank irq).
141 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
143 /* disable the pflip int */
144 radeon_irq_kms_pflip_irq_put(rdev, crtc);
148 * r100_page_flip - pageflip callback.
150 * @rdev: radeon_device pointer
151 * @crtc_id: crtc to cleanup pageflip on
152 * @crtc_base: new address of the crtc (GPU MC address)
154 * Does the actual pageflip (r1xx-r4xx).
155 * During vblank we take the crtc lock and wait for the update_pending
156 * bit to go high, when it does, we release the lock, and allow the
157 * double buffered update to take place.
158 * Returns the current update pending status.
160 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
162 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
163 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
166 /* Lock the graphics update lock */
167 /* update the scanout addresses */
168 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
170 /* Wait for update_pending to go high. */
171 for (i = 0; i < rdev->usec_timeout; i++) {
172 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
176 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
178 /* Unlock the lock, so double-buffering can take place inside vblank */
179 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
180 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
182 /* Return current update_pending status: */
183 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
187 * r100_pm_get_dynpm_state - look up dynpm power state callback.
189 * @rdev: radeon_device pointer
191 * Look up the optimal power state based on the
192 * current state of the GPU (r1xx-r5xx).
193 * Used for dynpm only.
195 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
198 rdev->pm.dynpm_can_upclock = true;
199 rdev->pm.dynpm_can_downclock = true;
201 switch (rdev->pm.dynpm_planned_action) {
202 case DYNPM_ACTION_MINIMUM:
203 rdev->pm.requested_power_state_index = 0;
204 rdev->pm.dynpm_can_downclock = false;
206 case DYNPM_ACTION_DOWNCLOCK:
207 if (rdev->pm.current_power_state_index == 0) {
208 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
209 rdev->pm.dynpm_can_downclock = false;
211 if (rdev->pm.active_crtc_count > 1) {
212 for (i = 0; i < rdev->pm.num_power_states; i++) {
213 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
215 else if (i >= rdev->pm.current_power_state_index) {
216 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
219 rdev->pm.requested_power_state_index = i;
224 rdev->pm.requested_power_state_index =
225 rdev->pm.current_power_state_index - 1;
227 /* don't use the power state if crtcs are active and no display flag is set */
228 if ((rdev->pm.active_crtc_count > 0) &&
229 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
230 RADEON_PM_MODE_NO_DISPLAY)) {
231 rdev->pm.requested_power_state_index++;
234 case DYNPM_ACTION_UPCLOCK:
235 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
236 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
237 rdev->pm.dynpm_can_upclock = false;
239 if (rdev->pm.active_crtc_count > 1) {
240 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
241 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
243 else if (i <= rdev->pm.current_power_state_index) {
244 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
247 rdev->pm.requested_power_state_index = i;
252 rdev->pm.requested_power_state_index =
253 rdev->pm.current_power_state_index + 1;
256 case DYNPM_ACTION_DEFAULT:
257 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
258 rdev->pm.dynpm_can_upclock = false;
260 case DYNPM_ACTION_NONE:
262 DRM_ERROR("Requested mode for not defined action\n");
265 /* only one clock mode per power state */
266 rdev->pm.requested_clock_mode_index = 0;
268 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
269 rdev->pm.power_state[rdev->pm.requested_power_state_index].
270 clock_info[rdev->pm.requested_clock_mode_index].sclk,
271 rdev->pm.power_state[rdev->pm.requested_power_state_index].
272 clock_info[rdev->pm.requested_clock_mode_index].mclk,
273 rdev->pm.power_state[rdev->pm.requested_power_state_index].
278 * r100_pm_init_profile - Initialize power profiles callback.
280 * @rdev: radeon_device pointer
282 * Initialize the power states used in profile mode
284 * Used for profile mode only.
286 void r100_pm_init_profile(struct radeon_device *rdev)
289 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
290 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
291 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
292 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
294 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
295 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
296 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
297 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
299 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
300 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
301 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
305 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
306 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
311 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
316 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
321 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
326 * r100_pm_misc - set additional pm hw parameters callback.
328 * @rdev: radeon_device pointer
330 * Set non-clock parameters associated with a power state
331 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
333 void r100_pm_misc(struct radeon_device *rdev)
335 int requested_index = rdev->pm.requested_power_state_index;
336 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
337 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
338 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
340 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
341 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
342 tmp = RREG32(voltage->gpio.reg);
343 if (voltage->active_high)
344 tmp |= voltage->gpio.mask;
346 tmp &= ~(voltage->gpio.mask);
347 WREG32(voltage->gpio.reg, tmp);
349 udelay(voltage->delay);
351 tmp = RREG32(voltage->gpio.reg);
352 if (voltage->active_high)
353 tmp &= ~voltage->gpio.mask;
355 tmp |= voltage->gpio.mask;
356 WREG32(voltage->gpio.reg, tmp);
358 udelay(voltage->delay);
362 sclk_cntl = RREG32_PLL(SCLK_CNTL);
363 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
364 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
365 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
366 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
367 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
368 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
369 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
370 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
372 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
373 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
374 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
375 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
376 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
378 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
380 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
381 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
382 if (voltage->delay) {
383 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
384 switch (voltage->delay) {
386 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
389 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
392 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
395 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
399 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
401 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
403 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
404 sclk_cntl &= ~FORCE_HDP;
406 sclk_cntl |= FORCE_HDP;
408 WREG32_PLL(SCLK_CNTL, sclk_cntl);
409 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
410 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
413 if ((rdev->flags & RADEON_IS_PCIE) &&
414 !(rdev->flags & RADEON_IS_IGP) &&
415 rdev->asic->pm.set_pcie_lanes &&
417 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
418 radeon_set_pcie_lanes(rdev,
420 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
425 * r100_pm_prepare - pre-power state change callback.
427 * @rdev: radeon_device pointer
429 * Prepare for a power state change (r1xx-r4xx).
431 void r100_pm_prepare(struct radeon_device *rdev)
433 struct drm_device *ddev = rdev->ddev;
434 struct drm_crtc *crtc;
435 struct radeon_crtc *radeon_crtc;
438 /* disable any active CRTCs */
439 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
440 radeon_crtc = to_radeon_crtc(crtc);
441 if (radeon_crtc->enabled) {
442 if (radeon_crtc->crtc_id) {
443 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
444 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
445 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
447 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
448 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
449 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
456 * r100_pm_finish - post-power state change callback.
458 * @rdev: radeon_device pointer
460 * Clean up after a power state change (r1xx-r4xx).
462 void r100_pm_finish(struct radeon_device *rdev)
464 struct drm_device *ddev = rdev->ddev;
465 struct drm_crtc *crtc;
466 struct radeon_crtc *radeon_crtc;
469 /* enable any active CRTCs */
470 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
471 radeon_crtc = to_radeon_crtc(crtc);
472 if (radeon_crtc->enabled) {
473 if (radeon_crtc->crtc_id) {
474 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
475 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
476 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
478 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
479 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
480 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
487 * r100_gui_idle - gui idle callback.
489 * @rdev: radeon_device pointer
491 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
492 * Returns true if idle, false if not.
494 bool r100_gui_idle(struct radeon_device *rdev)
496 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
502 /* hpd for digital panel detect/disconnect */
504 * r100_hpd_sense - hpd sense callback.
506 * @rdev: radeon_device pointer
507 * @hpd: hpd (hotplug detect) pin
509 * Checks if a digital monitor is connected (r1xx-r4xx).
510 * Returns true if connected, false if not connected.
512 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
514 bool connected = false;
518 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
522 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
532 * r100_hpd_set_polarity - hpd set polarity callback.
534 * @rdev: radeon_device pointer
535 * @hpd: hpd (hotplug detect) pin
537 * Set the polarity of the hpd pin (r1xx-r4xx).
539 void r100_hpd_set_polarity(struct radeon_device *rdev,
540 enum radeon_hpd_id hpd)
543 bool connected = r100_hpd_sense(rdev, hpd);
547 tmp = RREG32(RADEON_FP_GEN_CNTL);
549 tmp &= ~RADEON_FP_DETECT_INT_POL;
551 tmp |= RADEON_FP_DETECT_INT_POL;
552 WREG32(RADEON_FP_GEN_CNTL, tmp);
555 tmp = RREG32(RADEON_FP2_GEN_CNTL);
557 tmp &= ~RADEON_FP2_DETECT_INT_POL;
559 tmp |= RADEON_FP2_DETECT_INT_POL;
560 WREG32(RADEON_FP2_GEN_CNTL, tmp);
568 * r100_hpd_init - hpd setup callback.
570 * @rdev: radeon_device pointer
572 * Setup the hpd pins used by the card (r1xx-r4xx).
573 * Set the polarity, and enable the hpd interrupts.
575 void r100_hpd_init(struct radeon_device *rdev)
577 struct drm_device *dev = rdev->ddev;
578 struct drm_connector *connector;
581 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
582 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
583 enable |= 1 << radeon_connector->hpd.hpd;
584 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
586 radeon_irq_kms_enable_hpd(rdev, enable);
590 * r100_hpd_fini - hpd tear down callback.
592 * @rdev: radeon_device pointer
594 * Tear down the hpd pins used by the card (r1xx-r4xx).
595 * Disable the hpd interrupts.
597 void r100_hpd_fini(struct radeon_device *rdev)
599 struct drm_device *dev = rdev->ddev;
600 struct drm_connector *connector;
601 unsigned disable = 0;
603 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
604 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
605 disable |= 1 << radeon_connector->hpd.hpd;
607 radeon_irq_kms_disable_hpd(rdev, disable);
613 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
615 /* TODO: can we do somethings here ? */
616 /* It seems hw only cache one entry so we should discard this
617 * entry otherwise if first GPU GART read hit this entry it
618 * could end up in wrong address. */
621 int r100_pci_gart_init(struct radeon_device *rdev)
625 if (rdev->gart.ptr) {
626 WARN(1, "R100 PCI GART already initialized\n");
629 /* Initialize common gart structure */
630 r = radeon_gart_init(rdev);
633 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
634 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
635 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
636 return radeon_gart_table_ram_alloc(rdev);
639 int r100_pci_gart_enable(struct radeon_device *rdev)
643 radeon_gart_restore(rdev);
644 /* discard memory request outside of configured range */
645 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
646 WREG32(RADEON_AIC_CNTL, tmp);
647 /* set address range for PCI address translate */
648 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
649 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
650 /* set PCI GART page-table base address */
651 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
652 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
653 WREG32(RADEON_AIC_CNTL, tmp);
654 r100_pci_gart_tlb_flush(rdev);
655 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
656 (unsigned)(rdev->mc.gtt_size >> 20),
657 (unsigned long long)rdev->gart.table_addr);
658 rdev->gart.ready = true;
662 void r100_pci_gart_disable(struct radeon_device *rdev)
666 /* discard memory request outside of configured range */
667 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
668 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
669 WREG32(RADEON_AIC_LO_ADDR, 0);
670 WREG32(RADEON_AIC_HI_ADDR, 0);
673 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
675 u32 *gtt = rdev->gart.ptr;
677 if (i < 0 || i > rdev->gart.num_gpu_pages) {
680 gtt[i] = cpu_to_le32(lower_32_bits(addr));
684 void r100_pci_gart_fini(struct radeon_device *rdev)
686 radeon_gart_fini(rdev);
687 r100_pci_gart_disable(rdev);
688 radeon_gart_table_ram_free(rdev);
691 int r100_irq_set(struct radeon_device *rdev)
695 if (!rdev->irq.installed) {
696 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
697 WREG32(R_000040_GEN_INT_CNTL, 0);
700 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
701 tmp |= RADEON_SW_INT_ENABLE;
703 if (rdev->irq.gui_idle) {
704 tmp |= RADEON_GUI_IDLE_MASK;
706 if (rdev->irq.crtc_vblank_int[0] ||
707 atomic_read(&rdev->irq.pflip[0])) {
708 tmp |= RADEON_CRTC_VBLANK_MASK;
710 if (rdev->irq.crtc_vblank_int[1] ||
711 atomic_read(&rdev->irq.pflip[1])) {
712 tmp |= RADEON_CRTC2_VBLANK_MASK;
714 if (rdev->irq.hpd[0]) {
715 tmp |= RADEON_FP_DETECT_MASK;
717 if (rdev->irq.hpd[1]) {
718 tmp |= RADEON_FP2_DETECT_MASK;
720 WREG32(RADEON_GEN_INT_CNTL, tmp);
724 void r100_irq_disable(struct radeon_device *rdev)
728 WREG32(R_000040_GEN_INT_CNTL, 0);
729 /* Wait and acknowledge irq */
731 tmp = RREG32(R_000044_GEN_INT_STATUS);
732 WREG32(R_000044_GEN_INT_STATUS, tmp);
735 static uint32_t r100_irq_ack(struct radeon_device *rdev)
737 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
738 uint32_t irq_mask = RADEON_SW_INT_TEST |
739 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
740 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
742 /* the interrupt works, but the status bit is permanently asserted */
743 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
744 if (!rdev->irq.gui_idle_acked)
745 irq_mask |= RADEON_GUI_IDLE_STAT;
749 WREG32(RADEON_GEN_INT_STATUS, irqs);
751 return irqs & irq_mask;
754 int r100_irq_process(struct radeon_device *rdev)
756 uint32_t status, msi_rearm;
757 bool queue_hotplug = false;
759 /* reset gui idle ack. the status bit is broken */
760 rdev->irq.gui_idle_acked = false;
762 status = r100_irq_ack(rdev);
766 if (rdev->shutdown) {
771 if (status & RADEON_SW_INT_TEST) {
772 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
774 /* gui idle interrupt */
775 if (status & RADEON_GUI_IDLE_STAT) {
776 rdev->irq.gui_idle_acked = true;
777 wake_up(&rdev->irq.idle_queue);
779 /* Vertical blank interrupts */
780 if (status & RADEON_CRTC_VBLANK_STAT) {
781 if (rdev->irq.crtc_vblank_int[0]) {
782 drm_handle_vblank(rdev->ddev, 0);
783 rdev->pm.vblank_sync = true;
784 wake_up(&rdev->irq.vblank_queue);
786 if (atomic_read(&rdev->irq.pflip[0]))
787 radeon_crtc_handle_flip(rdev, 0);
789 if (status & RADEON_CRTC2_VBLANK_STAT) {
790 if (rdev->irq.crtc_vblank_int[1]) {
791 drm_handle_vblank(rdev->ddev, 1);
792 rdev->pm.vblank_sync = true;
793 wake_up(&rdev->irq.vblank_queue);
795 if (atomic_read(&rdev->irq.pflip[1]))
796 radeon_crtc_handle_flip(rdev, 1);
798 if (status & RADEON_FP_DETECT_STAT) {
799 queue_hotplug = true;
802 if (status & RADEON_FP2_DETECT_STAT) {
803 queue_hotplug = true;
806 status = r100_irq_ack(rdev);
808 /* reset gui idle ack. the status bit is broken */
809 rdev->irq.gui_idle_acked = false;
811 schedule_work(&rdev->hotplug_work);
812 if (rdev->msi_enabled) {
813 switch (rdev->family) {
816 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
817 WREG32(RADEON_AIC_CNTL, msi_rearm);
818 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
821 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
828 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
831 return RREG32(RADEON_CRTC_CRNT_FRAME);
833 return RREG32(RADEON_CRTC2_CRNT_FRAME);
836 /* Who ever call radeon_fence_emit should call ring_lock and ask
837 * for enough space (today caller are ib schedule and buffer move) */
838 void r100_fence_ring_emit(struct radeon_device *rdev,
839 struct radeon_fence *fence)
841 struct radeon_ring *ring = &rdev->ring[fence->ring];
843 /* We have to make sure that caches are flushed before
844 * CPU might read something from VRAM. */
845 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
846 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
847 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
848 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
849 /* Wait until IDLE & CLEAN */
850 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
851 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
852 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
853 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
854 RADEON_HDP_READ_BUFFER_INVALIDATE);
855 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
856 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
857 /* Emit fence sequence & fire IRQ */
858 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
859 radeon_ring_write(ring, fence->seq);
860 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
861 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
864 void r100_semaphore_ring_emit(struct radeon_device *rdev,
865 struct radeon_ring *ring,
866 struct radeon_semaphore *semaphore,
869 /* Unused on older asics, since we don't have semaphores or multiple rings */
873 int r100_copy_blit(struct radeon_device *rdev,
876 unsigned num_gpu_pages,
877 struct radeon_fence **fence)
879 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
881 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
883 uint32_t stride_pixels;
888 /* radeon limited to 16k stride */
889 stride_bytes &= 0x3fff;
890 /* radeon pitch is /64 */
891 pitch = stride_bytes / 64;
892 stride_pixels = stride_bytes / 4;
893 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
895 /* Ask for enough room for blit + flush + fence */
896 ndw = 64 + (10 * num_loops);
897 r = radeon_ring_lock(rdev, ring, ndw);
899 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
902 while (num_gpu_pages > 0) {
903 cur_pages = num_gpu_pages;
904 if (cur_pages > 8191) {
907 num_gpu_pages -= cur_pages;
909 /* pages are in Y direction - height
910 page width in X direction - width */
911 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
912 radeon_ring_write(ring,
913 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
914 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
915 RADEON_GMC_SRC_CLIPPING |
916 RADEON_GMC_DST_CLIPPING |
917 RADEON_GMC_BRUSH_NONE |
918 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
919 RADEON_GMC_SRC_DATATYPE_COLOR |
921 RADEON_DP_SRC_SOURCE_MEMORY |
922 RADEON_GMC_CLR_CMP_CNTL_DIS |
923 RADEON_GMC_WR_MSK_DIS);
924 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
925 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
926 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
927 radeon_ring_write(ring, 0);
928 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
929 radeon_ring_write(ring, num_gpu_pages);
930 radeon_ring_write(ring, num_gpu_pages);
931 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
933 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
934 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
935 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
936 radeon_ring_write(ring,
937 RADEON_WAIT_2D_IDLECLEAN |
938 RADEON_WAIT_HOST_IDLECLEAN |
939 RADEON_WAIT_DMA_GUI_IDLE);
941 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
943 radeon_ring_unlock_commit(rdev, ring);
947 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
952 for (i = 0; i < rdev->usec_timeout; i++) {
953 tmp = RREG32(R_000E40_RBBM_STATUS);
954 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
962 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
966 r = radeon_ring_lock(rdev, ring, 2);
970 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
971 radeon_ring_write(ring,
972 RADEON_ISYNC_ANY2D_IDLE3D |
973 RADEON_ISYNC_ANY3D_IDLE2D |
974 RADEON_ISYNC_WAIT_IDLEGUI |
975 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
976 radeon_ring_unlock_commit(rdev, ring);
980 /* Load the microcode for the CP */
981 static int r100_cp_init_microcode(struct radeon_device *rdev)
983 struct platform_device *pdev;
984 const char *fw_name = NULL;
989 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
992 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
995 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
996 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
997 (rdev->family == CHIP_RS200)) {
998 DRM_INFO("Loading R100 Microcode\n");
999 fw_name = FIRMWARE_R100;
1000 } else if ((rdev->family == CHIP_R200) ||
1001 (rdev->family == CHIP_RV250) ||
1002 (rdev->family == CHIP_RV280) ||
1003 (rdev->family == CHIP_RS300)) {
1004 DRM_INFO("Loading R200 Microcode\n");
1005 fw_name = FIRMWARE_R200;
1006 } else if ((rdev->family == CHIP_R300) ||
1007 (rdev->family == CHIP_R350) ||
1008 (rdev->family == CHIP_RV350) ||
1009 (rdev->family == CHIP_RV380) ||
1010 (rdev->family == CHIP_RS400) ||
1011 (rdev->family == CHIP_RS480)) {
1012 DRM_INFO("Loading R300 Microcode\n");
1013 fw_name = FIRMWARE_R300;
1014 } else if ((rdev->family == CHIP_R420) ||
1015 (rdev->family == CHIP_R423) ||
1016 (rdev->family == CHIP_RV410)) {
1017 DRM_INFO("Loading R400 Microcode\n");
1018 fw_name = FIRMWARE_R420;
1019 } else if ((rdev->family == CHIP_RS690) ||
1020 (rdev->family == CHIP_RS740)) {
1021 DRM_INFO("Loading RS690/RS740 Microcode\n");
1022 fw_name = FIRMWARE_RS690;
1023 } else if (rdev->family == CHIP_RS600) {
1024 DRM_INFO("Loading RS600 Microcode\n");
1025 fw_name = FIRMWARE_RS600;
1026 } else if ((rdev->family == CHIP_RV515) ||
1027 (rdev->family == CHIP_R520) ||
1028 (rdev->family == CHIP_RV530) ||
1029 (rdev->family == CHIP_R580) ||
1030 (rdev->family == CHIP_RV560) ||
1031 (rdev->family == CHIP_RV570)) {
1032 DRM_INFO("Loading R500 Microcode\n");
1033 fw_name = FIRMWARE_R520;
1036 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1037 platform_device_unregister(pdev);
1039 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1041 } else if (rdev->me_fw->size % 8) {
1043 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1044 rdev->me_fw->size, fw_name);
1046 release_firmware(rdev->me_fw);
1052 static void r100_cp_load_microcode(struct radeon_device *rdev)
1054 const __be32 *fw_data;
1057 if (r100_gui_wait_for_idle(rdev)) {
1058 printk(KERN_WARNING "Failed to wait GUI idle while "
1059 "programming pipes. Bad things might happen.\n");
1063 size = rdev->me_fw->size / 4;
1064 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1065 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1066 for (i = 0; i < size; i += 2) {
1067 WREG32(RADEON_CP_ME_RAM_DATAH,
1068 be32_to_cpup(&fw_data[i]));
1069 WREG32(RADEON_CP_ME_RAM_DATAL,
1070 be32_to_cpup(&fw_data[i + 1]));
1075 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1077 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1081 unsigned pre_write_timer;
1082 unsigned pre_write_limit;
1083 unsigned indirect2_start;
1084 unsigned indirect1_start;
1088 if (r100_debugfs_cp_init(rdev)) {
1089 DRM_ERROR("Failed to register debugfs file for CP !\n");
1092 r = r100_cp_init_microcode(rdev);
1094 DRM_ERROR("Failed to load firmware!\n");
1099 /* Align ring size */
1100 rb_bufsz = drm_order(ring_size / 8);
1101 ring_size = (1 << (rb_bufsz + 1)) * 4;
1102 r100_cp_load_microcode(rdev);
1103 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1104 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1105 0, 0x7fffff, RADEON_CP_PACKET2);
1109 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1110 * the rptr copy in system ram */
1112 /* cp will read 128bytes at a time (4 dwords) */
1114 ring->align_mask = 16 - 1;
1115 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1116 pre_write_timer = 64;
1117 /* Force CP_RB_WPTR write if written more than one time before the
1120 pre_write_limit = 0;
1121 /* Setup the cp cache like this (cache size is 96 dwords) :
1123 * INDIRECT1 16 to 79
1124 * INDIRECT2 80 to 95
1125 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1126 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1127 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1128 * Idea being that most of the gpu cmd will be through indirect1 buffer
1129 * so it gets the bigger cache.
1131 indirect2_start = 80;
1132 indirect1_start = 16;
1134 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1135 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1136 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1137 REG_SET(RADEON_MAX_FETCH, max_fetch));
1139 tmp |= RADEON_BUF_SWAP_32BIT;
1141 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1143 /* Set ring address */
1144 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1145 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1146 /* Force read & write ptr to 0 */
1147 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1148 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1150 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1152 /* set the wb address whether it's enabled or not */
1153 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1154 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1155 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1157 if (rdev->wb.enabled)
1158 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1160 tmp |= RADEON_RB_NO_UPDATE;
1161 WREG32(R_000770_SCRATCH_UMSK, 0);
1164 WREG32(RADEON_CP_RB_CNTL, tmp);
1166 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1167 /* Set cp mode to bus mastering & enable cp*/
1168 WREG32(RADEON_CP_CSQ_MODE,
1169 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1170 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1171 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1172 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1173 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1175 /* at this point everything should be setup correctly to enable master */
1176 pci_set_master(rdev->pdev);
1178 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1179 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1181 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1185 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1187 if (!ring->rptr_save_reg /* not resuming from suspend */
1188 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1189 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1191 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1192 ring->rptr_save_reg = 0;
1198 void r100_cp_fini(struct radeon_device *rdev)
1200 if (r100_cp_wait_for_idle(rdev)) {
1201 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1204 r100_cp_disable(rdev);
1205 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1206 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1207 DRM_INFO("radeon: cp finalized\n");
1210 void r100_cp_disable(struct radeon_device *rdev)
1213 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1214 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1215 WREG32(RADEON_CP_CSQ_MODE, 0);
1216 WREG32(RADEON_CP_CSQ_CNTL, 0);
1217 WREG32(R_000770_SCRATCH_UMSK, 0);
1218 if (r100_gui_wait_for_idle(rdev)) {
1219 printk(KERN_WARNING "Failed to wait GUI idle while "
1220 "programming pipes. Bad things might happen.\n");
1227 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1228 struct radeon_cs_packet *pkt,
1235 struct radeon_cs_reloc *reloc;
1238 r = r100_cs_packet_next_reloc(p, &reloc);
1240 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1242 r100_cs_dump_packet(p, pkt);
1246 value = radeon_get_ib_value(p, idx);
1247 tmp = value & 0x003fffff;
1248 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1250 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1251 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1252 tile_flags |= RADEON_DST_TILE_MACRO;
1253 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1254 if (reg == RADEON_SRC_PITCH_OFFSET) {
1255 DRM_ERROR("Cannot src blit from microtiled surface\n");
1256 r100_cs_dump_packet(p, pkt);
1259 tile_flags |= RADEON_DST_TILE_MICRO;
1263 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1265 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1269 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1270 struct radeon_cs_packet *pkt,
1274 struct radeon_cs_reloc *reloc;
1275 struct r100_cs_track *track;
1277 volatile uint32_t *ib;
1281 track = (struct r100_cs_track *)p->track;
1282 c = radeon_get_ib_value(p, idx++) & 0x1F;
1284 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1286 r100_cs_dump_packet(p, pkt);
1289 track->num_arrays = c;
1290 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1291 r = r100_cs_packet_next_reloc(p, &reloc);
1293 DRM_ERROR("No reloc for packet3 %d\n",
1295 r100_cs_dump_packet(p, pkt);
1298 idx_value = radeon_get_ib_value(p, idx);
1299 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1301 track->arrays[i + 0].esize = idx_value >> 8;
1302 track->arrays[i + 0].robj = reloc->robj;
1303 track->arrays[i + 0].esize &= 0x7F;
1304 r = r100_cs_packet_next_reloc(p, &reloc);
1306 DRM_ERROR("No reloc for packet3 %d\n",
1308 r100_cs_dump_packet(p, pkt);
1311 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
1312 track->arrays[i + 1].robj = reloc->robj;
1313 track->arrays[i + 1].esize = idx_value >> 24;
1314 track->arrays[i + 1].esize &= 0x7F;
1317 r = r100_cs_packet_next_reloc(p, &reloc);
1319 DRM_ERROR("No reloc for packet3 %d\n",
1321 r100_cs_dump_packet(p, pkt);
1324 idx_value = radeon_get_ib_value(p, idx);
1325 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1326 track->arrays[i + 0].robj = reloc->robj;
1327 track->arrays[i + 0].esize = idx_value >> 8;
1328 track->arrays[i + 0].esize &= 0x7F;
1333 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1334 struct radeon_cs_packet *pkt,
1335 const unsigned *auth, unsigned n,
1336 radeon_packet0_check_t check)
1345 /* Check that register fall into register range
1346 * determined by the number of entry (n) in the
1347 * safe register bitmap.
1349 if (pkt->one_reg_wr) {
1350 if ((reg >> 7) > n) {
1354 if (((reg + (pkt->count << 2)) >> 7) > n) {
1358 for (i = 0; i <= pkt->count; i++, idx++) {
1360 m = 1 << ((reg >> 2) & 31);
1362 r = check(p, pkt, idx, reg);
1367 if (pkt->one_reg_wr) {
1368 if (!(auth[j] & m)) {
1378 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1379 struct radeon_cs_packet *pkt)
1381 volatile uint32_t *ib;
1387 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1388 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1393 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1394 * @parser: parser structure holding parsing context.
1395 * @pkt: where to store packet informations
1397 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1398 * if packet is bigger than remaining ib size. or if packets is unknown.
1400 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1401 struct radeon_cs_packet *pkt,
1404 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1407 if (idx >= ib_chunk->length_dw) {
1408 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1409 idx, ib_chunk->length_dw);
1412 header = radeon_get_ib_value(p, idx);
1414 pkt->type = CP_PACKET_GET_TYPE(header);
1415 pkt->count = CP_PACKET_GET_COUNT(header);
1416 switch (pkt->type) {
1418 pkt->reg = CP_PACKET0_GET_REG(header);
1419 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1422 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1428 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1431 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1432 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1433 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1440 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1441 * @parser: parser structure holding parsing context.
1443 * Userspace sends a special sequence for VLINE waits.
1444 * PACKET0 - VLINE_START_END + value
1445 * PACKET0 - WAIT_UNTIL +_value
1446 * RELOC (P3) - crtc_id in reloc.
1448 * This function parses this and relocates the VLINE START END
1449 * and WAIT UNTIL packets to the correct crtc.
1450 * It also detects a switched off crtc and nulls out the
1451 * wait in that case.
1453 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1455 struct drm_mode_object *obj;
1456 struct drm_crtc *crtc;
1457 struct radeon_crtc *radeon_crtc;
1458 struct radeon_cs_packet p3reloc, waitreloc;
1461 uint32_t header, h_idx, reg;
1462 volatile uint32_t *ib;
1466 /* parse the wait until */
1467 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1471 /* check its a wait until and only 1 count */
1472 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1473 waitreloc.count != 0) {
1474 DRM_ERROR("vline wait had illegal wait until segment\n");
1478 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1479 DRM_ERROR("vline wait had illegal wait until\n");
1483 /* jump over the NOP */
1484 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1489 p->idx += waitreloc.count + 2;
1490 p->idx += p3reloc.count + 2;
1492 header = radeon_get_ib_value(p, h_idx);
1493 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1494 reg = CP_PACKET0_GET_REG(header);
1495 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1497 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1500 crtc = obj_to_crtc(obj);
1501 radeon_crtc = to_radeon_crtc(crtc);
1502 crtc_id = radeon_crtc->crtc_id;
1504 if (!crtc->enabled) {
1505 /* if the CRTC isn't enabled - we need to nop out the wait until */
1506 ib[h_idx + 2] = PACKET2(0);
1507 ib[h_idx + 3] = PACKET2(0);
1508 } else if (crtc_id == 1) {
1510 case AVIVO_D1MODE_VLINE_START_END:
1511 header &= ~R300_CP_PACKET0_REG_MASK;
1512 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1514 case RADEON_CRTC_GUI_TRIG_VLINE:
1515 header &= ~R300_CP_PACKET0_REG_MASK;
1516 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1519 DRM_ERROR("unknown crtc reloc\n");
1523 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1530 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1531 * @parser: parser structure holding parsing context.
1532 * @data: pointer to relocation data
1533 * @offset_start: starting offset
1534 * @offset_mask: offset mask (to align start offset on)
1535 * @reloc: reloc informations
1537 * Check next packet is relocation packet3, do bo validation and compute
1538 * GPU offset using the provided start.
1540 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1541 struct radeon_cs_reloc **cs_reloc)
1543 struct radeon_cs_chunk *relocs_chunk;
1544 struct radeon_cs_packet p3reloc;
1548 if (p->chunk_relocs_idx == -1) {
1549 DRM_ERROR("No relocation chunk !\n");
1553 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1554 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1558 p->idx += p3reloc.count + 2;
1559 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1560 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1562 r100_cs_dump_packet(p, &p3reloc);
1565 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1566 if (idx >= relocs_chunk->length_dw) {
1567 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1568 idx, relocs_chunk->length_dw);
1569 r100_cs_dump_packet(p, &p3reloc);
1572 /* FIXME: we assume reloc size is 4 dwords */
1573 *cs_reloc = p->relocs_ptr[(idx / 4)];
1577 static int r100_get_vtx_size(uint32_t vtx_fmt)
1581 /* ordered according to bits in spec */
1582 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1584 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1586 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1588 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1590 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1592 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1594 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1596 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1598 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1600 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1602 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1604 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1606 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1608 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1610 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1613 if (vtx_fmt & (0x7 << 15))
1614 vtx_size += (vtx_fmt >> 15) & 0x7;
1615 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1617 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1619 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1621 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1623 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1625 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1630 static int r100_packet0_check(struct radeon_cs_parser *p,
1631 struct radeon_cs_packet *pkt,
1632 unsigned idx, unsigned reg)
1634 struct radeon_cs_reloc *reloc;
1635 struct r100_cs_track *track;
1636 volatile uint32_t *ib;
1644 track = (struct r100_cs_track *)p->track;
1646 idx_value = radeon_get_ib_value(p, idx);
1649 case RADEON_CRTC_GUI_TRIG_VLINE:
1650 r = r100_cs_packet_parse_vline(p);
1652 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1654 r100_cs_dump_packet(p, pkt);
1658 /* FIXME: only allow PACKET3 blit? easier to check for out of
1660 case RADEON_DST_PITCH_OFFSET:
1661 case RADEON_SRC_PITCH_OFFSET:
1662 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1666 case RADEON_RB3D_DEPTHOFFSET:
1667 r = r100_cs_packet_next_reloc(p, &reloc);
1669 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1671 r100_cs_dump_packet(p, pkt);
1674 track->zb.robj = reloc->robj;
1675 track->zb.offset = idx_value;
1676 track->zb_dirty = true;
1677 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1679 case RADEON_RB3D_COLOROFFSET:
1680 r = r100_cs_packet_next_reloc(p, &reloc);
1682 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1684 r100_cs_dump_packet(p, pkt);
1687 track->cb[0].robj = reloc->robj;
1688 track->cb[0].offset = idx_value;
1689 track->cb_dirty = true;
1690 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1692 case RADEON_PP_TXOFFSET_0:
1693 case RADEON_PP_TXOFFSET_1:
1694 case RADEON_PP_TXOFFSET_2:
1695 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1696 r = r100_cs_packet_next_reloc(p, &reloc);
1698 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1700 r100_cs_dump_packet(p, pkt);
1703 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1704 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1705 tile_flags |= RADEON_TXO_MACRO_TILE;
1706 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1707 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1709 tmp = idx_value & ~(0x7 << 2);
1711 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1713 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1714 track->textures[i].robj = reloc->robj;
1715 track->tex_dirty = true;
1717 case RADEON_PP_CUBIC_OFFSET_T0_0:
1718 case RADEON_PP_CUBIC_OFFSET_T0_1:
1719 case RADEON_PP_CUBIC_OFFSET_T0_2:
1720 case RADEON_PP_CUBIC_OFFSET_T0_3:
1721 case RADEON_PP_CUBIC_OFFSET_T0_4:
1722 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1723 r = r100_cs_packet_next_reloc(p, &reloc);
1725 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1727 r100_cs_dump_packet(p, pkt);
1730 track->textures[0].cube_info[i].offset = idx_value;
1731 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1732 track->textures[0].cube_info[i].robj = reloc->robj;
1733 track->tex_dirty = true;
1735 case RADEON_PP_CUBIC_OFFSET_T1_0:
1736 case RADEON_PP_CUBIC_OFFSET_T1_1:
1737 case RADEON_PP_CUBIC_OFFSET_T1_2:
1738 case RADEON_PP_CUBIC_OFFSET_T1_3:
1739 case RADEON_PP_CUBIC_OFFSET_T1_4:
1740 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1741 r = r100_cs_packet_next_reloc(p, &reloc);
1743 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1745 r100_cs_dump_packet(p, pkt);
1748 track->textures[1].cube_info[i].offset = idx_value;
1749 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1750 track->textures[1].cube_info[i].robj = reloc->robj;
1751 track->tex_dirty = true;
1753 case RADEON_PP_CUBIC_OFFSET_T2_0:
1754 case RADEON_PP_CUBIC_OFFSET_T2_1:
1755 case RADEON_PP_CUBIC_OFFSET_T2_2:
1756 case RADEON_PP_CUBIC_OFFSET_T2_3:
1757 case RADEON_PP_CUBIC_OFFSET_T2_4:
1758 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1759 r = r100_cs_packet_next_reloc(p, &reloc);
1761 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1763 r100_cs_dump_packet(p, pkt);
1766 track->textures[2].cube_info[i].offset = idx_value;
1767 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1768 track->textures[2].cube_info[i].robj = reloc->robj;
1769 track->tex_dirty = true;
1771 case RADEON_RE_WIDTH_HEIGHT:
1772 track->maxy = ((idx_value >> 16) & 0x7FF);
1773 track->cb_dirty = true;
1774 track->zb_dirty = true;
1776 case RADEON_RB3D_COLORPITCH:
1777 r = r100_cs_packet_next_reloc(p, &reloc);
1779 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1781 r100_cs_dump_packet(p, pkt);
1784 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1785 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1786 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1787 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1788 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1790 tmp = idx_value & ~(0x7 << 16);
1794 ib[idx] = idx_value;
1796 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1797 track->cb_dirty = true;
1799 case RADEON_RB3D_DEPTHPITCH:
1800 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1801 track->zb_dirty = true;
1803 case RADEON_RB3D_CNTL:
1804 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1810 track->cb[0].cpp = 1;
1815 track->cb[0].cpp = 2;
1818 track->cb[0].cpp = 4;
1821 DRM_ERROR("Invalid color buffer format (%d) !\n",
1822 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1825 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1826 track->cb_dirty = true;
1827 track->zb_dirty = true;
1829 case RADEON_RB3D_ZSTENCILCNTL:
1830 switch (idx_value & 0xf) {
1845 track->zb_dirty = true;
1847 case RADEON_RB3D_ZPASS_ADDR:
1848 r = r100_cs_packet_next_reloc(p, &reloc);
1850 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1852 r100_cs_dump_packet(p, pkt);
1855 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1857 case RADEON_PP_CNTL:
1859 uint32_t temp = idx_value >> 4;
1860 for (i = 0; i < track->num_texture; i++)
1861 track->textures[i].enabled = !!(temp & (1 << i));
1862 track->tex_dirty = true;
1865 case RADEON_SE_VF_CNTL:
1866 track->vap_vf_cntl = idx_value;
1868 case RADEON_SE_VTX_FMT:
1869 track->vtx_size = r100_get_vtx_size(idx_value);
1871 case RADEON_PP_TEX_SIZE_0:
1872 case RADEON_PP_TEX_SIZE_1:
1873 case RADEON_PP_TEX_SIZE_2:
1874 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1875 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1876 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1877 track->tex_dirty = true;
1879 case RADEON_PP_TEX_PITCH_0:
1880 case RADEON_PP_TEX_PITCH_1:
1881 case RADEON_PP_TEX_PITCH_2:
1882 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1883 track->textures[i].pitch = idx_value + 32;
1884 track->tex_dirty = true;
1886 case RADEON_PP_TXFILTER_0:
1887 case RADEON_PP_TXFILTER_1:
1888 case RADEON_PP_TXFILTER_2:
1889 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1890 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1891 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1892 tmp = (idx_value >> 23) & 0x7;
1893 if (tmp == 2 || tmp == 6)
1894 track->textures[i].roundup_w = false;
1895 tmp = (idx_value >> 27) & 0x7;
1896 if (tmp == 2 || tmp == 6)
1897 track->textures[i].roundup_h = false;
1898 track->tex_dirty = true;
1900 case RADEON_PP_TXFORMAT_0:
1901 case RADEON_PP_TXFORMAT_1:
1902 case RADEON_PP_TXFORMAT_2:
1903 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1904 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1905 track->textures[i].use_pitch = 1;
1907 track->textures[i].use_pitch = 0;
1908 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1909 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1911 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1912 track->textures[i].tex_coord_type = 2;
1913 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1914 case RADEON_TXFORMAT_I8:
1915 case RADEON_TXFORMAT_RGB332:
1916 case RADEON_TXFORMAT_Y8:
1917 track->textures[i].cpp = 1;
1918 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1920 case RADEON_TXFORMAT_AI88:
1921 case RADEON_TXFORMAT_ARGB1555:
1922 case RADEON_TXFORMAT_RGB565:
1923 case RADEON_TXFORMAT_ARGB4444:
1924 case RADEON_TXFORMAT_VYUY422:
1925 case RADEON_TXFORMAT_YVYU422:
1926 case RADEON_TXFORMAT_SHADOW16:
1927 case RADEON_TXFORMAT_LDUDV655:
1928 case RADEON_TXFORMAT_DUDV88:
1929 track->textures[i].cpp = 2;
1930 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1932 case RADEON_TXFORMAT_ARGB8888:
1933 case RADEON_TXFORMAT_RGBA8888:
1934 case RADEON_TXFORMAT_SHADOW32:
1935 case RADEON_TXFORMAT_LDUDUV8888:
1936 track->textures[i].cpp = 4;
1937 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1939 case RADEON_TXFORMAT_DXT1:
1940 track->textures[i].cpp = 1;
1941 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1943 case RADEON_TXFORMAT_DXT23:
1944 case RADEON_TXFORMAT_DXT45:
1945 track->textures[i].cpp = 1;
1946 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1949 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1950 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1951 track->tex_dirty = true;
1953 case RADEON_PP_CUBIC_FACES_0:
1954 case RADEON_PP_CUBIC_FACES_1:
1955 case RADEON_PP_CUBIC_FACES_2:
1957 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1958 for (face = 0; face < 4; face++) {
1959 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1960 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1962 track->tex_dirty = true;
1965 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1972 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1973 struct radeon_cs_packet *pkt,
1974 struct radeon_bo *robj)
1979 value = radeon_get_ib_value(p, idx + 2);
1980 if ((value + 1) > radeon_bo_size(robj)) {
1981 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1982 "(need %u have %lu) !\n",
1984 radeon_bo_size(robj));
1990 static int r100_packet3_check(struct radeon_cs_parser *p,
1991 struct radeon_cs_packet *pkt)
1993 struct radeon_cs_reloc *reloc;
1994 struct r100_cs_track *track;
1996 volatile uint32_t *ib;
2001 track = (struct r100_cs_track *)p->track;
2002 switch (pkt->opcode) {
2003 case PACKET3_3D_LOAD_VBPNTR:
2004 r = r100_packet3_load_vbpntr(p, pkt, idx);
2008 case PACKET3_INDX_BUFFER:
2009 r = r100_cs_packet_next_reloc(p, &reloc);
2011 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
2012 r100_cs_dump_packet(p, pkt);
2015 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
2016 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
2022 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
2023 r = r100_cs_packet_next_reloc(p, &reloc);
2025 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
2026 r100_cs_dump_packet(p, pkt);
2029 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
2030 track->num_arrays = 1;
2031 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
2033 track->arrays[0].robj = reloc->robj;
2034 track->arrays[0].esize = track->vtx_size;
2036 track->max_indx = radeon_get_ib_value(p, idx+1);
2038 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
2039 track->immd_dwords = pkt->count - 1;
2040 r = r100_cs_track_check(p->rdev, track);
2044 case PACKET3_3D_DRAW_IMMD:
2045 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
2046 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
2049 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
2050 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2051 track->immd_dwords = pkt->count - 1;
2052 r = r100_cs_track_check(p->rdev, track);
2056 /* triggers drawing using in-packet vertex data */
2057 case PACKET3_3D_DRAW_IMMD_2:
2058 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
2059 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
2062 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2063 track->immd_dwords = pkt->count;
2064 r = r100_cs_track_check(p->rdev, track);
2068 /* triggers drawing using in-packet vertex data */
2069 case PACKET3_3D_DRAW_VBUF_2:
2070 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2071 r = r100_cs_track_check(p->rdev, track);
2075 /* triggers drawing of vertex buffers setup elsewhere */
2076 case PACKET3_3D_DRAW_INDX_2:
2077 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2078 r = r100_cs_track_check(p->rdev, track);
2082 /* triggers drawing using indices to vertex buffer */
2083 case PACKET3_3D_DRAW_VBUF:
2084 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2085 r = r100_cs_track_check(p->rdev, track);
2089 /* triggers drawing of vertex buffers setup elsewhere */
2090 case PACKET3_3D_DRAW_INDX:
2091 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2092 r = r100_cs_track_check(p->rdev, track);
2096 /* triggers drawing using indices to vertex buffer */
2097 case PACKET3_3D_CLEAR_HIZ:
2098 case PACKET3_3D_CLEAR_ZMASK:
2099 if (p->rdev->hyperz_filp != p->filp)
2105 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2111 int r100_cs_parse(struct radeon_cs_parser *p)
2113 struct radeon_cs_packet pkt;
2114 struct r100_cs_track *track;
2117 track = kzalloc(sizeof(*track), GFP_KERNEL);
2120 r100_cs_track_clear(p->rdev, track);
2123 r = r100_cs_packet_parse(p, &pkt, p->idx);
2127 p->idx += pkt.count + 2;
2130 if (p->rdev->family >= CHIP_R200)
2131 r = r100_cs_parse_packet0(p, &pkt,
2132 p->rdev->config.r100.reg_safe_bm,
2133 p->rdev->config.r100.reg_safe_bm_size,
2134 &r200_packet0_check);
2136 r = r100_cs_parse_packet0(p, &pkt,
2137 p->rdev->config.r100.reg_safe_bm,
2138 p->rdev->config.r100.reg_safe_bm_size,
2139 &r100_packet0_check);
2144 r = r100_packet3_check(p, &pkt);
2147 DRM_ERROR("Unknown packet type %d !\n",
2154 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2158 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2160 DRM_ERROR("pitch %d\n", t->pitch);
2161 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2162 DRM_ERROR("width %d\n", t->width);
2163 DRM_ERROR("width_11 %d\n", t->width_11);
2164 DRM_ERROR("height %d\n", t->height);
2165 DRM_ERROR("height_11 %d\n", t->height_11);
2166 DRM_ERROR("num levels %d\n", t->num_levels);
2167 DRM_ERROR("depth %d\n", t->txdepth);
2168 DRM_ERROR("bpp %d\n", t->cpp);
2169 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2170 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2171 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2172 DRM_ERROR("compress format %d\n", t->compress_format);
2175 static int r100_track_compress_size(int compress_format, int w, int h)
2177 int block_width, block_height, block_bytes;
2178 int wblocks, hblocks;
2185 switch (compress_format) {
2186 case R100_TRACK_COMP_DXT1:
2191 case R100_TRACK_COMP_DXT35:
2197 hblocks = (h + block_height - 1) / block_height;
2198 wblocks = (w + block_width - 1) / block_width;
2199 if (wblocks < min_wblocks)
2200 wblocks = min_wblocks;
2201 sz = wblocks * hblocks * block_bytes;
2205 static int r100_cs_track_cube(struct radeon_device *rdev,
2206 struct r100_cs_track *track, unsigned idx)
2208 unsigned face, w, h;
2209 struct radeon_bo *cube_robj;
2211 unsigned compress_format = track->textures[idx].compress_format;
2213 for (face = 0; face < 5; face++) {
2214 cube_robj = track->textures[idx].cube_info[face].robj;
2215 w = track->textures[idx].cube_info[face].width;
2216 h = track->textures[idx].cube_info[face].height;
2218 if (compress_format) {
2219 size = r100_track_compress_size(compress_format, w, h);
2222 size *= track->textures[idx].cpp;
2224 size += track->textures[idx].cube_info[face].offset;
2226 if (size > radeon_bo_size(cube_robj)) {
2227 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2228 size, radeon_bo_size(cube_robj));
2229 r100_cs_track_texture_print(&track->textures[idx]);
2236 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2237 struct r100_cs_track *track)
2239 struct radeon_bo *robj;
2241 unsigned u, i, w, h, d;
2244 for (u = 0; u < track->num_texture; u++) {
2245 if (!track->textures[u].enabled)
2247 if (track->textures[u].lookup_disable)
2249 robj = track->textures[u].robj;
2251 DRM_ERROR("No texture bound to unit %u\n", u);
2255 for (i = 0; i <= track->textures[u].num_levels; i++) {
2256 if (track->textures[u].use_pitch) {
2257 if (rdev->family < CHIP_R300)
2258 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2260 w = track->textures[u].pitch / (1 << i);
2262 w = track->textures[u].width;
2263 if (rdev->family >= CHIP_RV515)
2264 w |= track->textures[u].width_11;
2266 if (track->textures[u].roundup_w)
2267 w = roundup_pow_of_two(w);
2269 h = track->textures[u].height;
2270 if (rdev->family >= CHIP_RV515)
2271 h |= track->textures[u].height_11;
2273 if (track->textures[u].roundup_h)
2274 h = roundup_pow_of_two(h);
2275 if (track->textures[u].tex_coord_type == 1) {
2276 d = (1 << track->textures[u].txdepth) / (1 << i);
2282 if (track->textures[u].compress_format) {
2284 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2285 /* compressed textures are block based */
2289 size *= track->textures[u].cpp;
2291 switch (track->textures[u].tex_coord_type) {
2296 if (track->separate_cube) {
2297 ret = r100_cs_track_cube(rdev, track, u);
2304 DRM_ERROR("Invalid texture coordinate type %u for unit "
2305 "%u\n", track->textures[u].tex_coord_type, u);
2308 if (size > radeon_bo_size(robj)) {
2309 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2310 "%lu\n", u, size, radeon_bo_size(robj));
2311 r100_cs_track_texture_print(&track->textures[u]);
2318 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2324 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2326 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2327 !track->blend_read_enable)
2330 for (i = 0; i < num_cb; i++) {
2331 if (track->cb[i].robj == NULL) {
2332 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2335 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2336 size += track->cb[i].offset;
2337 if (size > radeon_bo_size(track->cb[i].robj)) {
2338 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2339 "(need %lu have %lu) !\n", i, size,
2340 radeon_bo_size(track->cb[i].robj));
2341 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2342 i, track->cb[i].pitch, track->cb[i].cpp,
2343 track->cb[i].offset, track->maxy);
2347 track->cb_dirty = false;
2349 if (track->zb_dirty && track->z_enabled) {
2350 if (track->zb.robj == NULL) {
2351 DRM_ERROR("[drm] No buffer for z buffer !\n");
2354 size = track->zb.pitch * track->zb.cpp * track->maxy;
2355 size += track->zb.offset;
2356 if (size > radeon_bo_size(track->zb.robj)) {
2357 DRM_ERROR("[drm] Buffer too small for z buffer "
2358 "(need %lu have %lu) !\n", size,
2359 radeon_bo_size(track->zb.robj));
2360 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2361 track->zb.pitch, track->zb.cpp,
2362 track->zb.offset, track->maxy);
2366 track->zb_dirty = false;
2368 if (track->aa_dirty && track->aaresolve) {
2369 if (track->aa.robj == NULL) {
2370 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2373 /* I believe the format comes from colorbuffer0. */
2374 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2375 size += track->aa.offset;
2376 if (size > radeon_bo_size(track->aa.robj)) {
2377 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2378 "(need %lu have %lu) !\n", i, size,
2379 radeon_bo_size(track->aa.robj));
2380 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2381 i, track->aa.pitch, track->cb[0].cpp,
2382 track->aa.offset, track->maxy);
2386 track->aa_dirty = false;
2388 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2389 if (track->vap_vf_cntl & (1 << 14)) {
2390 nverts = track->vap_alt_nverts;
2392 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2394 switch (prim_walk) {
2396 for (i = 0; i < track->num_arrays; i++) {
2397 size = track->arrays[i].esize * track->max_indx * 4;
2398 if (track->arrays[i].robj == NULL) {
2399 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2400 "bound\n", prim_walk, i);
2403 if (size > radeon_bo_size(track->arrays[i].robj)) {
2404 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2405 "need %lu dwords have %lu dwords\n",
2406 prim_walk, i, size >> 2,
2407 radeon_bo_size(track->arrays[i].robj)
2409 DRM_ERROR("Max indices %u\n", track->max_indx);
2415 for (i = 0; i < track->num_arrays; i++) {
2416 size = track->arrays[i].esize * (nverts - 1) * 4;
2417 if (track->arrays[i].robj == NULL) {
2418 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2419 "bound\n", prim_walk, i);
2422 if (size > radeon_bo_size(track->arrays[i].robj)) {
2423 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2424 "need %lu dwords have %lu dwords\n",
2425 prim_walk, i, size >> 2,
2426 radeon_bo_size(track->arrays[i].robj)
2433 size = track->vtx_size * nverts;
2434 if (size != track->immd_dwords) {
2435 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2436 track->immd_dwords, size);
2437 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2438 nverts, track->vtx_size);
2443 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2448 if (track->tex_dirty) {
2449 track->tex_dirty = false;
2450 return r100_cs_track_texture_check(rdev, track);
2455 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2459 track->cb_dirty = true;
2460 track->zb_dirty = true;
2461 track->tex_dirty = true;
2462 track->aa_dirty = true;
2464 if (rdev->family < CHIP_R300) {
2466 if (rdev->family <= CHIP_RS200)
2467 track->num_texture = 3;
2469 track->num_texture = 6;
2471 track->separate_cube = 1;
2474 track->num_texture = 16;
2476 track->separate_cube = 0;
2477 track->aaresolve = false;
2478 track->aa.robj = NULL;
2481 for (i = 0; i < track->num_cb; i++) {
2482 track->cb[i].robj = NULL;
2483 track->cb[i].pitch = 8192;
2484 track->cb[i].cpp = 16;
2485 track->cb[i].offset = 0;
2487 track->z_enabled = true;
2488 track->zb.robj = NULL;
2489 track->zb.pitch = 8192;
2491 track->zb.offset = 0;
2492 track->vtx_size = 0x7F;
2493 track->immd_dwords = 0xFFFFFFFFUL;
2494 track->num_arrays = 11;
2495 track->max_indx = 0x00FFFFFFUL;
2496 for (i = 0; i < track->num_arrays; i++) {
2497 track->arrays[i].robj = NULL;
2498 track->arrays[i].esize = 0x7F;
2500 for (i = 0; i < track->num_texture; i++) {
2501 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2502 track->textures[i].pitch = 16536;
2503 track->textures[i].width = 16536;
2504 track->textures[i].height = 16536;
2505 track->textures[i].width_11 = 1 << 11;
2506 track->textures[i].height_11 = 1 << 11;
2507 track->textures[i].num_levels = 12;
2508 if (rdev->family <= CHIP_RS200) {
2509 track->textures[i].tex_coord_type = 0;
2510 track->textures[i].txdepth = 0;
2512 track->textures[i].txdepth = 16;
2513 track->textures[i].tex_coord_type = 1;
2515 track->textures[i].cpp = 64;
2516 track->textures[i].robj = NULL;
2517 /* CS IB emission code makes sure texture unit are disabled */
2518 track->textures[i].enabled = false;
2519 track->textures[i].lookup_disable = false;
2520 track->textures[i].roundup_w = true;
2521 track->textures[i].roundup_h = true;
2522 if (track->separate_cube)
2523 for (face = 0; face < 5; face++) {
2524 track->textures[i].cube_info[face].robj = NULL;
2525 track->textures[i].cube_info[face].width = 16536;
2526 track->textures[i].cube_info[face].height = 16536;
2527 track->textures[i].cube_info[face].offset = 0;
2533 * Global GPU functions
2535 void r100_errata(struct radeon_device *rdev)
2537 rdev->pll_errata = 0;
2539 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2540 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2543 if (rdev->family == CHIP_RV100 ||
2544 rdev->family == CHIP_RS100 ||
2545 rdev->family == CHIP_RS200) {
2546 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2550 /* Wait for vertical sync on primary CRTC */
2551 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2553 uint32_t crtc_gen_cntl, tmp;
2556 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2557 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2558 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2561 /* Clear the CRTC_VBLANK_SAVE bit */
2562 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2563 for (i = 0; i < rdev->usec_timeout; i++) {
2564 tmp = RREG32(RADEON_CRTC_STATUS);
2565 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2572 /* Wait for vertical sync on secondary CRTC */
2573 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2575 uint32_t crtc2_gen_cntl, tmp;
2578 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2579 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2580 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2583 /* Clear the CRTC_VBLANK_SAVE bit */
2584 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2585 for (i = 0; i < rdev->usec_timeout; i++) {
2586 tmp = RREG32(RADEON_CRTC2_STATUS);
2587 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2594 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2599 for (i = 0; i < rdev->usec_timeout; i++) {
2600 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2609 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2614 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2615 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2616 " Bad things might happen.\n");
2618 for (i = 0; i < rdev->usec_timeout; i++) {
2619 tmp = RREG32(RADEON_RBBM_STATUS);
2620 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2628 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2633 for (i = 0; i < rdev->usec_timeout; i++) {
2634 /* read MC_STATUS */
2635 tmp = RREG32(RADEON_MC_STATUS);
2636 if (tmp & RADEON_MC_IDLE) {
2644 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2648 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2649 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2650 radeon_ring_lockup_update(ring);
2653 /* force CP activities */
2654 radeon_ring_force_activity(rdev, ring);
2655 return radeon_ring_test_lockup(rdev, ring);
2658 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2659 void r100_enable_bm(struct radeon_device *rdev)
2662 /* Enable bus mastering */
2663 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2664 WREG32(RADEON_BUS_CNTL, tmp);
2667 void r100_bm_disable(struct radeon_device *rdev)
2671 /* disable bus mastering */
2672 tmp = RREG32(R_000030_BUS_CNTL);
2673 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2675 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2677 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2678 tmp = RREG32(RADEON_BUS_CNTL);
2680 pci_clear_master(rdev->pdev);
2684 int r100_asic_reset(struct radeon_device *rdev)
2686 struct r100_mc_save save;
2690 status = RREG32(R_000E40_RBBM_STATUS);
2691 if (!G_000E40_GUI_ACTIVE(status)) {
2694 r100_mc_stop(rdev, &save);
2695 status = RREG32(R_000E40_RBBM_STATUS);
2696 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2698 WREG32(RADEON_CP_CSQ_CNTL, 0);
2699 tmp = RREG32(RADEON_CP_RB_CNTL);
2700 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2701 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2702 WREG32(RADEON_CP_RB_WPTR, 0);
2703 WREG32(RADEON_CP_RB_CNTL, tmp);
2704 /* save PCI state */
2705 pci_save_state(rdev->pdev);
2706 /* disable bus mastering */
2707 r100_bm_disable(rdev);
2708 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2709 S_0000F0_SOFT_RESET_RE(1) |
2710 S_0000F0_SOFT_RESET_PP(1) |
2711 S_0000F0_SOFT_RESET_RB(1));
2712 RREG32(R_0000F0_RBBM_SOFT_RESET);
2714 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2716 status = RREG32(R_000E40_RBBM_STATUS);
2717 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2719 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2720 RREG32(R_0000F0_RBBM_SOFT_RESET);
2722 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2724 status = RREG32(R_000E40_RBBM_STATUS);
2725 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2726 /* restore PCI & busmastering */
2727 pci_restore_state(rdev->pdev);
2728 r100_enable_bm(rdev);
2729 /* Check if GPU is idle */
2730 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2731 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2732 dev_err(rdev->dev, "failed to reset GPU\n");
2735 dev_info(rdev->dev, "GPU reset succeed\n");
2736 r100_mc_resume(rdev, &save);
2740 void r100_set_common_regs(struct radeon_device *rdev)
2742 struct drm_device *dev = rdev->ddev;
2743 bool force_dac2 = false;
2746 /* set these so they don't interfere with anything */
2747 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2748 WREG32(RADEON_SUBPIC_CNTL, 0);
2749 WREG32(RADEON_VIPH_CONTROL, 0);
2750 WREG32(RADEON_I2C_CNTL_1, 0);
2751 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2752 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2753 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2755 /* always set up dac2 on rn50 and some rv100 as lots
2756 * of servers seem to wire it up to a VGA port but
2757 * don't report it in the bios connector
2760 switch (dev->pdev->device) {
2769 /* DELL triple head servers */
2770 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2771 ((dev->pdev->subsystem_device == 0x016c) ||
2772 (dev->pdev->subsystem_device == 0x016d) ||
2773 (dev->pdev->subsystem_device == 0x016e) ||
2774 (dev->pdev->subsystem_device == 0x016f) ||
2775 (dev->pdev->subsystem_device == 0x0170) ||
2776 (dev->pdev->subsystem_device == 0x017d) ||
2777 (dev->pdev->subsystem_device == 0x017e) ||
2778 (dev->pdev->subsystem_device == 0x0183) ||
2779 (dev->pdev->subsystem_device == 0x018a) ||
2780 (dev->pdev->subsystem_device == 0x019a)))
2786 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2787 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2788 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2790 /* For CRT on DAC2, don't turn it on if BIOS didn't
2791 enable it, even it's detected.
2794 /* force it to crtc0 */
2795 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2796 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2797 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2799 /* set up the TV DAC */
2800 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2801 RADEON_TV_DAC_STD_MASK |
2802 RADEON_TV_DAC_RDACPD |
2803 RADEON_TV_DAC_GDACPD |
2804 RADEON_TV_DAC_BDACPD |
2805 RADEON_TV_DAC_BGADJ_MASK |
2806 RADEON_TV_DAC_DACADJ_MASK);
2807 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2808 RADEON_TV_DAC_NHOLD |
2809 RADEON_TV_DAC_STD_PS2 |
2812 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2813 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2814 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2817 /* switch PM block to ACPI mode */
2818 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2819 tmp &= ~RADEON_PM_MODE_SEL;
2820 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2827 static void r100_vram_get_type(struct radeon_device *rdev)
2831 rdev->mc.vram_is_ddr = false;
2832 if (rdev->flags & RADEON_IS_IGP)
2833 rdev->mc.vram_is_ddr = true;
2834 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2835 rdev->mc.vram_is_ddr = true;
2836 if ((rdev->family == CHIP_RV100) ||
2837 (rdev->family == CHIP_RS100) ||
2838 (rdev->family == CHIP_RS200)) {
2839 tmp = RREG32(RADEON_MEM_CNTL);
2840 if (tmp & RV100_HALF_MODE) {
2841 rdev->mc.vram_width = 32;
2843 rdev->mc.vram_width = 64;
2845 if (rdev->flags & RADEON_SINGLE_CRTC) {
2846 rdev->mc.vram_width /= 4;
2847 rdev->mc.vram_is_ddr = true;
2849 } else if (rdev->family <= CHIP_RV280) {
2850 tmp = RREG32(RADEON_MEM_CNTL);
2851 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2852 rdev->mc.vram_width = 128;
2854 rdev->mc.vram_width = 64;
2858 rdev->mc.vram_width = 128;
2862 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2867 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2869 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2870 * that is has the 2nd generation multifunction PCI interface
2872 if (rdev->family == CHIP_RV280 ||
2873 rdev->family >= CHIP_RV350) {
2874 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2875 ~RADEON_HDP_APER_CNTL);
2876 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2877 return aper_size * 2;
2880 /* Older cards have all sorts of funny issues to deal with. First
2881 * check if it's a multifunction card by reading the PCI config
2882 * header type... Limit those to one aperture size
2884 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2886 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2887 DRM_INFO("Limiting VRAM to one aperture\n");
2891 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2892 * have set it up. We don't write this as it's broken on some ASICs but
2893 * we expect the BIOS to have done the right thing (might be too optimistic...)
2895 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2896 return aper_size * 2;
2900 void r100_vram_init_sizes(struct radeon_device *rdev)
2902 u64 config_aper_size;
2904 /* work out accessible VRAM */
2905 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2906 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2907 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2908 /* FIXME we don't use the second aperture yet when we could use it */
2909 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2910 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2911 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2912 if (rdev->flags & RADEON_IS_IGP) {
2914 /* read NB_TOM to get the amount of ram stolen for the GPU */
2915 tom = RREG32(RADEON_NB_TOM);
2916 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2917 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2918 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2920 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2921 /* Some production boards of m6 will report 0
2924 if (rdev->mc.real_vram_size == 0) {
2925 rdev->mc.real_vram_size = 8192 * 1024;
2926 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2928 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2929 * Novell bug 204882 + along with lots of ubuntu ones
2931 if (rdev->mc.aper_size > config_aper_size)
2932 config_aper_size = rdev->mc.aper_size;
2934 if (config_aper_size > rdev->mc.real_vram_size)
2935 rdev->mc.mc_vram_size = config_aper_size;
2937 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2941 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2945 temp = RREG32(RADEON_CONFIG_CNTL);
2946 if (state == false) {
2947 temp &= ~RADEON_CFG_VGA_RAM_EN;
2948 temp |= RADEON_CFG_VGA_IO_DIS;
2950 temp &= ~RADEON_CFG_VGA_IO_DIS;
2952 WREG32(RADEON_CONFIG_CNTL, temp);
2955 void r100_mc_init(struct radeon_device *rdev)
2959 r100_vram_get_type(rdev);
2960 r100_vram_init_sizes(rdev);
2961 base = rdev->mc.aper_base;
2962 if (rdev->flags & RADEON_IS_IGP)
2963 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2964 radeon_vram_location(rdev, &rdev->mc, base);
2965 rdev->mc.gtt_base_align = 0;
2966 if (!(rdev->flags & RADEON_IS_AGP))
2967 radeon_gtt_location(rdev, &rdev->mc);
2968 radeon_update_bandwidth_info(rdev);
2973 * Indirect registers accessor
2975 void r100_pll_errata_after_index(struct radeon_device *rdev)
2977 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2978 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2979 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2983 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2985 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2986 * or the chip could hang on a subsequent access
2988 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2992 /* This function is required to workaround a hardware bug in some (all?)
2993 * revisions of the R300. This workaround should be called after every
2994 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2995 * may not be correct.
2997 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
3000 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
3001 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
3002 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
3003 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
3004 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
3008 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
3012 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
3013 r100_pll_errata_after_index(rdev);
3014 data = RREG32(RADEON_CLOCK_CNTL_DATA);
3015 r100_pll_errata_after_data(rdev);
3019 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
3021 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
3022 r100_pll_errata_after_index(rdev);
3023 WREG32(RADEON_CLOCK_CNTL_DATA, v);
3024 r100_pll_errata_after_data(rdev);
3027 void r100_set_safe_registers(struct radeon_device *rdev)
3029 if (ASIC_IS_RN50(rdev)) {
3030 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
3031 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
3032 } else if (rdev->family < CHIP_R200) {
3033 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
3034 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
3036 r200_set_safe_registers(rdev);
3043 #if defined(CONFIG_DEBUG_FS)
3044 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
3046 struct drm_info_node *node = (struct drm_info_node *) m->private;
3047 struct drm_device *dev = node->minor->dev;
3048 struct radeon_device *rdev = dev->dev_private;
3049 uint32_t reg, value;
3052 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
3053 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
3054 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3055 for (i = 0; i < 64; i++) {
3056 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
3057 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
3058 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
3059 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
3060 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
3065 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
3067 struct drm_info_node *node = (struct drm_info_node *) m->private;
3068 struct drm_device *dev = node->minor->dev;
3069 struct radeon_device *rdev = dev->dev_private;
3070 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3072 unsigned count, i, j;
3074 radeon_ring_free_size(rdev, ring);
3075 rdp = RREG32(RADEON_CP_RB_RPTR);
3076 wdp = RREG32(RADEON_CP_RB_WPTR);
3077 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
3078 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3079 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
3080 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
3081 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
3082 seq_printf(m, "%u dwords in ring\n", count);
3083 for (j = 0; j <= count; j++) {
3084 i = (rdp + j) & ring->ptr_mask;
3085 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
3091 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
3093 struct drm_info_node *node = (struct drm_info_node *) m->private;
3094 struct drm_device *dev = node->minor->dev;
3095 struct radeon_device *rdev = dev->dev_private;
3096 uint32_t csq_stat, csq2_stat, tmp;
3097 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
3100 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3101 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
3102 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
3103 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
3104 r_rptr = (csq_stat >> 0) & 0x3ff;
3105 r_wptr = (csq_stat >> 10) & 0x3ff;
3106 ib1_rptr = (csq_stat >> 20) & 0x3ff;
3107 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
3108 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
3109 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
3110 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
3111 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
3112 seq_printf(m, "Ring rptr %u\n", r_rptr);
3113 seq_printf(m, "Ring wptr %u\n", r_wptr);
3114 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
3115 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
3116 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3117 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3118 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3119 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3120 seq_printf(m, "Ring fifo:\n");
3121 for (i = 0; i < 256; i++) {
3122 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3123 tmp = RREG32(RADEON_CP_CSQ_DATA);
3124 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3126 seq_printf(m, "Indirect1 fifo:\n");
3127 for (i = 256; i <= 512; i++) {
3128 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3129 tmp = RREG32(RADEON_CP_CSQ_DATA);
3130 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3132 seq_printf(m, "Indirect2 fifo:\n");
3133 for (i = 640; i < ib1_wptr; i++) {
3134 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3135 tmp = RREG32(RADEON_CP_CSQ_DATA);
3136 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3141 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3143 struct drm_info_node *node = (struct drm_info_node *) m->private;
3144 struct drm_device *dev = node->minor->dev;
3145 struct radeon_device *rdev = dev->dev_private;
3148 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3149 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3150 tmp = RREG32(RADEON_MC_FB_LOCATION);
3151 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3152 tmp = RREG32(RADEON_BUS_CNTL);
3153 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3154 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3155 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3156 tmp = RREG32(RADEON_AGP_BASE);
3157 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3158 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3159 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3160 tmp = RREG32(0x01D0);
3161 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3162 tmp = RREG32(RADEON_AIC_LO_ADDR);
3163 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3164 tmp = RREG32(RADEON_AIC_HI_ADDR);
3165 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3166 tmp = RREG32(0x01E4);
3167 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3171 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3172 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3175 static struct drm_info_list r100_debugfs_cp_list[] = {
3176 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3177 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3180 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3181 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3185 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3187 #if defined(CONFIG_DEBUG_FS)
3188 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3194 int r100_debugfs_cp_init(struct radeon_device *rdev)
3196 #if defined(CONFIG_DEBUG_FS)
3197 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3203 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3205 #if defined(CONFIG_DEBUG_FS)
3206 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3212 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3213 uint32_t tiling_flags, uint32_t pitch,
3214 uint32_t offset, uint32_t obj_size)
3216 int surf_index = reg * 16;
3219 if (rdev->family <= CHIP_RS200) {
3220 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3221 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3222 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3223 if (tiling_flags & RADEON_TILING_MACRO)
3224 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3225 } else if (rdev->family <= CHIP_RV280) {
3226 if (tiling_flags & (RADEON_TILING_MACRO))
3227 flags |= R200_SURF_TILE_COLOR_MACRO;
3228 if (tiling_flags & RADEON_TILING_MICRO)
3229 flags |= R200_SURF_TILE_COLOR_MICRO;
3231 if (tiling_flags & RADEON_TILING_MACRO)
3232 flags |= R300_SURF_TILE_MACRO;
3233 if (tiling_flags & RADEON_TILING_MICRO)
3234 flags |= R300_SURF_TILE_MICRO;
3237 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3238 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3239 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3240 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3242 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
3243 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
3244 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
3245 if (ASIC_IS_RN50(rdev))
3249 /* r100/r200 divide by 16 */
3250 if (rdev->family < CHIP_R300)
3251 flags |= pitch / 16;
3256 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3257 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3258 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3259 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3263 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3265 int surf_index = reg * 16;
3266 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3269 void r100_bandwidth_update(struct radeon_device *rdev)
3271 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3272 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3273 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3274 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3275 fixed20_12 memtcas_ff[8] = {
3280 dfixed_init_half(1),
3281 dfixed_init_half(2),
3284 fixed20_12 memtcas_rs480_ff[8] = {
3290 dfixed_init_half(1),
3291 dfixed_init_half(2),
3292 dfixed_init_half(3),
3294 fixed20_12 memtcas2_ff[8] = {
3304 fixed20_12 memtrbs[8] = {
3306 dfixed_init_half(1),
3308 dfixed_init_half(2),
3310 dfixed_init_half(3),
3314 fixed20_12 memtrbs_r4xx[8] = {
3324 fixed20_12 min_mem_eff;
3325 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3326 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3327 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3328 disp_drain_rate2, read_return_rate;
3329 fixed20_12 time_disp1_drop_priority;
3331 int cur_size = 16; /* in octawords */
3332 int critical_point = 0, critical_point2;
3333 /* uint32_t read_return_rate, time_disp1_drop_priority; */
3334 int stop_req, max_stop_req;
3335 struct drm_display_mode *mode1 = NULL;
3336 struct drm_display_mode *mode2 = NULL;
3337 uint32_t pixel_bytes1 = 0;
3338 uint32_t pixel_bytes2 = 0;
3340 radeon_update_display_priority(rdev);
3342 if (rdev->mode_info.crtcs[0]->base.enabled) {
3343 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3344 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
3346 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3347 if (rdev->mode_info.crtcs[1]->base.enabled) {
3348 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3349 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
3353 min_mem_eff.full = dfixed_const_8(0);
3355 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3356 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3357 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3358 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3359 /* check crtc enables */
3361 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3363 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3364 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3368 * determine is there is enough bw for current mode
3370 sclk_ff = rdev->pm.sclk;
3371 mclk_ff = rdev->pm.mclk;
3373 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3374 temp_ff.full = dfixed_const(temp);
3375 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3379 peak_disp_bw.full = 0;
3381 temp_ff.full = dfixed_const(1000);
3382 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3383 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3384 temp_ff.full = dfixed_const(pixel_bytes1);
3385 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3388 temp_ff.full = dfixed_const(1000);
3389 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3390 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3391 temp_ff.full = dfixed_const(pixel_bytes2);
3392 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3395 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3396 if (peak_disp_bw.full >= mem_bw.full) {
3397 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3398 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3401 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3402 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3403 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3404 mem_trcd = ((temp >> 2) & 0x3) + 1;
3405 mem_trp = ((temp & 0x3)) + 1;
3406 mem_tras = ((temp & 0x70) >> 4) + 1;
3407 } else if (rdev->family == CHIP_R300 ||
3408 rdev->family == CHIP_R350) { /* r300, r350 */
3409 mem_trcd = (temp & 0x7) + 1;
3410 mem_trp = ((temp >> 8) & 0x7) + 1;
3411 mem_tras = ((temp >> 11) & 0xf) + 4;
3412 } else if (rdev->family == CHIP_RV350 ||
3413 rdev->family <= CHIP_RV380) {
3415 mem_trcd = (temp & 0x7) + 3;
3416 mem_trp = ((temp >> 8) & 0x7) + 3;
3417 mem_tras = ((temp >> 11) & 0xf) + 6;
3418 } else if (rdev->family == CHIP_R420 ||
3419 rdev->family == CHIP_R423 ||
3420 rdev->family == CHIP_RV410) {
3422 mem_trcd = (temp & 0xf) + 3;
3425 mem_trp = ((temp >> 8) & 0xf) + 3;
3428 mem_tras = ((temp >> 12) & 0x1f) + 6;
3431 } else { /* RV200, R200 */
3432 mem_trcd = (temp & 0x7) + 1;
3433 mem_trp = ((temp >> 8) & 0x7) + 1;
3434 mem_tras = ((temp >> 12) & 0xf) + 4;
3437 trcd_ff.full = dfixed_const(mem_trcd);
3438 trp_ff.full = dfixed_const(mem_trp);
3439 tras_ff.full = dfixed_const(mem_tras);
3441 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3442 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3443 data = (temp & (7 << 20)) >> 20;
3444 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3445 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3446 tcas_ff = memtcas_rs480_ff[data];
3448 tcas_ff = memtcas_ff[data];
3450 tcas_ff = memtcas2_ff[data];
3452 if (rdev->family == CHIP_RS400 ||
3453 rdev->family == CHIP_RS480) {
3454 /* extra cas latency stored in bits 23-25 0-4 clocks */
3455 data = (temp >> 23) & 0x7;
3457 tcas_ff.full += dfixed_const(data);
3460 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3461 /* on the R300, Tcas is included in Trbs.
3463 temp = RREG32(RADEON_MEM_CNTL);
3464 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3466 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3467 temp = RREG32(R300_MC_IND_INDEX);
3468 temp &= ~R300_MC_IND_ADDR_MASK;
3469 temp |= R300_MC_READ_CNTL_CD_mcind;
3470 WREG32(R300_MC_IND_INDEX, temp);
3471 temp = RREG32(R300_MC_IND_DATA);
3472 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3474 temp = RREG32(R300_MC_READ_CNTL_AB);
3475 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3478 temp = RREG32(R300_MC_READ_CNTL_AB);
3479 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3481 if (rdev->family == CHIP_RV410 ||
3482 rdev->family == CHIP_R420 ||
3483 rdev->family == CHIP_R423)
3484 trbs_ff = memtrbs_r4xx[data];
3486 trbs_ff = memtrbs[data];
3487 tcas_ff.full += trbs_ff.full;
3490 sclk_eff_ff.full = sclk_ff.full;
3492 if (rdev->flags & RADEON_IS_AGP) {
3493 fixed20_12 agpmode_ff;
3494 agpmode_ff.full = dfixed_const(radeon_agpmode);
3495 temp_ff.full = dfixed_const_666(16);
3496 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3498 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3500 if (ASIC_IS_R300(rdev)) {
3501 sclk_delay_ff.full = dfixed_const(250);
3503 if ((rdev->family == CHIP_RV100) ||
3504 rdev->flags & RADEON_IS_IGP) {
3505 if (rdev->mc.vram_is_ddr)
3506 sclk_delay_ff.full = dfixed_const(41);
3508 sclk_delay_ff.full = dfixed_const(33);
3510 if (rdev->mc.vram_width == 128)
3511 sclk_delay_ff.full = dfixed_const(57);
3513 sclk_delay_ff.full = dfixed_const(41);
3517 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3519 if (rdev->mc.vram_is_ddr) {
3520 if (rdev->mc.vram_width == 32) {
3521 k1.full = dfixed_const(40);
3524 k1.full = dfixed_const(20);
3528 k1.full = dfixed_const(40);
3532 temp_ff.full = dfixed_const(2);
3533 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3534 temp_ff.full = dfixed_const(c);
3535 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3536 temp_ff.full = dfixed_const(4);
3537 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3538 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3539 mc_latency_mclk.full += k1.full;
3541 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3542 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3545 HW cursor time assuming worst case of full size colour cursor.
3547 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3548 temp_ff.full += trcd_ff.full;
3549 if (temp_ff.full < tras_ff.full)
3550 temp_ff.full = tras_ff.full;
3551 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3553 temp_ff.full = dfixed_const(cur_size);
3554 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3556 Find the total latency for the display data.
3558 disp_latency_overhead.full = dfixed_const(8);
3559 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3560 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3561 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3563 if (mc_latency_mclk.full > mc_latency_sclk.full)
3564 disp_latency.full = mc_latency_mclk.full;
3566 disp_latency.full = mc_latency_sclk.full;
3568 /* setup Max GRPH_STOP_REQ default value */
3569 if (ASIC_IS_RV100(rdev))
3570 max_stop_req = 0x5c;
3572 max_stop_req = 0x7c;
3576 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3577 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3579 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3581 if (stop_req > max_stop_req)
3582 stop_req = max_stop_req;
3585 Find the drain rate of the display buffer.
3587 temp_ff.full = dfixed_const((16/pixel_bytes1));
3588 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3591 Find the critical point of the display buffer.
3593 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3594 crit_point_ff.full += dfixed_const_half(0);
3596 critical_point = dfixed_trunc(crit_point_ff);
3598 if (rdev->disp_priority == 2) {
3603 The critical point should never be above max_stop_req-4. Setting
3604 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3606 if (max_stop_req - critical_point < 4)
3609 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3610 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3611 critical_point = 0x10;
3614 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3615 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3616 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3617 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3618 if ((rdev->family == CHIP_R350) &&
3619 (stop_req > 0x15)) {
3622 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3623 temp |= RADEON_GRPH_BUFFER_SIZE;
3624 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3625 RADEON_GRPH_CRITICAL_AT_SOF |
3626 RADEON_GRPH_STOP_CNTL);
3628 Write the result into the register.
3630 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3631 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3634 if ((rdev->family == CHIP_RS400) ||
3635 (rdev->family == CHIP_RS480)) {
3636 /* attempt to program RS400 disp regs correctly ??? */
3637 temp = RREG32(RS400_DISP1_REG_CNTL);
3638 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3639 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3640 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3641 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3642 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3643 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3644 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3645 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3646 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3647 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3648 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3652 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3653 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3654 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3659 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3661 if (stop_req > max_stop_req)
3662 stop_req = max_stop_req;
3665 Find the drain rate of the display buffer.
3667 temp_ff.full = dfixed_const((16/pixel_bytes2));
3668 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3670 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3671 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3672 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3673 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3674 if ((rdev->family == CHIP_R350) &&
3675 (stop_req > 0x15)) {
3678 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3679 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3680 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3681 RADEON_GRPH_CRITICAL_AT_SOF |
3682 RADEON_GRPH_STOP_CNTL);
3684 if ((rdev->family == CHIP_RS100) ||
3685 (rdev->family == CHIP_RS200))
3686 critical_point2 = 0;
3688 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3689 temp_ff.full = dfixed_const(temp);
3690 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3691 if (sclk_ff.full < temp_ff.full)
3692 temp_ff.full = sclk_ff.full;
3694 read_return_rate.full = temp_ff.full;
3697 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3698 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3700 time_disp1_drop_priority.full = 0;
3702 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3703 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3704 crit_point_ff.full += dfixed_const_half(0);
3706 critical_point2 = dfixed_trunc(crit_point_ff);
3708 if (rdev->disp_priority == 2) {
3709 critical_point2 = 0;
3712 if (max_stop_req - critical_point2 < 4)
3713 critical_point2 = 0;
3717 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3718 /* some R300 cards have problem with this set to 0 */
3719 critical_point2 = 0x10;
3722 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3723 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3725 if ((rdev->family == CHIP_RS400) ||
3726 (rdev->family == CHIP_RS480)) {
3728 /* attempt to program RS400 disp2 regs correctly ??? */
3729 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3730 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3731 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3732 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3733 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3734 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3735 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3736 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3737 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3738 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3739 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3740 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3742 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3743 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3744 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3745 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3748 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3749 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3753 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3760 r = radeon_scratch_get(rdev, &scratch);
3762 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3765 WREG32(scratch, 0xCAFEDEAD);
3766 r = radeon_ring_lock(rdev, ring, 2);
3768 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3769 radeon_scratch_free(rdev, scratch);
3772 radeon_ring_write(ring, PACKET0(scratch, 0));
3773 radeon_ring_write(ring, 0xDEADBEEF);
3774 radeon_ring_unlock_commit(rdev, ring);
3775 for (i = 0; i < rdev->usec_timeout; i++) {
3776 tmp = RREG32(scratch);
3777 if (tmp == 0xDEADBEEF) {
3782 if (i < rdev->usec_timeout) {
3783 DRM_INFO("ring test succeeded in %d usecs\n", i);
3785 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3789 radeon_scratch_free(rdev, scratch);
3793 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3795 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3797 if (ring->rptr_save_reg) {
3798 u32 next_rptr = ring->wptr + 2 + 3;
3799 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3800 radeon_ring_write(ring, next_rptr);
3803 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3804 radeon_ring_write(ring, ib->gpu_addr);
3805 radeon_ring_write(ring, ib->length_dw);
3808 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3810 struct radeon_ib ib;
3816 r = radeon_scratch_get(rdev, &scratch);
3818 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3821 WREG32(scratch, 0xCAFEDEAD);
3822 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
3826 ib.ptr[0] = PACKET0(scratch, 0);
3827 ib.ptr[1] = 0xDEADBEEF;
3828 ib.ptr[2] = PACKET2(0);
3829 ib.ptr[3] = PACKET2(0);
3830 ib.ptr[4] = PACKET2(0);
3831 ib.ptr[5] = PACKET2(0);
3832 ib.ptr[6] = PACKET2(0);
3833 ib.ptr[7] = PACKET2(0);
3835 r = radeon_ib_schedule(rdev, &ib, NULL);
3837 radeon_scratch_free(rdev, scratch);
3838 radeon_ib_free(rdev, &ib);
3841 r = radeon_fence_wait(ib.fence, false);
3845 for (i = 0; i < rdev->usec_timeout; i++) {
3846 tmp = RREG32(scratch);
3847 if (tmp == 0xDEADBEEF) {
3852 if (i < rdev->usec_timeout) {
3853 DRM_INFO("ib test succeeded in %u usecs\n", i);
3855 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3859 radeon_scratch_free(rdev, scratch);
3860 radeon_ib_free(rdev, &ib);
3864 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3866 /* Shutdown CP we shouldn't need to do that but better be safe than
3869 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3870 WREG32(R_000740_CP_CSQ_CNTL, 0);
3872 /* Save few CRTC registers */
3873 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3874 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3875 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3876 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3877 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3878 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3879 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3882 /* Disable VGA aperture access */
3883 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3884 /* Disable cursor, overlay, crtc */
3885 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3886 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3887 S_000054_CRTC_DISPLAY_DIS(1));
3888 WREG32(R_000050_CRTC_GEN_CNTL,
3889 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3890 S_000050_CRTC_DISP_REQ_EN_B(1));
3891 WREG32(R_000420_OV0_SCALE_CNTL,
3892 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3893 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3894 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3895 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3896 S_000360_CUR2_LOCK(1));
3897 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3898 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3899 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3900 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3901 WREG32(R_000360_CUR2_OFFSET,
3902 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3906 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3908 /* Update base address for crtc */
3909 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3910 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3911 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3913 /* Restore CRTC registers */
3914 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3915 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3916 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3917 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3918 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3922 void r100_vga_render_disable(struct radeon_device *rdev)
3926 tmp = RREG8(R_0003C2_GENMO_WT);
3927 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3930 static void r100_debugfs(struct radeon_device *rdev)
3934 r = r100_debugfs_mc_info_init(rdev);
3936 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3939 static void r100_mc_program(struct radeon_device *rdev)
3941 struct r100_mc_save save;
3943 /* Stops all mc clients */
3944 r100_mc_stop(rdev, &save);
3945 if (rdev->flags & RADEON_IS_AGP) {
3946 WREG32(R_00014C_MC_AGP_LOCATION,
3947 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3948 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3949 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3950 if (rdev->family > CHIP_RV200)
3951 WREG32(R_00015C_AGP_BASE_2,
3952 upper_32_bits(rdev->mc.agp_base) & 0xff);
3954 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3955 WREG32(R_000170_AGP_BASE, 0);
3956 if (rdev->family > CHIP_RV200)
3957 WREG32(R_00015C_AGP_BASE_2, 0);
3959 /* Wait for mc idle */
3960 if (r100_mc_wait_for_idle(rdev))
3961 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3962 /* Program MC, should be a 32bits limited address space */
3963 WREG32(R_000148_MC_FB_LOCATION,
3964 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3965 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3966 r100_mc_resume(rdev, &save);
3969 void r100_clock_startup(struct radeon_device *rdev)
3973 if (radeon_dynclks != -1 && radeon_dynclks)
3974 radeon_legacy_set_clock_gating(rdev, 1);
3975 /* We need to force on some of the block */
3976 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3977 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3978 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3979 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3980 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3983 static int r100_startup(struct radeon_device *rdev)
3987 /* set common regs */
3988 r100_set_common_regs(rdev);
3990 r100_mc_program(rdev);
3992 r100_clock_startup(rdev);
3993 /* Initialize GART (initialize after TTM so we can allocate
3994 * memory through TTM but finalize after TTM) */
3995 r100_enable_bm(rdev);
3996 if (rdev->flags & RADEON_IS_PCI) {
3997 r = r100_pci_gart_enable(rdev);
4002 /* allocate wb buffer */
4003 r = radeon_wb_init(rdev);
4007 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
4009 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4015 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
4016 /* 1M ring buffer */
4017 r = r100_cp_init(rdev, 1024 * 1024);
4019 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
4023 r = radeon_ib_pool_init(rdev);
4025 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4032 int r100_resume(struct radeon_device *rdev)
4036 /* Make sur GART are not working */
4037 if (rdev->flags & RADEON_IS_PCI)
4038 r100_pci_gart_disable(rdev);
4039 /* Resume clock before doing reset */
4040 r100_clock_startup(rdev);
4041 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4042 if (radeon_asic_reset(rdev)) {
4043 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4044 RREG32(R_000E40_RBBM_STATUS),
4045 RREG32(R_0007C0_CP_STAT));
4048 radeon_combios_asic_init(rdev->ddev);
4049 /* Resume clock after posting */
4050 r100_clock_startup(rdev);
4051 /* Initialize surface registers */
4052 radeon_surface_init(rdev);
4054 rdev->accel_working = true;
4055 r = r100_startup(rdev);
4057 rdev->accel_working = false;
4062 int r100_suspend(struct radeon_device *rdev)
4064 r100_cp_disable(rdev);
4065 radeon_wb_disable(rdev);
4066 r100_irq_disable(rdev);
4067 if (rdev->flags & RADEON_IS_PCI)
4068 r100_pci_gart_disable(rdev);
4072 void r100_fini(struct radeon_device *rdev)
4075 radeon_wb_fini(rdev);
4076 radeon_ib_pool_fini(rdev);
4077 radeon_gem_fini(rdev);
4078 if (rdev->flags & RADEON_IS_PCI)
4079 r100_pci_gart_fini(rdev);
4080 radeon_agp_fini(rdev);
4081 radeon_irq_kms_fini(rdev);
4082 radeon_fence_driver_fini(rdev);
4083 radeon_bo_fini(rdev);
4084 radeon_atombios_fini(rdev);
4090 * Due to how kexec works, it can leave the hw fully initialised when it
4091 * boots the new kernel. However doing our init sequence with the CP and
4092 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
4093 * do some quick sanity checks and restore sane values to avoid this
4096 void r100_restore_sanity(struct radeon_device *rdev)
4100 tmp = RREG32(RADEON_CP_CSQ_CNTL);
4102 WREG32(RADEON_CP_CSQ_CNTL, 0);
4104 tmp = RREG32(RADEON_CP_RB_CNTL);
4106 WREG32(RADEON_CP_RB_CNTL, 0);
4108 tmp = RREG32(RADEON_SCRATCH_UMSK);
4110 WREG32(RADEON_SCRATCH_UMSK, 0);
4114 int r100_init(struct radeon_device *rdev)
4118 /* Register debugfs file specific to this group of asics */
4121 r100_vga_render_disable(rdev);
4122 /* Initialize scratch registers */
4123 radeon_scratch_init(rdev);
4124 /* Initialize surface registers */
4125 radeon_surface_init(rdev);
4126 /* sanity check some register to avoid hangs like after kexec */
4127 r100_restore_sanity(rdev);
4128 /* TODO: disable VGA need to use VGA request */
4130 if (!radeon_get_bios(rdev)) {
4131 if (ASIC_IS_AVIVO(rdev))
4134 if (rdev->is_atom_bios) {
4135 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4138 r = radeon_combios_init(rdev);
4142 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4143 if (radeon_asic_reset(rdev)) {
4145 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4146 RREG32(R_000E40_RBBM_STATUS),
4147 RREG32(R_0007C0_CP_STAT));
4149 /* check if cards are posted or not */
4150 if (radeon_boot_test_post_card(rdev) == false)
4152 /* Set asic errata */
4154 /* Initialize clocks */
4155 radeon_get_clock_info(rdev->ddev);
4156 /* initialize AGP */
4157 if (rdev->flags & RADEON_IS_AGP) {
4158 r = radeon_agp_init(rdev);
4160 radeon_agp_disable(rdev);
4163 /* initialize VRAM */
4166 r = radeon_fence_driver_init(rdev);
4169 r = radeon_irq_kms_init(rdev);
4172 /* Memory manager */
4173 r = radeon_bo_init(rdev);
4176 if (rdev->flags & RADEON_IS_PCI) {
4177 r = r100_pci_gart_init(rdev);
4181 r100_set_safe_registers(rdev);
4183 rdev->accel_working = true;
4184 r = r100_startup(rdev);
4186 /* Somethings want wront with the accel init stop accel */
4187 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4189 radeon_wb_fini(rdev);
4190 radeon_ib_pool_fini(rdev);
4191 radeon_irq_kms_fini(rdev);
4192 if (rdev->flags & RADEON_IS_PCI)
4193 r100_pci_gart_fini(rdev);
4194 rdev->accel_working = false;
4199 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4201 if (reg < rdev->rmmio_size)
4202 return readl(((void __iomem *)rdev->rmmio) + reg);
4204 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4205 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4209 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4211 if (reg < rdev->rmmio_size)
4212 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4214 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4215 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4219 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4221 if (reg < rdev->rio_mem_size)
4222 return ioread32(rdev->rio_mem + reg);
4224 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4225 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4229 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4231 if (reg < rdev->rio_mem_size)
4232 iowrite32(v, rdev->rio_mem + reg);
4234 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4235 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);