drivers/gpu/drm/radeon/ni.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include <drm/radeon_drm.h>
  32 #include "nid.h"
  33 #include "atom.h"
  34 #include "ni_reg.h"
  35 #include "cayman_blit_shaders.h"
  36
  37 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  38 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  39 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
  40 extern void evergreen_mc_program(struct radeon_device *rdev);
  41 extern void evergreen_irq_suspend(struct radeon_device *rdev);
  42 extern int evergreen_mc_init(struct radeon_device *rdev);
  43 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  44 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  45 extern void si_rlc_fini(struct radeon_device *rdev);
  46 extern int si_rlc_init(struct radeon_device *rdev);
  47
  48 #define EVERGREEN_PFP_UCODE_SIZE 1120
  49 #define EVERGREEN_PM4_UCODE_SIZE 1376
  50 #define EVERGREEN_RLC_UCODE_SIZE 768
  51 #define BTC_MC_UCODE_SIZE 6024
  52
  53 #define CAYMAN_PFP_UCODE_SIZE 2176
  54 #define CAYMAN_PM4_UCODE_SIZE 2176
  55 #define CAYMAN_RLC_UCODE_SIZE 1024
  56 #define CAYMAN_MC_UCODE_SIZE 6037
  57
  58 #define ARUBA_RLC_UCODE_SIZE 1536
  59
  60 /* Firmware Names */
  61 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
  62 MODULE_FIRMWARE("radeon/BARTS_me.bin");
  63 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
  64 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
  65 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
  66 MODULE_FIRMWARE("radeon/TURKS_me.bin");
  67 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
  68 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
  69 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
  70 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
  71 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
  72 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
  73 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
  74 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
  75 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
  76 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
  77 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
  78
  79 #define BTC_IO_MC_REGS_SIZE 29
  80
  81 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  82         {0x00000077, 0xff010100},
  83         {0x00000078, 0x00000000},
  84         {0x00000079, 0x00001434},
  85         {0x0000007a, 0xcc08ec08},
  86         {0x0000007b, 0x00040000},
  87         {0x0000007c, 0x000080c0},
  88         {0x0000007d, 0x09000000},
  89         {0x0000007e, 0x00210404},
  90         {0x00000081, 0x08a8e800},
  91         {0x00000082, 0x00030444},
  92         {0x00000083, 0x00000000},
  93         {0x00000085, 0x00000001},
  94         {0x00000086, 0x00000002},
  95         {0x00000087, 0x48490000},
  96         {0x00000088, 0x20244647},
  97         {0x00000089, 0x00000005},
  98         {0x0000008b, 0x66030000},
  99         {0x0000008c, 0x00006603},
 100         {0x0000008d, 0x00000100},
 101         {0x0000008f, 0x00001c0a},
 102         {0x00000090, 0xff000001},
 103         {0x00000094, 0x00101101},
 104         {0x00000095, 0x00000fff},
 105         {0x00000096, 0x00116fff},
 106         {0x00000097, 0x60010000},
 107         {0x00000098, 0x10010000},
 108         {0x00000099, 0x00006000},
 109         {0x0000009a, 0x00001000},
 110         {0x0000009f, 0x00946a00}
 111 };
 112
 113 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 114         {0x00000077, 0xff010100},
 115         {0x00000078, 0x00000000},
 116         {0x00000079, 0x00001434},
 117         {0x0000007a, 0xcc08ec08},
 118         {0x0000007b, 0x00040000},
 119         {0x0000007c, 0x000080c0},
 120         {0x0000007d, 0x09000000},
 121         {0x0000007e, 0x00210404},
 122         {0x00000081, 0x08a8e800},
 123         {0x00000082, 0x00030444},
 124         {0x00000083, 0x00000000},
 125         {0x00000085, 0x00000001},
 126         {0x00000086, 0x00000002},
 127         {0x00000087, 0x48490000},
 128         {0x00000088, 0x20244647},
 129         {0x00000089, 0x00000005},
 130         {0x0000008b, 0x66030000},
 131         {0x0000008c, 0x00006603},
 132         {0x0000008d, 0x00000100},
 133         {0x0000008f, 0x00001c0a},
 134         {0x00000090, 0xff000001},
 135         {0x00000094, 0x00101101},
 136         {0x00000095, 0x00000fff},
 137         {0x00000096, 0x00116fff},
 138         {0x00000097, 0x60010000},
 139         {0x00000098, 0x10010000},
 140         {0x00000099, 0x00006000},
 141         {0x0000009a, 0x00001000},
 142         {0x0000009f, 0x00936a00}
 143 };
 144
 145 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 146         {0x00000077, 0xff010100},
 147         {0x00000078, 0x00000000},
 148         {0x00000079, 0x00001434},
 149         {0x0000007a, 0xcc08ec08},
 150         {0x0000007b, 0x00040000},
 151         {0x0000007c, 0x000080c0},
 152         {0x0000007d, 0x09000000},
 153         {0x0000007e, 0x00210404},
 154         {0x00000081, 0x08a8e800},
 155         {0x00000082, 0x00030444},
 156         {0x00000083, 0x00000000},
 157         {0x00000085, 0x00000001},
 158         {0x00000086, 0x00000002},
 159         {0x00000087, 0x48490000},
 160         {0x00000088, 0x20244647},
 161         {0x00000089, 0x00000005},
 162         {0x0000008b, 0x66030000},
 163         {0x0000008c, 0x00006603},
 164         {0x0000008d, 0x00000100},
 165         {0x0000008f, 0x00001c0a},
 166         {0x00000090, 0xff000001},
 167         {0x00000094, 0x00101101},
 168         {0x00000095, 0x00000fff},
 169         {0x00000096, 0x00116fff},
 170         {0x00000097, 0x60010000},
 171         {0x00000098, 0x10010000},
 172         {0x00000099, 0x00006000},
 173         {0x0000009a, 0x00001000},
 174         {0x0000009f, 0x00916a00}
 175 };
 176
 177 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 178         {0x00000077, 0xff010100},
 179         {0x00000078, 0x00000000},
 180         {0x00000079, 0x00001434},
 181         {0x0000007a, 0xcc08ec08},
 182         {0x0000007b, 0x00040000},
 183         {0x0000007c, 0x000080c0},
 184         {0x0000007d, 0x09000000},
 185         {0x0000007e, 0x00210404},
 186         {0x00000081, 0x08a8e800},
 187         {0x00000082, 0x00030444},
 188         {0x00000083, 0x00000000},
 189         {0x00000085, 0x00000001},
 190         {0x00000086, 0x00000002},
 191         {0x00000087, 0x48490000},
 192         {0x00000088, 0x20244647},
 193         {0x00000089, 0x00000005},
 194         {0x0000008b, 0x66030000},
 195         {0x0000008c, 0x00006603},
 196         {0x0000008d, 0x00000100},
 197         {0x0000008f, 0x00001c0a},
 198         {0x00000090, 0xff000001},
 199         {0x00000094, 0x00101101},
 200         {0x00000095, 0x00000fff},
 201         {0x00000096, 0x00116fff},
 202         {0x00000097, 0x60010000},
 203         {0x00000098, 0x10010000},
 204         {0x00000099, 0x00006000},
 205         {0x0000009a, 0x00001000},
 206         {0x0000009f, 0x00976b00}
 207 };
 208
 209 int ni_mc_load_microcode(struct radeon_device *rdev)
 210 {
 211         const __be32 *fw_data;
 212         u32 mem_type, running, blackout = 0;
 213         u32 *io_mc_regs;
 214         int i, ucode_size, regs_size;
 215
 216         if (!rdev->mc_fw)
 217                 return -EINVAL;
 218
 219         switch (rdev->family) {
 220         case CHIP_BARTS:
 221                 io_mc_regs = (u32 *)&barts_io_mc_regs;
 222                 ucode_size = BTC_MC_UCODE_SIZE;
 223                 regs_size = BTC_IO_MC_REGS_SIZE;
 224                 break;
 225         case CHIP_TURKS:
 226                 io_mc_regs = (u32 *)&turks_io_mc_regs;
 227                 ucode_size = BTC_MC_UCODE_SIZE;
 228                 regs_size = BTC_IO_MC_REGS_SIZE;
 229                 break;
 230         case CHIP_CAICOS:
 231         default:
 232                 io_mc_regs = (u32 *)&caicos_io_mc_regs;
 233                 ucode_size = BTC_MC_UCODE_SIZE;
 234                 regs_size = BTC_IO_MC_REGS_SIZE;
 235                 break;
 236         case CHIP_CAYMAN:
 237                 io_mc_regs = (u32 *)&cayman_io_mc_regs;
 238                 ucode_size = CAYMAN_MC_UCODE_SIZE;
 239                 regs_size = BTC_IO_MC_REGS_SIZE;
 240                 break;
 241         }
 242
 243         mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
 244         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
 245
 246         if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
 247                 if (running) {
 248                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
 249                         WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
 250                 }
 251
 252                 /* reset the engine and set to writable */
 253                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 254                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
 255
 256                 /* load mc io regs */
 257                 for (i = 0; i < regs_size; i++) {
 258                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
 259                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
 260                 }
 261                 /* load the MC ucode */
 262                 fw_data = (const __be32 *)rdev->mc_fw->data;
 263                 for (i = 0; i < ucode_size; i++)
 264                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
 265
 266                 /* put the engine back into the active state */
 267                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 268                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
 269                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
 270
 271                 /* wait for training to complete */
 272                 for (i = 0; i < rdev->usec_timeout; i++) {
 273                         if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
 274                                 break;
 275                         udelay(1);
 276                 }
 277
 278                 if (running)
 279                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
 280         }
 281
 282         return 0;
 283 }
 284
 285 int ni_init_microcode(struct radeon_device *rdev)
 286 {
 287         struct platform_device *pdev;
 288         const char *chip_name;
 289         const char *rlc_chip_name;
 290         size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
 291         char fw_name[30];
 292         int err;
 293
 294         DRM_DEBUG("\n");
 295
 296         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 297         err = IS_ERR(pdev);
 298         if (err) {
 299                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 300                 return -EINVAL;
 301         }
 302
 303         switch (rdev->family) {
 304         case CHIP_BARTS:
 305                 chip_name = "BARTS";
 306                 rlc_chip_name = "BTC";
 307                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 308                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 309                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 310                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 311                 break;
 312         case CHIP_TURKS:
 313                 chip_name = "TURKS";
 314                 rlc_chip_name = "BTC";
 315                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 316                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 317                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 318                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 319                 break;
 320         case CHIP_CAICOS:
 321                 chip_name = "CAICOS";
 322                 rlc_chip_name = "BTC";
 323                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 324                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 325                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 326                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 327                 break;
 328         case CHIP_CAYMAN:
 329                 chip_name = "CAYMAN";
 330                 rlc_chip_name = "CAYMAN";
 331                 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
 332                 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
 333                 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
 334                 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
 335                 break;
 336         case CHIP_ARUBA:
 337                 chip_name = "ARUBA";
 338                 rlc_chip_name = "ARUBA";
 339                 /* pfp/me same size as CAYMAN */
 340                 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
 341                 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
 342                 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
 343                 mc_req_size = 0;
 344                 break;
 345         default: BUG();
 346         }
 347
 348         DRM_INFO("Loading %s Microcode\n", chip_name);
 349
 350         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 351         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
 352         if (err)
 353                 goto out;
 354         if (rdev->pfp_fw->size != pfp_req_size) {
 355                 printk(KERN_ERR
 356                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 357                        rdev->pfp_fw->size, fw_name);
 358                 err = -EINVAL;
 359                 goto out;
 360         }
 361
 362         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 363         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 364         if (err)
 365                 goto out;
 366         if (rdev->me_fw->size != me_req_size) {
 367                 printk(KERN_ERR
 368                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 369                        rdev->me_fw->size, fw_name);
 370                 err = -EINVAL;
 371         }
 372
 373         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
 374         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
 375         if (err)
 376                 goto out;
 377         if (rdev->rlc_fw->size != rlc_req_size) {
 378                 printk(KERN_ERR
 379                        "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
 380                        rdev->rlc_fw->size, fw_name);
 381                 err = -EINVAL;
 382         }
 383
 384         /* no MC ucode on TN */
 385         if (!(rdev->flags & RADEON_IS_IGP)) {
 386                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 387                 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
 388                 if (err)
 389                         goto out;
 390                 if (rdev->mc_fw->size != mc_req_size) {
 391                         printk(KERN_ERR
 392                                "ni_mc: Bogus length %zu in firmware \"%s\"\n",
 393                                rdev->mc_fw->size, fw_name);
 394                         err = -EINVAL;
 395                 }
 396         }
 397 out:
 398         platform_device_unregister(pdev);
 399
 400         if (err) {
 401                 if (err != -EINVAL)
 402                         printk(KERN_ERR
 403                                "ni_cp: Failed to load firmware \"%s\"\n",
 404                                fw_name);
 405                 release_firmware(rdev->pfp_fw);
 406                 rdev->pfp_fw = NULL;
 407                 release_firmware(rdev->me_fw);
 408                 rdev->me_fw = NULL;
 409                 release_firmware(rdev->rlc_fw);
 410                 rdev->rlc_fw = NULL;
 411                 release_firmware(rdev->mc_fw);
 412                 rdev->mc_fw = NULL;
 413         }
 414         return err;
 415 }
 416
 417 /*
 418  * Core functions
 419  */
 420 static void cayman_gpu_init(struct radeon_device *rdev)
 421 {
 422         u32 gb_addr_config = 0;
 423         u32 mc_shared_chmap, mc_arb_ramcfg;
 424         u32 cgts_tcc_disable;
 425         u32 sx_debug_1;
 426         u32 smx_dc_ctl0;
 427         u32 cgts_sm_ctrl_reg;
 428         u32 hdp_host_path_cntl;
 429         u32 tmp;
 430         u32 disabled_rb_mask;
 431         int i, j;
 432
 433         switch (rdev->family) {
 434         case CHIP_CAYMAN:
 435                 rdev->config.cayman.max_shader_engines = 2;
 436                 rdev->config.cayman.max_pipes_per_simd = 4;
 437                 rdev->config.cayman.max_tile_pipes = 8;
 438                 rdev->config.cayman.max_simds_per_se = 12;
 439                 rdev->config.cayman.max_backends_per_se = 4;
 440                 rdev->config.cayman.max_texture_channel_caches = 8;
 441                 rdev->config.cayman.max_gprs = 256;
 442                 rdev->config.cayman.max_threads = 256;
 443                 rdev->config.cayman.max_gs_threads = 32;
 444                 rdev->config.cayman.max_stack_entries = 512;
 445                 rdev->config.cayman.sx_num_of_sets = 8;
 446                 rdev->config.cayman.sx_max_export_size = 256;
 447                 rdev->config.cayman.sx_max_export_pos_size = 64;
 448                 rdev->config.cayman.sx_max_export_smx_size = 192;
 449                 rdev->config.cayman.max_hw_contexts = 8;
 450                 rdev->config.cayman.sq_num_cf_insts = 2;
 451
 452                 rdev->config.cayman.sc_prim_fifo_size = 0x100;
 453                 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
 454                 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
 455                 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
 456                 break;
 457         case CHIP_ARUBA:
 458         default:
 459                 rdev->config.cayman.max_shader_engines = 1;
 460                 rdev->config.cayman.max_pipes_per_simd = 4;
 461                 rdev->config.cayman.max_tile_pipes = 2;
 462                 if ((rdev->pdev->device == 0x9900) ||
 463                     (rdev->pdev->device == 0x9901) ||
 464                     (rdev->pdev->device == 0x9905) ||
 465                     (rdev->pdev->device == 0x9906) ||
 466                     (rdev->pdev->device == 0x9907) ||
 467                     (rdev->pdev->device == 0x9908) ||
 468                     (rdev->pdev->device == 0x9909) ||
 469                     (rdev->pdev->device == 0x9910) ||
 470                     (rdev->pdev->device == 0x9917)) {
 471                         rdev->config.cayman.max_simds_per_se = 6;
 472                         rdev->config.cayman.max_backends_per_se = 2;
 473                 } else if ((rdev->pdev->device == 0x9903) ||
 474                            (rdev->pdev->device == 0x9904) ||
 475                            (rdev->pdev->device == 0x990A) ||
 476                            (rdev->pdev->device == 0x9913) ||
 477                            (rdev->pdev->device == 0x9918)) {
 478                         rdev->config.cayman.max_simds_per_se = 4;
 479                         rdev->config.cayman.max_backends_per_se = 2;
 480                 } else if ((rdev->pdev->device == 0x9919) ||
 481                            (rdev->pdev->device == 0x9990) ||
 482                            (rdev->pdev->device == 0x9991) ||
 483                            (rdev->pdev->device == 0x9994) ||
 484                            (rdev->pdev->device == 0x99A0)) {
 485                         rdev->config.cayman.max_simds_per_se = 3;
 486                         rdev->config.cayman.max_backends_per_se = 1;
 487                 } else {
 488                         rdev->config.cayman.max_simds_per_se = 2;
 489                         rdev->config.cayman.max_backends_per_se = 1;
 490                 }
 491                 rdev->config.cayman.max_texture_channel_caches = 2;
 492                 rdev->config.cayman.max_gprs = 256;
 493                 rdev->config.cayman.max_threads = 256;
 494                 rdev->config.cayman.max_gs_threads = 32;
 495                 rdev->config.cayman.max_stack_entries = 512;
 496                 rdev->config.cayman.sx_num_of_sets = 8;
 497                 rdev->config.cayman.sx_max_export_size = 256;
 498                 rdev->config.cayman.sx_max_export_pos_size = 64;
 499                 rdev->config.cayman.sx_max_export_smx_size = 192;
 500                 rdev->config.cayman.max_hw_contexts = 8;
 501                 rdev->config.cayman.sq_num_cf_insts = 2;
 502
 503                 rdev->config.cayman.sc_prim_fifo_size = 0x40;
 504                 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
 505                 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
 506                 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
 507                 break;
 508         }
 509
 510         /* Initialize HDP */
 511         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 512                 WREG32((0x2c14 + j), 0x00000000);
 513                 WREG32((0x2c18 + j), 0x00000000);
 514                 WREG32((0x2c1c + j), 0x00000000);
 515                 WREG32((0x2c20 + j), 0x00000000);
 516                 WREG32((0x2c24 + j), 0x00000000);
 517         }
 518
 519         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 520
 521         evergreen_fix_pci_max_read_req_size(rdev);
 522
 523         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
 524         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 525
 526         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
 527         rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
 528         if (rdev->config.cayman.mem_row_size_in_kb > 4)
 529                 rdev->config.cayman.mem_row_size_in_kb = 4;
 530         /* XXX use MC settings? */
 531         rdev->config.cayman.shader_engine_tile_size = 32;
 532         rdev->config.cayman.num_gpus = 1;
 533         rdev->config.cayman.multi_gpu_tile_size = 64;
 534
 535         tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
 536         rdev->config.cayman.num_tile_pipes = (1 << tmp);
 537         tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
 538         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 539         tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
 540         rdev->config.cayman.num_shader_engines = tmp + 1;
 541         tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
 542         rdev->config.cayman.num_gpus = tmp + 1;
 543         tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
 544         rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
 545         tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
 546         rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
 547
 548
 549         /* setup tiling info dword.  gb_addr_config is not adequate since it does
 550          * not have bank info, so create a custom tiling dword.
 551          * bits 3:0   num_pipes
 552          * bits 7:4   num_banks
 553          * bits 11:8  group_size
 554          * bits 15:12 row_size
 555          */
 556         rdev->config.cayman.tile_config = 0;
 557         switch (rdev->config.cayman.num_tile_pipes) {
 558         case 1:
 559         default:
 560                 rdev->config.cayman.tile_config |= (0 << 0);
 561                 break;
 562         case 2:
 563                 rdev->config.cayman.tile_config |= (1 << 0);
 564                 break;
 565         case 4:
 566                 rdev->config.cayman.tile_config |= (2 << 0);
 567                 break;
 568         case 8:
 569                 rdev->config.cayman.tile_config |= (3 << 0);
 570                 break;
 571         }
 572
 573         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
 574         if (rdev->flags & RADEON_IS_IGP)
 575                 rdev->config.cayman.tile_config |= 1 << 4;
 576         else {
 577                 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
 578                 case 0: /* four banks */
 579                         rdev->config.cayman.tile_config |= 0 << 4;
 580                         break;
 581                 case 1: /* eight banks */
 582                         rdev->config.cayman.tile_config |= 1 << 4;
 583                         break;
 584                 case 2: /* sixteen banks */
 585                 default:
 586                         rdev->config.cayman.tile_config |= 2 << 4;
 587                         break;
 588                 }
 589         }
 590         rdev->config.cayman.tile_config |=
 591                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
 592         rdev->config.cayman.tile_config |=
 593                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
 594
 595         tmp = 0;
 596         for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
 597                 u32 rb_disable_bitmap;
 598
 599                 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
 600                 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
 601                 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
 602                 tmp <<= 4;
 603                 tmp |= rb_disable_bitmap;
 604         }
 605         /* enabled rb are just the one not disabled :) */
 606         disabled_rb_mask = tmp;
 607
 608         WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
 609         WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
 610
 611         WREG32(GB_ADDR_CONFIG, gb_addr_config);
 612         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
 613         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 614         WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
 615         WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
 616
 617         tmp = gb_addr_config & NUM_PIPES_MASK;
 618         tmp = r6xx_remap_render_backend(rdev, tmp,
 619                                         rdev->config.cayman.max_backends_per_se *
 620                                         rdev->config.cayman.max_shader_engines,
 621                                         CAYMAN_MAX_BACKENDS, disabled_rb_mask);
 622         WREG32(GB_BACKEND_MAP, tmp);
 623
 624         cgts_tcc_disable = 0xffff0000;
 625         for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
 626                 cgts_tcc_disable &= ~(1 << (16 + i));
 627         WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
 628         WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
 629         WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
 630         WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
 631
 632         /* reprogram the shader complex */
 633         cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
 634         for (i = 0; i < 16; i++)
 635                 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
 636         WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
 637
 638         /* set HW defaults for 3D engine */
 639         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
 640
 641         sx_debug_1 = RREG32(SX_DEBUG_1);
 642         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 643         WREG32(SX_DEBUG_1, sx_debug_1);
 644
 645         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 646         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
 647         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
 648         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 649
 650         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
 651
 652         /* need to be explicitly zero-ed */
 653         WREG32(VGT_OFFCHIP_LDS_BASE, 0);
 654         WREG32(SQ_LSTMP_RING_BASE, 0);
 655         WREG32(SQ_HSTMP_RING_BASE, 0);
 656         WREG32(SQ_ESTMP_RING_BASE, 0);
 657         WREG32(SQ_GSTMP_RING_BASE, 0);
 658         WREG32(SQ_VSTMP_RING_BASE, 0);
 659         WREG32(SQ_PSTMP_RING_BASE, 0);
 660
 661         WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
 662
 663         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
 664                                         POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
 665                                         SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
 666
 667         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
 668                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
 669                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
 670
 671
 672         WREG32(VGT_NUM_INSTANCES, 1);
 673
 674         WREG32(CP_PERFMON_CNTL, 0);
 675
 676         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
 677                                   FETCH_FIFO_HIWATER(0x4) |
 678                                   DONE_FIFO_HIWATER(0xe0) |
 679                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
 680
 681         WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
 682         WREG32(SQ_CONFIG, (VC_ENABLE |
 683                            EXPORT_SRC_C |
 684                            GFX_PRIO(0) |
 685                            CS1_PRIO(0) |
 686                            CS2_PRIO(1)));
 687         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
 688
 689         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 690                                           FORCE_EOV_MAX_REZ_CNT(255)));
 691
 692         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
 693                AUTO_INVLD_EN(ES_AND_GS_AUTO));
 694
 695         WREG32(VGT_GS_VERTEX_REUSE, 16);
 696         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 697
 698         WREG32(CB_PERF_CTR0_SEL_0, 0);
 699         WREG32(CB_PERF_CTR0_SEL_1, 0);
 700         WREG32(CB_PERF_CTR1_SEL_0, 0);
 701         WREG32(CB_PERF_CTR1_SEL_1, 0);
 702         WREG32(CB_PERF_CTR2_SEL_0, 0);
 703         WREG32(CB_PERF_CTR2_SEL_1, 0);
 704         WREG32(CB_PERF_CTR3_SEL_0, 0);
 705         WREG32(CB_PERF_CTR3_SEL_1, 0);
 706
 707         tmp = RREG32(HDP_MISC_CNTL);
 708         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
 709         WREG32(HDP_MISC_CNTL, tmp);
 710
 711         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 712         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 713
 714         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
 715
 716         udelay(50);
 717 }
 718
 719 /*
 720  * GART
 721  */
 722 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
 723 {
 724         /* flush hdp cache */
 725         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 726
 727         /* bits 0-7 are the VM contexts0-7 */
 728         WREG32(VM_INVALIDATE_REQUEST, 1);
 729 }
 730
 731 static int cayman_pcie_gart_enable(struct radeon_device *rdev)
 732 {
 733         int i, r;
 734
 735         if (rdev->gart.robj == NULL) {
 736                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 737                 return -EINVAL;
 738         }
 739         r = radeon_gart_table_vram_pin(rdev);
 740         if (r)
 741                 return r;
 742         radeon_gart_restore(rdev);
 743         /* Setup TLB control */
 744         WREG32(MC_VM_MX_L1_TLB_CNTL,
 745                (0xA << 7) |
 746                ENABLE_L1_TLB |
 747                ENABLE_L1_FRAGMENT_PROCESSING |
 748                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 749                ENABLE_ADVANCED_DRIVER_MODEL |
 750                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
 751         /* Setup L2 cache */
 752         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
 753                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 754                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
 755                EFFECTIVE_L2_QUEUE_SIZE(7) |
 756                CONTEXT1_IDENTITY_ACCESS_MODE(1));
 757         WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
 758         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
 759                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
 760         /* setup context0 */
 761         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 762         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 763         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 764         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 765                         (u32)(rdev->dummy_page.addr >> 12));
 766         WREG32(VM_CONTEXT0_CNTL2, 0);
 767         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 768                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 769
 770         WREG32(0x15D4, 0);
 771         WREG32(0x15D8, 0);
 772         WREG32(0x15DC, 0);
 773
 774         /* empty context1-7 */
 775         /* Assign the pt base to something valid for now; the pts used for
 776          * the VMs are determined by the application and setup and assigned
 777          * on the fly in the vm part of radeon_gart.c
 778          */
 779         for (i = 1; i < 8; i++) {
 780                 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
 781                 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
 782                 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
 783                         rdev->gart.table_addr >> 12);
 784         }
 785
 786         /* enable context1-7 */
 787         WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 788                (u32)(rdev->dummy_page.addr >> 12));
 789         WREG32(VM_CONTEXT1_CNTL2, 4);
 790         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
 791                                 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
 792                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
 793                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
 794                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
 795                                 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
 796                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
 797                                 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
 798                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
 799                                 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
 800                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
 801                                 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
 802                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
 803
 804         cayman_pcie_gart_tlb_flush(rdev);
 805         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 806                  (unsigned)(rdev->mc.gtt_size >> 20),
 807                  (unsigned long long)rdev->gart.table_addr);
 808         rdev->gart.ready = true;
 809         return 0;
 810 }
 811
 812 static void cayman_pcie_gart_disable(struct radeon_device *rdev)
 813 {
 814         /* Disable all tables */
 815         WREG32(VM_CONTEXT0_CNTL, 0);
 816         WREG32(VM_CONTEXT1_CNTL, 0);
 817         /* Setup TLB control */
 818         WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
 819                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 820                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
 821         /* Setup L2 cache */
 822         WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 823                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
 824                EFFECTIVE_L2_QUEUE_SIZE(7) |
 825                CONTEXT1_IDENTITY_ACCESS_MODE(1));
 826         WREG32(VM_L2_CNTL2, 0);
 827         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
 828                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
 829         radeon_gart_table_vram_unpin(rdev);
 830 }
 831
 832 static void cayman_pcie_gart_fini(struct radeon_device *rdev)
 833 {
 834         cayman_pcie_gart_disable(rdev);
 835         radeon_gart_table_vram_free(rdev);
 836         radeon_gart_fini(rdev);
 837 }
 838
 839 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
 840                               int ring, u32 cp_int_cntl)
 841 {
 842         u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
 843
 844         WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
 845         WREG32(CP_INT_CNTL, cp_int_cntl);
 846 }
 847
 848 /*
 849  * CP.
 850  */
 851 void cayman_fence_ring_emit(struct radeon_device *rdev,
 852                             struct radeon_fence *fence)
 853 {
 854         struct radeon_ring *ring = &rdev->ring[fence->ring];
 855         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
 856
 857         /* flush read cache over gart for this vmid */
 858         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 859         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
 860         radeon_ring_write(ring, 0);
 861         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
 862         radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
 863         radeon_ring_write(ring, 0xFFFFFFFF);
 864         radeon_ring_write(ring, 0);
 865         radeon_ring_write(ring, 10); /* poll interval */
 866         /* EVENT_WRITE_EOP - flush caches, send int */
 867         radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
 868         radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
 869         radeon_ring_write(ring, addr & 0xffffffff);
 870         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
 871         radeon_ring_write(ring, fence->seq);
 872         radeon_ring_write(ring, 0);
 873 }
 874
 875 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 876 {
 877         struct radeon_ring *ring = &rdev->ring[ib->ring];
 878
 879         /* set to DX10/11 mode */
 880         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
 881         radeon_ring_write(ring, 1);
 882
 883         if (ring->rptr_save_reg) {
 884                 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
 885                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 886                 radeon_ring_write(ring, ((ring->rptr_save_reg -
 887                                           PACKET3_SET_CONFIG_REG_START) >> 2));
 888                 radeon_ring_write(ring, next_rptr);
 889         }
 890
 891         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 892         radeon_ring_write(ring,
 893 #ifdef __BIG_ENDIAN
 894                           (2 << 0) |
 895 #endif
 896                           (ib->gpu_addr & 0xFFFFFFFC));
 897         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
 898         radeon_ring_write(ring, ib->length_dw |
 899                           (ib->vm ? (ib->vm->id << 24) : 0));
 900
 901         /* flush read cache over gart for this vmid */
 902         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 903         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
 904         radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
 905         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
 906         radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
 907         radeon_ring_write(ring, 0xFFFFFFFF);
 908         radeon_ring_write(ring, 0);
 909         radeon_ring_write(ring, 10); /* poll interval */
 910 }
 911
 912 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
 913 {
 914         if (enable)
 915                 WREG32(CP_ME_CNTL, 0);
 916         else {
 917                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 918                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
 919                 WREG32(SCRATCH_UMSK, 0);
 920                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
 921         }
 922 }
 923
 924 static int cayman_cp_load_microcode(struct radeon_device *rdev)
 925 {
 926         const __be32 *fw_data;
 927         int i;
 928
 929         if (!rdev->me_fw || !rdev->pfp_fw)
 930                 return -EINVAL;
 931
 932         cayman_cp_enable(rdev, false);
 933
 934         fw_data = (const __be32 *)rdev->pfp_fw->data;
 935         WREG32(CP_PFP_UCODE_ADDR, 0);
 936         for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
 937                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 938         WREG32(CP_PFP_UCODE_ADDR, 0);
 939
 940         fw_data = (const __be32 *)rdev->me_fw->data;
 941         WREG32(CP_ME_RAM_WADDR, 0);
 942         for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
 943                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 944
 945         WREG32(CP_PFP_UCODE_ADDR, 0);
 946         WREG32(CP_ME_RAM_WADDR, 0);
 947         WREG32(CP_ME_RAM_RADDR, 0);
 948         return 0;
 949 }
 950
 951 static int cayman_cp_start(struct radeon_device *rdev)
 952 {
 953         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 954         int r, i;
 955
 956         r = radeon_ring_lock(rdev, ring, 7);
 957         if (r) {
 958                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
 959                 return r;
 960         }
 961         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
 962         radeon_ring_write(ring, 0x1);
 963         radeon_ring_write(ring, 0x0);
 964         radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
 965         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
 966         radeon_ring_write(ring, 0);
 967         radeon_ring_write(ring, 0);
 968         radeon_ring_unlock_commit(rdev, ring);
 969
 970         cayman_cp_enable(rdev, true);
 971
 972         r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
 973         if (r) {
 974                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
 975                 return r;
 976         }
 977
 978         /* setup clear context state */
 979         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 980         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 981
 982         for (i = 0; i < cayman_default_size; i++)
 983                 radeon_ring_write(ring, cayman_default_state[i]);
 984
 985         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 986         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
 987
 988         /* set clear context state */
 989         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
 990         radeon_ring_write(ring, 0);
 991
 992         /* SQ_VTX_BASE_VTX_LOC */
 993         radeon_ring_write(ring, 0xc0026f00);
 994         radeon_ring_write(ring, 0x00000000);
 995         radeon_ring_write(ring, 0x00000000);
 996         radeon_ring_write(ring, 0x00000000);
 997
 998         /* Clear consts */
 999         radeon_ring_write(ring, 0xc0036f00);
1000         radeon_ring_write(ring, 0x00000bc4);
1001         radeon_ring_write(ring, 0xffffffff);
1002         radeon_ring_write(ring, 0xffffffff);
1003         radeon_ring_write(ring, 0xffffffff);
1004
1005         radeon_ring_write(ring, 0xc0026900);
1006         radeon_ring_write(ring, 0x00000316);
1007         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1008         radeon_ring_write(ring, 0x00000010); /*  */
1009
1010         radeon_ring_unlock_commit(rdev, ring);
1011
1012         /* XXX init other rings */
1013
1014         return 0;
1015 }
1016
1017 static void cayman_cp_fini(struct radeon_device *rdev)
1018 {
1019         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1020         cayman_cp_enable(rdev, false);
1021         radeon_ring_fini(rdev, ring);
1022         radeon_scratch_free(rdev, ring->rptr_save_reg);
1023 }
1024
1025 static int cayman_cp_resume(struct radeon_device *rdev)
1026 {
1027         static const int ridx[] = {
1028                 RADEON_RING_TYPE_GFX_INDEX,
1029                 CAYMAN_RING_TYPE_CP1_INDEX,
1030                 CAYMAN_RING_TYPE_CP2_INDEX
1031         };
1032         static const unsigned cp_rb_cntl[] = {
1033                 CP_RB0_CNTL,
1034                 CP_RB1_CNTL,
1035                 CP_RB2_CNTL,
1036         };
1037         static const unsigned cp_rb_rptr_addr[] = {
1038                 CP_RB0_RPTR_ADDR,
1039                 CP_RB1_RPTR_ADDR,
1040                 CP_RB2_RPTR_ADDR
1041         };
1042         static const unsigned cp_rb_rptr_addr_hi[] = {
1043                 CP_RB0_RPTR_ADDR_HI,
1044                 CP_RB1_RPTR_ADDR_HI,
1045                 CP_RB2_RPTR_ADDR_HI
1046         };
1047         static const unsigned cp_rb_base[] = {
1048                 CP_RB0_BASE,
1049                 CP_RB1_BASE,
1050                 CP_RB2_BASE
1051         };
1052         struct radeon_ring *ring;
1053         int i, r;
1054
1055         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1056         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1057                                  SOFT_RESET_PA |
1058                                  SOFT_RESET_SH |
1059                                  SOFT_RESET_VGT |
1060                                  SOFT_RESET_SPI |
1061                                  SOFT_RESET_SX));
1062         RREG32(GRBM_SOFT_RESET);
1063         mdelay(15);
1064         WREG32(GRBM_SOFT_RESET, 0);
1065         RREG32(GRBM_SOFT_RESET);
1066
1067         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1068         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1069
1070         /* Set the write pointer delay */
1071         WREG32(CP_RB_WPTR_DELAY, 0);
1072
1073         WREG32(CP_DEBUG, (1 << 27));
1074
1075         /* set the wb address whether it's enabled or not */
1076         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1077         WREG32(SCRATCH_UMSK, 0xff);
1078
1079         for (i = 0; i < 3; ++i) {
1080                 uint32_t rb_cntl;
1081                 uint64_t addr;
1082
1083                 /* Set ring buffer size */
1084                 ring = &rdev->ring[ridx[i]];
1085                 rb_cntl = drm_order(ring->ring_size / 8);
1086                 rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8;
1087 #ifdef __BIG_ENDIAN
1088                 rb_cntl |= BUF_SWAP_32BIT;
1089 #endif
1090                 WREG32(cp_rb_cntl[i], rb_cntl);
1091
1092                 /* set the wb address whether it's enabled or not */
1093                 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1094                 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1095                 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1096         }
1097
1098         /* set the rb base addr, this causes an internal reset of ALL rings */
1099         for (i = 0; i < 3; ++i) {
1100                 ring = &rdev->ring[ridx[i]];
1101                 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1102         }
1103
1104         for (i = 0; i < 3; ++i) {
1105                 /* Initialize the ring buffer's read and write pointers */
1106                 ring = &rdev->ring[ridx[i]];
1107                 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1108
1109                 ring->rptr = ring->wptr = 0;
1110                 WREG32(ring->rptr_reg, ring->rptr);
1111                 WREG32(ring->wptr_reg, ring->wptr);
1112
1113                 mdelay(1);
1114                 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1115         }
1116
1117         /* start the rings */
1118         cayman_cp_start(rdev);
1119         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1120         rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1121         rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1122         /* this only test cp0 */
1123         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1124         if (r) {
1125                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1126                 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1127                 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1128                 return r;
1129         }
1130
1131         return 0;
1132 }
1133
1134 /*
1135  * DMA
1136  * Starting with R600, the GPU has an asynchronous
1137  * DMA engine.  The programming model is very similar
1138  * to the 3D engine (ring buffer, IBs, etc.), but the
1139  * DMA controller has it's own packet format that is
1140  * different form the PM4 format used by the 3D engine.
1141  * It supports copying data, writing embedded data,
1142  * solid fills, and a number of other things.  It also
1143  * has support for tiling/detiling of buffers.
1144  * Cayman and newer support two asynchronous DMA engines.
1145  */
1146 /**
1147  * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine
1148  *
1149  * @rdev: radeon_device pointer
1150  * @ib: IB object to schedule
1151  *
1152  * Schedule an IB in the DMA ring (cayman-SI).
1153  */
1154 void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
1155                                 struct radeon_ib *ib)
1156 {
1157         struct radeon_ring *ring = &rdev->ring[ib->ring];
1158
1159         if (rdev->wb.enabled) {
1160                 u32 next_rptr = ring->wptr + 4;
1161                 while ((next_rptr & 7) != 5)
1162                         next_rptr++;
1163                 next_rptr += 3;
1164                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
1165                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1166                 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
1167                 radeon_ring_write(ring, next_rptr);
1168         }
1169
1170         /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
1171          * Pad as necessary with NOPs.
1172          */
1173         while ((ring->wptr & 7) != 5)
1174                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1175         radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, ib->vm ? ib->vm->id : 0, 0));
1176         radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
1177         radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
1178
1179 }
1180
1181 /**
1182  * cayman_dma_stop - stop the async dma engines
1183  *
1184  * @rdev: radeon_device pointer
1185  *
1186  * Stop the async dma engines (cayman-SI).
1187  */
1188 void cayman_dma_stop(struct radeon_device *rdev)
1189 {
1190         u32 rb_cntl;
1191
1192         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1193
1194         /* dma0 */
1195         rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1196         rb_cntl &= ~DMA_RB_ENABLE;
1197         WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
1198
1199         /* dma1 */
1200         rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1201         rb_cntl &= ~DMA_RB_ENABLE;
1202         WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);
1203
1204         rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
1205         rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
1206 }
1207
1208 /**
1209  * cayman_dma_resume - setup and start the async dma engines
1210  *
1211  * @rdev: radeon_device pointer
1212  *
1213  * Set up the DMA ring buffers and enable them. (cayman-SI).
1214  * Returns 0 for success, error for failure.
1215  */
1216 int cayman_dma_resume(struct radeon_device *rdev)
1217 {
1218         struct radeon_ring *ring;
1219         u32 rb_cntl, dma_cntl;
1220         u32 rb_bufsz;
1221         u32 reg_offset, wb_offset;
1222         int i, r;
1223
1224         /* Reset dma */
1225         WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
1226         RREG32(SRBM_SOFT_RESET);
1227         udelay(50);
1228         WREG32(SRBM_SOFT_RESET, 0);
1229
1230         for (i = 0; i < 2; i++) {
1231                 if (i == 0) {
1232                         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1233                         reg_offset = DMA0_REGISTER_OFFSET;
1234                         wb_offset = R600_WB_DMA_RPTR_OFFSET;
1235                 } else {
1236                         ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1237                         reg_offset = DMA1_REGISTER_OFFSET;
1238                         wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
1239                 }
1240
1241                 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
1242                 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
1243
1244                 /* Set ring buffer size in dwords */
1245                 rb_bufsz = drm_order(ring->ring_size / 4);
1246                 rb_cntl = rb_bufsz << 1;
1247 #ifdef __BIG_ENDIAN
1248                 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
1249 #endif
1250                 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
1251
1252                 /* Initialize the ring buffer's read and write pointers */
1253                 WREG32(DMA_RB_RPTR + reg_offset, 0);
1254                 WREG32(DMA_RB_WPTR + reg_offset, 0);
1255
1256                 /* set the wb address whether it's enabled or not */
1257                 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
1258                        upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);
1259                 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
1260                        ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
1261
1262                 if (rdev->wb.enabled)
1263                         rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
1264
1265                 WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
1266
1267                 /* enable DMA IBs */
1268                 WREG32(DMA_IB_CNTL + reg_offset, DMA_IB_ENABLE | CMD_VMID_FORCE);
1269
1270                 dma_cntl = RREG32(DMA_CNTL + reg_offset);
1271                 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
1272                 WREG32(DMA_CNTL + reg_offset, dma_cntl);
1273
1274                 ring->wptr = 0;
1275                 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
1276
1277                 ring->rptr = RREG32(DMA_RB_RPTR + reg_offset) >> 2;
1278
1279                 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);
1280
1281                 ring->ready = true;
1282
1283                 r = radeon_ring_test(rdev, ring->idx, ring);
1284                 if (r) {
1285                         ring->ready = false;
1286                         return r;
1287                 }
1288         }
1289
1290         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1291
1292         return 0;
1293 }
1294
1295 /**
1296  * cayman_dma_fini - tear down the async dma engines
1297  *
1298  * @rdev: radeon_device pointer
1299  *
1300  * Stop the async dma engines and free the rings (cayman-SI).
1301  */
1302 void cayman_dma_fini(struct radeon_device *rdev)
1303 {
1304         cayman_dma_stop(rdev);
1305         radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
1306         radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
1307 }
1308
1309 static void cayman_gpu_soft_reset_gfx(struct radeon_device *rdev)
1310 {
1311         u32 grbm_reset = 0;
1312
1313         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1314                 return;
1315
1316         dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
1317                 RREG32(GRBM_STATUS));
1318         dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
1319                 RREG32(GRBM_STATUS_SE0));
1320         dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
1321                 RREG32(GRBM_STATUS_SE1));
1322         dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
1323                 RREG32(SRBM_STATUS));
1324         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1325                 RREG32(CP_STALLED_STAT1));
1326         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1327                 RREG32(CP_STALLED_STAT2));
1328         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1329                 RREG32(CP_BUSY_STAT));
1330         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1331                 RREG32(CP_STAT));
1332
1333         /* Disable CP parsing/prefetching */
1334         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1335
1336         /* reset all the gfx blocks */
1337         grbm_reset = (SOFT_RESET_CP |
1338                       SOFT_RESET_CB |
1339                       SOFT_RESET_DB |
1340                       SOFT_RESET_GDS |
1341                       SOFT_RESET_PA |
1342                       SOFT_RESET_SC |
1343                       SOFT_RESET_SPI |
1344                       SOFT_RESET_SH |
1345                       SOFT_RESET_SX |
1346                       SOFT_RESET_TC |
1347                       SOFT_RESET_TA |
1348                       SOFT_RESET_VGT |
1349                       SOFT_RESET_IA);
1350
1351         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1352         WREG32(GRBM_SOFT_RESET, grbm_reset);
1353         (void)RREG32(GRBM_SOFT_RESET);
1354         udelay(50);
1355         WREG32(GRBM_SOFT_RESET, 0);
1356         (void)RREG32(GRBM_SOFT_RESET);
1357
1358         dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
1359                 RREG32(GRBM_STATUS));
1360         dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
1361                 RREG32(GRBM_STATUS_SE0));
1362         dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
1363                 RREG32(GRBM_STATUS_SE1));
1364         dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
1365                 RREG32(SRBM_STATUS));
1366         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1367                 RREG32(CP_STALLED_STAT1));
1368         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1369                 RREG32(CP_STALLED_STAT2));
1370         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1371                 RREG32(CP_BUSY_STAT));
1372         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1373                 RREG32(CP_STAT));
1374
1375 }
1376
1377 static void cayman_gpu_soft_reset_dma(struct radeon_device *rdev)
1378 {
1379         u32 tmp;
1380
1381         if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1382                 return;
1383
1384         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1385                 RREG32(DMA_STATUS_REG));
1386
1387         /* dma0 */
1388         tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1389         tmp &= ~DMA_RB_ENABLE;
1390         WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1391
1392         /* dma1 */
1393         tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1394         tmp &= ~DMA_RB_ENABLE;
1395         WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1396
1397         /* Reset dma */
1398         WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
1399         RREG32(SRBM_SOFT_RESET);
1400         udelay(50);
1401         WREG32(SRBM_SOFT_RESET, 0);
1402
1403         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1404                 RREG32(DMA_STATUS_REG));
1405
1406 }
1407
1408 static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1409 {
1410         struct evergreen_mc_save save;
1411
1412         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1413                 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
1414
1415         if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1416                 reset_mask &= ~RADEON_RESET_DMA;
1417
1418         if (reset_mask == 0)
1419                 return 0;
1420
1421         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1422
1423         dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",
1424                  RREG32(0x14F8));
1425         dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1426                  RREG32(0x14D8));
1427         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1428                  RREG32(0x14FC));
1429         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1430                  RREG32(0x14DC));
1431
1432         evergreen_mc_stop(rdev, &save);
1433         if (evergreen_mc_wait_for_idle(rdev)) {
1434                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1435         }
1436
1437         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
1438                 cayman_gpu_soft_reset_gfx(rdev);
1439
1440         if (reset_mask & RADEON_RESET_DMA)
1441                 cayman_gpu_soft_reset_dma(rdev);
1442
1443         /* Wait a little for things to settle down */
1444         udelay(50);
1445
1446         evergreen_mc_resume(rdev, &save);
1447         return 0;
1448 }
1449
1450 int cayman_asic_reset(struct radeon_device *rdev)
1451 {
1452         return cayman_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
1453                                             RADEON_RESET_COMPUTE |
1454                                             RADEON_RESET_DMA));
1455 }
1456
1457 /**
1458  * cayman_dma_is_lockup - Check if the DMA engine is locked up
1459  *
1460  * @rdev: radeon_device pointer
1461  * @ring: radeon_ring structure holding ring information
1462  *
1463  * Check if the async DMA engine is locked up (cayman-SI).
1464  * Returns true if the engine appears to be locked up, false if not.
1465  */
1466 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1467 {
1468         u32 dma_status_reg;
1469
1470         if (ring->idx == R600_RING_TYPE_DMA_INDEX)
1471                 dma_status_reg = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1472         else
1473                 dma_status_reg = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1474         if (dma_status_reg & DMA_IDLE) {
1475                 radeon_ring_lockup_update(ring);
1476                 return false;
1477         }
1478         /* force ring activities */
1479         radeon_ring_force_activity(rdev, ring);
1480         return radeon_ring_test_lockup(rdev, ring);
1481 }
1482
1483 static int cayman_startup(struct radeon_device *rdev)
1484 {
1485         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1486         int r;
1487
1488         /* enable pcie gen2 link */
1489         evergreen_pcie_gen2_enable(rdev);
1490
1491         if (rdev->flags & RADEON_IS_IGP) {
1492                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1493                         r = ni_init_microcode(rdev);
1494                         if (r) {
1495                                 DRM_ERROR("Failed to load firmware!\n");
1496                                 return r;
1497                         }
1498                 }
1499         } else {
1500                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1501                         r = ni_init_microcode(rdev);
1502                         if (r) {
1503                                 DRM_ERROR("Failed to load firmware!\n");
1504                                 return r;
1505                         }
1506                 }
1507
1508                 r = ni_mc_load_microcode(rdev);
1509                 if (r) {
1510                         DRM_ERROR("Failed to load MC firmware!\n");
1511                         return r;
1512                 }
1513         }
1514
1515         r = r600_vram_scratch_init(rdev);
1516         if (r)
1517                 return r;
1518
1519         evergreen_mc_program(rdev);
1520         r = cayman_pcie_gart_enable(rdev);
1521         if (r)
1522                 return r;
1523         cayman_gpu_init(rdev);
1524
1525         r = evergreen_blit_init(rdev);
1526         if (r) {
1527                 r600_blit_fini(rdev);
1528                 rdev->asic->copy.copy = NULL;
1529                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1530         }
1531
1532         /* allocate rlc buffers */
1533         if (rdev->flags & RADEON_IS_IGP) {
1534                 r = si_rlc_init(rdev);
1535                 if (r) {
1536                         DRM_ERROR("Failed to init rlc BOs!\n");
1537                         return r;
1538                 }
1539         }
1540
1541         /* allocate wb buffer */
1542         r = radeon_wb_init(rdev);
1543         if (r)
1544                 return r;
1545
1546         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1547         if (r) {
1548                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1549                 return r;
1550         }
1551
1552         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1553         if (r) {
1554                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1555                 return r;
1556         }
1557
1558         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1559         if (r) {
1560                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1561                 return r;
1562         }
1563
1564         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1565         if (r) {
1566                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1567                 return r;
1568         }
1569
1570         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
1571         if (r) {
1572                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1573                 return r;
1574         }
1575
1576         /* Enable IRQ */
1577         r = r600_irq_init(rdev);
1578         if (r) {
1579                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1580                 radeon_irq_kms_fini(rdev);
1581                 return r;
1582         }
1583         evergreen_irq_set(rdev);
1584
1585         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1586                              CP_RB0_RPTR, CP_RB0_WPTR,
1587                              0, 0xfffff, RADEON_CP_PACKET2);
1588         if (r)
1589                 return r;
1590
1591         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1592         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1593                              DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
1594                              DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
1595                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1596         if (r)
1597                 return r;
1598
1599         ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1600         r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
1601                              DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
1602                              DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
1603                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1604         if (r)
1605                 return r;
1606
1607         r = cayman_cp_load_microcode(rdev);
1608         if (r)
1609                 return r;
1610         r = cayman_cp_resume(rdev);
1611         if (r)
1612                 return r;
1613
1614         r = cayman_dma_resume(rdev);
1615         if (r)
1616                 return r;
1617
1618         r = radeon_ib_pool_init(rdev);
1619         if (r) {
1620                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1621                 return r;
1622         }
1623
1624         r = radeon_vm_manager_init(rdev);
1625         if (r) {
1626                 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
1627                 return r;
1628         }
1629
1630         r = r600_audio_init(rdev);
1631         if (r)
1632                 return r;
1633
1634         return 0;
1635 }
1636
1637 int cayman_resume(struct radeon_device *rdev)
1638 {
1639         int r;
1640
1641         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1642          * posting will perform necessary task to bring back GPU into good
1643          * shape.
1644          */
1645         /* post card */
1646         atom_asic_init(rdev->mode_info.atom_context);
1647
1648         rdev->accel_working = true;
1649         r = cayman_startup(rdev);
1650         if (r) {
1651                 DRM_ERROR("cayman startup failed on resume\n");
1652                 rdev->accel_working = false;
1653                 return r;
1654         }
1655         return r;
1656 }
1657
1658 int cayman_suspend(struct radeon_device *rdev)
1659 {
1660         r600_audio_fini(rdev);
1661         cayman_cp_enable(rdev, false);
1662         cayman_dma_stop(rdev);
1663         evergreen_irq_suspend(rdev);
1664         radeon_wb_disable(rdev);
1665         cayman_pcie_gart_disable(rdev);
1666         return 0;
1667 }
1668
1669 /* Plan is to move initialization in that function and use
1670  * helper function so that radeon_device_init pretty much
1671  * do nothing more than calling asic specific function. This
1672  * should also allow to remove a bunch of callback function
1673  * like vram_info.
1674  */
1675 int cayman_init(struct radeon_device *rdev)
1676 {
1677         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1678         int r;
1679
1680         /* Read BIOS */
1681         if (!radeon_get_bios(rdev)) {
1682                 if (ASIC_IS_AVIVO(rdev))
1683                         return -EINVAL;
1684         }
1685         /* Must be an ATOMBIOS */
1686         if (!rdev->is_atom_bios) {
1687                 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1688                 return -EINVAL;
1689         }
1690         r = radeon_atombios_init(rdev);
1691         if (r)
1692                 return r;
1693
1694         /* Post card if necessary */
1695         if (!radeon_card_posted(rdev)) {
1696                 if (!rdev->bios) {
1697                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1698                         return -EINVAL;
1699                 }
1700                 DRM_INFO("GPU not posted. posting now...\n");
1701                 atom_asic_init(rdev->mode_info.atom_context);
1702         }
1703         /* Initialize scratch registers */
1704         r600_scratch_init(rdev);
1705         /* Initialize surface registers */
1706         radeon_surface_init(rdev);
1707         /* Initialize clocks */
1708         radeon_get_clock_info(rdev->ddev);
1709         /* Fence driver */
1710         r = radeon_fence_driver_init(rdev);
1711         if (r)
1712                 return r;
1713         /* initialize memory controller */
1714         r = evergreen_mc_init(rdev);
1715         if (r)
1716                 return r;
1717         /* Memory manager */
1718         r = radeon_bo_init(rdev);
1719         if (r)
1720                 return r;
1721
1722         r = radeon_irq_kms_init(rdev);
1723         if (r)
1724                 return r;
1725
1726         ring->ring_obj = NULL;
1727         r600_ring_init(rdev, ring, 1024 * 1024);
1728
1729         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1730         ring->ring_obj = NULL;
1731         r600_ring_init(rdev, ring, 64 * 1024);
1732
1733         ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1734         ring->ring_obj = NULL;
1735         r600_ring_init(rdev, ring, 64 * 1024);
1736
1737         rdev->ih.ring_obj = NULL;
1738         r600_ih_ring_init(rdev, 64 * 1024);
1739
1740         r = r600_pcie_gart_init(rdev);
1741         if (r)
1742                 return r;
1743
1744         rdev->accel_working = true;
1745         r = cayman_startup(rdev);
1746         if (r) {
1747                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1748                 cayman_cp_fini(rdev);
1749                 cayman_dma_fini(rdev);
1750                 r600_irq_fini(rdev);
1751                 if (rdev->flags & RADEON_IS_IGP)
1752                         si_rlc_fini(rdev);
1753                 radeon_wb_fini(rdev);
1754                 radeon_ib_pool_fini(rdev);
1755                 radeon_vm_manager_fini(rdev);
1756                 radeon_irq_kms_fini(rdev);
1757                 cayman_pcie_gart_fini(rdev);
1758                 rdev->accel_working = false;
1759         }
1760
1761         /* Don't start up if the MC ucode is missing.
1762          * The default clocks and voltages before the MC ucode
1763          * is loaded are not suffient for advanced operations.
1764          *
1765          * We can skip this check for TN, because there is no MC
1766          * ucode.
1767          */
1768         if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
1769                 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1770                 return -EINVAL;
1771         }
1772
1773         return 0;
1774 }
1775
1776 void cayman_fini(struct radeon_device *rdev)
1777 {
1778         r600_blit_fini(rdev);
1779         cayman_cp_fini(rdev);
1780         cayman_dma_fini(rdev);
1781         r600_irq_fini(rdev);
1782         if (rdev->flags & RADEON_IS_IGP)
1783                 si_rlc_fini(rdev);
1784         radeon_wb_fini(rdev);
1785         radeon_vm_manager_fini(rdev);
1786         radeon_ib_pool_fini(rdev);
1787         radeon_irq_kms_fini(rdev);
1788         cayman_pcie_gart_fini(rdev);
1789         r600_vram_scratch_fini(rdev);
1790         radeon_gem_fini(rdev);
1791         radeon_fence_driver_fini(rdev);
1792         radeon_bo_fini(rdev);
1793         radeon_atombios_fini(rdev);
1794         kfree(rdev->bios);
1795         rdev->bios = NULL;
1796 }
1797
1798 /*
1799  * vm
1800  */
1801 int cayman_vm_init(struct radeon_device *rdev)
1802 {
1803         /* number of VMs */
1804         rdev->vm_manager.nvm = 8;
1805         /* base offset of vram pages */
1806         if (rdev->flags & RADEON_IS_IGP) {
1807                 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1808                 tmp <<= 22;
1809                 rdev->vm_manager.vram_base_offset = tmp;
1810         } else
1811                 rdev->vm_manager.vram_base_offset = 0;
1812         return 0;
1813 }
1814
1815 void cayman_vm_fini(struct radeon_device *rdev)
1816 {
1817 }
1818
1819 #define R600_ENTRY_VALID   (1 << 0)
1820 #define R600_PTE_SYSTEM    (1 << 1)
1821 #define R600_PTE_SNOOPED   (1 << 2)
1822 #define R600_PTE_READABLE  (1 << 5)
1823 #define R600_PTE_WRITEABLE (1 << 6)
1824
1825 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
1826 {
1827         uint32_t r600_flags = 0;
1828         r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
1829         r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1830         r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1831         if (flags & RADEON_VM_PAGE_SYSTEM) {
1832                 r600_flags |= R600_PTE_SYSTEM;
1833                 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1834         }
1835         return r600_flags;
1836 }
1837
1838 /**
1839  * cayman_vm_set_page - update the page tables using the CP
1840  *
1841  * @rdev: radeon_device pointer
1842  * @pe: addr of the page entry
1843  * @addr: dst addr to write into pe
1844  * @count: number of page entries to update
1845  * @incr: increase next addr by incr bytes
1846  * @flags: access flags
1847  *
1848  * Update the page tables using the CP (cayman-si).
1849  */
1850 void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
1851                         uint64_t addr, unsigned count,
1852                         uint32_t incr, uint32_t flags)
1853 {
1854         struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
1855         uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
1856         uint64_t value;
1857         unsigned ndw;
1858
1859         if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
1860                 while (count) {
1861                         ndw = 1 + count * 2;
1862                         if (ndw > 0x3FFF)
1863                                 ndw = 0x3FFF;
1864
1865                         radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, ndw));
1866                         radeon_ring_write(ring, pe);
1867                         radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
1868                         for (; ndw > 1; ndw -= 2, --count, pe += 8) {
1869                                 if (flags & RADEON_VM_PAGE_SYSTEM) {
1870                                         value = radeon_vm_map_gart(rdev, addr);
1871                                         value &= 0xFFFFFFFFFFFFF000ULL;
1872                                 } else if (flags & RADEON_VM_PAGE_VALID) {
1873                                         value = addr;
1874                                 } else {
1875                                         value = 0;
1876                                 }
1877                                 addr += incr;
1878                                 value |= r600_flags;
1879                                 radeon_ring_write(ring, value);
1880                                 radeon_ring_write(ring, upper_32_bits(value));
1881                         }
1882                 }
1883         } else {
1884                 while (count) {
1885                         ndw = count * 2;
1886                         if (ndw > 0xFFFFE)
1887                                 ndw = 0xFFFFE;
1888
1889                         /* for non-physically contiguous pages (system) */
1890                         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw));
1891                         radeon_ring_write(ring, pe);
1892                         radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
1893                         for (; ndw > 0; ndw -= 2, --count, pe += 8) {
1894                                 if (flags & RADEON_VM_PAGE_SYSTEM) {
1895                                         value = radeon_vm_map_gart(rdev, addr);
1896                                         value &= 0xFFFFFFFFFFFFF000ULL;
1897                                 } else if (flags & RADEON_VM_PAGE_VALID) {
1898                                         value = addr;
1899                                 } else {
1900                                         value = 0;
1901                                 }
1902                                 addr += incr;
1903                                 value |= r600_flags;
1904                                 radeon_ring_write(ring, value);
1905                                 radeon_ring_write(ring, upper_32_bits(value));
1906                         }
1907                 }
1908         }
1909 }
1910
1911 /**
1912  * cayman_vm_flush - vm flush using the CP
1913  *
1914  * @rdev: radeon_device pointer
1915  *
1916  * Update the page table base and flush the VM TLB
1917  * using the CP (cayman-si).
1918  */
1919 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
1920 {
1921         struct radeon_ring *ring = &rdev->ring[ridx];
1922
1923         if (vm == NULL)
1924                 return;
1925
1926         radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
1927         radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
1928
1929         /* flush hdp cache */
1930         radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
1931         radeon_ring_write(ring, 0x1);
1932
1933         /* bits 0-7 are the VM contexts0-7 */
1934         radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
1935         radeon_ring_write(ring, 1 << vm->id);
1936
1937         /* sync PFP to ME, otherwise we might get invalid PFP reads */
1938         radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
1939         radeon_ring_write(ring, 0x0);
1940 }
1941
1942 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
1943 {
1944         struct radeon_ring *ring = &rdev->ring[ridx];
1945
1946         if (vm == NULL)
1947                 return;
1948
1949         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
1950         radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
1951         radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
1952
1953         /* flush hdp cache */
1954         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
1955         radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
1956         radeon_ring_write(ring, 1);
1957
1958         /* bits 0-7 are the VM contexts0-7 */
1959         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
1960         radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
1961         radeon_ring_write(ring, 1 << vm->id);
1962 }
1963