2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #define EVERGREEN_MAX_SH_GPRS 256
28 #define EVERGREEN_MAX_TEMP_GPRS 16
29 #define EVERGREEN_MAX_SH_THREADS 256
30 #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096
31 #define EVERGREEN_MAX_FRC_EOV_CNT 16384
32 #define EVERGREEN_MAX_BACKENDS 8
33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF
34 #define EVERGREEN_MAX_SIMDS 16
35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
36 #define EVERGREEN_MAX_PIPES 8
37 #define EVERGREEN_MAX_PIPES_MASK 0xFF
38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF
42 #define RCU_IND_INDEX 0x100
43 #define RCU_IND_DATA 0x104
45 #define GRBM_GFX_INDEX 0x802C
46 #define INSTANCE_INDEX(x) ((x) << 0)
47 #define SE_INDEX(x) ((x) << 16)
48 #define INSTANCE_BROADCAST_WRITES (1 << 30)
49 #define SE_BROADCAST_WRITES (1 << 31)
50 #define RLC_GFX_INDEX 0x3fC4
51 #define CC_GC_SHADER_PIPE_CONFIG 0x8950
52 #define WRITE_DIS (1 << 0)
53 #define CC_RB_BACKEND_DISABLE 0x98F4
54 #define BACKEND_DISABLE(x) ((x) << 16)
55 #define GB_ADDR_CONFIG 0x98F8
56 #define NUM_PIPES(x) ((x) << 0)
57 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
58 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
59 #define NUM_SHADER_ENGINES(x) ((x) << 12)
60 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
61 #define NUM_GPUS(x) ((x) << 20)
62 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
63 #define ROW_SIZE(x) ((x) << 28)
64 #define GB_BACKEND_MAP 0x98FC
65 #define DMIF_ADDR_CONFIG 0xBD4
66 #define HDP_ADDR_CONFIG 0x2F48
67 #define HDP_MISC_CNTL 0x2F4C
68 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
70 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
71 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
73 #define CGTS_SYS_TCC_DISABLE 0x3F90
74 #define CGTS_TCC_DISABLE 0x9148
75 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94
76 #define CGTS_USER_TCC_DISABLE 0x914C
78 #define CONFIG_MEMSIZE 0x5428
80 #define BIF_FB_EN 0x5490
81 #define FB_READ_EN (1 << 0)
82 #define FB_WRITE_EN (1 << 1)
84 #define CP_ME_CNTL 0x86D8
85 #define CP_ME_HALT (1 << 28)
86 #define CP_PFP_HALT (1 << 26)
87 #define CP_ME_RAM_DATA 0xC160
88 #define CP_ME_RAM_RADDR 0xC158
89 #define CP_ME_RAM_WADDR 0xC15C
90 #define CP_MEQ_THRESHOLDS 0x8764
91 #define STQ_SPLIT(x) ((x) << 0)
92 #define CP_PERFMON_CNTL 0x87FC
93 #define CP_PFP_UCODE_ADDR 0xC150
94 #define CP_PFP_UCODE_DATA 0xC154
95 #define CP_QUEUE_THRESHOLDS 0x8760
96 #define ROQ_IB1_START(x) ((x) << 0)
97 #define ROQ_IB2_START(x) ((x) << 8)
98 #define CP_RB_BASE 0xC100
99 #define CP_RB_CNTL 0xC104
100 #define RB_BUFSZ(x) ((x) << 0)
101 #define RB_BLKSZ(x) ((x) << 8)
102 #define RB_NO_UPDATE (1 << 27)
103 #define RB_RPTR_WR_ENA (1 << 31)
104 #define BUF_SWAP_32BIT (2 << 16)
105 #define CP_RB_RPTR 0x8700
106 #define CP_RB_RPTR_ADDR 0xC10C
107 #define RB_RPTR_SWAP(x) ((x) << 0)
108 #define CP_RB_RPTR_ADDR_HI 0xC110
109 #define CP_RB_RPTR_WR 0xC108
110 #define CP_RB_WPTR 0xC114
111 #define CP_RB_WPTR_ADDR 0xC118
112 #define CP_RB_WPTR_ADDR_HI 0xC11C
113 #define CP_RB_WPTR_DELAY 0x8704
114 #define CP_SEM_WAIT_TIMER 0x85BC
115 #define CP_DEBUG 0xC1FC
118 #define GC_USER_SHADER_PIPE_CONFIG 0x8954
119 #define INACTIVE_QD_PIPES(x) ((x) << 8)
120 #define INACTIVE_QD_PIPES_MASK 0x0000FF00
121 #define INACTIVE_SIMDS(x) ((x) << 16)
122 #define INACTIVE_SIMDS_MASK 0x00FF0000
124 #define GRBM_CNTL 0x8000
125 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
126 #define GRBM_SOFT_RESET 0x8020
127 #define SOFT_RESET_CP (1 << 0)
128 #define SOFT_RESET_CB (1 << 1)
129 #define SOFT_RESET_DB (1 << 3)
130 #define SOFT_RESET_PA (1 << 5)
131 #define SOFT_RESET_SC (1 << 6)
132 #define SOFT_RESET_SPI (1 << 8)
133 #define SOFT_RESET_SH (1 << 9)
134 #define SOFT_RESET_SX (1 << 10)
135 #define SOFT_RESET_TC (1 << 11)
136 #define SOFT_RESET_TA (1 << 12)
137 #define SOFT_RESET_VC (1 << 13)
138 #define SOFT_RESET_VGT (1 << 14)
140 #define GRBM_STATUS 0x8010
141 #define CMDFIFO_AVAIL_MASK 0x0000000F
142 #define SRBM_RQ_PENDING (1 << 5)
143 #define CF_RQ_PENDING (1 << 7)
144 #define PF_RQ_PENDING (1 << 8)
145 #define GRBM_EE_BUSY (1 << 10)
146 #define SX_CLEAN (1 << 11)
147 #define DB_CLEAN (1 << 12)
148 #define CB_CLEAN (1 << 13)
149 #define TA_BUSY (1 << 14)
150 #define VGT_BUSY_NO_DMA (1 << 16)
151 #define VGT_BUSY (1 << 17)
152 #define SX_BUSY (1 << 20)
153 #define SH_BUSY (1 << 21)
154 #define SPI_BUSY (1 << 22)
155 #define SC_BUSY (1 << 24)
156 #define PA_BUSY (1 << 25)
157 #define DB_BUSY (1 << 26)
158 #define CP_COHERENCY_BUSY (1 << 28)
159 #define CP_BUSY (1 << 29)
160 #define CB_BUSY (1 << 30)
161 #define GUI_ACTIVE (1 << 31)
162 #define GRBM_STATUS_SE0 0x8014
163 #define GRBM_STATUS_SE1 0x8018
164 #define SE_SX_CLEAN (1 << 0)
165 #define SE_DB_CLEAN (1 << 1)
166 #define SE_CB_CLEAN (1 << 2)
167 #define SE_TA_BUSY (1 << 25)
168 #define SE_SX_BUSY (1 << 26)
169 #define SE_SPI_BUSY (1 << 27)
170 #define SE_SH_BUSY (1 << 28)
171 #define SE_SC_BUSY (1 << 29)
172 #define SE_DB_BUSY (1 << 30)
173 #define SE_CB_BUSY (1 << 31)
175 #define CG_THERMAL_CTRL 0x72c
176 #define TOFFSET_MASK 0x00003FE0
177 #define TOFFSET_SHIFT 5
178 #define CG_MULT_THERMAL_STATUS 0x740
179 #define ASIC_T(x) ((x) << 16)
180 #define ASIC_T_MASK 0x07FF0000
181 #define ASIC_T_SHIFT 16
182 #define CG_TS0_STATUS 0x760
183 #define TS0_ADC_DOUT_MASK 0x000003FF
184 #define TS0_ADC_DOUT_SHIFT 0
186 #define CG_THERMAL_STATUS 0x678
188 #define HDP_HOST_PATH_CNTL 0x2C00
189 #define HDP_NONSURFACE_BASE 0x2C04
190 #define HDP_NONSURFACE_INFO 0x2C08
191 #define HDP_NONSURFACE_SIZE 0x2C0C
192 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
193 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
194 #define HDP_TILING_CONFIG 0x2F3C
196 #define MC_SHARED_CHMAP 0x2004
197 #define NOOFCHAN_SHIFT 12
198 #define NOOFCHAN_MASK 0x00003000
199 #define MC_SHARED_CHREMAP 0x2008
201 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
202 #define BLACKOUT_MODE_MASK 0x00000007
204 #define MC_ARB_RAMCFG 0x2760
205 #define NOOFBANK_SHIFT 0
206 #define NOOFBANK_MASK 0x00000003
207 #define NOOFRANK_SHIFT 2
208 #define NOOFRANK_MASK 0x00000004
209 #define NOOFROWS_SHIFT 3
210 #define NOOFROWS_MASK 0x00000038
211 #define NOOFCOLS_SHIFT 6
212 #define NOOFCOLS_MASK 0x000000C0
213 #define CHANSIZE_SHIFT 8
214 #define CHANSIZE_MASK 0x00000100
215 #define BURSTLENGTH_SHIFT 9
216 #define BURSTLENGTH_MASK 0x00000200
217 #define CHANSIZE_OVERRIDE (1 << 11)
218 #define FUS_MC_ARB_RAMCFG 0x2768
219 #define MC_VM_AGP_TOP 0x2028
220 #define MC_VM_AGP_BOT 0x202C
221 #define MC_VM_AGP_BASE 0x2030
222 #define MC_VM_FB_LOCATION 0x2024
223 #define MC_FUS_VM_FB_OFFSET 0x2898
224 #define MC_VM_MB_L1_TLB0_CNTL 0x2234
225 #define MC_VM_MB_L1_TLB1_CNTL 0x2238
226 #define MC_VM_MB_L1_TLB2_CNTL 0x223C
227 #define MC_VM_MB_L1_TLB3_CNTL 0x2240
228 #define ENABLE_L1_TLB (1 << 0)
229 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
230 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
231 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
232 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
233 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
234 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
235 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
236 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
237 #define MC_VM_MD_L1_TLB0_CNTL 0x2654
238 #define MC_VM_MD_L1_TLB1_CNTL 0x2658
239 #define MC_VM_MD_L1_TLB2_CNTL 0x265C
240 #define MC_VM_MD_L1_TLB3_CNTL 0x2698
242 #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C
243 #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660
244 #define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664
246 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
247 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
248 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
250 #define PA_CL_ENHANCE 0x8A14
251 #define CLIP_VTX_REORDER_ENA (1 << 0)
252 #define NUM_CLIP_SEQ(x) ((x) << 1)
253 #define PA_SC_AA_CONFIG 0x28C04
254 #define MSAA_NUM_SAMPLES_SHIFT 0
255 #define MSAA_NUM_SAMPLES_MASK 0x3
256 #define PA_SC_CLIPRECT_RULE 0x2820C
257 #define PA_SC_EDGERULE 0x28230
258 #define PA_SC_FIFO_SIZE 0x8BCC
259 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
260 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
261 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
262 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
263 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
264 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
265 #define PA_SC_LINE_STIPPLE 0x28A0C
266 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60
267 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
269 #define SCRATCH_REG0 0x8500
270 #define SCRATCH_REG1 0x8504
271 #define SCRATCH_REG2 0x8508
272 #define SCRATCH_REG3 0x850C
273 #define SCRATCH_REG4 0x8510
274 #define SCRATCH_REG5 0x8514
275 #define SCRATCH_REG6 0x8518
276 #define SCRATCH_REG7 0x851C
277 #define SCRATCH_UMSK 0x8540
278 #define SCRATCH_ADDR 0x8544
280 #define SMX_SAR_CTL0 0xA008
281 #define SMX_DC_CTL0 0xA020
282 #define USE_HASH_FUNCTION (1 << 0)
283 #define NUMBER_OF_SETS(x) ((x) << 1)
284 #define FLUSH_ALL_ON_EVENT (1 << 10)
285 #define STALL_ON_EVENT (1 << 11)
286 #define SMX_EVENT_CTL 0xA02C
287 #define ES_FLUSH_CTL(x) ((x) << 0)
288 #define GS_FLUSH_CTL(x) ((x) << 3)
289 #define ACK_FLUSH_CTL(x) ((x) << 6)
290 #define SYNC_FLUSH_CTL (1 << 8)
292 #define SPI_CONFIG_CNTL 0x9100
293 #define GPR_WRITE_PRIORITY(x) ((x) << 0)
294 #define SPI_CONFIG_CNTL_1 0x913C
295 #define VTX_DONE_DELAY(x) ((x) << 0)
296 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
297 #define SPI_INPUT_Z 0x286D8
298 #define SPI_PS_IN_CONTROL_0 0x286CC
299 #define NUM_INTERP(x) ((x)<<0)
300 #define POSITION_ENA (1<<8)
301 #define POSITION_CENTROID (1<<9)
302 #define POSITION_ADDR(x) ((x)<<10)
303 #define PARAM_GEN(x) ((x)<<15)
304 #define PARAM_GEN_ADDR(x) ((x)<<19)
305 #define BARYC_SAMPLE_CNTL(x) ((x)<<26)
306 #define PERSP_GRADIENT_ENA (1<<28)
307 #define LINEAR_GRADIENT_ENA (1<<29)
308 #define POSITION_SAMPLE (1<<30)
309 #define BARYC_AT_SAMPLE_ENA (1<<31)
311 #define SQ_CONFIG 0x8C00
312 #define VC_ENABLE (1 << 0)
313 #define EXPORT_SRC_C (1 << 1)
314 #define CS_PRIO(x) ((x) << 18)
315 #define LS_PRIO(x) ((x) << 20)
316 #define HS_PRIO(x) ((x) << 22)
317 #define PS_PRIO(x) ((x) << 24)
318 #define VS_PRIO(x) ((x) << 26)
319 #define GS_PRIO(x) ((x) << 28)
320 #define ES_PRIO(x) ((x) << 30)
321 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04
322 #define NUM_PS_GPRS(x) ((x) << 0)
323 #define NUM_VS_GPRS(x) ((x) << 16)
324 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
325 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08
326 #define NUM_GS_GPRS(x) ((x) << 0)
327 #define NUM_ES_GPRS(x) ((x) << 16)
328 #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C
329 #define NUM_HS_GPRS(x) ((x) << 0)
330 #define NUM_LS_GPRS(x) ((x) << 16)
331 #define SQ_THREAD_RESOURCE_MGMT 0x8C18
332 #define NUM_PS_THREADS(x) ((x) << 0)
333 #define NUM_VS_THREADS(x) ((x) << 8)
334 #define NUM_GS_THREADS(x) ((x) << 16)
335 #define NUM_ES_THREADS(x) ((x) << 24)
336 #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C
337 #define NUM_HS_THREADS(x) ((x) << 0)
338 #define NUM_LS_THREADS(x) ((x) << 8)
339 #define SQ_STACK_RESOURCE_MGMT_1 0x8C20
340 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
341 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
342 #define SQ_STACK_RESOURCE_MGMT_2 0x8C24
343 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
344 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
345 #define SQ_STACK_RESOURCE_MGMT_3 0x8C28
346 #define NUM_HS_STACK_ENTRIES(x) ((x) << 0)
347 #define NUM_LS_STACK_ENTRIES(x) ((x) << 16)
348 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
349 #define SQ_LDS_RESOURCE_MGMT 0x8E2C
351 #define SQ_MS_FIFO_SIZES 0x8CF0
352 #define CACHE_FIFO_SIZE(x) ((x) << 0)
353 #define FETCH_FIFO_HIWATER(x) ((x) << 8)
354 #define DONE_FIFO_HIWATER(x) ((x) << 16)
355 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
357 #define SX_DEBUG_1 0x9058
358 #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
359 #define SX_EXPORT_BUFFER_SIZES 0x900C
360 #define COLOR_BUFFER_SIZE(x) ((x) << 0)
361 #define POSITION_BUFFER_SIZE(x) ((x) << 8)
362 #define SMX_BUFFER_SIZE(x) ((x) << 16)
363 #define SX_MEMORY_EXPORT_BASE 0x9010
364 #define SX_MISC 0x28350
366 #define CB_PERF_CTR0_SEL_0 0x9A20
367 #define CB_PERF_CTR0_SEL_1 0x9A24
368 #define CB_PERF_CTR1_SEL_0 0x9A28
369 #define CB_PERF_CTR1_SEL_1 0x9A2C
370 #define CB_PERF_CTR2_SEL_0 0x9A30
371 #define CB_PERF_CTR2_SEL_1 0x9A34
372 #define CB_PERF_CTR3_SEL_0 0x9A38
373 #define CB_PERF_CTR3_SEL_1 0x9A3C
375 #define TA_CNTL_AUX 0x9508
376 #define DISABLE_CUBE_WRAP (1 << 0)
377 #define DISABLE_CUBE_ANISO (1 << 1)
378 #define SYNC_GRADIENT (1 << 24)
379 #define SYNC_WALKER (1 << 25)
380 #define SYNC_ALIGNER (1 << 26)
382 #define TCP_CHAN_STEER_LO 0x960c
383 #define TCP_CHAN_STEER_HI 0x9610
385 #define VGT_CACHE_INVALIDATION 0x88C4
386 #define CACHE_INVALIDATION(x) ((x) << 0)
390 #define AUTO_INVLD_EN(x) ((x) << 6)
394 #define ES_AND_GS_AUTO 3
395 #define VGT_GS_VERTEX_REUSE 0x88D4
396 #define VGT_NUM_INSTANCES 0x8974
397 #define VGT_OUT_DEALLOC_CNTL 0x28C5C
398 #define DEALLOC_DIST_MASK 0x0000007F
399 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
400 #define VTX_REUSE_DEPTH_MASK 0x000000FF
402 #define VM_CONTEXT0_CNTL 0x1410
403 #define ENABLE_CONTEXT (1 << 0)
404 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
405 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
406 #define VM_CONTEXT1_CNTL 0x1414
407 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
408 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
409 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
410 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
411 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
412 #define REQUEST_TYPE(x) (((x) & 0xf) << 0)
413 #define RESPONSE_TYPE_MASK 0x000000F0
414 #define RESPONSE_TYPE_SHIFT 4
415 #define VM_L2_CNTL 0x1400
416 #define ENABLE_L2_CACHE (1 << 0)
417 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
418 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
419 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
420 #define VM_L2_CNTL2 0x1404
421 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
422 #define INVALIDATE_L2_CACHE (1 << 1)
423 #define VM_L2_CNTL3 0x1408
424 #define BANK_SELECT(x) ((x) << 0)
425 #define CACHE_UPDATE_MODE(x) ((x) << 6)
426 #define VM_L2_STATUS 0x140C
427 #define L2_BUSY (1 << 0)
429 #define WAIT_UNTIL 0x8040
431 #define SRBM_STATUS 0x0E50
432 #define SRBM_SOFT_RESET 0x0E60
433 #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
434 #define SOFT_RESET_BIF (1 << 1)
435 #define SOFT_RESET_CG (1 << 2)
436 #define SOFT_RESET_DC (1 << 5)
437 #define SOFT_RESET_GRBM (1 << 8)
438 #define SOFT_RESET_HDP (1 << 9)
439 #define SOFT_RESET_IH (1 << 10)
440 #define SOFT_RESET_MC (1 << 11)
441 #define SOFT_RESET_RLC (1 << 13)
442 #define SOFT_RESET_ROM (1 << 14)
443 #define SOFT_RESET_SEM (1 << 15)
444 #define SOFT_RESET_VMC (1 << 17)
445 #define SOFT_RESET_TST (1 << 21)
446 #define SOFT_RESET_REGBB (1 << 22)
447 #define SOFT_RESET_ORB (1 << 23)
449 /* display watermarks */
450 #define DC_LB_MEMORY_SPLIT 0x6b0c
451 #define PRIORITY_A_CNT 0x6b18
452 #define PRIORITY_MARK_MASK 0x7fff
453 #define PRIORITY_OFF (1 << 16)
454 #define PRIORITY_ALWAYS_ON (1 << 20)
455 #define PRIORITY_B_CNT 0x6b1c
456 #define PIPE0_ARBITRATION_CONTROL3 0x0bf0
457 # define LATENCY_WATERMARK_MASK(x) ((x) << 16)
458 #define PIPE0_LATENCY_CONTROL 0x0bf4
459 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
460 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
462 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
463 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
464 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
466 #define IH_RB_CNTL 0x3e00
467 # define IH_RB_ENABLE (1 << 0)
468 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */
469 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
470 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
471 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
472 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
473 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
474 #define IH_RB_BASE 0x3e04
475 #define IH_RB_RPTR 0x3e08
476 #define IH_RB_WPTR 0x3e0c
477 # define RB_OVERFLOW (1 << 0)
478 # define WPTR_OFFSET_MASK 0x3fffc
479 #define IH_RB_WPTR_ADDR_HI 0x3e10
480 #define IH_RB_WPTR_ADDR_LO 0x3e14
481 #define IH_CNTL 0x3e18
482 # define ENABLE_INTR (1 << 0)
483 # define IH_MC_SWAP(x) ((x) << 1)
484 # define IH_MC_SWAP_NONE 0
485 # define IH_MC_SWAP_16BIT 1
486 # define IH_MC_SWAP_32BIT 2
487 # define IH_MC_SWAP_64BIT 3
488 # define RPTR_REARM (1 << 4)
489 # define MC_WRREQ_CREDIT(x) ((x) << 15)
490 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
492 #define CP_INT_CNTL 0xc124
493 # define CNTX_BUSY_INT_ENABLE (1 << 19)
494 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
495 # define SCRATCH_INT_ENABLE (1 << 25)
496 # define TIME_STAMP_INT_ENABLE (1 << 26)
497 # define IB2_INT_ENABLE (1 << 29)
498 # define IB1_INT_ENABLE (1 << 30)
499 # define RB_INT_ENABLE (1 << 31)
500 #define CP_INT_STATUS 0xc128
501 # define SCRATCH_INT_STAT (1 << 25)
502 # define TIME_STAMP_INT_STAT (1 << 26)
503 # define IB2_INT_STAT (1 << 29)
504 # define IB1_INT_STAT (1 << 30)
505 # define RB_INT_STAT (1 << 31)
507 #define GRBM_INT_CNTL 0x8060
508 # define RDERR_INT_ENABLE (1 << 0)
509 # define GUI_IDLE_INT_ENABLE (1 << 19)
511 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
512 #define CRTC_STATUS_FRAME_COUNT 0x6e98
514 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
515 #define VLINE_STATUS 0x6bb8
516 # define VLINE_OCCURRED (1 << 0)
517 # define VLINE_ACK (1 << 4)
518 # define VLINE_STAT (1 << 12)
519 # define VLINE_INTERRUPT (1 << 16)
520 # define VLINE_INTERRUPT_TYPE (1 << 17)
521 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
522 #define VBLANK_STATUS 0x6bbc
523 # define VBLANK_OCCURRED (1 << 0)
524 # define VBLANK_ACK (1 << 4)
525 # define VBLANK_STAT (1 << 12)
526 # define VBLANK_INTERRUPT (1 << 16)
527 # define VBLANK_INTERRUPT_TYPE (1 << 17)
529 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
530 #define INT_MASK 0x6b40
531 # define VBLANK_INT_MASK (1 << 0)
532 # define VLINE_INT_MASK (1 << 4)
534 #define DISP_INTERRUPT_STATUS 0x60f4
535 # define LB_D1_VLINE_INTERRUPT (1 << 2)
536 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
537 # define DC_HPD1_INTERRUPT (1 << 17)
538 # define DC_HPD1_RX_INTERRUPT (1 << 18)
539 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
540 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
541 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
542 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
543 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
544 # define LB_D2_VLINE_INTERRUPT (1 << 2)
545 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
546 # define DC_HPD2_INTERRUPT (1 << 17)
547 # define DC_HPD2_RX_INTERRUPT (1 << 18)
548 # define DISP_TIMER_INTERRUPT (1 << 24)
549 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
550 # define LB_D3_VLINE_INTERRUPT (1 << 2)
551 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
552 # define DC_HPD3_INTERRUPT (1 << 17)
553 # define DC_HPD3_RX_INTERRUPT (1 << 18)
554 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
555 # define LB_D4_VLINE_INTERRUPT (1 << 2)
556 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
557 # define DC_HPD4_INTERRUPT (1 << 17)
558 # define DC_HPD4_RX_INTERRUPT (1 << 18)
559 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
560 # define LB_D5_VLINE_INTERRUPT (1 << 2)
561 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
562 # define DC_HPD5_INTERRUPT (1 << 17)
563 # define DC_HPD5_RX_INTERRUPT (1 << 18)
564 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
565 # define LB_D6_VLINE_INTERRUPT (1 << 2)
566 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
567 # define DC_HPD6_INTERRUPT (1 << 17)
568 # define DC_HPD6_RX_INTERRUPT (1 << 18)
570 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
571 #define GRPH_INT_STATUS 0x6858
572 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
573 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
574 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
575 #define GRPH_INT_CONTROL 0x685c
576 # define GRPH_PFLIP_INT_MASK (1 << 0)
577 # define GRPH_PFLIP_INT_TYPE (1 << 8)
579 #define DACA_AUTODETECT_INT_CONTROL 0x66c8
580 #define DACB_AUTODETECT_INT_CONTROL 0x67c8
582 #define DC_HPD1_INT_STATUS 0x601c
583 #define DC_HPD2_INT_STATUS 0x6028
584 #define DC_HPD3_INT_STATUS 0x6034
585 #define DC_HPD4_INT_STATUS 0x6040
586 #define DC_HPD5_INT_STATUS 0x604c
587 #define DC_HPD6_INT_STATUS 0x6058
588 # define DC_HPDx_INT_STATUS (1 << 0)
589 # define DC_HPDx_SENSE (1 << 1)
590 # define DC_HPDx_RX_INT_STATUS (1 << 8)
592 #define DC_HPD1_INT_CONTROL 0x6020
593 #define DC_HPD2_INT_CONTROL 0x602c
594 #define DC_HPD3_INT_CONTROL 0x6038
595 #define DC_HPD4_INT_CONTROL 0x6044
596 #define DC_HPD5_INT_CONTROL 0x6050
597 #define DC_HPD6_INT_CONTROL 0x605c
598 # define DC_HPDx_INT_ACK (1 << 0)
599 # define DC_HPDx_INT_POLARITY (1 << 8)
600 # define DC_HPDx_INT_EN (1 << 16)
601 # define DC_HPDx_RX_INT_ACK (1 << 20)
602 # define DC_HPDx_RX_INT_EN (1 << 24)
604 #define DC_HPD1_CONTROL 0x6024
605 #define DC_HPD2_CONTROL 0x6030
606 #define DC_HPD3_CONTROL 0x603c
607 #define DC_HPD4_CONTROL 0x6048
608 #define DC_HPD5_CONTROL 0x6054
609 #define DC_HPD6_CONTROL 0x6060
610 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
611 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
612 # define DC_HPDx_EN (1 << 28)
614 /* PCIE link stuff */
615 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
616 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
617 # define LC_LINK_WIDTH_SHIFT 0
618 # define LC_LINK_WIDTH_MASK 0x7
619 # define LC_LINK_WIDTH_X0 0
620 # define LC_LINK_WIDTH_X1 1
621 # define LC_LINK_WIDTH_X2 2
622 # define LC_LINK_WIDTH_X4 3
623 # define LC_LINK_WIDTH_X8 4
624 # define LC_LINK_WIDTH_X16 6
625 # define LC_LINK_WIDTH_RD_SHIFT 4
626 # define LC_LINK_WIDTH_RD_MASK 0x70
627 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
628 # define LC_RECONFIG_NOW (1 << 8)
629 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
630 # define LC_RENEGOTIATE_EN (1 << 10)
631 # define LC_SHORT_RECONFIG_EN (1 << 11)
632 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
633 # define LC_UPCONFIGURE_DIS (1 << 13)
634 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
635 # define LC_GEN2_EN_STRAP (1 << 0)
636 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
637 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
638 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
639 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
640 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
641 # define LC_CURRENT_DATA_RATE (1 << 11)
642 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
643 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
644 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
645 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
646 #define MM_CFGREGS_CNTL 0x544c
647 # define MM_WR_TO_CFG_EN (1 << 3)
648 #define LINK_CNTL2 0x88 /* F0 */
649 # define TARGET_LINK_SPEED_MASK (0xf << 0)
650 # define SELECTABLE_DEEMPHASIS (1 << 6)
655 #define PACKET_TYPE0 0
656 #define PACKET_TYPE1 1
657 #define PACKET_TYPE2 2
658 #define PACKET_TYPE3 3
660 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
661 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
662 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
663 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
664 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
665 (((reg) >> 2) & 0xFFFF) | \
666 ((n) & 0x3FFF) << 16)
667 #define CP_PACKET2 0x80000000
668 #define PACKET2_PAD_SHIFT 0
669 #define PACKET2_PAD_MASK (0x3fffffff << 0)
671 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
673 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
674 (((op) & 0xFF) << 8) | \
675 ((n) & 0x3FFF) << 16)
678 #define PACKET3_NOP 0x10
679 #define PACKET3_SET_BASE 0x11
680 #define PACKET3_CLEAR_STATE 0x12
681 #define PACKET3_INDEX_BUFFER_SIZE 0x13
682 #define PACKET3_DISPATCH_DIRECT 0x15
683 #define PACKET3_DISPATCH_INDIRECT 0x16
684 #define PACKET3_INDIRECT_BUFFER_END 0x17
685 #define PACKET3_MODE_CONTROL 0x18
686 #define PACKET3_SET_PREDICATION 0x20
687 #define PACKET3_REG_RMW 0x21
688 #define PACKET3_COND_EXEC 0x22
689 #define PACKET3_PRED_EXEC 0x23
690 #define PACKET3_DRAW_INDIRECT 0x24
691 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
692 #define PACKET3_INDEX_BASE 0x26
693 #define PACKET3_DRAW_INDEX_2 0x27
694 #define PACKET3_CONTEXT_CONTROL 0x28
695 #define PACKET3_DRAW_INDEX_OFFSET 0x29
696 #define PACKET3_INDEX_TYPE 0x2A
697 #define PACKET3_DRAW_INDEX 0x2B
698 #define PACKET3_DRAW_INDEX_AUTO 0x2D
699 #define PACKET3_DRAW_INDEX_IMMD 0x2E
700 #define PACKET3_NUM_INSTANCES 0x2F
701 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
702 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
703 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
704 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
705 #define PACKET3_MEM_SEMAPHORE 0x39
706 #define PACKET3_MPEG_INDEX 0x3A
707 #define PACKET3_WAIT_REG_MEM 0x3C
708 #define PACKET3_MEM_WRITE 0x3D
709 #define PACKET3_INDIRECT_BUFFER 0x32
710 #define PACKET3_SURFACE_SYNC 0x43
711 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
712 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
713 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
714 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
715 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
716 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
717 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
718 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
719 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
720 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
721 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
722 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
723 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
724 # define PACKET3_FULL_CACHE_ENA (1 << 20)
725 # define PACKET3_TC_ACTION_ENA (1 << 23)
726 # define PACKET3_VC_ACTION_ENA (1 << 24)
727 # define PACKET3_CB_ACTION_ENA (1 << 25)
728 # define PACKET3_DB_ACTION_ENA (1 << 26)
729 # define PACKET3_SH_ACTION_ENA (1 << 27)
730 # define PACKET3_SX_ACTION_ENA (1 << 28)
731 #define PACKET3_ME_INITIALIZE 0x44
732 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
733 #define PACKET3_COND_WRITE 0x45
734 #define PACKET3_EVENT_WRITE 0x46
735 #define PACKET3_EVENT_WRITE_EOP 0x47
736 #define PACKET3_EVENT_WRITE_EOS 0x48
737 #define PACKET3_PREAMBLE_CNTL 0x4A
738 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
739 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
740 #define PACKET3_RB_OFFSET 0x4B
741 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
742 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
743 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E
744 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F
745 #define PACKET3_ONE_REG_WRITE 0x57
746 #define PACKET3_SET_CONFIG_REG 0x68
747 #define PACKET3_SET_CONFIG_REG_START 0x00008000
748 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00
749 #define PACKET3_SET_CONTEXT_REG 0x69
750 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
751 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
752 #define PACKET3_SET_ALU_CONST 0x6A
753 /* alu const buffers only; no reg file */
754 #define PACKET3_SET_BOOL_CONST 0x6B
755 #define PACKET3_SET_BOOL_CONST_START 0x0003a500
756 #define PACKET3_SET_BOOL_CONST_END 0x0003a518
757 #define PACKET3_SET_LOOP_CONST 0x6C
758 #define PACKET3_SET_LOOP_CONST_START 0x0003a200
759 #define PACKET3_SET_LOOP_CONST_END 0x0003a500
760 #define PACKET3_SET_RESOURCE 0x6D
761 #define PACKET3_SET_RESOURCE_START 0x00030000
762 #define PACKET3_SET_RESOURCE_END 0x00038000
763 #define PACKET3_SET_SAMPLER 0x6E
764 #define PACKET3_SET_SAMPLER_START 0x0003c000
765 #define PACKET3_SET_SAMPLER_END 0x0003c600
766 #define PACKET3_SET_CTL_CONST 0x6F
767 #define PACKET3_SET_CTL_CONST_START 0x0003cff0
768 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c
769 #define PACKET3_SET_RESOURCE_OFFSET 0x70
770 #define PACKET3_SET_ALU_CONST_VS 0x71
771 #define PACKET3_SET_ALU_CONST_DI 0x72
772 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
773 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
774 #define PACKET3_SET_APPEND_CNT 0x75
776 #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c
777 #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30)
778 #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3)
779 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0
780 #define SQ_TEX_VTX_INVALID_BUFFER 0x1
781 #define SQ_TEX_VTX_VALID_TEXTURE 0x2
782 #define SQ_TEX_VTX_VALID_BUFFER 0x3
784 #define SQ_CONST_MEM_BASE 0x8df8
786 #define SQ_ESGS_RING_BASE 0x8c40
787 #define SQ_ESGS_RING_SIZE 0x8c44
788 #define SQ_GSVS_RING_BASE 0x8c48
789 #define SQ_GSVS_RING_SIZE 0x8c4c
790 #define SQ_ESTMP_RING_BASE 0x8c50
791 #define SQ_ESTMP_RING_SIZE 0x8c54
792 #define SQ_GSTMP_RING_BASE 0x8c58
793 #define SQ_GSTMP_RING_SIZE 0x8c5c
794 #define SQ_VSTMP_RING_BASE 0x8c60
795 #define SQ_VSTMP_RING_SIZE 0x8c64
796 #define SQ_PSTMP_RING_BASE 0x8c68
797 #define SQ_PSTMP_RING_SIZE 0x8c6c
798 #define SQ_LSTMP_RING_BASE 0x8e10
799 #define SQ_LSTMP_RING_SIZE 0x8e14
800 #define SQ_HSTMP_RING_BASE 0x8e18
801 #define SQ_HSTMP_RING_SIZE 0x8e1c
802 #define VGT_TF_RING_SIZE 0x8988
804 #define SQ_ESGS_RING_ITEMSIZE 0x28900
805 #define SQ_GSVS_RING_ITEMSIZE 0x28904
806 #define SQ_ESTMP_RING_ITEMSIZE 0x28908
807 #define SQ_GSTMP_RING_ITEMSIZE 0x2890c
808 #define SQ_VSTMP_RING_ITEMSIZE 0x28910
809 #define SQ_PSTMP_RING_ITEMSIZE 0x28914
810 #define SQ_LSTMP_RING_ITEMSIZE 0x28830
811 #define SQ_HSTMP_RING_ITEMSIZE 0x28834
813 #define SQ_GS_VERT_ITEMSIZE 0x2891c
814 #define SQ_GS_VERT_ITEMSIZE_1 0x28920
815 #define SQ_GS_VERT_ITEMSIZE_2 0x28924
816 #define SQ_GS_VERT_ITEMSIZE_3 0x28928
817 #define SQ_GSVS_RING_OFFSET_1 0x2892c
818 #define SQ_GSVS_RING_OFFSET_2 0x28930
819 #define SQ_GSVS_RING_OFFSET_3 0x28934
821 #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140
822 #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80
824 #define SQ_ALU_CONST_CACHE_PS_0 0x28940
825 #define SQ_ALU_CONST_CACHE_PS_1 0x28944
826 #define SQ_ALU_CONST_CACHE_PS_2 0x28948
827 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c
828 #define SQ_ALU_CONST_CACHE_PS_4 0x28950
829 #define SQ_ALU_CONST_CACHE_PS_5 0x28954
830 #define SQ_ALU_CONST_CACHE_PS_6 0x28958
831 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c
832 #define SQ_ALU_CONST_CACHE_PS_8 0x28960
833 #define SQ_ALU_CONST_CACHE_PS_9 0x28964
834 #define SQ_ALU_CONST_CACHE_PS_10 0x28968
835 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c
836 #define SQ_ALU_CONST_CACHE_PS_12 0x28970
837 #define SQ_ALU_CONST_CACHE_PS_13 0x28974
838 #define SQ_ALU_CONST_CACHE_PS_14 0x28978
839 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c
840 #define SQ_ALU_CONST_CACHE_VS_0 0x28980
841 #define SQ_ALU_CONST_CACHE_VS_1 0x28984
842 #define SQ_ALU_CONST_CACHE_VS_2 0x28988
843 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c
844 #define SQ_ALU_CONST_CACHE_VS_4 0x28990
845 #define SQ_ALU_CONST_CACHE_VS_5 0x28994
846 #define SQ_ALU_CONST_CACHE_VS_6 0x28998
847 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c
848 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0
849 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4
850 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8
851 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac
852 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0
853 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4
854 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8
855 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc
856 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0
857 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4
858 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8
859 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc
860 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0
861 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4
862 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8
863 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc
864 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0
865 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4
866 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8
867 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec
868 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0
869 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4
870 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8
871 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc
872 #define SQ_ALU_CONST_CACHE_HS_0 0x28f00
873 #define SQ_ALU_CONST_CACHE_HS_1 0x28f04
874 #define SQ_ALU_CONST_CACHE_HS_2 0x28f08
875 #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c
876 #define SQ_ALU_CONST_CACHE_HS_4 0x28f10
877 #define SQ_ALU_CONST_CACHE_HS_5 0x28f14
878 #define SQ_ALU_CONST_CACHE_HS_6 0x28f18
879 #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c
880 #define SQ_ALU_CONST_CACHE_HS_8 0x28f20
881 #define SQ_ALU_CONST_CACHE_HS_9 0x28f24
882 #define SQ_ALU_CONST_CACHE_HS_10 0x28f28
883 #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c
884 #define SQ_ALU_CONST_CACHE_HS_12 0x28f30
885 #define SQ_ALU_CONST_CACHE_HS_13 0x28f34
886 #define SQ_ALU_CONST_CACHE_HS_14 0x28f38
887 #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c
888 #define SQ_ALU_CONST_CACHE_LS_0 0x28f40
889 #define SQ_ALU_CONST_CACHE_LS_1 0x28f44
890 #define SQ_ALU_CONST_CACHE_LS_2 0x28f48
891 #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c
892 #define SQ_ALU_CONST_CACHE_LS_4 0x28f50
893 #define SQ_ALU_CONST_CACHE_LS_5 0x28f54
894 #define SQ_ALU_CONST_CACHE_LS_6 0x28f58
895 #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c
896 #define SQ_ALU_CONST_CACHE_LS_8 0x28f60
897 #define SQ_ALU_CONST_CACHE_LS_9 0x28f64
898 #define SQ_ALU_CONST_CACHE_LS_10 0x28f68
899 #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c
900 #define SQ_ALU_CONST_CACHE_LS_12 0x28f70
901 #define SQ_ALU_CONST_CACHE_LS_13 0x28f74
902 #define SQ_ALU_CONST_CACHE_LS_14 0x28f78
903 #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c
905 #define PA_SC_SCREEN_SCISSOR_TL 0x28030
906 #define PA_SC_GENERIC_SCISSOR_TL 0x28240
907 #define PA_SC_WINDOW_SCISSOR_TL 0x28204
908 #define VGT_PRIMITIVE_TYPE 0x8958
910 #define DB_DEPTH_CONTROL 0x28800
911 #define DB_DEPTH_VIEW 0x28008
912 #define DB_HTILE_DATA_BASE 0x28014
913 #define DB_Z_INFO 0x28040
914 # define Z_ARRAY_MODE(x) ((x) << 4)
915 # define DB_TILE_SPLIT(x) (((x) & 0x7) << 8)
916 # define DB_NUM_BANKS(x) (((x) & 0x3) << 12)
917 # define DB_BANK_WIDTH(x) (((x) & 0x3) << 16)
918 # define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20)
919 #define DB_STENCIL_INFO 0x28044
920 #define DB_Z_READ_BASE 0x28048
921 #define DB_STENCIL_READ_BASE 0x2804c
922 #define DB_Z_WRITE_BASE 0x28050
923 #define DB_STENCIL_WRITE_BASE 0x28054
924 #define DB_DEPTH_SIZE 0x28058
926 #define SQ_PGM_START_PS 0x28840
927 #define SQ_PGM_START_VS 0x2885c
928 #define SQ_PGM_START_GS 0x28874
929 #define SQ_PGM_START_ES 0x2888c
930 #define SQ_PGM_START_FS 0x288a4
931 #define SQ_PGM_START_HS 0x288b8
932 #define SQ_PGM_START_LS 0x288d0
934 #define VGT_STRMOUT_CONFIG 0x28b94
935 #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98
937 #define CB_TARGET_MASK 0x28238
938 #define CB_SHADER_MASK 0x2823c
940 #define GDS_ADDR_BASE 0x28720
942 #define CB_IMMED0_BASE 0x28b9c
943 #define CB_IMMED1_BASE 0x28ba0
944 #define CB_IMMED2_BASE 0x28ba4
945 #define CB_IMMED3_BASE 0x28ba8
946 #define CB_IMMED4_BASE 0x28bac
947 #define CB_IMMED5_BASE 0x28bb0
948 #define CB_IMMED6_BASE 0x28bb4
949 #define CB_IMMED7_BASE 0x28bb8
950 #define CB_IMMED8_BASE 0x28bbc
951 #define CB_IMMED9_BASE 0x28bc0
952 #define CB_IMMED10_BASE 0x28bc4
953 #define CB_IMMED11_BASE 0x28bc8
955 /* all 12 CB blocks have these regs */
956 #define CB_COLOR0_BASE 0x28c60
957 #define CB_COLOR0_PITCH 0x28c64
958 #define CB_COLOR0_SLICE 0x28c68
959 #define CB_COLOR0_VIEW 0x28c6c
960 #define CB_COLOR0_INFO 0x28c70
961 # define CB_FORMAT(x) ((x) << 2)
962 # define CB_ARRAY_MODE(x) ((x) << 8)
963 # define ARRAY_LINEAR_GENERAL 0
964 # define ARRAY_LINEAR_ALIGNED 1
965 # define ARRAY_1D_TILED_THIN1 2
966 # define ARRAY_2D_TILED_THIN1 4
967 # define CB_SOURCE_FORMAT(x) ((x) << 24)
968 # define CB_SF_EXPORT_FULL 0
969 # define CB_SF_EXPORT_NORM 1
970 #define CB_COLOR0_ATTRIB 0x28c74
971 # define CB_TILE_SPLIT(x) (((x) & 0x7) << 5)
972 # define ADDR_SURF_TILE_SPLIT_64B 0
973 # define ADDR_SURF_TILE_SPLIT_128B 1
974 # define ADDR_SURF_TILE_SPLIT_256B 2
975 # define ADDR_SURF_TILE_SPLIT_512B 3
976 # define ADDR_SURF_TILE_SPLIT_1KB 4
977 # define ADDR_SURF_TILE_SPLIT_2KB 5
978 # define ADDR_SURF_TILE_SPLIT_4KB 6
979 # define CB_NUM_BANKS(x) (((x) & 0x3) << 10)
980 # define ADDR_SURF_2_BANK 0
981 # define ADDR_SURF_4_BANK 1
982 # define ADDR_SURF_8_BANK 2
983 # define ADDR_SURF_16_BANK 3
984 # define CB_BANK_WIDTH(x) (((x) & 0x3) << 13)
985 # define ADDR_SURF_BANK_WIDTH_1 0
986 # define ADDR_SURF_BANK_WIDTH_2 1
987 # define ADDR_SURF_BANK_WIDTH_4 2
988 # define ADDR_SURF_BANK_WIDTH_8 3
989 # define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16)
990 # define ADDR_SURF_BANK_HEIGHT_1 0
991 # define ADDR_SURF_BANK_HEIGHT_2 1
992 # define ADDR_SURF_BANK_HEIGHT_4 2
993 # define ADDR_SURF_BANK_HEIGHT_8 3
994 #define CB_COLOR0_DIM 0x28c78
995 /* only CB0-7 blocks have these regs */
996 #define CB_COLOR0_CMASK 0x28c7c
997 #define CB_COLOR0_CMASK_SLICE 0x28c80
998 #define CB_COLOR0_FMASK 0x28c84
999 #define CB_COLOR0_FMASK_SLICE 0x28c88
1000 #define CB_COLOR0_CLEAR_WORD0 0x28c8c
1001 #define CB_COLOR0_CLEAR_WORD1 0x28c90
1002 #define CB_COLOR0_CLEAR_WORD2 0x28c94
1003 #define CB_COLOR0_CLEAR_WORD3 0x28c98
1005 #define CB_COLOR1_BASE 0x28c9c
1006 #define CB_COLOR2_BASE 0x28cd8
1007 #define CB_COLOR3_BASE 0x28d14
1008 #define CB_COLOR4_BASE 0x28d50
1009 #define CB_COLOR5_BASE 0x28d8c
1010 #define CB_COLOR6_BASE 0x28dc8
1011 #define CB_COLOR7_BASE 0x28e04
1012 #define CB_COLOR8_BASE 0x28e40
1013 #define CB_COLOR9_BASE 0x28e5c
1014 #define CB_COLOR10_BASE 0x28e78
1015 #define CB_COLOR11_BASE 0x28e94
1017 #define CB_COLOR1_PITCH 0x28ca0
1018 #define CB_COLOR2_PITCH 0x28cdc
1019 #define CB_COLOR3_PITCH 0x28d18
1020 #define CB_COLOR4_PITCH 0x28d54
1021 #define CB_COLOR5_PITCH 0x28d90
1022 #define CB_COLOR6_PITCH 0x28dcc
1023 #define CB_COLOR7_PITCH 0x28e08
1024 #define CB_COLOR8_PITCH 0x28e44
1025 #define CB_COLOR9_PITCH 0x28e60
1026 #define CB_COLOR10_PITCH 0x28e7c
1027 #define CB_COLOR11_PITCH 0x28e98
1029 #define CB_COLOR1_SLICE 0x28ca4
1030 #define CB_COLOR2_SLICE 0x28ce0
1031 #define CB_COLOR3_SLICE 0x28d1c
1032 #define CB_COLOR4_SLICE 0x28d58
1033 #define CB_COLOR5_SLICE 0x28d94
1034 #define CB_COLOR6_SLICE 0x28dd0
1035 #define CB_COLOR7_SLICE 0x28e0c
1036 #define CB_COLOR8_SLICE 0x28e48
1037 #define CB_COLOR9_SLICE 0x28e64
1038 #define CB_COLOR10_SLICE 0x28e80
1039 #define CB_COLOR11_SLICE 0x28e9c
1041 #define CB_COLOR1_VIEW 0x28ca8
1042 #define CB_COLOR2_VIEW 0x28ce4
1043 #define CB_COLOR3_VIEW 0x28d20
1044 #define CB_COLOR4_VIEW 0x28d5c
1045 #define CB_COLOR5_VIEW 0x28d98
1046 #define CB_COLOR6_VIEW 0x28dd4
1047 #define CB_COLOR7_VIEW 0x28e10
1048 #define CB_COLOR8_VIEW 0x28e4c
1049 #define CB_COLOR9_VIEW 0x28e68
1050 #define CB_COLOR10_VIEW 0x28e84
1051 #define CB_COLOR11_VIEW 0x28ea0
1053 #define CB_COLOR1_INFO 0x28cac
1054 #define CB_COLOR2_INFO 0x28ce8
1055 #define CB_COLOR3_INFO 0x28d24
1056 #define CB_COLOR4_INFO 0x28d60
1057 #define CB_COLOR5_INFO 0x28d9c
1058 #define CB_COLOR6_INFO 0x28dd8
1059 #define CB_COLOR7_INFO 0x28e14
1060 #define CB_COLOR8_INFO 0x28e50
1061 #define CB_COLOR9_INFO 0x28e6c
1062 #define CB_COLOR10_INFO 0x28e88
1063 #define CB_COLOR11_INFO 0x28ea4
1065 #define CB_COLOR1_ATTRIB 0x28cb0
1066 #define CB_COLOR2_ATTRIB 0x28cec
1067 #define CB_COLOR3_ATTRIB 0x28d28
1068 #define CB_COLOR4_ATTRIB 0x28d64
1069 #define CB_COLOR5_ATTRIB 0x28da0
1070 #define CB_COLOR6_ATTRIB 0x28ddc
1071 #define CB_COLOR7_ATTRIB 0x28e18
1072 #define CB_COLOR8_ATTRIB 0x28e54
1073 #define CB_COLOR9_ATTRIB 0x28e70
1074 #define CB_COLOR10_ATTRIB 0x28e8c
1075 #define CB_COLOR11_ATTRIB 0x28ea8
1077 #define CB_COLOR1_DIM 0x28cb4
1078 #define CB_COLOR2_DIM 0x28cf0
1079 #define CB_COLOR3_DIM 0x28d2c
1080 #define CB_COLOR4_DIM 0x28d68
1081 #define CB_COLOR5_DIM 0x28da4
1082 #define CB_COLOR6_DIM 0x28de0
1083 #define CB_COLOR7_DIM 0x28e1c
1084 #define CB_COLOR8_DIM 0x28e58
1085 #define CB_COLOR9_DIM 0x28e74
1086 #define CB_COLOR10_DIM 0x28e90
1087 #define CB_COLOR11_DIM 0x28eac
1089 #define CB_COLOR1_CMASK 0x28cb8
1090 #define CB_COLOR2_CMASK 0x28cf4
1091 #define CB_COLOR3_CMASK 0x28d30
1092 #define CB_COLOR4_CMASK 0x28d6c
1093 #define CB_COLOR5_CMASK 0x28da8
1094 #define CB_COLOR6_CMASK 0x28de4
1095 #define CB_COLOR7_CMASK 0x28e20
1097 #define CB_COLOR1_CMASK_SLICE 0x28cbc
1098 #define CB_COLOR2_CMASK_SLICE 0x28cf8
1099 #define CB_COLOR3_CMASK_SLICE 0x28d34
1100 #define CB_COLOR4_CMASK_SLICE 0x28d70
1101 #define CB_COLOR5_CMASK_SLICE 0x28dac
1102 #define CB_COLOR6_CMASK_SLICE 0x28de8
1103 #define CB_COLOR7_CMASK_SLICE 0x28e24
1105 #define CB_COLOR1_FMASK 0x28cc0
1106 #define CB_COLOR2_FMASK 0x28cfc
1107 #define CB_COLOR3_FMASK 0x28d38
1108 #define CB_COLOR4_FMASK 0x28d74
1109 #define CB_COLOR5_FMASK 0x28db0
1110 #define CB_COLOR6_FMASK 0x28dec
1111 #define CB_COLOR7_FMASK 0x28e28
1113 #define CB_COLOR1_FMASK_SLICE 0x28cc4
1114 #define CB_COLOR2_FMASK_SLICE 0x28d00
1115 #define CB_COLOR3_FMASK_SLICE 0x28d3c
1116 #define CB_COLOR4_FMASK_SLICE 0x28d78
1117 #define CB_COLOR5_FMASK_SLICE 0x28db4
1118 #define CB_COLOR6_FMASK_SLICE 0x28df0
1119 #define CB_COLOR7_FMASK_SLICE 0x28e2c
1121 #define CB_COLOR1_CLEAR_WORD0 0x28cc8
1122 #define CB_COLOR2_CLEAR_WORD0 0x28d04
1123 #define CB_COLOR3_CLEAR_WORD0 0x28d40
1124 #define CB_COLOR4_CLEAR_WORD0 0x28d7c
1125 #define CB_COLOR5_CLEAR_WORD0 0x28db8
1126 #define CB_COLOR6_CLEAR_WORD0 0x28df4
1127 #define CB_COLOR7_CLEAR_WORD0 0x28e30
1129 #define CB_COLOR1_CLEAR_WORD1 0x28ccc
1130 #define CB_COLOR2_CLEAR_WORD1 0x28d08
1131 #define CB_COLOR3_CLEAR_WORD1 0x28d44
1132 #define CB_COLOR4_CLEAR_WORD1 0x28d80
1133 #define CB_COLOR5_CLEAR_WORD1 0x28dbc
1134 #define CB_COLOR6_CLEAR_WORD1 0x28df8
1135 #define CB_COLOR7_CLEAR_WORD1 0x28e34
1137 #define CB_COLOR1_CLEAR_WORD2 0x28cd0
1138 #define CB_COLOR2_CLEAR_WORD2 0x28d0c
1139 #define CB_COLOR3_CLEAR_WORD2 0x28d48
1140 #define CB_COLOR4_CLEAR_WORD2 0x28d84
1141 #define CB_COLOR5_CLEAR_WORD2 0x28dc0
1142 #define CB_COLOR6_CLEAR_WORD2 0x28dfc
1143 #define CB_COLOR7_CLEAR_WORD2 0x28e38
1145 #define CB_COLOR1_CLEAR_WORD3 0x28cd4
1146 #define CB_COLOR2_CLEAR_WORD3 0x28d10
1147 #define CB_COLOR3_CLEAR_WORD3 0x28d4c
1148 #define CB_COLOR4_CLEAR_WORD3 0x28d88
1149 #define CB_COLOR5_CLEAR_WORD3 0x28dc4
1150 #define CB_COLOR6_CLEAR_WORD3 0x28e00
1151 #define CB_COLOR7_CLEAR_WORD3 0x28e3c
1153 #define SQ_TEX_RESOURCE_WORD0_0 0x30000
1154 # define TEX_DIM(x) ((x) << 0)
1155 # define SQ_TEX_DIM_1D 0
1156 # define SQ_TEX_DIM_2D 1
1157 # define SQ_TEX_DIM_3D 2
1158 # define SQ_TEX_DIM_CUBEMAP 3
1159 # define SQ_TEX_DIM_1D_ARRAY 4
1160 # define SQ_TEX_DIM_2D_ARRAY 5
1161 # define SQ_TEX_DIM_2D_MSAA 6
1162 # define SQ_TEX_DIM_2D_ARRAY_MSAA 7
1163 #define SQ_TEX_RESOURCE_WORD1_0 0x30004
1164 # define TEX_ARRAY_MODE(x) ((x) << 28)
1165 #define SQ_TEX_RESOURCE_WORD2_0 0x30008
1166 #define SQ_TEX_RESOURCE_WORD3_0 0x3000C
1167 #define SQ_TEX_RESOURCE_WORD4_0 0x30010
1168 # define TEX_DST_SEL_X(x) ((x) << 16)
1169 # define TEX_DST_SEL_Y(x) ((x) << 19)
1170 # define TEX_DST_SEL_Z(x) ((x) << 22)
1171 # define TEX_DST_SEL_W(x) ((x) << 25)
1178 #define SQ_TEX_RESOURCE_WORD5_0 0x30014
1179 #define SQ_TEX_RESOURCE_WORD6_0 0x30018
1180 # define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29)
1181 #define SQ_TEX_RESOURCE_WORD7_0 0x3001c
1182 # define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8)
1183 # define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10)
1184 # define TEX_NUM_BANKS(x) (((x) & 0x3) << 16)
1186 #define SQ_VTX_CONSTANT_WORD0_0 0x30000
1187 #define SQ_VTX_CONSTANT_WORD1_0 0x30004
1188 #define SQ_VTX_CONSTANT_WORD2_0 0x30008
1189 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)
1190 # define SQ_VTXC_STRIDE(x) ((x) << 8)
1191 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)
1192 # define SQ_ENDIAN_NONE 0
1193 # define SQ_ENDIAN_8IN16 1
1194 # define SQ_ENDIAN_8IN32 2
1195 #define SQ_VTX_CONSTANT_WORD3_0 0x3000C
1196 # define SQ_VTCX_SEL_X(x) ((x) << 3)
1197 # define SQ_VTCX_SEL_Y(x) ((x) << 6)
1198 # define SQ_VTCX_SEL_Z(x) ((x) << 9)
1199 # define SQ_VTCX_SEL_W(x) ((x) << 12)
1200 #define SQ_VTX_CONSTANT_WORD4_0 0x30010
1201 #define SQ_VTX_CONSTANT_WORD5_0 0x30014
1202 #define SQ_VTX_CONSTANT_WORD6_0 0x30018
1203 #define SQ_VTX_CONSTANT_WORD7_0 0x3001c
1205 /* cayman 3D regs */
1206 #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B0
1207 #define CAYMAN_DB_EQAA 0x28804
1208 #define CAYMAN_DB_DEPTH_INFO 0x2803C
1209 #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0
1210 #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0
1211 #define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7
1212 #define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358
1213 /* cayman packet3 addition */
1214 #define CAYMAN_PACKET3_DEALLOC_STATE 0x14