drivers/gpu/drm/radeon/evergreen_hdmi.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Christian König.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Christian König
  25  *          Rafał Miłecki
  26  */
  27 #include <linux/hdmi.h>
  28 #include <drm/drmP.h>
  29 #include <drm/radeon_drm.h>
  30 #include "radeon.h"
  31 #include "radeon_asic.h"
  32 #include "evergreend.h"
  33 #include "atom.h"
  34
  35 extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder);
  36 extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder);
  37 extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
  38
  39 /*
  40  * update the N and CTS parameters for a given pixel clock rate
  41  */
  42 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
  43 {
  44         struct drm_device *dev = encoder->dev;
  45         struct radeon_device *rdev = dev->dev_private;
  46         struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
  47         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  48         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  49         uint32_t offset = dig->afmt->offset;
  50
  51         WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
  52         WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
  53
  54         WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
  55         WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
  56
  57         WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
  58         WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
  59 }
  60
  61 static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
  62 {
  63         struct radeon_device *rdev = encoder->dev->dev_private;
  64         struct drm_connector *connector;
  65         struct radeon_connector *radeon_connector = NULL;
  66         struct cea_sad *sads;
  67         int i, sad_count;
  68
  69         static const u16 eld_reg_to_type[][2] = {
  70                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
  71                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
  72                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
  73                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
  74                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
  75                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
  76                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
  77                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
  78                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
  79                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
  80                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
  81                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
  82         };
  83
  84         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
  85                 if (connector->encoder == encoder)
  86                         radeon_connector = to_radeon_connector(connector);
  87         }
  88
  89         if (!radeon_connector) {
  90                 DRM_ERROR("Couldn't find encoder's connector\n");
  91                 return;
  92         }
  93
  94         sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
  95         if (sad_count < 0) {
  96                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
  97                 return;
  98         }
  99         BUG_ON(!sads);
 100
 101         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
 102                 u32 value = 0;
 103                 int j;
 104
 105                 for (j = 0; j < sad_count; j++) {
 106                         struct cea_sad *sad = &sads[j];
 107
 108                         if (sad->format == eld_reg_to_type[i][1]) {
 109                                 value = MAX_CHANNELS(sad->channels) |
 110                                         DESCRIPTOR_BYTE_2(sad->byte2) |
 111                                         SUPPORTED_FREQUENCIES(sad->freq);
 112                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
 113                                         value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);
 114                                 break;
 115                         }
 116                 }
 117                 WREG32(eld_reg_to_type[i][0], value);
 118         }
 119
 120         kfree(sads);
 121 }
 122
 123 /*
 124  * build a HDMI Video Info Frame
 125  */
 126 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
 127                                                 void *buffer, size_t size)
 128 {
 129         struct drm_device *dev = encoder->dev;
 130         struct radeon_device *rdev = dev->dev_private;
 131         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 132         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 133         uint32_t offset = dig->afmt->offset;
 134         uint8_t *frame = buffer + 3;
 135         uint8_t *header = buffer;
 136
 137         WREG32(AFMT_AVI_INFO0 + offset,
 138                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
 139         WREG32(AFMT_AVI_INFO1 + offset,
 140                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
 141         WREG32(AFMT_AVI_INFO2 + offset,
 142                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
 143         WREG32(AFMT_AVI_INFO3 + offset,
 144                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
 145 }
 146
 147 static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
 148 {
 149         struct drm_device *dev = encoder->dev;
 150         struct radeon_device *rdev = dev->dev_private;
 151         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 152         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 153         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 154         u32 base_rate = 24000;
 155         u32 max_ratio = clock / base_rate;
 156         u32 dto_phase;
 157         u32 dto_modulo = clock;
 158         u32 wallclock_ratio;
 159         u32 dto_cntl;
 160
 161         if (!dig || !dig->afmt)
 162                 return;
 163
 164         if (ASIC_IS_DCE6(rdev)) {
 165                 dto_phase = 24 * 1000;
 166         } else {
 167                 if (max_ratio >= 8) {
 168                         dto_phase = 192 * 1000;
 169                         wallclock_ratio = 3;
 170                 } else if (max_ratio >= 4) {
 171                         dto_phase = 96 * 1000;
 172                         wallclock_ratio = 2;
 173                 } else if (max_ratio >= 2) {
 174                         dto_phase = 48 * 1000;
 175                         wallclock_ratio = 1;
 176                 } else {
 177                         dto_phase = 24 * 1000;
 178                         wallclock_ratio = 0;
 179                 }
 180                 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
 181                 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
 182                 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
 183         }
 184
 185         /* XXX two dtos; generally use dto0 for hdmi */
 186         /* Express [24MHz / target pixel clock] as an exact rational
 187          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
 188          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
 189          */
 190         WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
 191         WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
 192         WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
 193 }
 194
 195
 196 /*
 197  * update the info frames with the data from the current display mode
 198  */
 199 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
 200 {
 201         struct drm_device *dev = encoder->dev;
 202         struct radeon_device *rdev = dev->dev_private;
 203         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 204         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 205         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 206         struct hdmi_avi_infoframe frame;
 207         uint32_t offset;
 208         ssize_t err;
 209
 210         if (!dig || !dig->afmt)
 211                 return;
 212
 213         /* Silent, r600_hdmi_enable will raise WARN for us */
 214         if (!dig->afmt->enabled)
 215                 return;
 216         offset = dig->afmt->offset;
 217
 218         evergreen_audio_set_dto(encoder, mode->clock);
 219
 220         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 221                HDMI_NULL_SEND); /* send null packets when required */
 222
 223         WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
 224
 225         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 226                HDMI_NULL_SEND | /* send null packets when required */
 227                HDMI_GC_SEND | /* send general control packets */
 228                HDMI_GC_CONT); /* send general control packets every frame */
 229
 230         WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
 231                HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
 232                HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
 233
 234         WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
 235                AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
 236
 237         WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
 238                HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
 239
 240         WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
 241
 242         WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
 243                HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
 244                HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
 245
 246         WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
 247                AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
 248
 249         /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
 250
 251         WREG32(HDMI_ACR_PACKET_CONTROL + offset,
 252                HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
 253                HDMI_ACR_SOURCE); /* select SW CTS value */
 254
 255         evergreen_hdmi_update_ACR(encoder, mode->clock);
 256
 257         WREG32(AFMT_60958_0 + offset,
 258                AFMT_60958_CS_CHANNEL_NUMBER_L(1));
 259
 260         WREG32(AFMT_60958_1 + offset,
 261                AFMT_60958_CS_CHANNEL_NUMBER_R(2));
 262
 263         WREG32(AFMT_60958_2 + offset,
 264                AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
 265                AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
 266                AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
 267                AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
 268                AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
 269                AFMT_60958_CS_CHANNEL_NUMBER_7(8));
 270
 271         if (ASIC_IS_DCE6(rdev)) {
 272                 dce6_afmt_write_speaker_allocation(encoder);
 273         } else {
 274                 /* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */
 275         }
 276
 277         WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
 278                AFMT_AUDIO_CHANNEL_ENABLE(0xff));
 279
 280         /* fglrx sets 0x40 in 0x5f80 here */
 281
 282         if (ASIC_IS_DCE6(rdev)) {
 283                 dce6_afmt_select_pin(encoder);
 284                 dce6_afmt_write_sad_regs(encoder);
 285         } else {
 286                 evergreen_hdmi_write_sad_regs(encoder);
 287         }
 288
 289         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 290         if (err < 0) {
 291                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
 292                 return;
 293         }
 294
 295         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 296         if (err < 0) {
 297                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
 298                 return;
 299         }
 300
 301         evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
 302
 303         WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
 304                   HDMI_AVI_INFO_SEND | /* enable AVI info frames */
 305                   HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
 306
 307         WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
 308                  HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
 309                  ~HDMI_AVI_INFO_LINE_MASK);
 310
 311         WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
 312                   AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
 313
 314         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
 315         WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
 316         WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
 317         WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
 318         WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
 319 }
 320
 321 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
 322 {
 323         struct drm_device *dev = encoder->dev;
 324         struct radeon_device *rdev = dev->dev_private;
 325         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 326         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 327
 328         if (!dig || !dig->afmt)
 329                 return;
 330
 331         /* Silent, r600_hdmi_enable will raise WARN for us */
 332         if (enable && dig->afmt->enabled)
 333                 return;
 334         if (!enable && !dig->afmt->enabled)
 335                 return;
 336
 337         if (enable) {
 338                 if (ASIC_IS_DCE6(rdev))
 339                         dig->afmt->pin = dce6_audio_get_pin(rdev);
 340                 else
 341                         dig->afmt->pin = r600_audio_get_pin(rdev);
 342         } else {
 343                 dig->afmt->pin = NULL;
 344         }
 345
 346         dig->afmt->enabled = enable;
 347
 348         DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
 349                   enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
 350 }