drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static void evergreen_gpu_init(struct radeon_device *rdev);
  41 void evergreen_fini(struct radeon_device *rdev);
  42 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  43
  44 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
  45 {
  46         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
  47         u32 tmp;
  48
  49         /* make sure flip is at vb rather than hb */
  50         tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
  51         tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
  52         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
  53
  54         /* set pageflip to happen anywhere in vblank interval */
  55         WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
  56
  57         /* enable the pflip int */
  58         radeon_irq_kms_pflip_irq_get(rdev, crtc);
  59 }
  60
  61 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
  62 {
  63         /* disable the pflip int */
  64         radeon_irq_kms_pflip_irq_put(rdev, crtc);
  65 }
  66
  67 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  68 {
  69         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  70         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
  71
  72         /* Lock the graphics update lock */
  73         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
  74         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  75
  76         /* update the scanout addresses */
  77         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  78                upper_32_bits(crtc_base));
  79         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  80                (u32)crtc_base);
  81
  82         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  83                upper_32_bits(crtc_base));
  84         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  85                (u32)crtc_base);
  86
  87         /* Wait for update_pending to go high. */
  88         while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
  89         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  90
  91         /* Unlock the lock, so double-buffering can take place inside vblank */
  92         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
  93         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  94
  95         /* Return current update_pending status: */
  96         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
  97 }
  98
  99 /* get temperature in millidegrees */
 100 int evergreen_get_temp(struct radeon_device *rdev)
 101 {
 102         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 103                 ASIC_T_SHIFT;
 104         u32 actual_temp = 0;
 105
 106         if (temp & 0x400)
 107                 actual_temp = -256;
 108         else if (temp & 0x200)
 109                 actual_temp = 255;
 110         else if (temp & 0x100) {
 111                 actual_temp = temp & 0x1ff;
 112                 actual_temp |= ~0x1ff;
 113         } else
 114                 actual_temp = temp & 0xff;
 115
 116         return (actual_temp * 1000) / 2;
 117 }
 118
 119 int sumo_get_temp(struct radeon_device *rdev)
 120 {
 121         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 122         int actual_temp = temp - 49;
 123
 124         return actual_temp * 1000;
 125 }
 126
 127 void evergreen_pm_misc(struct radeon_device *rdev)
 128 {
 129         int req_ps_idx = rdev->pm.requested_power_state_index;
 130         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 131         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 132         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 133
 134         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 135                 if (voltage->voltage != rdev->pm.current_vddc) {
 136                         radeon_atom_set_voltage(rdev, voltage->voltage);
 137                         rdev->pm.current_vddc = voltage->voltage;
 138                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 139                 }
 140         }
 141 }
 142
 143 void evergreen_pm_prepare(struct radeon_device *rdev)
 144 {
 145         struct drm_device *ddev = rdev->ddev;
 146         struct drm_crtc *crtc;
 147         struct radeon_crtc *radeon_crtc;
 148         u32 tmp;
 149
 150         /* disable any active CRTCs */
 151         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 152                 radeon_crtc = to_radeon_crtc(crtc);
 153                 if (radeon_crtc->enabled) {
 154                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 155                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 156                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 157                 }
 158         }
 159 }
 160
 161 void evergreen_pm_finish(struct radeon_device *rdev)
 162 {
 163         struct drm_device *ddev = rdev->ddev;
 164         struct drm_crtc *crtc;
 165         struct radeon_crtc *radeon_crtc;
 166         u32 tmp;
 167
 168         /* enable any active CRTCs */
 169         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 170                 radeon_crtc = to_radeon_crtc(crtc);
 171                 if (radeon_crtc->enabled) {
 172                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 173                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 174                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 175                 }
 176         }
 177 }
 178
 179 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 180 {
 181         bool connected = false;
 182
 183         switch (hpd) {
 184         case RADEON_HPD_1:
 185                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 186                         connected = true;
 187                 break;
 188         case RADEON_HPD_2:
 189                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 190                         connected = true;
 191                 break;
 192         case RADEON_HPD_3:
 193                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 194                         connected = true;
 195                 break;
 196         case RADEON_HPD_4:
 197                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 198                         connected = true;
 199                 break;
 200         case RADEON_HPD_5:
 201                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 202                         connected = true;
 203                 break;
 204         case RADEON_HPD_6:
 205                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 206                         connected = true;
 207                         break;
 208         default:
 209                 break;
 210         }
 211
 212         return connected;
 213 }
 214
 215 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 216                                 enum radeon_hpd_id hpd)
 217 {
 218         u32 tmp;
 219         bool connected = evergreen_hpd_sense(rdev, hpd);
 220
 221         switch (hpd) {
 222         case RADEON_HPD_1:
 223                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 224                 if (connected)
 225                         tmp &= ~DC_HPDx_INT_POLARITY;
 226                 else
 227                         tmp |= DC_HPDx_INT_POLARITY;
 228                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 229                 break;
 230         case RADEON_HPD_2:
 231                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 232                 if (connected)
 233                         tmp &= ~DC_HPDx_INT_POLARITY;
 234                 else
 235                         tmp |= DC_HPDx_INT_POLARITY;
 236                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 237                 break;
 238         case RADEON_HPD_3:
 239                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 240                 if (connected)
 241                         tmp &= ~DC_HPDx_INT_POLARITY;
 242                 else
 243                         tmp |= DC_HPDx_INT_POLARITY;
 244                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 245                 break;
 246         case RADEON_HPD_4:
 247                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 248                 if (connected)
 249                         tmp &= ~DC_HPDx_INT_POLARITY;
 250                 else
 251                         tmp |= DC_HPDx_INT_POLARITY;
 252                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 253                 break;
 254         case RADEON_HPD_5:
 255                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 256                 if (connected)
 257                         tmp &= ~DC_HPDx_INT_POLARITY;
 258                 else
 259                         tmp |= DC_HPDx_INT_POLARITY;
 260                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 261                         break;
 262         case RADEON_HPD_6:
 263                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 264                 if (connected)
 265                         tmp &= ~DC_HPDx_INT_POLARITY;
 266                 else
 267                         tmp |= DC_HPDx_INT_POLARITY;
 268                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 269                 break;
 270         default:
 271                 break;
 272         }
 273 }
 274
 275 void evergreen_hpd_init(struct radeon_device *rdev)
 276 {
 277         struct drm_device *dev = rdev->ddev;
 278         struct drm_connector *connector;
 279         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 280                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 281
 282         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 283                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 284                 switch (radeon_connector->hpd.hpd) {
 285                 case RADEON_HPD_1:
 286                         WREG32(DC_HPD1_CONTROL, tmp);
 287                         rdev->irq.hpd[0] = true;
 288                         break;
 289                 case RADEON_HPD_2:
 290                         WREG32(DC_HPD2_CONTROL, tmp);
 291                         rdev->irq.hpd[1] = true;
 292                         break;
 293                 case RADEON_HPD_3:
 294                         WREG32(DC_HPD3_CONTROL, tmp);
 295                         rdev->irq.hpd[2] = true;
 296                         break;
 297                 case RADEON_HPD_4:
 298                         WREG32(DC_HPD4_CONTROL, tmp);
 299                         rdev->irq.hpd[3] = true;
 300                         break;
 301                 case RADEON_HPD_5:
 302                         WREG32(DC_HPD5_CONTROL, tmp);
 303                         rdev->irq.hpd[4] = true;
 304                         break;
 305                 case RADEON_HPD_6:
 306                         WREG32(DC_HPD6_CONTROL, tmp);
 307                         rdev->irq.hpd[5] = true;
 308                         break;
 309                 default:
 310                         break;
 311                 }
 312         }
 313         if (rdev->irq.installed)
 314                 evergreen_irq_set(rdev);
 315 }
 316
 317 void evergreen_hpd_fini(struct radeon_device *rdev)
 318 {
 319         struct drm_device *dev = rdev->ddev;
 320         struct drm_connector *connector;
 321
 322         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 323                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 324                 switch (radeon_connector->hpd.hpd) {
 325                 case RADEON_HPD_1:
 326                         WREG32(DC_HPD1_CONTROL, 0);
 327                         rdev->irq.hpd[0] = false;
 328                         break;
 329                 case RADEON_HPD_2:
 330                         WREG32(DC_HPD2_CONTROL, 0);
 331                         rdev->irq.hpd[1] = false;
 332                         break;
 333                 case RADEON_HPD_3:
 334                         WREG32(DC_HPD3_CONTROL, 0);
 335                         rdev->irq.hpd[2] = false;
 336                         break;
 337                 case RADEON_HPD_4:
 338                         WREG32(DC_HPD4_CONTROL, 0);
 339                         rdev->irq.hpd[3] = false;
 340                         break;
 341                 case RADEON_HPD_5:
 342                         WREG32(DC_HPD5_CONTROL, 0);
 343                         rdev->irq.hpd[4] = false;
 344                         break;
 345                 case RADEON_HPD_6:
 346                         WREG32(DC_HPD6_CONTROL, 0);
 347                         rdev->irq.hpd[5] = false;
 348                         break;
 349                 default:
 350                         break;
 351                 }
 352         }
 353 }
 354
 355 /* watermark setup */
 356
 357 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 358                                         struct radeon_crtc *radeon_crtc,
 359                                         struct drm_display_mode *mode,
 360                                         struct drm_display_mode *other_mode)
 361 {
 362         u32 tmp = 0;
 363         /*
 364          * Line Buffer Setup
 365          * There are 3 line buffers, each one shared by 2 display controllers.
 366          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 367          * the display controllers.  The paritioning is done via one of four
 368          * preset allocations specified in bits 2:0:
 369          * first display controller
 370          *  0 - first half of lb (3840 * 2)
 371          *  1 - first 3/4 of lb (5760 * 2)
 372          *  2 - whole lb (7680 * 2)
 373          *  3 - first 1/4 of lb (1920 * 2)
 374          * second display controller
 375          *  4 - second half of lb (3840 * 2)
 376          *  5 - second 3/4 of lb (5760 * 2)
 377          *  6 - whole lb (7680 * 2)
 378          *  7 - last 1/4 of lb (1920 * 2)
 379          */
 380         if (mode && other_mode) {
 381                 if (mode->hdisplay > other_mode->hdisplay) {
 382                         if (mode->hdisplay > 2560)
 383                                 tmp = 1; /* 3/4 */
 384                         else
 385                                 tmp = 0; /* 1/2 */
 386                 } else if (other_mode->hdisplay > mode->hdisplay) {
 387                         if (other_mode->hdisplay > 2560)
 388                                 tmp = 3; /* 1/4 */
 389                         else
 390                                 tmp = 0; /* 1/2 */
 391                 } else
 392                         tmp = 0; /* 1/2 */
 393         } else if (mode)
 394                 tmp = 2; /* whole */
 395         else if (other_mode)
 396                 tmp = 3; /* 1/4 */
 397
 398         /* second controller of the pair uses second half of the lb */
 399         if (radeon_crtc->crtc_id % 2)
 400                 tmp += 4;
 401         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 402
 403         switch (tmp) {
 404         case 0:
 405         case 4:
 406         default:
 407                 if (ASIC_IS_DCE5(rdev))
 408                         return 4096 * 2;
 409                 else
 410                         return 3840 * 2;
 411         case 1:
 412         case 5:
 413                 if (ASIC_IS_DCE5(rdev))
 414                         return 6144 * 2;
 415                 else
 416                         return 5760 * 2;
 417         case 2:
 418         case 6:
 419                 if (ASIC_IS_DCE5(rdev))
 420                         return 8192 * 2;
 421                 else
 422                         return 7680 * 2;
 423         case 3:
 424         case 7:
 425                 if (ASIC_IS_DCE5(rdev))
 426                         return 2048 * 2;
 427                 else
 428                         return 1920 * 2;
 429         }
 430 }
 431
 432 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 433 {
 434         u32 tmp = RREG32(MC_SHARED_CHMAP);
 435
 436         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 437         case 0:
 438         default:
 439                 return 1;
 440         case 1:
 441                 return 2;
 442         case 2:
 443                 return 4;
 444         case 3:
 445                 return 8;
 446         }
 447 }
 448
 449 struct evergreen_wm_params {
 450         u32 dram_channels; /* number of dram channels */
 451         u32 yclk;          /* bandwidth per dram data pin in kHz */
 452         u32 sclk;          /* engine clock in kHz */
 453         u32 disp_clk;      /* display clock in kHz */
 454         u32 src_width;     /* viewport width */
 455         u32 active_time;   /* active display time in ns */
 456         u32 blank_time;    /* blank time in ns */
 457         bool interlaced;    /* mode is interlaced */
 458         fixed20_12 vsc;    /* vertical scale ratio */
 459         u32 num_heads;     /* number of active crtcs */
 460         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 461         u32 lb_size;       /* line buffer allocated to pipe */
 462         u32 vtaps;         /* vertical scaler taps */
 463 };
 464
 465 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 466 {
 467         /* Calculate DRAM Bandwidth and the part allocated to display. */
 468         fixed20_12 dram_efficiency; /* 0.7 */
 469         fixed20_12 yclk, dram_channels, bandwidth;
 470         fixed20_12 a;
 471
 472         a.full = dfixed_const(1000);
 473         yclk.full = dfixed_const(wm->yclk);
 474         yclk.full = dfixed_div(yclk, a);
 475         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 476         a.full = dfixed_const(10);
 477         dram_efficiency.full = dfixed_const(7);
 478         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 479         bandwidth.full = dfixed_mul(dram_channels, yclk);
 480         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 481
 482         return dfixed_trunc(bandwidth);
 483 }
 484
 485 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 486 {
 487         /* Calculate DRAM Bandwidth and the part allocated to display. */
 488         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 489         fixed20_12 yclk, dram_channels, bandwidth;
 490         fixed20_12 a;
 491
 492         a.full = dfixed_const(1000);
 493         yclk.full = dfixed_const(wm->yclk);
 494         yclk.full = dfixed_div(yclk, a);
 495         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 496         a.full = dfixed_const(10);
 497         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 498         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 499         bandwidth.full = dfixed_mul(dram_channels, yclk);
 500         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 501
 502         return dfixed_trunc(bandwidth);
 503 }
 504
 505 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 506 {
 507         /* Calculate the display Data return Bandwidth */
 508         fixed20_12 return_efficiency; /* 0.8 */
 509         fixed20_12 sclk, bandwidth;
 510         fixed20_12 a;
 511
 512         a.full = dfixed_const(1000);
 513         sclk.full = dfixed_const(wm->sclk);
 514         sclk.full = dfixed_div(sclk, a);
 515         a.full = dfixed_const(10);
 516         return_efficiency.full = dfixed_const(8);
 517         return_efficiency.full = dfixed_div(return_efficiency, a);
 518         a.full = dfixed_const(32);
 519         bandwidth.full = dfixed_mul(a, sclk);
 520         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 521
 522         return dfixed_trunc(bandwidth);
 523 }
 524
 525 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 526 {
 527         /* Calculate the DMIF Request Bandwidth */
 528         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 529         fixed20_12 disp_clk, bandwidth;
 530         fixed20_12 a;
 531
 532         a.full = dfixed_const(1000);
 533         disp_clk.full = dfixed_const(wm->disp_clk);
 534         disp_clk.full = dfixed_div(disp_clk, a);
 535         a.full = dfixed_const(10);
 536         disp_clk_request_efficiency.full = dfixed_const(8);
 537         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 538         a.full = dfixed_const(32);
 539         bandwidth.full = dfixed_mul(a, disp_clk);
 540         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 541
 542         return dfixed_trunc(bandwidth);
 543 }
 544
 545 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 546 {
 547         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 548         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 549         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 550         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 551
 552         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 553 }
 554
 555 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 556 {
 557         /* Calculate the display mode Average Bandwidth
 558          * DisplayMode should contain the source and destination dimensions,
 559          * timing, etc.
 560          */
 561         fixed20_12 bpp;
 562         fixed20_12 line_time;
 563         fixed20_12 src_width;
 564         fixed20_12 bandwidth;
 565         fixed20_12 a;
 566
 567         a.full = dfixed_const(1000);
 568         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 569         line_time.full = dfixed_div(line_time, a);
 570         bpp.full = dfixed_const(wm->bytes_per_pixel);
 571         src_width.full = dfixed_const(wm->src_width);
 572         bandwidth.full = dfixed_mul(src_width, bpp);
 573         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 574         bandwidth.full = dfixed_div(bandwidth, line_time);
 575
 576         return dfixed_trunc(bandwidth);
 577 }
 578
 579 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 580 {
 581         /* First calcualte the latency in ns */
 582         u32 mc_latency = 2000; /* 2000 ns. */
 583         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 584         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 585         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 586         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 587         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 588                 (wm->num_heads * cursor_line_pair_return_time);
 589         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 590         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 591         fixed20_12 a, b, c;
 592
 593         if (wm->num_heads == 0)
 594                 return 0;
 595
 596         a.full = dfixed_const(2);
 597         b.full = dfixed_const(1);
 598         if ((wm->vsc.full > a.full) ||
 599             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 600             (wm->vtaps >= 5) ||
 601             ((wm->vsc.full >= a.full) && wm->interlaced))
 602                 max_src_lines_per_dst_line = 4;
 603         else
 604                 max_src_lines_per_dst_line = 2;
 605
 606         a.full = dfixed_const(available_bandwidth);
 607         b.full = dfixed_const(wm->num_heads);
 608         a.full = dfixed_div(a, b);
 609
 610         b.full = dfixed_const(1000);
 611         c.full = dfixed_const(wm->disp_clk);
 612         b.full = dfixed_div(c, b);
 613         c.full = dfixed_const(wm->bytes_per_pixel);
 614         b.full = dfixed_mul(b, c);
 615
 616         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 617
 618         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 619         b.full = dfixed_const(1000);
 620         c.full = dfixed_const(lb_fill_bw);
 621         b.full = dfixed_div(c, b);
 622         a.full = dfixed_div(a, b);
 623         line_fill_time = dfixed_trunc(a);
 624
 625         if (line_fill_time < wm->active_time)
 626                 return latency;
 627         else
 628                 return latency + (line_fill_time - wm->active_time);
 629
 630 }
 631
 632 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 633 {
 634         if (evergreen_average_bandwidth(wm) <=
 635             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 636                 return true;
 637         else
 638                 return false;
 639 };
 640
 641 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 642 {
 643         if (evergreen_average_bandwidth(wm) <=
 644             (evergreen_available_bandwidth(wm) / wm->num_heads))
 645                 return true;
 646         else
 647                 return false;
 648 };
 649
 650 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 651 {
 652         u32 lb_partitions = wm->lb_size / wm->src_width;
 653         u32 line_time = wm->active_time + wm->blank_time;
 654         u32 latency_tolerant_lines;
 655         u32 latency_hiding;
 656         fixed20_12 a;
 657
 658         a.full = dfixed_const(1);
 659         if (wm->vsc.full > a.full)
 660                 latency_tolerant_lines = 1;
 661         else {
 662                 if (lb_partitions <= (wm->vtaps + 1))
 663                         latency_tolerant_lines = 1;
 664                 else
 665                         latency_tolerant_lines = 2;
 666         }
 667
 668         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 669
 670         if (evergreen_latency_watermark(wm) <= latency_hiding)
 671                 return true;
 672         else
 673                 return false;
 674 }
 675
 676 static void evergreen_program_watermarks(struct radeon_device *rdev,
 677                                          struct radeon_crtc *radeon_crtc,
 678                                          u32 lb_size, u32 num_heads)
 679 {
 680         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 681         struct evergreen_wm_params wm;
 682         u32 pixel_period;
 683         u32 line_time = 0;
 684         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 685         u32 priority_a_mark = 0, priority_b_mark = 0;
 686         u32 priority_a_cnt = PRIORITY_OFF;
 687         u32 priority_b_cnt = PRIORITY_OFF;
 688         u32 pipe_offset = radeon_crtc->crtc_id * 16;
 689         u32 tmp, arb_control3;
 690         fixed20_12 a, b, c;
 691
 692         if (radeon_crtc->base.enabled && num_heads && mode) {
 693                 pixel_period = 1000000 / (u32)mode->clock;
 694                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 695                 priority_a_cnt = 0;
 696                 priority_b_cnt = 0;
 697
 698                 wm.yclk = rdev->pm.current_mclk * 10;
 699                 wm.sclk = rdev->pm.current_sclk * 10;
 700                 wm.disp_clk = mode->clock;
 701                 wm.src_width = mode->crtc_hdisplay;
 702                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 703                 wm.blank_time = line_time - wm.active_time;
 704                 wm.interlaced = false;
 705                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 706                         wm.interlaced = true;
 707                 wm.vsc = radeon_crtc->vsc;
 708                 wm.vtaps = 1;
 709                 if (radeon_crtc->rmx_type != RMX_OFF)
 710                         wm.vtaps = 2;
 711                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 712                 wm.lb_size = lb_size;
 713                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 714                 wm.num_heads = num_heads;
 715
 716                 /* set for high clocks */
 717                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
 718                 /* set for low clocks */
 719                 /* wm.yclk = low clk; wm.sclk = low clk */
 720                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
 721
 722                 /* possibly force display priority to high */
 723                 /* should really do this at mode validation time... */
 724                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 725                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
 726                     !evergreen_check_latency_hiding(&wm) ||
 727                     (rdev->disp_priority == 2)) {
 728                         DRM_INFO("force priority to high\n");
 729                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 730                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 731                 }
 732
 733                 a.full = dfixed_const(1000);
 734                 b.full = dfixed_const(mode->clock);
 735                 b.full = dfixed_div(b, a);
 736                 c.full = dfixed_const(latency_watermark_a);
 737                 c.full = dfixed_mul(c, b);
 738                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 739                 c.full = dfixed_div(c, a);
 740                 a.full = dfixed_const(16);
 741                 c.full = dfixed_div(c, a);
 742                 priority_a_mark = dfixed_trunc(c);
 743                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 744
 745                 a.full = dfixed_const(1000);
 746                 b.full = dfixed_const(mode->clock);
 747                 b.full = dfixed_div(b, a);
 748                 c.full = dfixed_const(latency_watermark_b);
 749                 c.full = dfixed_mul(c, b);
 750                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 751                 c.full = dfixed_div(c, a);
 752                 a.full = dfixed_const(16);
 753                 c.full = dfixed_div(c, a);
 754                 priority_b_mark = dfixed_trunc(c);
 755                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 756         }
 757
 758         /* select wm A */
 759         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 760         tmp = arb_control3;
 761         tmp &= ~LATENCY_WATERMARK_MASK(3);
 762         tmp |= LATENCY_WATERMARK_MASK(1);
 763         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 764         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 765                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
 766                 LATENCY_HIGH_WATERMARK(line_time)));
 767         /* select wm B */
 768         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 769         tmp &= ~LATENCY_WATERMARK_MASK(3);
 770         tmp |= LATENCY_WATERMARK_MASK(2);
 771         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 772         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 773                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
 774                 LATENCY_HIGH_WATERMARK(line_time)));
 775         /* restore original selection */
 776         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
 777
 778         /* write the priority marks */
 779         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
 780         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 781
 782 }
 783
 784 void evergreen_bandwidth_update(struct radeon_device *rdev)
 785 {
 786         struct drm_display_mode *mode0 = NULL;
 787         struct drm_display_mode *mode1 = NULL;
 788         u32 num_heads = 0, lb_size;
 789         int i;
 790
 791         radeon_update_display_priority(rdev);
 792
 793         for (i = 0; i < rdev->num_crtc; i++) {
 794                 if (rdev->mode_info.crtcs[i]->base.enabled)
 795                         num_heads++;
 796         }
 797         for (i = 0; i < rdev->num_crtc; i += 2) {
 798                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
 799                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
 800                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
 801                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
 802                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
 803                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
 804         }
 805 }
 806
 807 static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
 808 {
 809         unsigned i;
 810         u32 tmp;
 811
 812         for (i = 0; i < rdev->usec_timeout; i++) {
 813                 /* read MC_STATUS */
 814                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
 815                 if (!tmp)
 816                         return 0;
 817                 udelay(1);
 818         }
 819         return -1;
 820 }
 821
 822 /*
 823  * GART
 824  */
 825 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
 826 {
 827         unsigned i;
 828         u32 tmp;
 829
 830         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 831
 832         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 833         for (i = 0; i < rdev->usec_timeout; i++) {
 834                 /* read MC_STATUS */
 835                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 836                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 837                 if (tmp == 2) {
 838                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 839                         return;
 840                 }
 841                 if (tmp) {
 842                         return;
 843                 }
 844                 udelay(1);
 845         }
 846 }
 847
 848 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
 849 {
 850         u32 tmp;
 851         int r;
 852
 853         if (rdev->gart.table.vram.robj == NULL) {
 854                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 855                 return -EINVAL;
 856         }
 857         r = radeon_gart_table_vram_pin(rdev);
 858         if (r)
 859                 return r;
 860         radeon_gart_restore(rdev);
 861         /* Setup L2 cache */
 862         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 863                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 864                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 865         WREG32(VM_L2_CNTL2, 0);
 866         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 867         /* Setup TLB control */
 868         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 869                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 870                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 871                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 872         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 873         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 874         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 875         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 876         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 877         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 878         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 879         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 880         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 881         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 882         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 883                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 884         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 885                         (u32)(rdev->dummy_page.addr >> 12));
 886         WREG32(VM_CONTEXT1_CNTL, 0);
 887
 888         evergreen_pcie_gart_tlb_flush(rdev);
 889         rdev->gart.ready = true;
 890         return 0;
 891 }
 892
 893 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
 894 {
 895         u32 tmp;
 896         int r;
 897
 898         /* Disable all tables */
 899         WREG32(VM_CONTEXT0_CNTL, 0);
 900         WREG32(VM_CONTEXT1_CNTL, 0);
 901
 902         /* Setup L2 cache */
 903         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 904                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 905         WREG32(VM_L2_CNTL2, 0);
 906         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 907         /* Setup TLB control */
 908         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 909         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 910         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 911         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 912         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 913         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 914         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 915         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 916         if (rdev->gart.table.vram.robj) {
 917                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 918                 if (likely(r == 0)) {
 919                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 920                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 921                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 922                 }
 923         }
 924 }
 925
 926 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
 927 {
 928         evergreen_pcie_gart_disable(rdev);
 929         radeon_gart_table_vram_free(rdev);
 930         radeon_gart_fini(rdev);
 931 }
 932
 933
 934 void evergreen_agp_enable(struct radeon_device *rdev)
 935 {
 936         u32 tmp;
 937
 938         /* Setup L2 cache */
 939         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 940                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 941                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 942         WREG32(VM_L2_CNTL2, 0);
 943         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 944         /* Setup TLB control */
 945         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 946                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 947                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 948                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 949         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 950         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 951         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 952         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 953         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 954         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 955         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 956         WREG32(VM_CONTEXT0_CNTL, 0);
 957         WREG32(VM_CONTEXT1_CNTL, 0);
 958 }
 959
 960 static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
 961 {
 962         save->vga_control[0] = RREG32(D1VGA_CONTROL);
 963         save->vga_control[1] = RREG32(D2VGA_CONTROL);
 964         save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
 965         save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
 966         save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
 967         save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
 968         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
 969         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
 970         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
 971         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 972         if (!(rdev->flags & RADEON_IS_IGP)) {
 973                 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
 974                 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
 975                 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
 976                 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 977         }
 978
 979         /* Stop all video */
 980         WREG32(VGA_RENDER_CONTROL, 0);
 981         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
 982         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
 983         if (!(rdev->flags & RADEON_IS_IGP)) {
 984                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
 985                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
 986                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
 987                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
 988         }
 989         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 990         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 991         if (!(rdev->flags & RADEON_IS_IGP)) {
 992                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 993                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 994                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
 995                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
 996         }
 997         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 998         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 999         if (!(rdev->flags & RADEON_IS_IGP)) {
1000                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1001                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1002                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1003                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1004         }
1005
1006         WREG32(D1VGA_CONTROL, 0);
1007         WREG32(D2VGA_CONTROL, 0);
1008         WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1009         WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1010         WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1011         WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1012 }
1013
1014 static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1015 {
1016         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1017                upper_32_bits(rdev->mc.vram_start));
1018         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1019                upper_32_bits(rdev->mc.vram_start));
1020         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1021                (u32)rdev->mc.vram_start);
1022         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1023                (u32)rdev->mc.vram_start);
1024
1025         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1026                upper_32_bits(rdev->mc.vram_start));
1027         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1028                upper_32_bits(rdev->mc.vram_start));
1029         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1030                (u32)rdev->mc.vram_start);
1031         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1032                (u32)rdev->mc.vram_start);
1033
1034         if (!(rdev->flags & RADEON_IS_IGP)) {
1035                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1036                        upper_32_bits(rdev->mc.vram_start));
1037                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1038                        upper_32_bits(rdev->mc.vram_start));
1039                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1040                        (u32)rdev->mc.vram_start);
1041                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1042                        (u32)rdev->mc.vram_start);
1043
1044                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1045                        upper_32_bits(rdev->mc.vram_start));
1046                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1047                        upper_32_bits(rdev->mc.vram_start));
1048                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1049                        (u32)rdev->mc.vram_start);
1050                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1051                        (u32)rdev->mc.vram_start);
1052
1053                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1054                        upper_32_bits(rdev->mc.vram_start));
1055                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1056                        upper_32_bits(rdev->mc.vram_start));
1057                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1058                        (u32)rdev->mc.vram_start);
1059                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1060                        (u32)rdev->mc.vram_start);
1061
1062                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1063                        upper_32_bits(rdev->mc.vram_start));
1064                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1065                        upper_32_bits(rdev->mc.vram_start));
1066                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1067                        (u32)rdev->mc.vram_start);
1068                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1069                        (u32)rdev->mc.vram_start);
1070         }
1071
1072         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1073         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1074         /* Unlock host access */
1075         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1076         mdelay(1);
1077         /* Restore video state */
1078         WREG32(D1VGA_CONTROL, save->vga_control[0]);
1079         WREG32(D2VGA_CONTROL, save->vga_control[1]);
1080         WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1081         WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1082         WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1083         WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1084         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1085         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1086         if (!(rdev->flags & RADEON_IS_IGP)) {
1087                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1088                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1089                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1090                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1091         }
1092         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1093         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1094         if (!(rdev->flags & RADEON_IS_IGP)) {
1095                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1096                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1097                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1098                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1099         }
1100         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1101         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1102         if (!(rdev->flags & RADEON_IS_IGP)) {
1103                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1104                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1105                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1106                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1107         }
1108         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1109 }
1110
1111 static void evergreen_mc_program(struct radeon_device *rdev)
1112 {
1113         struct evergreen_mc_save save;
1114         u32 tmp;
1115         int i, j;
1116
1117         /* Initialize HDP */
1118         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1119                 WREG32((0x2c14 + j), 0x00000000);
1120                 WREG32((0x2c18 + j), 0x00000000);
1121                 WREG32((0x2c1c + j), 0x00000000);
1122                 WREG32((0x2c20 + j), 0x00000000);
1123                 WREG32((0x2c24 + j), 0x00000000);
1124         }
1125         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1126
1127         evergreen_mc_stop(rdev, &save);
1128         if (evergreen_mc_wait_for_idle(rdev)) {
1129                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1130         }
1131         /* Lockout access through VGA aperture*/
1132         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1133         /* Update configuration */
1134         if (rdev->flags & RADEON_IS_AGP) {
1135                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1136                         /* VRAM before AGP */
1137                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1138                                 rdev->mc.vram_start >> 12);
1139                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1140                                 rdev->mc.gtt_end >> 12);
1141                 } else {
1142                         /* VRAM after AGP */
1143                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1144                                 rdev->mc.gtt_start >> 12);
1145                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1146                                 rdev->mc.vram_end >> 12);
1147                 }
1148         } else {
1149                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1150                         rdev->mc.vram_start >> 12);
1151                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1152                         rdev->mc.vram_end >> 12);
1153         }
1154         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1155         if (rdev->flags & RADEON_IS_IGP) {
1156                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1157                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1158                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1159                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1160         }
1161         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1162         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1163         WREG32(MC_VM_FB_LOCATION, tmp);
1164         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1165         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1166         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1167         if (rdev->flags & RADEON_IS_AGP) {
1168                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1169                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1170                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1171         } else {
1172                 WREG32(MC_VM_AGP_BASE, 0);
1173                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1174                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1175         }
1176         if (evergreen_mc_wait_for_idle(rdev)) {
1177                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1178         }
1179         evergreen_mc_resume(rdev, &save);
1180         /* we need to own VRAM, so turn off the VGA renderer here
1181          * to stop it overwriting our objects */
1182         rv515_vga_render_disable(rdev);
1183 }
1184
1185 /*
1186  * CP.
1187  */
1188 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1189 {
1190         /* set to DX10/11 mode */
1191         radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1192         radeon_ring_write(rdev, 1);
1193         /* FIXME: implement */
1194         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1195         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
1196         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1197         radeon_ring_write(rdev, ib->length_dw);
1198 }
1199
1200
1201 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1202 {
1203         const __be32 *fw_data;
1204         int i;
1205
1206         if (!rdev->me_fw || !rdev->pfp_fw)
1207                 return -EINVAL;
1208
1209         r700_cp_stop(rdev);
1210         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
1211
1212         fw_data = (const __be32 *)rdev->pfp_fw->data;
1213         WREG32(CP_PFP_UCODE_ADDR, 0);
1214         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1215                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1216         WREG32(CP_PFP_UCODE_ADDR, 0);
1217
1218         fw_data = (const __be32 *)rdev->me_fw->data;
1219         WREG32(CP_ME_RAM_WADDR, 0);
1220         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1221                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1222
1223         WREG32(CP_PFP_UCODE_ADDR, 0);
1224         WREG32(CP_ME_RAM_WADDR, 0);
1225         WREG32(CP_ME_RAM_RADDR, 0);
1226         return 0;
1227 }
1228
1229 static int evergreen_cp_start(struct radeon_device *rdev)
1230 {
1231         int r, i;
1232         uint32_t cp_me;
1233
1234         r = radeon_ring_lock(rdev, 7);
1235         if (r) {
1236                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1237                 return r;
1238         }
1239         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1240         radeon_ring_write(rdev, 0x1);
1241         radeon_ring_write(rdev, 0x0);
1242         radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1243         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1244         radeon_ring_write(rdev, 0);
1245         radeon_ring_write(rdev, 0);
1246         radeon_ring_unlock_commit(rdev);
1247
1248         cp_me = 0xff;
1249         WREG32(CP_ME_CNTL, cp_me);
1250
1251         r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1252         if (r) {
1253                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1254                 return r;
1255         }
1256
1257         /* setup clear context state */
1258         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1259         radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1260
1261         for (i = 0; i < evergreen_default_size; i++)
1262                 radeon_ring_write(rdev, evergreen_default_state[i]);
1263
1264         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1265         radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1266
1267         /* set clear context state */
1268         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1269         radeon_ring_write(rdev, 0);
1270
1271         /* SQ_VTX_BASE_VTX_LOC */
1272         radeon_ring_write(rdev, 0xc0026f00);
1273         radeon_ring_write(rdev, 0x00000000);
1274         radeon_ring_write(rdev, 0x00000000);
1275         radeon_ring_write(rdev, 0x00000000);
1276
1277         /* Clear consts */
1278         radeon_ring_write(rdev, 0xc0036f00);
1279         radeon_ring_write(rdev, 0x00000bc4);
1280         radeon_ring_write(rdev, 0xffffffff);
1281         radeon_ring_write(rdev, 0xffffffff);
1282         radeon_ring_write(rdev, 0xffffffff);
1283
1284         radeon_ring_write(rdev, 0xc0026900);
1285         radeon_ring_write(rdev, 0x00000316);
1286         radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1287         radeon_ring_write(rdev, 0x00000010); /*  */
1288
1289         radeon_ring_unlock_commit(rdev);
1290
1291         return 0;
1292 }
1293
1294 int evergreen_cp_resume(struct radeon_device *rdev)
1295 {
1296         u32 tmp;
1297         u32 rb_bufsz;
1298         int r;
1299
1300         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1301         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1302                                  SOFT_RESET_PA |
1303                                  SOFT_RESET_SH |
1304                                  SOFT_RESET_VGT |
1305                                  SOFT_RESET_SX));
1306         RREG32(GRBM_SOFT_RESET);
1307         mdelay(15);
1308         WREG32(GRBM_SOFT_RESET, 0);
1309         RREG32(GRBM_SOFT_RESET);
1310
1311         /* Set ring buffer size */
1312         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1313         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1314 #ifdef __BIG_ENDIAN
1315         tmp |= BUF_SWAP_32BIT;
1316 #endif
1317         WREG32(CP_RB_CNTL, tmp);
1318         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1319
1320         /* Set the write pointer delay */
1321         WREG32(CP_RB_WPTR_DELAY, 0);
1322
1323         /* Initialize the ring buffer's read and write pointers */
1324         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1325         WREG32(CP_RB_RPTR_WR, 0);
1326         WREG32(CP_RB_WPTR, 0);
1327
1328         /* set the wb address wether it's enabled or not */
1329         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1330         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1331         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1332
1333         if (rdev->wb.enabled)
1334                 WREG32(SCRATCH_UMSK, 0xff);
1335         else {
1336                 tmp |= RB_NO_UPDATE;
1337                 WREG32(SCRATCH_UMSK, 0);
1338         }
1339
1340         mdelay(1);
1341         WREG32(CP_RB_CNTL, tmp);
1342
1343         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1344         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1345
1346         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1347         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1348
1349         evergreen_cp_start(rdev);
1350         rdev->cp.ready = true;
1351         r = radeon_ring_test(rdev);
1352         if (r) {
1353                 rdev->cp.ready = false;
1354                 return r;
1355         }
1356         return 0;
1357 }
1358
1359 /*
1360  * Core functions
1361  */
1362 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1363                                                   u32 num_tile_pipes,
1364                                                   u32 num_backends,
1365                                                   u32 backend_disable_mask)
1366 {
1367         u32 backend_map = 0;
1368         u32 enabled_backends_mask = 0;
1369         u32 enabled_backends_count = 0;
1370         u32 cur_pipe;
1371         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1372         u32 cur_backend = 0;
1373         u32 i;
1374         bool force_no_swizzle;
1375
1376         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1377                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1378         if (num_tile_pipes < 1)
1379                 num_tile_pipes = 1;
1380         if (num_backends > EVERGREEN_MAX_BACKENDS)
1381                 num_backends = EVERGREEN_MAX_BACKENDS;
1382         if (num_backends < 1)
1383                 num_backends = 1;
1384
1385         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1386                 if (((backend_disable_mask >> i) & 1) == 0) {
1387                         enabled_backends_mask |= (1 << i);
1388                         ++enabled_backends_count;
1389                 }
1390                 if (enabled_backends_count == num_backends)
1391                         break;
1392         }
1393
1394         if (enabled_backends_count == 0) {
1395                 enabled_backends_mask = 1;
1396                 enabled_backends_count = 1;
1397         }
1398
1399         if (enabled_backends_count != num_backends)
1400                 num_backends = enabled_backends_count;
1401
1402         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1403         switch (rdev->family) {
1404         case CHIP_CEDAR:
1405         case CHIP_REDWOOD:
1406         case CHIP_PALM:
1407         case CHIP_TURKS:
1408         case CHIP_CAICOS:
1409                 force_no_swizzle = false;
1410                 break;
1411         case CHIP_CYPRESS:
1412         case CHIP_HEMLOCK:
1413         case CHIP_JUNIPER:
1414         case CHIP_BARTS:
1415         default:
1416                 force_no_swizzle = true;
1417                 break;
1418         }
1419         if (force_no_swizzle) {
1420                 bool last_backend_enabled = false;
1421
1422                 force_no_swizzle = false;
1423                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1424                         if (((enabled_backends_mask >> i) & 1) == 1) {
1425                                 if (last_backend_enabled)
1426                                         force_no_swizzle = true;
1427                                 last_backend_enabled = true;
1428                         } else
1429                                 last_backend_enabled = false;
1430                 }
1431         }
1432
1433         switch (num_tile_pipes) {
1434         case 1:
1435         case 3:
1436         case 5:
1437         case 7:
1438                 DRM_ERROR("odd number of pipes!\n");
1439                 break;
1440         case 2:
1441                 swizzle_pipe[0] = 0;
1442                 swizzle_pipe[1] = 1;
1443                 break;
1444         case 4:
1445                 if (force_no_swizzle) {
1446                         swizzle_pipe[0] = 0;
1447                         swizzle_pipe[1] = 1;
1448                         swizzle_pipe[2] = 2;
1449                         swizzle_pipe[3] = 3;
1450                 } else {
1451                         swizzle_pipe[0] = 0;
1452                         swizzle_pipe[1] = 2;
1453                         swizzle_pipe[2] = 1;
1454                         swizzle_pipe[3] = 3;
1455                 }
1456                 break;
1457         case 6:
1458                 if (force_no_swizzle) {
1459                         swizzle_pipe[0] = 0;
1460                         swizzle_pipe[1] = 1;
1461                         swizzle_pipe[2] = 2;
1462                         swizzle_pipe[3] = 3;
1463                         swizzle_pipe[4] = 4;
1464                         swizzle_pipe[5] = 5;
1465                 } else {
1466                         swizzle_pipe[0] = 0;
1467                         swizzle_pipe[1] = 2;
1468                         swizzle_pipe[2] = 4;
1469                         swizzle_pipe[3] = 1;
1470                         swizzle_pipe[4] = 3;
1471                         swizzle_pipe[5] = 5;
1472                 }
1473                 break;
1474         case 8:
1475                 if (force_no_swizzle) {
1476                         swizzle_pipe[0] = 0;
1477                         swizzle_pipe[1] = 1;
1478                         swizzle_pipe[2] = 2;
1479                         swizzle_pipe[3] = 3;
1480                         swizzle_pipe[4] = 4;
1481                         swizzle_pipe[5] = 5;
1482                         swizzle_pipe[6] = 6;
1483                         swizzle_pipe[7] = 7;
1484                 } else {
1485                         swizzle_pipe[0] = 0;
1486                         swizzle_pipe[1] = 2;
1487                         swizzle_pipe[2] = 4;
1488                         swizzle_pipe[3] = 6;
1489                         swizzle_pipe[4] = 1;
1490                         swizzle_pipe[5] = 3;
1491                         swizzle_pipe[6] = 5;
1492                         swizzle_pipe[7] = 7;
1493                 }
1494                 break;
1495         }
1496
1497         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1498                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1499                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1500
1501                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1502
1503                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1504         }
1505
1506         return backend_map;
1507 }
1508
1509 static void evergreen_program_channel_remap(struct radeon_device *rdev)
1510 {
1511         u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1512
1513         tmp = RREG32(MC_SHARED_CHMAP);
1514         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1515         case 0:
1516         case 1:
1517         case 2:
1518         case 3:
1519         default:
1520                 /* default mapping */
1521                 mc_shared_chremap = 0x00fac688;
1522                 break;
1523         }
1524
1525         switch (rdev->family) {
1526         case CHIP_HEMLOCK:
1527         case CHIP_CYPRESS:
1528         case CHIP_BARTS:
1529                 tcp_chan_steer_lo = 0x54763210;
1530                 tcp_chan_steer_hi = 0x0000ba98;
1531                 break;
1532         case CHIP_JUNIPER:
1533         case CHIP_REDWOOD:
1534         case CHIP_CEDAR:
1535         case CHIP_PALM:
1536         case CHIP_TURKS:
1537         case CHIP_CAICOS:
1538         default:
1539                 tcp_chan_steer_lo = 0x76543210;
1540                 tcp_chan_steer_hi = 0x0000ba98;
1541                 break;
1542         }
1543
1544         WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1545         WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1546         WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1547 }
1548
1549 static void evergreen_gpu_init(struct radeon_device *rdev)
1550 {
1551         u32 cc_rb_backend_disable = 0;
1552         u32 cc_gc_shader_pipe_config;
1553         u32 gb_addr_config = 0;
1554         u32 mc_shared_chmap, mc_arb_ramcfg;
1555         u32 gb_backend_map;
1556         u32 grbm_gfx_index;
1557         u32 sx_debug_1;
1558         u32 smx_dc_ctl0;
1559         u32 sq_config;
1560         u32 sq_lds_resource_mgmt;
1561         u32 sq_gpr_resource_mgmt_1;
1562         u32 sq_gpr_resource_mgmt_2;
1563         u32 sq_gpr_resource_mgmt_3;
1564         u32 sq_thread_resource_mgmt;
1565         u32 sq_thread_resource_mgmt_2;
1566         u32 sq_stack_resource_mgmt_1;
1567         u32 sq_stack_resource_mgmt_2;
1568         u32 sq_stack_resource_mgmt_3;
1569         u32 vgt_cache_invalidation;
1570         u32 hdp_host_path_cntl;
1571         int i, j, num_shader_engines, ps_thread_count;
1572
1573         switch (rdev->family) {
1574         case CHIP_CYPRESS:
1575         case CHIP_HEMLOCK:
1576                 rdev->config.evergreen.num_ses = 2;
1577                 rdev->config.evergreen.max_pipes = 4;
1578                 rdev->config.evergreen.max_tile_pipes = 8;
1579                 rdev->config.evergreen.max_simds = 10;
1580                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1581                 rdev->config.evergreen.max_gprs = 256;
1582                 rdev->config.evergreen.max_threads = 248;
1583                 rdev->config.evergreen.max_gs_threads = 32;
1584                 rdev->config.evergreen.max_stack_entries = 512;
1585                 rdev->config.evergreen.sx_num_of_sets = 4;
1586                 rdev->config.evergreen.sx_max_export_size = 256;
1587                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1588                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1589                 rdev->config.evergreen.max_hw_contexts = 8;
1590                 rdev->config.evergreen.sq_num_cf_insts = 2;
1591
1592                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1593                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1594                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1595                 break;
1596         case CHIP_JUNIPER:
1597                 rdev->config.evergreen.num_ses = 1;
1598                 rdev->config.evergreen.max_pipes = 4;
1599                 rdev->config.evergreen.max_tile_pipes = 4;
1600                 rdev->config.evergreen.max_simds = 10;
1601                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1602                 rdev->config.evergreen.max_gprs = 256;
1603                 rdev->config.evergreen.max_threads = 248;
1604                 rdev->config.evergreen.max_gs_threads = 32;
1605                 rdev->config.evergreen.max_stack_entries = 512;
1606                 rdev->config.evergreen.sx_num_of_sets = 4;
1607                 rdev->config.evergreen.sx_max_export_size = 256;
1608                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1609                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1610                 rdev->config.evergreen.max_hw_contexts = 8;
1611                 rdev->config.evergreen.sq_num_cf_insts = 2;
1612
1613                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1614                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1615                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1616                 break;
1617         case CHIP_REDWOOD:
1618                 rdev->config.evergreen.num_ses = 1;
1619                 rdev->config.evergreen.max_pipes = 4;
1620                 rdev->config.evergreen.max_tile_pipes = 4;
1621                 rdev->config.evergreen.max_simds = 5;
1622                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1623                 rdev->config.evergreen.max_gprs = 256;
1624                 rdev->config.evergreen.max_threads = 248;
1625                 rdev->config.evergreen.max_gs_threads = 32;
1626                 rdev->config.evergreen.max_stack_entries = 256;
1627                 rdev->config.evergreen.sx_num_of_sets = 4;
1628                 rdev->config.evergreen.sx_max_export_size = 256;
1629                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1630                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1631                 rdev->config.evergreen.max_hw_contexts = 8;
1632                 rdev->config.evergreen.sq_num_cf_insts = 2;
1633
1634                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1635                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1636                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1637                 break;
1638         case CHIP_CEDAR:
1639         default:
1640                 rdev->config.evergreen.num_ses = 1;
1641                 rdev->config.evergreen.max_pipes = 2;
1642                 rdev->config.evergreen.max_tile_pipes = 2;
1643                 rdev->config.evergreen.max_simds = 2;
1644                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1645                 rdev->config.evergreen.max_gprs = 256;
1646                 rdev->config.evergreen.max_threads = 192;
1647                 rdev->config.evergreen.max_gs_threads = 16;
1648                 rdev->config.evergreen.max_stack_entries = 256;
1649                 rdev->config.evergreen.sx_num_of_sets = 4;
1650                 rdev->config.evergreen.sx_max_export_size = 128;
1651                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1652                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1653                 rdev->config.evergreen.max_hw_contexts = 4;
1654                 rdev->config.evergreen.sq_num_cf_insts = 1;
1655
1656                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1657                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1658                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1659                 break;
1660         case CHIP_PALM:
1661                 rdev->config.evergreen.num_ses = 1;
1662                 rdev->config.evergreen.max_pipes = 2;
1663                 rdev->config.evergreen.max_tile_pipes = 2;
1664                 rdev->config.evergreen.max_simds = 2;
1665                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1666                 rdev->config.evergreen.max_gprs = 256;
1667                 rdev->config.evergreen.max_threads = 192;
1668                 rdev->config.evergreen.max_gs_threads = 16;
1669                 rdev->config.evergreen.max_stack_entries = 256;
1670                 rdev->config.evergreen.sx_num_of_sets = 4;
1671                 rdev->config.evergreen.sx_max_export_size = 128;
1672                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1673                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1674                 rdev->config.evergreen.max_hw_contexts = 4;
1675                 rdev->config.evergreen.sq_num_cf_insts = 1;
1676
1677                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1678                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1679                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1680                 break;
1681         case CHIP_BARTS:
1682                 rdev->config.evergreen.num_ses = 2;
1683                 rdev->config.evergreen.max_pipes = 4;
1684                 rdev->config.evergreen.max_tile_pipes = 8;
1685                 rdev->config.evergreen.max_simds = 7;
1686                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1687                 rdev->config.evergreen.max_gprs = 256;
1688                 rdev->config.evergreen.max_threads = 248;
1689                 rdev->config.evergreen.max_gs_threads = 32;
1690                 rdev->config.evergreen.max_stack_entries = 512;
1691                 rdev->config.evergreen.sx_num_of_sets = 4;
1692                 rdev->config.evergreen.sx_max_export_size = 256;
1693                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1694                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1695                 rdev->config.evergreen.max_hw_contexts = 8;
1696                 rdev->config.evergreen.sq_num_cf_insts = 2;
1697
1698                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1699                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1700                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1701                 break;
1702         case CHIP_TURKS:
1703                 rdev->config.evergreen.num_ses = 1;
1704                 rdev->config.evergreen.max_pipes = 4;
1705                 rdev->config.evergreen.max_tile_pipes = 4;
1706                 rdev->config.evergreen.max_simds = 6;
1707                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1708                 rdev->config.evergreen.max_gprs = 256;
1709                 rdev->config.evergreen.max_threads = 248;
1710                 rdev->config.evergreen.max_gs_threads = 32;
1711                 rdev->config.evergreen.max_stack_entries = 256;
1712                 rdev->config.evergreen.sx_num_of_sets = 4;
1713                 rdev->config.evergreen.sx_max_export_size = 256;
1714                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1715                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1716                 rdev->config.evergreen.max_hw_contexts = 8;
1717                 rdev->config.evergreen.sq_num_cf_insts = 2;
1718
1719                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1720                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1721                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1722                 break;
1723         case CHIP_CAICOS:
1724                 rdev->config.evergreen.num_ses = 1;
1725                 rdev->config.evergreen.max_pipes = 4;
1726                 rdev->config.evergreen.max_tile_pipes = 2;
1727                 rdev->config.evergreen.max_simds = 2;
1728                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1729                 rdev->config.evergreen.max_gprs = 256;
1730                 rdev->config.evergreen.max_threads = 192;
1731                 rdev->config.evergreen.max_gs_threads = 16;
1732                 rdev->config.evergreen.max_stack_entries = 256;
1733                 rdev->config.evergreen.sx_num_of_sets = 4;
1734                 rdev->config.evergreen.sx_max_export_size = 128;
1735                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1736                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1737                 rdev->config.evergreen.max_hw_contexts = 4;
1738                 rdev->config.evergreen.sq_num_cf_insts = 1;
1739
1740                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1741                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1742                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1743                 break;
1744         }
1745
1746         /* Initialize HDP */
1747         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1748                 WREG32((0x2c14 + j), 0x00000000);
1749                 WREG32((0x2c18 + j), 0x00000000);
1750                 WREG32((0x2c1c + j), 0x00000000);
1751                 WREG32((0x2c20 + j), 0x00000000);
1752                 WREG32((0x2c24 + j), 0x00000000);
1753         }
1754
1755         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1756
1757         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1758
1759         cc_gc_shader_pipe_config |=
1760                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1761                                   & EVERGREEN_MAX_PIPES_MASK);
1762         cc_gc_shader_pipe_config |=
1763                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1764                                & EVERGREEN_MAX_SIMDS_MASK);
1765
1766         cc_rb_backend_disable =
1767                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1768                                 & EVERGREEN_MAX_BACKENDS_MASK);
1769
1770
1771         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1772         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1773
1774         switch (rdev->config.evergreen.max_tile_pipes) {
1775         case 1:
1776         default:
1777                 gb_addr_config |= NUM_PIPES(0);
1778                 break;
1779         case 2:
1780                 gb_addr_config |= NUM_PIPES(1);
1781                 break;
1782         case 4:
1783                 gb_addr_config |= NUM_PIPES(2);
1784                 break;
1785         case 8:
1786                 gb_addr_config |= NUM_PIPES(3);
1787                 break;
1788         }
1789
1790         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1791         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1792         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1793         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1794         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1795         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1796
1797         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1798                 gb_addr_config |= ROW_SIZE(2);
1799         else
1800                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1801
1802         if (rdev->ddev->pdev->device == 0x689e) {
1803                 u32 efuse_straps_4;
1804                 u32 efuse_straps_3;
1805                 u8 efuse_box_bit_131_124;
1806
1807                 WREG32(RCU_IND_INDEX, 0x204);
1808                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1809                 WREG32(RCU_IND_INDEX, 0x203);
1810                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1811                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1812
1813                 switch(efuse_box_bit_131_124) {
1814                 case 0x00:
1815                         gb_backend_map = 0x76543210;
1816                         break;
1817                 case 0x55:
1818                         gb_backend_map = 0x77553311;
1819                         break;
1820                 case 0x56:
1821                         gb_backend_map = 0x77553300;
1822                         break;
1823                 case 0x59:
1824                         gb_backend_map = 0x77552211;
1825                         break;
1826                 case 0x66:
1827                         gb_backend_map = 0x77443300;
1828                         break;
1829                 case 0x99:
1830                         gb_backend_map = 0x66552211;
1831                         break;
1832                 case 0x5a:
1833                         gb_backend_map = 0x77552200;
1834                         break;
1835                 case 0xaa:
1836                         gb_backend_map = 0x66442200;
1837                         break;
1838                 case 0x95:
1839                         gb_backend_map = 0x66553311;
1840                         break;
1841                 default:
1842                         DRM_ERROR("bad backend map, using default\n");
1843                         gb_backend_map =
1844                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1845                                                                        rdev->config.evergreen.max_tile_pipes,
1846                                                                        rdev->config.evergreen.max_backends,
1847                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1848                                                                    rdev->config.evergreen.max_backends) &
1849                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1850                         break;
1851                 }
1852         } else if (rdev->ddev->pdev->device == 0x68b9) {
1853                 u32 efuse_straps_3;
1854                 u8 efuse_box_bit_127_124;
1855
1856                 WREG32(RCU_IND_INDEX, 0x203);
1857                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1858                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1859
1860                 switch(efuse_box_bit_127_124) {
1861                 case 0x0:
1862                         gb_backend_map = 0x00003210;
1863                         break;
1864                 case 0x5:
1865                 case 0x6:
1866                 case 0x9:
1867                 case 0xa:
1868                         gb_backend_map = 0x00003311;
1869                         break;
1870                 default:
1871                         DRM_ERROR("bad backend map, using default\n");
1872                         gb_backend_map =
1873                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1874                                                                        rdev->config.evergreen.max_tile_pipes,
1875                                                                        rdev->config.evergreen.max_backends,
1876                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1877                                                                    rdev->config.evergreen.max_backends) &
1878                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1879                         break;
1880                 }
1881         } else {
1882                 switch (rdev->family) {
1883                 case CHIP_CYPRESS:
1884                 case CHIP_HEMLOCK:
1885                 case CHIP_BARTS:
1886                         gb_backend_map = 0x66442200;
1887                         break;
1888                 case CHIP_JUNIPER:
1889                         gb_backend_map = 0x00006420;
1890                         break;
1891                 default:
1892                         gb_backend_map =
1893                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1894                                                                        rdev->config.evergreen.max_tile_pipes,
1895                                                                        rdev->config.evergreen.max_backends,
1896                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1897                                                                          rdev->config.evergreen.max_backends) &
1898                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1899                 }
1900         }
1901
1902         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1903          * not have bank info, so create a custom tiling dword.
1904          * bits 3:0   num_pipes
1905          * bits 7:4   num_banks
1906          * bits 11:8  group_size
1907          * bits 15:12 row_size
1908          */
1909         rdev->config.evergreen.tile_config = 0;
1910         switch (rdev->config.evergreen.max_tile_pipes) {
1911         case 1:
1912         default:
1913                 rdev->config.evergreen.tile_config |= (0 << 0);
1914                 break;
1915         case 2:
1916                 rdev->config.evergreen.tile_config |= (1 << 0);
1917                 break;
1918         case 4:
1919                 rdev->config.evergreen.tile_config |= (2 << 0);
1920                 break;
1921         case 8:
1922                 rdev->config.evergreen.tile_config |= (3 << 0);
1923                 break;
1924         }
1925         rdev->config.evergreen.tile_config |=
1926                 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1927         rdev->config.evergreen.tile_config |=
1928                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1929         rdev->config.evergreen.tile_config |=
1930                 ((gb_addr_config & 0x30000000) >> 28) << 12;
1931
1932         WREG32(GB_BACKEND_MAP, gb_backend_map);
1933         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1934         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1935         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1936
1937         evergreen_program_channel_remap(rdev);
1938
1939         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1940         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1941
1942         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1943                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1944                 u32 sp = cc_gc_shader_pipe_config;
1945                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1946
1947                 if (i == num_shader_engines) {
1948                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1949                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1950                 }
1951
1952                 WREG32(GRBM_GFX_INDEX, gfx);
1953                 WREG32(RLC_GFX_INDEX, gfx);
1954
1955                 WREG32(CC_RB_BACKEND_DISABLE, rb);
1956                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1957                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1958                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1959         }
1960
1961         grbm_gfx_index |= SE_BROADCAST_WRITES;
1962         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1963         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1964
1965         WREG32(CGTS_SYS_TCC_DISABLE, 0);
1966         WREG32(CGTS_TCC_DISABLE, 0);
1967         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1968         WREG32(CGTS_USER_TCC_DISABLE, 0);
1969
1970         /* set HW defaults for 3D engine */
1971         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1972                                      ROQ_IB2_START(0x2b)));
1973
1974         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1975
1976         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1977                              SYNC_GRADIENT |
1978                              SYNC_WALKER |
1979                              SYNC_ALIGNER));
1980
1981         sx_debug_1 = RREG32(SX_DEBUG_1);
1982         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1983         WREG32(SX_DEBUG_1, sx_debug_1);
1984
1985
1986         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1987         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1988         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1989         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1990
1991         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1992                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1993                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1994
1995         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1996                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1997                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1998
1999         WREG32(VGT_NUM_INSTANCES, 1);
2000         WREG32(SPI_CONFIG_CNTL, 0);
2001         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2002         WREG32(CP_PERFMON_CNTL, 0);
2003
2004         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2005                                   FETCH_FIFO_HIWATER(0x4) |
2006                                   DONE_FIFO_HIWATER(0xe0) |
2007                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2008
2009         sq_config = RREG32(SQ_CONFIG);
2010         sq_config &= ~(PS_PRIO(3) |
2011                        VS_PRIO(3) |
2012                        GS_PRIO(3) |
2013                        ES_PRIO(3));
2014         sq_config |= (VC_ENABLE |
2015                       EXPORT_SRC_C |
2016                       PS_PRIO(0) |
2017                       VS_PRIO(1) |
2018                       GS_PRIO(2) |
2019                       ES_PRIO(3));
2020
2021         switch (rdev->family) {
2022         case CHIP_CEDAR:
2023         case CHIP_PALM:
2024         case CHIP_CAICOS:
2025                 /* no vertex cache */
2026                 sq_config &= ~VC_ENABLE;
2027                 break;
2028         default:
2029                 break;
2030         }
2031
2032         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2033
2034         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2035         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2036         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2037         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2038         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2039         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2040         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2041
2042         switch (rdev->family) {
2043         case CHIP_CEDAR:
2044         case CHIP_PALM:
2045                 ps_thread_count = 96;
2046                 break;
2047         default:
2048                 ps_thread_count = 128;
2049                 break;
2050         }
2051
2052         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2053         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2054         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2055         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2056         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2057         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2058
2059         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2060         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2061         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2062         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2063         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2064         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2065
2066         WREG32(SQ_CONFIG, sq_config);
2067         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2068         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2069         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2070         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2071         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2072         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2073         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2074         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2075         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2076         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2077
2078         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2079                                           FORCE_EOV_MAX_REZ_CNT(255)));
2080
2081         switch (rdev->family) {
2082         case CHIP_CEDAR:
2083         case CHIP_PALM:
2084         case CHIP_CAICOS:
2085                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2086                 break;
2087         default:
2088                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2089                 break;
2090         }
2091         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2092         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2093
2094         WREG32(VGT_GS_VERTEX_REUSE, 16);
2095         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2096         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2097
2098         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2099         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2100
2101         WREG32(CB_PERF_CTR0_SEL_0, 0);
2102         WREG32(CB_PERF_CTR0_SEL_1, 0);
2103         WREG32(CB_PERF_CTR1_SEL_0, 0);
2104         WREG32(CB_PERF_CTR1_SEL_1, 0);
2105         WREG32(CB_PERF_CTR2_SEL_0, 0);
2106         WREG32(CB_PERF_CTR2_SEL_1, 0);
2107         WREG32(CB_PERF_CTR3_SEL_0, 0);
2108         WREG32(CB_PERF_CTR3_SEL_1, 0);
2109
2110         /* clear render buffer base addresses */
2111         WREG32(CB_COLOR0_BASE, 0);
2112         WREG32(CB_COLOR1_BASE, 0);
2113         WREG32(CB_COLOR2_BASE, 0);
2114         WREG32(CB_COLOR3_BASE, 0);
2115         WREG32(CB_COLOR4_BASE, 0);
2116         WREG32(CB_COLOR5_BASE, 0);
2117         WREG32(CB_COLOR6_BASE, 0);
2118         WREG32(CB_COLOR7_BASE, 0);
2119         WREG32(CB_COLOR8_BASE, 0);
2120         WREG32(CB_COLOR9_BASE, 0);
2121         WREG32(CB_COLOR10_BASE, 0);
2122         WREG32(CB_COLOR11_BASE, 0);
2123
2124         /* set the shader const cache sizes to 0 */
2125         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2126                 WREG32(i, 0);
2127         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2128                 WREG32(i, 0);
2129
2130         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2131         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2132
2133         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2134
2135         udelay(50);
2136
2137 }
2138
2139 int evergreen_mc_init(struct radeon_device *rdev)
2140 {
2141         u32 tmp;
2142         int chansize, numchan;
2143
2144         /* Get VRAM informations */
2145         rdev->mc.vram_is_ddr = true;
2146         tmp = RREG32(MC_ARB_RAMCFG);
2147         if (tmp & CHANSIZE_OVERRIDE) {
2148                 chansize = 16;
2149         } else if (tmp & CHANSIZE_MASK) {
2150                 chansize = 64;
2151         } else {
2152                 chansize = 32;
2153         }
2154         tmp = RREG32(MC_SHARED_CHMAP);
2155         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2156         case 0:
2157         default:
2158                 numchan = 1;
2159                 break;
2160         case 1:
2161                 numchan = 2;
2162                 break;
2163         case 2:
2164                 numchan = 4;
2165                 break;
2166         case 3:
2167                 numchan = 8;
2168                 break;
2169         }
2170         rdev->mc.vram_width = numchan * chansize;
2171         /* Could aper size report 0 ? */
2172         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2173         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2174         /* Setup GPU memory space */
2175         if (rdev->flags & RADEON_IS_IGP) {
2176                 /* size in bytes on fusion */
2177                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2178                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2179         } else {
2180                 /* size in MB on evergreen */
2181                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2182                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2183         }
2184         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2185         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2186         r700_vram_gtt_location(rdev, &rdev->mc);
2187         radeon_update_bandwidth_info(rdev);
2188
2189         return 0;
2190 }
2191
2192 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2193 {
2194         u32 srbm_status;
2195         u32 grbm_status;
2196         u32 grbm_status_se0, grbm_status_se1;
2197         struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2198         int r;
2199
2200         srbm_status = RREG32(SRBM_STATUS);
2201         grbm_status = RREG32(GRBM_STATUS);
2202         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2203         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2204         if (!(grbm_status & GUI_ACTIVE)) {
2205                 r100_gpu_lockup_update(lockup, &rdev->cp);
2206                 return false;
2207         }
2208         /* force CP activities */
2209         r = radeon_ring_lock(rdev, 2);
2210         if (!r) {
2211                 /* PACKET2 NOP */
2212                 radeon_ring_write(rdev, 0x80000000);
2213                 radeon_ring_write(rdev, 0x80000000);
2214                 radeon_ring_unlock_commit(rdev);
2215         }
2216         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2217         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2218 }
2219
2220 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2221 {
2222         struct evergreen_mc_save save;
2223         u32 grbm_reset = 0;
2224
2225         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2226                 return 0;
2227
2228         dev_info(rdev->dev, "GPU softreset \n");
2229         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2230                 RREG32(GRBM_STATUS));
2231         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2232                 RREG32(GRBM_STATUS_SE0));
2233         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2234                 RREG32(GRBM_STATUS_SE1));
2235         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2236                 RREG32(SRBM_STATUS));
2237         evergreen_mc_stop(rdev, &save);
2238         if (evergreen_mc_wait_for_idle(rdev)) {
2239                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2240         }
2241         /* Disable CP parsing/prefetching */
2242         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2243
2244         /* reset all the gfx blocks */
2245         grbm_reset = (SOFT_RESET_CP |
2246                       SOFT_RESET_CB |
2247                       SOFT_RESET_DB |
2248                       SOFT_RESET_PA |
2249                       SOFT_RESET_SC |
2250                       SOFT_RESET_SPI |
2251                       SOFT_RESET_SH |
2252                       SOFT_RESET_SX |
2253                       SOFT_RESET_TC |
2254                       SOFT_RESET_TA |
2255                       SOFT_RESET_VC |
2256                       SOFT_RESET_VGT);
2257
2258         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2259         WREG32(GRBM_SOFT_RESET, grbm_reset);
2260         (void)RREG32(GRBM_SOFT_RESET);
2261         udelay(50);
2262         WREG32(GRBM_SOFT_RESET, 0);
2263         (void)RREG32(GRBM_SOFT_RESET);
2264         /* Wait a little for things to settle down */
2265         udelay(50);
2266         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2267                 RREG32(GRBM_STATUS));
2268         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2269                 RREG32(GRBM_STATUS_SE0));
2270         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2271                 RREG32(GRBM_STATUS_SE1));
2272         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2273                 RREG32(SRBM_STATUS));
2274         evergreen_mc_resume(rdev, &save);
2275         return 0;
2276 }
2277
2278 int evergreen_asic_reset(struct radeon_device *rdev)
2279 {
2280         return evergreen_gpu_soft_reset(rdev);
2281 }
2282
2283 /* Interrupts */
2284
2285 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2286 {
2287         switch (crtc) {
2288         case 0:
2289                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2290         case 1:
2291                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2292         case 2:
2293                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2294         case 3:
2295                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2296         case 4:
2297                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2298         case 5:
2299                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2300         default:
2301                 return 0;
2302         }
2303 }
2304
2305 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2306 {
2307         u32 tmp;
2308
2309         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2310         WREG32(GRBM_INT_CNTL, 0);
2311         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2312         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2313         if (!(rdev->flags & RADEON_IS_IGP)) {
2314                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2315                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2316                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2317                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2318         }
2319
2320         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2321         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2322         if (!(rdev->flags & RADEON_IS_IGP)) {
2323                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2324                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2325                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2326                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2327         }
2328
2329         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2330         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2331
2332         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2333         WREG32(DC_HPD1_INT_CONTROL, tmp);
2334         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2335         WREG32(DC_HPD2_INT_CONTROL, tmp);
2336         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2337         WREG32(DC_HPD3_INT_CONTROL, tmp);
2338         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2339         WREG32(DC_HPD4_INT_CONTROL, tmp);
2340         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2341         WREG32(DC_HPD5_INT_CONTROL, tmp);
2342         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2343         WREG32(DC_HPD6_INT_CONTROL, tmp);
2344
2345 }
2346
2347 int evergreen_irq_set(struct radeon_device *rdev)
2348 {
2349         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2350         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2351         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2352         u32 grbm_int_cntl = 0;
2353         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2354
2355         if (!rdev->irq.installed) {
2356                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2357                 return -EINVAL;
2358         }
2359         /* don't enable anything if the ih is disabled */
2360         if (!rdev->ih.enabled) {
2361                 r600_disable_interrupts(rdev);
2362                 /* force the active interrupt state to all disabled */
2363                 evergreen_disable_interrupt_state(rdev);
2364                 return 0;
2365         }
2366
2367         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2368         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2369         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2370         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2371         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2372         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2373
2374         if (rdev->irq.sw_int) {
2375                 DRM_DEBUG("evergreen_irq_set: sw int\n");
2376                 cp_int_cntl |= RB_INT_ENABLE;
2377                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2378         }
2379         if (rdev->irq.crtc_vblank_int[0] ||
2380             rdev->irq.pflip[0]) {
2381                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2382                 crtc1 |= VBLANK_INT_MASK;
2383         }
2384         if (rdev->irq.crtc_vblank_int[1] ||
2385             rdev->irq.pflip[1]) {
2386                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2387                 crtc2 |= VBLANK_INT_MASK;
2388         }
2389         if (rdev->irq.crtc_vblank_int[2] ||
2390             rdev->irq.pflip[2]) {
2391                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2392                 crtc3 |= VBLANK_INT_MASK;
2393         }
2394         if (rdev->irq.crtc_vblank_int[3] ||
2395             rdev->irq.pflip[3]) {
2396                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2397                 crtc4 |= VBLANK_INT_MASK;
2398         }
2399         if (rdev->irq.crtc_vblank_int[4] ||
2400             rdev->irq.pflip[4]) {
2401                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2402                 crtc5 |= VBLANK_INT_MASK;
2403         }
2404         if (rdev->irq.crtc_vblank_int[5] ||
2405             rdev->irq.pflip[5]) {
2406                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2407                 crtc6 |= VBLANK_INT_MASK;
2408         }
2409         if (rdev->irq.hpd[0]) {
2410                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2411                 hpd1 |= DC_HPDx_INT_EN;
2412         }
2413         if (rdev->irq.hpd[1]) {
2414                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2415                 hpd2 |= DC_HPDx_INT_EN;
2416         }
2417         if (rdev->irq.hpd[2]) {
2418                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2419                 hpd3 |= DC_HPDx_INT_EN;
2420         }
2421         if (rdev->irq.hpd[3]) {
2422                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2423                 hpd4 |= DC_HPDx_INT_EN;
2424         }
2425         if (rdev->irq.hpd[4]) {
2426                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2427                 hpd5 |= DC_HPDx_INT_EN;
2428         }
2429         if (rdev->irq.hpd[5]) {
2430                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2431                 hpd6 |= DC_HPDx_INT_EN;
2432         }
2433         if (rdev->irq.gui_idle) {
2434                 DRM_DEBUG("gui idle\n");
2435                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2436         }
2437
2438         WREG32(CP_INT_CNTL, cp_int_cntl);
2439         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2440
2441         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2442         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2443         if (!(rdev->flags & RADEON_IS_IGP)) {
2444                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2445                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2446                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2447                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2448         }
2449
2450         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2451         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2452         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2453         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2454         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2455         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2456
2457         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2458         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2459         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2460         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2461         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2462         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2463
2464         return 0;
2465 }
2466
2467 static inline void evergreen_irq_ack(struct radeon_device *rdev)
2468 {
2469         u32 tmp;
2470
2471         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2472         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2473         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2474         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2475         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2476         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2477         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2478         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2479         rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2480         rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2481         rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2482         rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2483
2484         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2485                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2486         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2487                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2488         if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2489                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2490         if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2491                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2492         if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2493                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2494         if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2495                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2496
2497         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2498                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2499         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2500                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2501
2502         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2503                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2504         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2505                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2506
2507         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2508                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2509         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2510                 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2511
2512         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2513                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2514         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2515                 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2516
2517         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2518                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2519         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2520                 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2521
2522         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2523                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2524         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2525                 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2526
2527         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2528                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2529                 tmp |= DC_HPDx_INT_ACK;
2530                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2531         }
2532         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2533                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2534                 tmp |= DC_HPDx_INT_ACK;
2535                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2536         }
2537         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2538                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2539                 tmp |= DC_HPDx_INT_ACK;
2540                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2541         }
2542         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2543                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2544                 tmp |= DC_HPDx_INT_ACK;
2545                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2546         }
2547         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2548                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2549                 tmp |= DC_HPDx_INT_ACK;
2550                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2551         }
2552         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2553                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2554                 tmp |= DC_HPDx_INT_ACK;
2555                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2556         }
2557 }
2558
2559 void evergreen_irq_disable(struct radeon_device *rdev)
2560 {
2561         r600_disable_interrupts(rdev);
2562         /* Wait and acknowledge irq */
2563         mdelay(1);
2564         evergreen_irq_ack(rdev);
2565         evergreen_disable_interrupt_state(rdev);
2566 }
2567
2568 static void evergreen_irq_suspend(struct radeon_device *rdev)
2569 {
2570         evergreen_irq_disable(rdev);
2571         r600_rlc_stop(rdev);
2572 }
2573
2574 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2575 {
2576         u32 wptr, tmp;
2577
2578         if (rdev->wb.enabled)
2579                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2580         else
2581                 wptr = RREG32(IH_RB_WPTR);
2582
2583         if (wptr & RB_OVERFLOW) {
2584                 /* When a ring buffer overflow happen start parsing interrupt
2585                  * from the last not overwritten vector (wptr + 16). Hopefully
2586                  * this should allow us to catchup.
2587                  */
2588                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2589                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2590                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2591                 tmp = RREG32(IH_RB_CNTL);
2592                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2593                 WREG32(IH_RB_CNTL, tmp);
2594         }
2595         return (wptr & rdev->ih.ptr_mask);
2596 }
2597
2598 int evergreen_irq_process(struct radeon_device *rdev)
2599 {
2600         u32 wptr = evergreen_get_ih_wptr(rdev);
2601         u32 rptr = rdev->ih.rptr;
2602         u32 src_id, src_data;
2603         u32 ring_index;
2604         unsigned long flags;
2605         bool queue_hotplug = false;
2606
2607         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2608         if (!rdev->ih.enabled)
2609                 return IRQ_NONE;
2610
2611         spin_lock_irqsave(&rdev->ih.lock, flags);
2612
2613         if (rptr == wptr) {
2614                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2615                 return IRQ_NONE;
2616         }
2617         if (rdev->shutdown) {
2618                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2619                 return IRQ_NONE;
2620         }
2621
2622 restart_ih:
2623         /* display interrupts */
2624         evergreen_irq_ack(rdev);
2625
2626         rdev->ih.wptr = wptr;
2627         while (rptr != wptr) {
2628                 /* wptr/rptr are in bytes! */
2629                 ring_index = rptr / 4;
2630                 src_id =  rdev->ih.ring[ring_index] & 0xff;
2631                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2632
2633                 switch (src_id) {
2634                 case 1: /* D1 vblank/vline */
2635                         switch (src_data) {
2636                         case 0: /* D1 vblank */
2637                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2638                                         if (rdev->irq.crtc_vblank_int[0]) {
2639                                                 drm_handle_vblank(rdev->ddev, 0);
2640                                                 rdev->pm.vblank_sync = true;
2641                                                 wake_up(&rdev->irq.vblank_queue);
2642                                         }
2643                                         if (rdev->irq.pflip[0])
2644                                                 radeon_crtc_handle_flip(rdev, 0);
2645                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2646                                         DRM_DEBUG("IH: D1 vblank\n");
2647                                 }
2648                                 break;
2649                         case 1: /* D1 vline */
2650                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2651                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2652                                         DRM_DEBUG("IH: D1 vline\n");
2653                                 }
2654                                 break;
2655                         default:
2656                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2657                                 break;
2658                         }
2659                         break;
2660                 case 2: /* D2 vblank/vline */
2661                         switch (src_data) {
2662                         case 0: /* D2 vblank */
2663                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2664                                         if (rdev->irq.crtc_vblank_int[1]) {
2665                                                 drm_handle_vblank(rdev->ddev, 1);
2666                                                 rdev->pm.vblank_sync = true;
2667                                                 wake_up(&rdev->irq.vblank_queue);
2668                                         }
2669                                         if (rdev->irq.pflip[1])
2670                                                 radeon_crtc_handle_flip(rdev, 1);
2671                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2672                                         DRM_DEBUG("IH: D2 vblank\n");
2673                                 }
2674                                 break;
2675                         case 1: /* D2 vline */
2676                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2677                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2678                                         DRM_DEBUG("IH: D2 vline\n");
2679                                 }
2680                                 break;
2681                         default:
2682                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2683                                 break;
2684                         }
2685                         break;
2686                 case 3: /* D3 vblank/vline */
2687                         switch (src_data) {
2688                         case 0: /* D3 vblank */
2689                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2690                                         if (rdev->irq.crtc_vblank_int[2]) {
2691                                                 drm_handle_vblank(rdev->ddev, 2);
2692                                                 rdev->pm.vblank_sync = true;
2693                                                 wake_up(&rdev->irq.vblank_queue);
2694                                         }
2695                                         if (rdev->irq.pflip[2])
2696                                                 radeon_crtc_handle_flip(rdev, 2);
2697                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2698                                         DRM_DEBUG("IH: D3 vblank\n");
2699                                 }
2700                                 break;
2701                         case 1: /* D3 vline */
2702                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2703                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2704                                         DRM_DEBUG("IH: D3 vline\n");
2705                                 }
2706                                 break;
2707                         default:
2708                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2709                                 break;
2710                         }
2711                         break;
2712                 case 4: /* D4 vblank/vline */
2713                         switch (src_data) {
2714                         case 0: /* D4 vblank */
2715                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2716                                         if (rdev->irq.crtc_vblank_int[3]) {
2717                                                 drm_handle_vblank(rdev->ddev, 3);
2718                                                 rdev->pm.vblank_sync = true;
2719                                                 wake_up(&rdev->irq.vblank_queue);
2720                                         }
2721                                         if (rdev->irq.pflip[3])
2722                                                 radeon_crtc_handle_flip(rdev, 3);
2723                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2724                                         DRM_DEBUG("IH: D4 vblank\n");
2725                                 }
2726                                 break;
2727                         case 1: /* D4 vline */
2728                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2729                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2730                                         DRM_DEBUG("IH: D4 vline\n");
2731                                 }
2732                                 break;
2733                         default:
2734                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2735                                 break;
2736                         }
2737                         break;
2738                 case 5: /* D5 vblank/vline */
2739                         switch (src_data) {
2740                         case 0: /* D5 vblank */
2741                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2742                                         if (rdev->irq.crtc_vblank_int[4]) {
2743                                                 drm_handle_vblank(rdev->ddev, 4);
2744                                                 rdev->pm.vblank_sync = true;
2745                                                 wake_up(&rdev->irq.vblank_queue);
2746                                         }
2747                                         if (rdev->irq.pflip[4])
2748                                                 radeon_crtc_handle_flip(rdev, 4);
2749                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2750                                         DRM_DEBUG("IH: D5 vblank\n");
2751                                 }
2752                                 break;
2753                         case 1: /* D5 vline */
2754                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2755                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2756                                         DRM_DEBUG("IH: D5 vline\n");
2757                                 }
2758                                 break;
2759                         default:
2760                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2761                                 break;
2762                         }
2763                         break;
2764                 case 6: /* D6 vblank/vline */
2765                         switch (src_data) {
2766                         case 0: /* D6 vblank */
2767                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2768                                         if (rdev->irq.crtc_vblank_int[5]) {
2769                                                 drm_handle_vblank(rdev->ddev, 5);
2770                                                 rdev->pm.vblank_sync = true;
2771                                                 wake_up(&rdev->irq.vblank_queue);
2772                                         }
2773                                         if (rdev->irq.pflip[5])
2774                                                 radeon_crtc_handle_flip(rdev, 5);
2775                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2776                                         DRM_DEBUG("IH: D6 vblank\n");
2777                                 }
2778                                 break;
2779                         case 1: /* D6 vline */
2780                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2781                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2782                                         DRM_DEBUG("IH: D6 vline\n");
2783                                 }
2784                                 break;
2785                         default:
2786                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2787                                 break;
2788                         }
2789                         break;
2790                 case 42: /* HPD hotplug */
2791                         switch (src_data) {
2792                         case 0:
2793                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2794                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2795                                         queue_hotplug = true;
2796                                         DRM_DEBUG("IH: HPD1\n");
2797                                 }
2798                                 break;
2799                         case 1:
2800                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2801                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2802                                         queue_hotplug = true;
2803                                         DRM_DEBUG("IH: HPD2\n");
2804                                 }
2805                                 break;
2806                         case 2:
2807                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2808                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2809                                         queue_hotplug = true;
2810                                         DRM_DEBUG("IH: HPD3\n");
2811                                 }
2812                                 break;
2813                         case 3:
2814                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2815                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2816                                         queue_hotplug = true;
2817                                         DRM_DEBUG("IH: HPD4\n");
2818                                 }
2819                                 break;
2820                         case 4:
2821                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2822                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2823                                         queue_hotplug = true;
2824                                         DRM_DEBUG("IH: HPD5\n");
2825                                 }
2826                                 break;
2827                         case 5:
2828                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2829                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2830                                         queue_hotplug = true;
2831                                         DRM_DEBUG("IH: HPD6\n");
2832                                 }
2833                                 break;
2834                         default:
2835                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2836                                 break;
2837                         }
2838                         break;
2839                 case 176: /* CP_INT in ring buffer */
2840                 case 177: /* CP_INT in IB1 */
2841                 case 178: /* CP_INT in IB2 */
2842                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2843                         radeon_fence_process(rdev);
2844                         break;
2845                 case 181: /* CP EOP event */
2846                         DRM_DEBUG("IH: CP EOP\n");
2847                         radeon_fence_process(rdev);
2848                         break;
2849                 case 233: /* GUI IDLE */
2850                         DRM_DEBUG("IH: CP EOP\n");
2851                         rdev->pm.gui_idle = true;
2852                         wake_up(&rdev->irq.idle_queue);
2853                         break;
2854                 default:
2855                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2856                         break;
2857                 }
2858
2859                 /* wptr/rptr are in bytes! */
2860                 rptr += 16;
2861                 rptr &= rdev->ih.ptr_mask;
2862         }
2863         /* make sure wptr hasn't changed while processing */
2864         wptr = evergreen_get_ih_wptr(rdev);
2865         if (wptr != rdev->ih.wptr)
2866                 goto restart_ih;
2867         if (queue_hotplug)
2868                 schedule_work(&rdev->hotplug_work);
2869         rdev->ih.rptr = rptr;
2870         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2871         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2872         return IRQ_HANDLED;
2873 }
2874
2875 static int evergreen_startup(struct radeon_device *rdev)
2876 {
2877         int r;
2878
2879         /* enable pcie gen2 link */
2880         if (!ASIC_IS_DCE5(rdev))
2881                 evergreen_pcie_gen2_enable(rdev);
2882
2883         if (ASIC_IS_DCE5(rdev)) {
2884                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2885                         r = ni_init_microcode(rdev);
2886                         if (r) {
2887                                 DRM_ERROR("Failed to load firmware!\n");
2888                                 return r;
2889                         }
2890                 }
2891                 r = btc_mc_load_microcode(rdev);
2892                 if (r) {
2893                         DRM_ERROR("Failed to load MC firmware!\n");
2894                         return r;
2895                 }
2896         } else {
2897                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2898                         r = r600_init_microcode(rdev);
2899                         if (r) {
2900                                 DRM_ERROR("Failed to load firmware!\n");
2901                                 return r;
2902                         }
2903                 }
2904         }
2905
2906         evergreen_mc_program(rdev);
2907         if (rdev->flags & RADEON_IS_AGP) {
2908                 evergreen_agp_enable(rdev);
2909         } else {
2910                 r = evergreen_pcie_gart_enable(rdev);
2911                 if (r)
2912                         return r;
2913         }
2914         evergreen_gpu_init(rdev);
2915
2916         r = evergreen_blit_init(rdev);
2917         if (r) {
2918                 evergreen_blit_fini(rdev);
2919                 rdev->asic->copy = NULL;
2920                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2921         }
2922         /* XXX: ontario has problems blitting to gart at the moment */
2923         if (rdev->family == CHIP_PALM) {
2924                 rdev->asic->copy = NULL;
2925                 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2926         }
2927
2928         /* allocate wb buffer */
2929         r = radeon_wb_init(rdev);
2930         if (r)
2931                 return r;
2932
2933         /* Enable IRQ */
2934         r = r600_irq_init(rdev);
2935         if (r) {
2936                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2937                 radeon_irq_kms_fini(rdev);
2938                 return r;
2939         }
2940         evergreen_irq_set(rdev);
2941
2942         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2943         if (r)
2944                 return r;
2945         r = evergreen_cp_load_microcode(rdev);
2946         if (r)
2947                 return r;
2948         r = evergreen_cp_resume(rdev);
2949         if (r)
2950                 return r;
2951
2952         return 0;
2953 }
2954
2955 int evergreen_resume(struct radeon_device *rdev)
2956 {
2957         int r;
2958
2959         /* reset the asic, the gfx blocks are often in a bad state
2960          * after the driver is unloaded or after a resume
2961          */
2962         if (radeon_asic_reset(rdev))
2963                 dev_warn(rdev->dev, "GPU reset failed !\n");
2964         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2965          * posting will perform necessary task to bring back GPU into good
2966          * shape.
2967          */
2968         /* post card */
2969         atom_asic_init(rdev->mode_info.atom_context);
2970
2971         r = evergreen_startup(rdev);
2972         if (r) {
2973                 DRM_ERROR("r600 startup failed on resume\n");
2974                 return r;
2975         }
2976
2977         r = r600_ib_test(rdev);
2978         if (r) {
2979                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2980                 return r;
2981         }
2982
2983         return r;
2984
2985 }
2986
2987 int evergreen_suspend(struct radeon_device *rdev)
2988 {
2989         int r;
2990
2991         /* FIXME: we should wait for ring to be empty */
2992         r700_cp_stop(rdev);
2993         rdev->cp.ready = false;
2994         evergreen_irq_suspend(rdev);
2995         radeon_wb_disable(rdev);
2996         evergreen_pcie_gart_disable(rdev);
2997
2998         /* unpin shaders bo */
2999         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
3000         if (likely(r == 0)) {
3001                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
3002                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
3003         }
3004
3005         return 0;
3006 }
3007
3008 int evergreen_copy_blit(struct radeon_device *rdev,
3009                         uint64_t src_offset, uint64_t dst_offset,
3010                         unsigned num_pages, struct radeon_fence *fence)
3011 {
3012         int r;
3013
3014         mutex_lock(&rdev->r600_blit.mutex);
3015         rdev->r600_blit.vb_ib = NULL;
3016         r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
3017         if (r) {
3018                 if (rdev->r600_blit.vb_ib)
3019                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
3020                 mutex_unlock(&rdev->r600_blit.mutex);
3021                 return r;
3022         }
3023         evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3024         evergreen_blit_done_copy(rdev, fence);
3025         mutex_unlock(&rdev->r600_blit.mutex);
3026         return 0;
3027 }
3028
3029 /* Plan is to move initialization in that function and use
3030  * helper function so that radeon_device_init pretty much
3031  * do nothing more than calling asic specific function. This
3032  * should also allow to remove a bunch of callback function
3033  * like vram_info.
3034  */
3035 int evergreen_init(struct radeon_device *rdev)
3036 {
3037         int r;
3038
3039         r = radeon_dummy_page_init(rdev);
3040         if (r)
3041                 return r;
3042         /* This don't do much */
3043         r = radeon_gem_init(rdev);
3044         if (r)
3045                 return r;
3046         /* Read BIOS */
3047         if (!radeon_get_bios(rdev)) {
3048                 if (ASIC_IS_AVIVO(rdev))
3049                         return -EINVAL;
3050         }
3051         /* Must be an ATOMBIOS */
3052         if (!rdev->is_atom_bios) {
3053                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3054                 return -EINVAL;
3055         }
3056         r = radeon_atombios_init(rdev);
3057         if (r)
3058                 return r;
3059         /* reset the asic, the gfx blocks are often in a bad state
3060          * after the driver is unloaded or after a resume
3061          */
3062         if (radeon_asic_reset(rdev))
3063                 dev_warn(rdev->dev, "GPU reset failed !\n");
3064         /* Post card if necessary */
3065         if (!radeon_card_posted(rdev)) {
3066                 if (!rdev->bios) {
3067                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3068                         return -EINVAL;
3069                 }
3070                 DRM_INFO("GPU not posted. posting now...\n");
3071                 atom_asic_init(rdev->mode_info.atom_context);
3072         }
3073         /* Initialize scratch registers */
3074         r600_scratch_init(rdev);
3075         /* Initialize surface registers */
3076         radeon_surface_init(rdev);
3077         /* Initialize clocks */
3078         radeon_get_clock_info(rdev->ddev);
3079         /* Fence driver */
3080         r = radeon_fence_driver_init(rdev);
3081         if (r)
3082                 return r;
3083         /* initialize AGP */
3084         if (rdev->flags & RADEON_IS_AGP) {
3085                 r = radeon_agp_init(rdev);
3086                 if (r)
3087                         radeon_agp_disable(rdev);
3088         }
3089         /* initialize memory controller */
3090         r = evergreen_mc_init(rdev);
3091         if (r)
3092                 return r;
3093         /* Memory manager */
3094         r = radeon_bo_init(rdev);
3095         if (r)
3096                 return r;
3097
3098         r = radeon_irq_kms_init(rdev);
3099         if (r)
3100                 return r;
3101
3102         rdev->cp.ring_obj = NULL;
3103         r600_ring_init(rdev, 1024 * 1024);
3104
3105         rdev->ih.ring_obj = NULL;
3106         r600_ih_ring_init(rdev, 64 * 1024);
3107
3108         r = r600_pcie_gart_init(rdev);
3109         if (r)
3110                 return r;
3111
3112         rdev->accel_working = true;
3113         r = evergreen_startup(rdev);
3114         if (r) {
3115                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3116                 r700_cp_fini(rdev);
3117                 r600_irq_fini(rdev);
3118                 radeon_wb_fini(rdev);
3119                 radeon_irq_kms_fini(rdev);
3120                 evergreen_pcie_gart_fini(rdev);
3121                 rdev->accel_working = false;
3122         }
3123         if (rdev->accel_working) {
3124                 r = radeon_ib_pool_init(rdev);
3125                 if (r) {
3126                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3127                         rdev->accel_working = false;
3128                 }
3129                 r = r600_ib_test(rdev);
3130                 if (r) {
3131                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3132                         rdev->accel_working = false;
3133                 }
3134         }
3135         return 0;
3136 }
3137
3138 void evergreen_fini(struct radeon_device *rdev)
3139 {
3140         evergreen_blit_fini(rdev);
3141         r700_cp_fini(rdev);
3142         r600_irq_fini(rdev);
3143         radeon_wb_fini(rdev);
3144         radeon_irq_kms_fini(rdev);
3145         evergreen_pcie_gart_fini(rdev);
3146         radeon_gem_fini(rdev);
3147         radeon_fence_driver_fini(rdev);
3148         radeon_agp_fini(rdev);
3149         radeon_bo_fini(rdev);
3150         radeon_atombios_fini(rdev);
3151         kfree(rdev->bios);
3152         rdev->bios = NULL;
3153         radeon_dummy_page_fini(rdev);
3154 }
3155
3156 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3157 {
3158         u32 link_width_cntl, speed_cntl;
3159
3160         if (radeon_pcie_gen2 == 0)
3161                 return;
3162
3163         if (rdev->flags & RADEON_IS_IGP)
3164                 return;
3165
3166         if (!(rdev->flags & RADEON_IS_PCIE))
3167                 return;
3168
3169         /* x2 cards have a special sequence */
3170         if (ASIC_IS_X2(rdev))
3171                 return;
3172
3173         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3174         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3175             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3176
3177                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3178                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3179                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3180
3181                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3182                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3183                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3184
3185                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3186                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3187                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3188
3189                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3190                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3191                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3192
3193                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3194                 speed_cntl |= LC_GEN2_EN_STRAP;
3195                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3196
3197         } else {
3198                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3199                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3200                 if (1)
3201                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3202                 else
3203                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3204                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3205         }
3206 }