drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static void evergreen_gpu_init(struct radeon_device *rdev);
  41 void evergreen_fini(struct radeon_device *rdev);
  42 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  43
  44 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
  45 {
  46         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
  47         u32 tmp;
  48
  49         /* make sure flip is at vb rather than hb */
  50         tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
  51         tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
  52         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
  53
  54         /* set pageflip to happen anywhere in vblank interval */
  55         WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
  56
  57         /* enable the pflip int */
  58         radeon_irq_kms_pflip_irq_get(rdev, crtc);
  59 }
  60
  61 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
  62 {
  63         /* disable the pflip int */
  64         radeon_irq_kms_pflip_irq_put(rdev, crtc);
  65 }
  66
  67 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  68 {
  69         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  70         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
  71
  72         /* Lock the graphics update lock */
  73         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
  74         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  75
  76         /* update the scanout addresses */
  77         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  78                upper_32_bits(crtc_base));
  79         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  80                (u32)crtc_base);
  81
  82         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  83                upper_32_bits(crtc_base));
  84         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  85                (u32)crtc_base);
  86
  87         /* Wait for update_pending to go high. */
  88         while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
  89         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  90
  91         /* Unlock the lock, so double-buffering can take place inside vblank */
  92         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
  93         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  94
  95         /* Return current update_pending status: */
  96         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
  97 }
  98
  99 /* get temperature in millidegrees */
 100 int evergreen_get_temp(struct radeon_device *rdev)
 101 {
 102         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 103                 ASIC_T_SHIFT;
 104         u32 actual_temp = 0;
 105
 106         if (temp & 0x400)
 107                 actual_temp = -256;
 108         else if (temp & 0x200)
 109                 actual_temp = 255;
 110         else if (temp & 0x100) {
 111                 actual_temp = temp & 0x1ff;
 112                 actual_temp |= ~0x1ff;
 113         } else
 114                 actual_temp = temp & 0xff;
 115
 116         return (actual_temp * 1000) / 2;
 117 }
 118
 119 int sumo_get_temp(struct radeon_device *rdev)
 120 {
 121         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 122         int actual_temp = temp - 49;
 123
 124         return actual_temp * 1000;
 125 }
 126
 127 void evergreen_pm_misc(struct radeon_device *rdev)
 128 {
 129         int req_ps_idx = rdev->pm.requested_power_state_index;
 130         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 131         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 132         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 133
 134         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 135                 if (voltage->voltage != rdev->pm.current_vddc) {
 136                         radeon_atom_set_voltage(rdev, voltage->voltage);
 137                         rdev->pm.current_vddc = voltage->voltage;
 138                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 139                 }
 140         }
 141 }
 142
 143 void evergreen_pm_prepare(struct radeon_device *rdev)
 144 {
 145         struct drm_device *ddev = rdev->ddev;
 146         struct drm_crtc *crtc;
 147         struct radeon_crtc *radeon_crtc;
 148         u32 tmp;
 149
 150         /* disable any active CRTCs */
 151         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 152                 radeon_crtc = to_radeon_crtc(crtc);
 153                 if (radeon_crtc->enabled) {
 154                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 155                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 156                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 157                 }
 158         }
 159 }
 160
 161 void evergreen_pm_finish(struct radeon_device *rdev)
 162 {
 163         struct drm_device *ddev = rdev->ddev;
 164         struct drm_crtc *crtc;
 165         struct radeon_crtc *radeon_crtc;
 166         u32 tmp;
 167
 168         /* enable any active CRTCs */
 169         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 170                 radeon_crtc = to_radeon_crtc(crtc);
 171                 if (radeon_crtc->enabled) {
 172                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 173                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 174                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 175                 }
 176         }
 177 }
 178
 179 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 180 {
 181         bool connected = false;
 182
 183         switch (hpd) {
 184         case RADEON_HPD_1:
 185                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 186                         connected = true;
 187                 break;
 188         case RADEON_HPD_2:
 189                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 190                         connected = true;
 191                 break;
 192         case RADEON_HPD_3:
 193                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 194                         connected = true;
 195                 break;
 196         case RADEON_HPD_4:
 197                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 198                         connected = true;
 199                 break;
 200         case RADEON_HPD_5:
 201                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 202                         connected = true;
 203                 break;
 204         case RADEON_HPD_6:
 205                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 206                         connected = true;
 207                         break;
 208         default:
 209                 break;
 210         }
 211
 212         return connected;
 213 }
 214
 215 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 216                                 enum radeon_hpd_id hpd)
 217 {
 218         u32 tmp;
 219         bool connected = evergreen_hpd_sense(rdev, hpd);
 220
 221         switch (hpd) {
 222         case RADEON_HPD_1:
 223                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 224                 if (connected)
 225                         tmp &= ~DC_HPDx_INT_POLARITY;
 226                 else
 227                         tmp |= DC_HPDx_INT_POLARITY;
 228                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 229                 break;
 230         case RADEON_HPD_2:
 231                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 232                 if (connected)
 233                         tmp &= ~DC_HPDx_INT_POLARITY;
 234                 else
 235                         tmp |= DC_HPDx_INT_POLARITY;
 236                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 237                 break;
 238         case RADEON_HPD_3:
 239                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 240                 if (connected)
 241                         tmp &= ~DC_HPDx_INT_POLARITY;
 242                 else
 243                         tmp |= DC_HPDx_INT_POLARITY;
 244                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 245                 break;
 246         case RADEON_HPD_4:
 247                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 248                 if (connected)
 249                         tmp &= ~DC_HPDx_INT_POLARITY;
 250                 else
 251                         tmp |= DC_HPDx_INT_POLARITY;
 252                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 253                 break;
 254         case RADEON_HPD_5:
 255                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 256                 if (connected)
 257                         tmp &= ~DC_HPDx_INT_POLARITY;
 258                 else
 259                         tmp |= DC_HPDx_INT_POLARITY;
 260                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 261                         break;
 262         case RADEON_HPD_6:
 263                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 264                 if (connected)
 265                         tmp &= ~DC_HPDx_INT_POLARITY;
 266                 else
 267                         tmp |= DC_HPDx_INT_POLARITY;
 268                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 269                 break;
 270         default:
 271                 break;
 272         }
 273 }
 274
 275 void evergreen_hpd_init(struct radeon_device *rdev)
 276 {
 277         struct drm_device *dev = rdev->ddev;
 278         struct drm_connector *connector;
 279         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 280                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 281
 282         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 283                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 284                 switch (radeon_connector->hpd.hpd) {
 285                 case RADEON_HPD_1:
 286                         WREG32(DC_HPD1_CONTROL, tmp);
 287                         rdev->irq.hpd[0] = true;
 288                         break;
 289                 case RADEON_HPD_2:
 290                         WREG32(DC_HPD2_CONTROL, tmp);
 291                         rdev->irq.hpd[1] = true;
 292                         break;
 293                 case RADEON_HPD_3:
 294                         WREG32(DC_HPD3_CONTROL, tmp);
 295                         rdev->irq.hpd[2] = true;
 296                         break;
 297                 case RADEON_HPD_4:
 298                         WREG32(DC_HPD4_CONTROL, tmp);
 299                         rdev->irq.hpd[3] = true;
 300                         break;
 301                 case RADEON_HPD_5:
 302                         WREG32(DC_HPD5_CONTROL, tmp);
 303                         rdev->irq.hpd[4] = true;
 304                         break;
 305                 case RADEON_HPD_6:
 306                         WREG32(DC_HPD6_CONTROL, tmp);
 307                         rdev->irq.hpd[5] = true;
 308                         break;
 309                 default:
 310                         break;
 311                 }
 312         }
 313         if (rdev->irq.installed)
 314                 evergreen_irq_set(rdev);
 315 }
 316
 317 void evergreen_hpd_fini(struct radeon_device *rdev)
 318 {
 319         struct drm_device *dev = rdev->ddev;
 320         struct drm_connector *connector;
 321
 322         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 323                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 324                 switch (radeon_connector->hpd.hpd) {
 325                 case RADEON_HPD_1:
 326                         WREG32(DC_HPD1_CONTROL, 0);
 327                         rdev->irq.hpd[0] = false;
 328                         break;
 329                 case RADEON_HPD_2:
 330                         WREG32(DC_HPD2_CONTROL, 0);
 331                         rdev->irq.hpd[1] = false;
 332                         break;
 333                 case RADEON_HPD_3:
 334                         WREG32(DC_HPD3_CONTROL, 0);
 335                         rdev->irq.hpd[2] = false;
 336                         break;
 337                 case RADEON_HPD_4:
 338                         WREG32(DC_HPD4_CONTROL, 0);
 339                         rdev->irq.hpd[3] = false;
 340                         break;
 341                 case RADEON_HPD_5:
 342                         WREG32(DC_HPD5_CONTROL, 0);
 343                         rdev->irq.hpd[4] = false;
 344                         break;
 345                 case RADEON_HPD_6:
 346                         WREG32(DC_HPD6_CONTROL, 0);
 347                         rdev->irq.hpd[5] = false;
 348                         break;
 349                 default:
 350                         break;
 351                 }
 352         }
 353 }
 354
 355 /* watermark setup */
 356
 357 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 358                                         struct radeon_crtc *radeon_crtc,
 359                                         struct drm_display_mode *mode,
 360                                         struct drm_display_mode *other_mode)
 361 {
 362         u32 tmp = 0;
 363         /*
 364          * Line Buffer Setup
 365          * There are 3 line buffers, each one shared by 2 display controllers.
 366          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 367          * the display controllers.  The paritioning is done via one of four
 368          * preset allocations specified in bits 2:0:
 369          * first display controller
 370          *  0 - first half of lb (3840 * 2)
 371          *  1 - first 3/4 of lb (5760 * 2)
 372          *  2 - whole lb (7680 * 2)
 373          *  3 - first 1/4 of lb (1920 * 2)
 374          * second display controller
 375          *  4 - second half of lb (3840 * 2)
 376          *  5 - second 3/4 of lb (5760 * 2)
 377          *  6 - whole lb (7680 * 2)
 378          *  7 - last 1/4 of lb (1920 * 2)
 379          */
 380         if (mode && other_mode) {
 381                 if (mode->hdisplay > other_mode->hdisplay) {
 382                         if (mode->hdisplay > 2560)
 383                                 tmp = 1; /* 3/4 */
 384                         else
 385                                 tmp = 0; /* 1/2 */
 386                 } else if (other_mode->hdisplay > mode->hdisplay) {
 387                         if (other_mode->hdisplay > 2560)
 388                                 tmp = 3; /* 1/4 */
 389                         else
 390                                 tmp = 0; /* 1/2 */
 391                 } else
 392                         tmp = 0; /* 1/2 */
 393         } else if (mode)
 394                 tmp = 2; /* whole */
 395         else if (other_mode)
 396                 tmp = 3; /* 1/4 */
 397
 398         /* second controller of the pair uses second half of the lb */
 399         if (radeon_crtc->crtc_id % 2)
 400                 tmp += 4;
 401         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 402
 403         switch (tmp) {
 404         case 0:
 405         case 4:
 406         default:
 407                 if (ASIC_IS_DCE5(rdev))
 408                         return 4096 * 2;
 409                 else
 410                         return 3840 * 2;
 411         case 1:
 412         case 5:
 413                 if (ASIC_IS_DCE5(rdev))
 414                         return 6144 * 2;
 415                 else
 416                         return 5760 * 2;
 417         case 2:
 418         case 6:
 419                 if (ASIC_IS_DCE5(rdev))
 420                         return 8192 * 2;
 421                 else
 422                         return 7680 * 2;
 423         case 3:
 424         case 7:
 425                 if (ASIC_IS_DCE5(rdev))
 426                         return 2048 * 2;
 427                 else
 428                         return 1920 * 2;
 429         }
 430 }
 431
 432 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 433 {
 434         u32 tmp = RREG32(MC_SHARED_CHMAP);
 435
 436         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 437         case 0:
 438         default:
 439                 return 1;
 440         case 1:
 441                 return 2;
 442         case 2:
 443                 return 4;
 444         case 3:
 445                 return 8;
 446         }
 447 }
 448
 449 struct evergreen_wm_params {
 450         u32 dram_channels; /* number of dram channels */
 451         u32 yclk;          /* bandwidth per dram data pin in kHz */
 452         u32 sclk;          /* engine clock in kHz */
 453         u32 disp_clk;      /* display clock in kHz */
 454         u32 src_width;     /* viewport width */
 455         u32 active_time;   /* active display time in ns */
 456         u32 blank_time;    /* blank time in ns */
 457         bool interlaced;    /* mode is interlaced */
 458         fixed20_12 vsc;    /* vertical scale ratio */
 459         u32 num_heads;     /* number of active crtcs */
 460         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 461         u32 lb_size;       /* line buffer allocated to pipe */
 462         u32 vtaps;         /* vertical scaler taps */
 463 };
 464
 465 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 466 {
 467         /* Calculate DRAM Bandwidth and the part allocated to display. */
 468         fixed20_12 dram_efficiency; /* 0.7 */
 469         fixed20_12 yclk, dram_channels, bandwidth;
 470         fixed20_12 a;
 471
 472         a.full = dfixed_const(1000);
 473         yclk.full = dfixed_const(wm->yclk);
 474         yclk.full = dfixed_div(yclk, a);
 475         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 476         a.full = dfixed_const(10);
 477         dram_efficiency.full = dfixed_const(7);
 478         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 479         bandwidth.full = dfixed_mul(dram_channels, yclk);
 480         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 481
 482         return dfixed_trunc(bandwidth);
 483 }
 484
 485 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 486 {
 487         /* Calculate DRAM Bandwidth and the part allocated to display. */
 488         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 489         fixed20_12 yclk, dram_channels, bandwidth;
 490         fixed20_12 a;
 491
 492         a.full = dfixed_const(1000);
 493         yclk.full = dfixed_const(wm->yclk);
 494         yclk.full = dfixed_div(yclk, a);
 495         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 496         a.full = dfixed_const(10);
 497         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 498         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 499         bandwidth.full = dfixed_mul(dram_channels, yclk);
 500         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 501
 502         return dfixed_trunc(bandwidth);
 503 }
 504
 505 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 506 {
 507         /* Calculate the display Data return Bandwidth */
 508         fixed20_12 return_efficiency; /* 0.8 */
 509         fixed20_12 sclk, bandwidth;
 510         fixed20_12 a;
 511
 512         a.full = dfixed_const(1000);
 513         sclk.full = dfixed_const(wm->sclk);
 514         sclk.full = dfixed_div(sclk, a);
 515         a.full = dfixed_const(10);
 516         return_efficiency.full = dfixed_const(8);
 517         return_efficiency.full = dfixed_div(return_efficiency, a);
 518         a.full = dfixed_const(32);
 519         bandwidth.full = dfixed_mul(a, sclk);
 520         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 521
 522         return dfixed_trunc(bandwidth);
 523 }
 524
 525 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 526 {
 527         /* Calculate the DMIF Request Bandwidth */
 528         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 529         fixed20_12 disp_clk, bandwidth;
 530         fixed20_12 a;
 531
 532         a.full = dfixed_const(1000);
 533         disp_clk.full = dfixed_const(wm->disp_clk);
 534         disp_clk.full = dfixed_div(disp_clk, a);
 535         a.full = dfixed_const(10);
 536         disp_clk_request_efficiency.full = dfixed_const(8);
 537         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 538         a.full = dfixed_const(32);
 539         bandwidth.full = dfixed_mul(a, disp_clk);
 540         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 541
 542         return dfixed_trunc(bandwidth);
 543 }
 544
 545 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 546 {
 547         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 548         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 549         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 550         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 551
 552         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 553 }
 554
 555 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 556 {
 557         /* Calculate the display mode Average Bandwidth
 558          * DisplayMode should contain the source and destination dimensions,
 559          * timing, etc.
 560          */
 561         fixed20_12 bpp;
 562         fixed20_12 line_time;
 563         fixed20_12 src_width;
 564         fixed20_12 bandwidth;
 565         fixed20_12 a;
 566
 567         a.full = dfixed_const(1000);
 568         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 569         line_time.full = dfixed_div(line_time, a);
 570         bpp.full = dfixed_const(wm->bytes_per_pixel);
 571         src_width.full = dfixed_const(wm->src_width);
 572         bandwidth.full = dfixed_mul(src_width, bpp);
 573         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 574         bandwidth.full = dfixed_div(bandwidth, line_time);
 575
 576         return dfixed_trunc(bandwidth);
 577 }
 578
 579 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 580 {
 581         /* First calcualte the latency in ns */
 582         u32 mc_latency = 2000; /* 2000 ns. */
 583         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 584         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 585         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 586         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 587         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 588                 (wm->num_heads * cursor_line_pair_return_time);
 589         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 590         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 591         fixed20_12 a, b, c;
 592
 593         if (wm->num_heads == 0)
 594                 return 0;
 595
 596         a.full = dfixed_const(2);
 597         b.full = dfixed_const(1);
 598         if ((wm->vsc.full > a.full) ||
 599             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 600             (wm->vtaps >= 5) ||
 601             ((wm->vsc.full >= a.full) && wm->interlaced))
 602                 max_src_lines_per_dst_line = 4;
 603         else
 604                 max_src_lines_per_dst_line = 2;
 605
 606         a.full = dfixed_const(available_bandwidth);
 607         b.full = dfixed_const(wm->num_heads);
 608         a.full = dfixed_div(a, b);
 609
 610         b.full = dfixed_const(1000);
 611         c.full = dfixed_const(wm->disp_clk);
 612         b.full = dfixed_div(c, b);
 613         c.full = dfixed_const(wm->bytes_per_pixel);
 614         b.full = dfixed_mul(b, c);
 615
 616         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 617
 618         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 619         b.full = dfixed_const(1000);
 620         c.full = dfixed_const(lb_fill_bw);
 621         b.full = dfixed_div(c, b);
 622         a.full = dfixed_div(a, b);
 623         line_fill_time = dfixed_trunc(a);
 624
 625         if (line_fill_time < wm->active_time)
 626                 return latency;
 627         else
 628                 return latency + (line_fill_time - wm->active_time);
 629
 630 }
 631
 632 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 633 {
 634         if (evergreen_average_bandwidth(wm) <=
 635             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 636                 return true;
 637         else
 638                 return false;
 639 };
 640
 641 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 642 {
 643         if (evergreen_average_bandwidth(wm) <=
 644             (evergreen_available_bandwidth(wm) / wm->num_heads))
 645                 return true;
 646         else
 647                 return false;
 648 };
 649
 650 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 651 {
 652         u32 lb_partitions = wm->lb_size / wm->src_width;
 653         u32 line_time = wm->active_time + wm->blank_time;
 654         u32 latency_tolerant_lines;
 655         u32 latency_hiding;
 656         fixed20_12 a;
 657
 658         a.full = dfixed_const(1);
 659         if (wm->vsc.full > a.full)
 660                 latency_tolerant_lines = 1;
 661         else {
 662                 if (lb_partitions <= (wm->vtaps + 1))
 663                         latency_tolerant_lines = 1;
 664                 else
 665                         latency_tolerant_lines = 2;
 666         }
 667
 668         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 669
 670         if (evergreen_latency_watermark(wm) <= latency_hiding)
 671                 return true;
 672         else
 673                 return false;
 674 }
 675
 676 static void evergreen_program_watermarks(struct radeon_device *rdev,
 677                                          struct radeon_crtc *radeon_crtc,
 678                                          u32 lb_size, u32 num_heads)
 679 {
 680         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 681         struct evergreen_wm_params wm;
 682         u32 pixel_period;
 683         u32 line_time = 0;
 684         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 685         u32 priority_a_mark = 0, priority_b_mark = 0;
 686         u32 priority_a_cnt = PRIORITY_OFF;
 687         u32 priority_b_cnt = PRIORITY_OFF;
 688         u32 pipe_offset = radeon_crtc->crtc_id * 16;
 689         u32 tmp, arb_control3;
 690         fixed20_12 a, b, c;
 691
 692         if (radeon_crtc->base.enabled && num_heads && mode) {
 693                 pixel_period = 1000000 / (u32)mode->clock;
 694                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 695                 priority_a_cnt = 0;
 696                 priority_b_cnt = 0;
 697
 698                 wm.yclk = rdev->pm.current_mclk * 10;
 699                 wm.sclk = rdev->pm.current_sclk * 10;
 700                 wm.disp_clk = mode->clock;
 701                 wm.src_width = mode->crtc_hdisplay;
 702                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 703                 wm.blank_time = line_time - wm.active_time;
 704                 wm.interlaced = false;
 705                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 706                         wm.interlaced = true;
 707                 wm.vsc = radeon_crtc->vsc;
 708                 wm.vtaps = 1;
 709                 if (radeon_crtc->rmx_type != RMX_OFF)
 710                         wm.vtaps = 2;
 711                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 712                 wm.lb_size = lb_size;
 713                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 714                 wm.num_heads = num_heads;
 715
 716                 /* set for high clocks */
 717                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
 718                 /* set for low clocks */
 719                 /* wm.yclk = low clk; wm.sclk = low clk */
 720                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
 721
 722                 /* possibly force display priority to high */
 723                 /* should really do this at mode validation time... */
 724                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 725                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
 726                     !evergreen_check_latency_hiding(&wm) ||
 727                     (rdev->disp_priority == 2)) {
 728                         DRM_INFO("force priority to high\n");
 729                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 730                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 731                 }
 732
 733                 a.full = dfixed_const(1000);
 734                 b.full = dfixed_const(mode->clock);
 735                 b.full = dfixed_div(b, a);
 736                 c.full = dfixed_const(latency_watermark_a);
 737                 c.full = dfixed_mul(c, b);
 738                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 739                 c.full = dfixed_div(c, a);
 740                 a.full = dfixed_const(16);
 741                 c.full = dfixed_div(c, a);
 742                 priority_a_mark = dfixed_trunc(c);
 743                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 744
 745                 a.full = dfixed_const(1000);
 746                 b.full = dfixed_const(mode->clock);
 747                 b.full = dfixed_div(b, a);
 748                 c.full = dfixed_const(latency_watermark_b);
 749                 c.full = dfixed_mul(c, b);
 750                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 751                 c.full = dfixed_div(c, a);
 752                 a.full = dfixed_const(16);
 753                 c.full = dfixed_div(c, a);
 754                 priority_b_mark = dfixed_trunc(c);
 755                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 756         }
 757
 758         /* select wm A */
 759         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 760         tmp = arb_control3;
 761         tmp &= ~LATENCY_WATERMARK_MASK(3);
 762         tmp |= LATENCY_WATERMARK_MASK(1);
 763         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 764         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 765                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
 766                 LATENCY_HIGH_WATERMARK(line_time)));
 767         /* select wm B */
 768         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 769         tmp &= ~LATENCY_WATERMARK_MASK(3);
 770         tmp |= LATENCY_WATERMARK_MASK(2);
 771         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 772         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 773                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
 774                 LATENCY_HIGH_WATERMARK(line_time)));
 775         /* restore original selection */
 776         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
 777
 778         /* write the priority marks */
 779         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
 780         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 781
 782 }
 783
 784 void evergreen_bandwidth_update(struct radeon_device *rdev)
 785 {
 786         struct drm_display_mode *mode0 = NULL;
 787         struct drm_display_mode *mode1 = NULL;
 788         u32 num_heads = 0, lb_size;
 789         int i;
 790
 791         radeon_update_display_priority(rdev);
 792
 793         for (i = 0; i < rdev->num_crtc; i++) {
 794                 if (rdev->mode_info.crtcs[i]->base.enabled)
 795                         num_heads++;
 796         }
 797         for (i = 0; i < rdev->num_crtc; i += 2) {
 798                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
 799                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
 800                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
 801                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
 802                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
 803                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
 804         }
 805 }
 806
 807 static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
 808 {
 809         unsigned i;
 810         u32 tmp;
 811
 812         for (i = 0; i < rdev->usec_timeout; i++) {
 813                 /* read MC_STATUS */
 814                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
 815                 if (!tmp)
 816                         return 0;
 817                 udelay(1);
 818         }
 819         return -1;
 820 }
 821
 822 /*
 823  * GART
 824  */
 825 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
 826 {
 827         unsigned i;
 828         u32 tmp;
 829
 830         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 831
 832         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 833         for (i = 0; i < rdev->usec_timeout; i++) {
 834                 /* read MC_STATUS */
 835                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 836                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 837                 if (tmp == 2) {
 838                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 839                         return;
 840                 }
 841                 if (tmp) {
 842                         return;
 843                 }
 844                 udelay(1);
 845         }
 846 }
 847
 848 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
 849 {
 850         u32 tmp;
 851         int r;
 852
 853         if (rdev->gart.table.vram.robj == NULL) {
 854                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 855                 return -EINVAL;
 856         }
 857         r = radeon_gart_table_vram_pin(rdev);
 858         if (r)
 859                 return r;
 860         radeon_gart_restore(rdev);
 861         /* Setup L2 cache */
 862         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 863                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 864                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 865         WREG32(VM_L2_CNTL2, 0);
 866         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 867         /* Setup TLB control */
 868         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 869                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 870                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 871                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 872         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 873         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 874         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 875         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 876         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 877         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 878         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 879         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 880         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 881         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 882         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 883                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 884         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 885                         (u32)(rdev->dummy_page.addr >> 12));
 886         WREG32(VM_CONTEXT1_CNTL, 0);
 887
 888         evergreen_pcie_gart_tlb_flush(rdev);
 889         rdev->gart.ready = true;
 890         return 0;
 891 }
 892
 893 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
 894 {
 895         u32 tmp;
 896         int r;
 897
 898         /* Disable all tables */
 899         WREG32(VM_CONTEXT0_CNTL, 0);
 900         WREG32(VM_CONTEXT1_CNTL, 0);
 901
 902         /* Setup L2 cache */
 903         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 904                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 905         WREG32(VM_L2_CNTL2, 0);
 906         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 907         /* Setup TLB control */
 908         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 909         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 910         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 911         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 912         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 913         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 914         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 915         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 916         if (rdev->gart.table.vram.robj) {
 917                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 918                 if (likely(r == 0)) {
 919                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 920                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 921                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 922                 }
 923         }
 924 }
 925
 926 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
 927 {
 928         evergreen_pcie_gart_disable(rdev);
 929         radeon_gart_table_vram_free(rdev);
 930         radeon_gart_fini(rdev);
 931 }
 932
 933
 934 void evergreen_agp_enable(struct radeon_device *rdev)
 935 {
 936         u32 tmp;
 937
 938         /* Setup L2 cache */
 939         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 940                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 941                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 942         WREG32(VM_L2_CNTL2, 0);
 943         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 944         /* Setup TLB control */
 945         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 946                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 947                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 948                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 949         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 950         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 951         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 952         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 953         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 954         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 955         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 956         WREG32(VM_CONTEXT0_CNTL, 0);
 957         WREG32(VM_CONTEXT1_CNTL, 0);
 958 }
 959
 960 static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
 961 {
 962         save->vga_control[0] = RREG32(D1VGA_CONTROL);
 963         save->vga_control[1] = RREG32(D2VGA_CONTROL);
 964         save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
 965         save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
 966         save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
 967         save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
 968         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
 969         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
 970         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
 971         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 972         if (!(rdev->flags & RADEON_IS_IGP)) {
 973                 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
 974                 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
 975                 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
 976                 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 977         }
 978
 979         /* Stop all video */
 980         WREG32(VGA_RENDER_CONTROL, 0);
 981         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
 982         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
 983         if (!(rdev->flags & RADEON_IS_IGP)) {
 984                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
 985                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
 986                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
 987                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
 988         }
 989         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 990         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 991         if (!(rdev->flags & RADEON_IS_IGP)) {
 992                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 993                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 994                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
 995                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
 996         }
 997         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 998         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 999         if (!(rdev->flags & RADEON_IS_IGP)) {
1000                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1001                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1002                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1003                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1004         }
1005
1006         WREG32(D1VGA_CONTROL, 0);
1007         WREG32(D2VGA_CONTROL, 0);
1008         WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1009         WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1010         WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1011         WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1012 }
1013
1014 static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1015 {
1016         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1017                upper_32_bits(rdev->mc.vram_start));
1018         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1019                upper_32_bits(rdev->mc.vram_start));
1020         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1021                (u32)rdev->mc.vram_start);
1022         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1023                (u32)rdev->mc.vram_start);
1024
1025         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1026                upper_32_bits(rdev->mc.vram_start));
1027         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1028                upper_32_bits(rdev->mc.vram_start));
1029         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1030                (u32)rdev->mc.vram_start);
1031         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1032                (u32)rdev->mc.vram_start);
1033
1034         if (!(rdev->flags & RADEON_IS_IGP)) {
1035                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1036                        upper_32_bits(rdev->mc.vram_start));
1037                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1038                        upper_32_bits(rdev->mc.vram_start));
1039                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1040                        (u32)rdev->mc.vram_start);
1041                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1042                        (u32)rdev->mc.vram_start);
1043
1044                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1045                        upper_32_bits(rdev->mc.vram_start));
1046                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1047                        upper_32_bits(rdev->mc.vram_start));
1048                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1049                        (u32)rdev->mc.vram_start);
1050                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1051                        (u32)rdev->mc.vram_start);
1052
1053                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1054                        upper_32_bits(rdev->mc.vram_start));
1055                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1056                        upper_32_bits(rdev->mc.vram_start));
1057                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1058                        (u32)rdev->mc.vram_start);
1059                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1060                        (u32)rdev->mc.vram_start);
1061
1062                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1063                        upper_32_bits(rdev->mc.vram_start));
1064                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1065                        upper_32_bits(rdev->mc.vram_start));
1066                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1067                        (u32)rdev->mc.vram_start);
1068                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1069                        (u32)rdev->mc.vram_start);
1070         }
1071
1072         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1073         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1074         /* Unlock host access */
1075         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1076         mdelay(1);
1077         /* Restore video state */
1078         WREG32(D1VGA_CONTROL, save->vga_control[0]);
1079         WREG32(D2VGA_CONTROL, save->vga_control[1]);
1080         WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1081         WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1082         WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1083         WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1084         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1085         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1086         if (!(rdev->flags & RADEON_IS_IGP)) {
1087                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1088                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1089                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1090                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1091         }
1092         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1093         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1094         if (!(rdev->flags & RADEON_IS_IGP)) {
1095                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1096                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1097                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1098                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1099         }
1100         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1101         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1102         if (!(rdev->flags & RADEON_IS_IGP)) {
1103                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1104                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1105                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1106                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1107         }
1108         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1109 }
1110
1111 static void evergreen_mc_program(struct radeon_device *rdev)
1112 {
1113         struct evergreen_mc_save save;
1114         u32 tmp;
1115         int i, j;
1116
1117         /* Initialize HDP */
1118         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1119                 WREG32((0x2c14 + j), 0x00000000);
1120                 WREG32((0x2c18 + j), 0x00000000);
1121                 WREG32((0x2c1c + j), 0x00000000);
1122                 WREG32((0x2c20 + j), 0x00000000);
1123                 WREG32((0x2c24 + j), 0x00000000);
1124         }
1125         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1126
1127         evergreen_mc_stop(rdev, &save);
1128         if (evergreen_mc_wait_for_idle(rdev)) {
1129                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1130         }
1131         /* Lockout access through VGA aperture*/
1132         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1133         /* Update configuration */
1134         if (rdev->flags & RADEON_IS_AGP) {
1135                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1136                         /* VRAM before AGP */
1137                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1138                                 rdev->mc.vram_start >> 12);
1139                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1140                                 rdev->mc.gtt_end >> 12);
1141                 } else {
1142                         /* VRAM after AGP */
1143                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1144                                 rdev->mc.gtt_start >> 12);
1145                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1146                                 rdev->mc.vram_end >> 12);
1147                 }
1148         } else {
1149                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1150                         rdev->mc.vram_start >> 12);
1151                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1152                         rdev->mc.vram_end >> 12);
1153         }
1154         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1155         if (rdev->flags & RADEON_IS_IGP) {
1156                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1157                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1158                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1159                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1160         }
1161         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1162         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1163         WREG32(MC_VM_FB_LOCATION, tmp);
1164         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1165         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1166         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1167         if (rdev->flags & RADEON_IS_AGP) {
1168                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1169                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1170                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1171         } else {
1172                 WREG32(MC_VM_AGP_BASE, 0);
1173                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1174                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1175         }
1176         if (evergreen_mc_wait_for_idle(rdev)) {
1177                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1178         }
1179         evergreen_mc_resume(rdev, &save);
1180         /* we need to own VRAM, so turn off the VGA renderer here
1181          * to stop it overwriting our objects */
1182         rv515_vga_render_disable(rdev);
1183 }
1184
1185 /*
1186  * CP.
1187  */
1188
1189 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1190 {
1191         const __be32 *fw_data;
1192         int i;
1193
1194         if (!rdev->me_fw || !rdev->pfp_fw)
1195                 return -EINVAL;
1196
1197         r700_cp_stop(rdev);
1198         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
1199
1200         fw_data = (const __be32 *)rdev->pfp_fw->data;
1201         WREG32(CP_PFP_UCODE_ADDR, 0);
1202         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1203                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1204         WREG32(CP_PFP_UCODE_ADDR, 0);
1205
1206         fw_data = (const __be32 *)rdev->me_fw->data;
1207         WREG32(CP_ME_RAM_WADDR, 0);
1208         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1209                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1210
1211         WREG32(CP_PFP_UCODE_ADDR, 0);
1212         WREG32(CP_ME_RAM_WADDR, 0);
1213         WREG32(CP_ME_RAM_RADDR, 0);
1214         return 0;
1215 }
1216
1217 static int evergreen_cp_start(struct radeon_device *rdev)
1218 {
1219         int r, i;
1220         uint32_t cp_me;
1221
1222         r = radeon_ring_lock(rdev, 7);
1223         if (r) {
1224                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1225                 return r;
1226         }
1227         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1228         radeon_ring_write(rdev, 0x1);
1229         radeon_ring_write(rdev, 0x0);
1230         radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1231         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1232         radeon_ring_write(rdev, 0);
1233         radeon_ring_write(rdev, 0);
1234         radeon_ring_unlock_commit(rdev);
1235
1236         cp_me = 0xff;
1237         WREG32(CP_ME_CNTL, cp_me);
1238
1239         r = radeon_ring_lock(rdev, evergreen_default_size + 15);
1240         if (r) {
1241                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1242                 return r;
1243         }
1244
1245         /* setup clear context state */
1246         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1247         radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1248
1249         for (i = 0; i < evergreen_default_size; i++)
1250                 radeon_ring_write(rdev, evergreen_default_state[i]);
1251
1252         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1253         radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1254
1255         /* set clear context state */
1256         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1257         radeon_ring_write(rdev, 0);
1258
1259         /* SQ_VTX_BASE_VTX_LOC */
1260         radeon_ring_write(rdev, 0xc0026f00);
1261         radeon_ring_write(rdev, 0x00000000);
1262         radeon_ring_write(rdev, 0x00000000);
1263         radeon_ring_write(rdev, 0x00000000);
1264
1265         /* Clear consts */
1266         radeon_ring_write(rdev, 0xc0036f00);
1267         radeon_ring_write(rdev, 0x00000bc4);
1268         radeon_ring_write(rdev, 0xffffffff);
1269         radeon_ring_write(rdev, 0xffffffff);
1270         radeon_ring_write(rdev, 0xffffffff);
1271
1272         radeon_ring_unlock_commit(rdev);
1273
1274         return 0;
1275 }
1276
1277 int evergreen_cp_resume(struct radeon_device *rdev)
1278 {
1279         u32 tmp;
1280         u32 rb_bufsz;
1281         int r;
1282
1283         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1284         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1285                                  SOFT_RESET_PA |
1286                                  SOFT_RESET_SH |
1287                                  SOFT_RESET_VGT |
1288                                  SOFT_RESET_SX));
1289         RREG32(GRBM_SOFT_RESET);
1290         mdelay(15);
1291         WREG32(GRBM_SOFT_RESET, 0);
1292         RREG32(GRBM_SOFT_RESET);
1293
1294         /* Set ring buffer size */
1295         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1296         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1297 #ifdef __BIG_ENDIAN
1298         tmp |= BUF_SWAP_32BIT;
1299 #endif
1300         WREG32(CP_RB_CNTL, tmp);
1301         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1302
1303         /* Set the write pointer delay */
1304         WREG32(CP_RB_WPTR_DELAY, 0);
1305
1306         /* Initialize the ring buffer's read and write pointers */
1307         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1308         WREG32(CP_RB_RPTR_WR, 0);
1309         WREG32(CP_RB_WPTR, 0);
1310
1311         /* set the wb address wether it's enabled or not */
1312         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1313         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1314         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1315
1316         if (rdev->wb.enabled)
1317                 WREG32(SCRATCH_UMSK, 0xff);
1318         else {
1319                 tmp |= RB_NO_UPDATE;
1320                 WREG32(SCRATCH_UMSK, 0);
1321         }
1322
1323         mdelay(1);
1324         WREG32(CP_RB_CNTL, tmp);
1325
1326         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1327         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1328
1329         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1330         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1331
1332         evergreen_cp_start(rdev);
1333         rdev->cp.ready = true;
1334         r = radeon_ring_test(rdev);
1335         if (r) {
1336                 rdev->cp.ready = false;
1337                 return r;
1338         }
1339         return 0;
1340 }
1341
1342 /*
1343  * Core functions
1344  */
1345 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1346                                                   u32 num_tile_pipes,
1347                                                   u32 num_backends,
1348                                                   u32 backend_disable_mask)
1349 {
1350         u32 backend_map = 0;
1351         u32 enabled_backends_mask = 0;
1352         u32 enabled_backends_count = 0;
1353         u32 cur_pipe;
1354         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1355         u32 cur_backend = 0;
1356         u32 i;
1357         bool force_no_swizzle;
1358
1359         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1360                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1361         if (num_tile_pipes < 1)
1362                 num_tile_pipes = 1;
1363         if (num_backends > EVERGREEN_MAX_BACKENDS)
1364                 num_backends = EVERGREEN_MAX_BACKENDS;
1365         if (num_backends < 1)
1366                 num_backends = 1;
1367
1368         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1369                 if (((backend_disable_mask >> i) & 1) == 0) {
1370                         enabled_backends_mask |= (1 << i);
1371                         ++enabled_backends_count;
1372                 }
1373                 if (enabled_backends_count == num_backends)
1374                         break;
1375         }
1376
1377         if (enabled_backends_count == 0) {
1378                 enabled_backends_mask = 1;
1379                 enabled_backends_count = 1;
1380         }
1381
1382         if (enabled_backends_count != num_backends)
1383                 num_backends = enabled_backends_count;
1384
1385         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1386         switch (rdev->family) {
1387         case CHIP_CEDAR:
1388         case CHIP_REDWOOD:
1389         case CHIP_PALM:
1390         case CHIP_TURKS:
1391         case CHIP_CAICOS:
1392                 force_no_swizzle = false;
1393                 break;
1394         case CHIP_CYPRESS:
1395         case CHIP_HEMLOCK:
1396         case CHIP_JUNIPER:
1397         case CHIP_BARTS:
1398         default:
1399                 force_no_swizzle = true;
1400                 break;
1401         }
1402         if (force_no_swizzle) {
1403                 bool last_backend_enabled = false;
1404
1405                 force_no_swizzle = false;
1406                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1407                         if (((enabled_backends_mask >> i) & 1) == 1) {
1408                                 if (last_backend_enabled)
1409                                         force_no_swizzle = true;
1410                                 last_backend_enabled = true;
1411                         } else
1412                                 last_backend_enabled = false;
1413                 }
1414         }
1415
1416         switch (num_tile_pipes) {
1417         case 1:
1418         case 3:
1419         case 5:
1420         case 7:
1421                 DRM_ERROR("odd number of pipes!\n");
1422                 break;
1423         case 2:
1424                 swizzle_pipe[0] = 0;
1425                 swizzle_pipe[1] = 1;
1426                 break;
1427         case 4:
1428                 if (force_no_swizzle) {
1429                         swizzle_pipe[0] = 0;
1430                         swizzle_pipe[1] = 1;
1431                         swizzle_pipe[2] = 2;
1432                         swizzle_pipe[3] = 3;
1433                 } else {
1434                         swizzle_pipe[0] = 0;
1435                         swizzle_pipe[1] = 2;
1436                         swizzle_pipe[2] = 1;
1437                         swizzle_pipe[3] = 3;
1438                 }
1439                 break;
1440         case 6:
1441                 if (force_no_swizzle) {
1442                         swizzle_pipe[0] = 0;
1443                         swizzle_pipe[1] = 1;
1444                         swizzle_pipe[2] = 2;
1445                         swizzle_pipe[3] = 3;
1446                         swizzle_pipe[4] = 4;
1447                         swizzle_pipe[5] = 5;
1448                 } else {
1449                         swizzle_pipe[0] = 0;
1450                         swizzle_pipe[1] = 2;
1451                         swizzle_pipe[2] = 4;
1452                         swizzle_pipe[3] = 1;
1453                         swizzle_pipe[4] = 3;
1454                         swizzle_pipe[5] = 5;
1455                 }
1456                 break;
1457         case 8:
1458                 if (force_no_swizzle) {
1459                         swizzle_pipe[0] = 0;
1460                         swizzle_pipe[1] = 1;
1461                         swizzle_pipe[2] = 2;
1462                         swizzle_pipe[3] = 3;
1463                         swizzle_pipe[4] = 4;
1464                         swizzle_pipe[5] = 5;
1465                         swizzle_pipe[6] = 6;
1466                         swizzle_pipe[7] = 7;
1467                 } else {
1468                         swizzle_pipe[0] = 0;
1469                         swizzle_pipe[1] = 2;
1470                         swizzle_pipe[2] = 4;
1471                         swizzle_pipe[3] = 6;
1472                         swizzle_pipe[4] = 1;
1473                         swizzle_pipe[5] = 3;
1474                         swizzle_pipe[6] = 5;
1475                         swizzle_pipe[7] = 7;
1476                 }
1477                 break;
1478         }
1479
1480         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1481                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1482                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1483
1484                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1485
1486                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1487         }
1488
1489         return backend_map;
1490 }
1491
1492 static void evergreen_program_channel_remap(struct radeon_device *rdev)
1493 {
1494         u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1495
1496         tmp = RREG32(MC_SHARED_CHMAP);
1497         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1498         case 0:
1499         case 1:
1500         case 2:
1501         case 3:
1502         default:
1503                 /* default mapping */
1504                 mc_shared_chremap = 0x00fac688;
1505                 break;
1506         }
1507
1508         switch (rdev->family) {
1509         case CHIP_HEMLOCK:
1510         case CHIP_CYPRESS:
1511         case CHIP_BARTS:
1512                 tcp_chan_steer_lo = 0x54763210;
1513                 tcp_chan_steer_hi = 0x0000ba98;
1514                 break;
1515         case CHIP_JUNIPER:
1516         case CHIP_REDWOOD:
1517         case CHIP_CEDAR:
1518         case CHIP_PALM:
1519         case CHIP_TURKS:
1520         case CHIP_CAICOS:
1521         default:
1522                 tcp_chan_steer_lo = 0x76543210;
1523                 tcp_chan_steer_hi = 0x0000ba98;
1524                 break;
1525         }
1526
1527         WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1528         WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1529         WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1530 }
1531
1532 static void evergreen_gpu_init(struct radeon_device *rdev)
1533 {
1534         u32 cc_rb_backend_disable = 0;
1535         u32 cc_gc_shader_pipe_config;
1536         u32 gb_addr_config = 0;
1537         u32 mc_shared_chmap, mc_arb_ramcfg;
1538         u32 gb_backend_map;
1539         u32 grbm_gfx_index;
1540         u32 sx_debug_1;
1541         u32 smx_dc_ctl0;
1542         u32 sq_config;
1543         u32 sq_lds_resource_mgmt;
1544         u32 sq_gpr_resource_mgmt_1;
1545         u32 sq_gpr_resource_mgmt_2;
1546         u32 sq_gpr_resource_mgmt_3;
1547         u32 sq_thread_resource_mgmt;
1548         u32 sq_thread_resource_mgmt_2;
1549         u32 sq_stack_resource_mgmt_1;
1550         u32 sq_stack_resource_mgmt_2;
1551         u32 sq_stack_resource_mgmt_3;
1552         u32 vgt_cache_invalidation;
1553         u32 hdp_host_path_cntl;
1554         int i, j, num_shader_engines, ps_thread_count;
1555
1556         switch (rdev->family) {
1557         case CHIP_CYPRESS:
1558         case CHIP_HEMLOCK:
1559                 rdev->config.evergreen.num_ses = 2;
1560                 rdev->config.evergreen.max_pipes = 4;
1561                 rdev->config.evergreen.max_tile_pipes = 8;
1562                 rdev->config.evergreen.max_simds = 10;
1563                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1564                 rdev->config.evergreen.max_gprs = 256;
1565                 rdev->config.evergreen.max_threads = 248;
1566                 rdev->config.evergreen.max_gs_threads = 32;
1567                 rdev->config.evergreen.max_stack_entries = 512;
1568                 rdev->config.evergreen.sx_num_of_sets = 4;
1569                 rdev->config.evergreen.sx_max_export_size = 256;
1570                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1571                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1572                 rdev->config.evergreen.max_hw_contexts = 8;
1573                 rdev->config.evergreen.sq_num_cf_insts = 2;
1574
1575                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1576                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1577                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1578                 break;
1579         case CHIP_JUNIPER:
1580                 rdev->config.evergreen.num_ses = 1;
1581                 rdev->config.evergreen.max_pipes = 4;
1582                 rdev->config.evergreen.max_tile_pipes = 4;
1583                 rdev->config.evergreen.max_simds = 10;
1584                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1585                 rdev->config.evergreen.max_gprs = 256;
1586                 rdev->config.evergreen.max_threads = 248;
1587                 rdev->config.evergreen.max_gs_threads = 32;
1588                 rdev->config.evergreen.max_stack_entries = 512;
1589                 rdev->config.evergreen.sx_num_of_sets = 4;
1590                 rdev->config.evergreen.sx_max_export_size = 256;
1591                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1592                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1593                 rdev->config.evergreen.max_hw_contexts = 8;
1594                 rdev->config.evergreen.sq_num_cf_insts = 2;
1595
1596                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1597                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1598                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1599                 break;
1600         case CHIP_REDWOOD:
1601                 rdev->config.evergreen.num_ses = 1;
1602                 rdev->config.evergreen.max_pipes = 4;
1603                 rdev->config.evergreen.max_tile_pipes = 4;
1604                 rdev->config.evergreen.max_simds = 5;
1605                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1606                 rdev->config.evergreen.max_gprs = 256;
1607                 rdev->config.evergreen.max_threads = 248;
1608                 rdev->config.evergreen.max_gs_threads = 32;
1609                 rdev->config.evergreen.max_stack_entries = 256;
1610                 rdev->config.evergreen.sx_num_of_sets = 4;
1611                 rdev->config.evergreen.sx_max_export_size = 256;
1612                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1613                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1614                 rdev->config.evergreen.max_hw_contexts = 8;
1615                 rdev->config.evergreen.sq_num_cf_insts = 2;
1616
1617                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1618                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1619                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1620                 break;
1621         case CHIP_CEDAR:
1622         default:
1623                 rdev->config.evergreen.num_ses = 1;
1624                 rdev->config.evergreen.max_pipes = 2;
1625                 rdev->config.evergreen.max_tile_pipes = 2;
1626                 rdev->config.evergreen.max_simds = 2;
1627                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1628                 rdev->config.evergreen.max_gprs = 256;
1629                 rdev->config.evergreen.max_threads = 192;
1630                 rdev->config.evergreen.max_gs_threads = 16;
1631                 rdev->config.evergreen.max_stack_entries = 256;
1632                 rdev->config.evergreen.sx_num_of_sets = 4;
1633                 rdev->config.evergreen.sx_max_export_size = 128;
1634                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1635                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1636                 rdev->config.evergreen.max_hw_contexts = 4;
1637                 rdev->config.evergreen.sq_num_cf_insts = 1;
1638
1639                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1640                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1641                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1642                 break;
1643         case CHIP_PALM:
1644                 rdev->config.evergreen.num_ses = 1;
1645                 rdev->config.evergreen.max_pipes = 2;
1646                 rdev->config.evergreen.max_tile_pipes = 2;
1647                 rdev->config.evergreen.max_simds = 2;
1648                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1649                 rdev->config.evergreen.max_gprs = 256;
1650                 rdev->config.evergreen.max_threads = 192;
1651                 rdev->config.evergreen.max_gs_threads = 16;
1652                 rdev->config.evergreen.max_stack_entries = 256;
1653                 rdev->config.evergreen.sx_num_of_sets = 4;
1654                 rdev->config.evergreen.sx_max_export_size = 128;
1655                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1656                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1657                 rdev->config.evergreen.max_hw_contexts = 4;
1658                 rdev->config.evergreen.sq_num_cf_insts = 1;
1659
1660                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1661                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1662                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1663                 break;
1664         case CHIP_BARTS:
1665                 rdev->config.evergreen.num_ses = 2;
1666                 rdev->config.evergreen.max_pipes = 4;
1667                 rdev->config.evergreen.max_tile_pipes = 8;
1668                 rdev->config.evergreen.max_simds = 7;
1669                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1670                 rdev->config.evergreen.max_gprs = 256;
1671                 rdev->config.evergreen.max_threads = 248;
1672                 rdev->config.evergreen.max_gs_threads = 32;
1673                 rdev->config.evergreen.max_stack_entries = 512;
1674                 rdev->config.evergreen.sx_num_of_sets = 4;
1675                 rdev->config.evergreen.sx_max_export_size = 256;
1676                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1677                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1678                 rdev->config.evergreen.max_hw_contexts = 8;
1679                 rdev->config.evergreen.sq_num_cf_insts = 2;
1680
1681                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1682                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1683                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1684                 break;
1685         case CHIP_TURKS:
1686                 rdev->config.evergreen.num_ses = 1;
1687                 rdev->config.evergreen.max_pipes = 4;
1688                 rdev->config.evergreen.max_tile_pipes = 4;
1689                 rdev->config.evergreen.max_simds = 6;
1690                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1691                 rdev->config.evergreen.max_gprs = 256;
1692                 rdev->config.evergreen.max_threads = 248;
1693                 rdev->config.evergreen.max_gs_threads = 32;
1694                 rdev->config.evergreen.max_stack_entries = 256;
1695                 rdev->config.evergreen.sx_num_of_sets = 4;
1696                 rdev->config.evergreen.sx_max_export_size = 256;
1697                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1698                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1699                 rdev->config.evergreen.max_hw_contexts = 8;
1700                 rdev->config.evergreen.sq_num_cf_insts = 2;
1701
1702                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1703                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1704                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1705                 break;
1706         case CHIP_CAICOS:
1707                 rdev->config.evergreen.num_ses = 1;
1708                 rdev->config.evergreen.max_pipes = 4;
1709                 rdev->config.evergreen.max_tile_pipes = 2;
1710                 rdev->config.evergreen.max_simds = 2;
1711                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1712                 rdev->config.evergreen.max_gprs = 256;
1713                 rdev->config.evergreen.max_threads = 192;
1714                 rdev->config.evergreen.max_gs_threads = 16;
1715                 rdev->config.evergreen.max_stack_entries = 256;
1716                 rdev->config.evergreen.sx_num_of_sets = 4;
1717                 rdev->config.evergreen.sx_max_export_size = 128;
1718                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1719                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1720                 rdev->config.evergreen.max_hw_contexts = 4;
1721                 rdev->config.evergreen.sq_num_cf_insts = 1;
1722
1723                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1724                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1725                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1726                 break;
1727         }
1728
1729         /* Initialize HDP */
1730         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1731                 WREG32((0x2c14 + j), 0x00000000);
1732                 WREG32((0x2c18 + j), 0x00000000);
1733                 WREG32((0x2c1c + j), 0x00000000);
1734                 WREG32((0x2c20 + j), 0x00000000);
1735                 WREG32((0x2c24 + j), 0x00000000);
1736         }
1737
1738         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1739
1740         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1741
1742         cc_gc_shader_pipe_config |=
1743                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1744                                   & EVERGREEN_MAX_PIPES_MASK);
1745         cc_gc_shader_pipe_config |=
1746                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1747                                & EVERGREEN_MAX_SIMDS_MASK);
1748
1749         cc_rb_backend_disable =
1750                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1751                                 & EVERGREEN_MAX_BACKENDS_MASK);
1752
1753
1754         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1755         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1756
1757         switch (rdev->config.evergreen.max_tile_pipes) {
1758         case 1:
1759         default:
1760                 gb_addr_config |= NUM_PIPES(0);
1761                 break;
1762         case 2:
1763                 gb_addr_config |= NUM_PIPES(1);
1764                 break;
1765         case 4:
1766                 gb_addr_config |= NUM_PIPES(2);
1767                 break;
1768         case 8:
1769                 gb_addr_config |= NUM_PIPES(3);
1770                 break;
1771         }
1772
1773         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1774         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1775         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1776         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1777         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1778         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1779
1780         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1781                 gb_addr_config |= ROW_SIZE(2);
1782         else
1783                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1784
1785         if (rdev->ddev->pdev->device == 0x689e) {
1786                 u32 efuse_straps_4;
1787                 u32 efuse_straps_3;
1788                 u8 efuse_box_bit_131_124;
1789
1790                 WREG32(RCU_IND_INDEX, 0x204);
1791                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1792                 WREG32(RCU_IND_INDEX, 0x203);
1793                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1794                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1795
1796                 switch(efuse_box_bit_131_124) {
1797                 case 0x00:
1798                         gb_backend_map = 0x76543210;
1799                         break;
1800                 case 0x55:
1801                         gb_backend_map = 0x77553311;
1802                         break;
1803                 case 0x56:
1804                         gb_backend_map = 0x77553300;
1805                         break;
1806                 case 0x59:
1807                         gb_backend_map = 0x77552211;
1808                         break;
1809                 case 0x66:
1810                         gb_backend_map = 0x77443300;
1811                         break;
1812                 case 0x99:
1813                         gb_backend_map = 0x66552211;
1814                         break;
1815                 case 0x5a:
1816                         gb_backend_map = 0x77552200;
1817                         break;
1818                 case 0xaa:
1819                         gb_backend_map = 0x66442200;
1820                         break;
1821                 case 0x95:
1822                         gb_backend_map = 0x66553311;
1823                         break;
1824                 default:
1825                         DRM_ERROR("bad backend map, using default\n");
1826                         gb_backend_map =
1827                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1828                                                                        rdev->config.evergreen.max_tile_pipes,
1829                                                                        rdev->config.evergreen.max_backends,
1830                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1831                                                                    rdev->config.evergreen.max_backends) &
1832                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1833                         break;
1834                 }
1835         } else if (rdev->ddev->pdev->device == 0x68b9) {
1836                 u32 efuse_straps_3;
1837                 u8 efuse_box_bit_127_124;
1838
1839                 WREG32(RCU_IND_INDEX, 0x203);
1840                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1841                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1842
1843                 switch(efuse_box_bit_127_124) {
1844                 case 0x0:
1845                         gb_backend_map = 0x00003210;
1846                         break;
1847                 case 0x5:
1848                 case 0x6:
1849                 case 0x9:
1850                 case 0xa:
1851                         gb_backend_map = 0x00003311;
1852                         break;
1853                 default:
1854                         DRM_ERROR("bad backend map, using default\n");
1855                         gb_backend_map =
1856                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1857                                                                        rdev->config.evergreen.max_tile_pipes,
1858                                                                        rdev->config.evergreen.max_backends,
1859                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1860                                                                    rdev->config.evergreen.max_backends) &
1861                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1862                         break;
1863                 }
1864         } else {
1865                 switch (rdev->family) {
1866                 case CHIP_CYPRESS:
1867                 case CHIP_HEMLOCK:
1868                 case CHIP_BARTS:
1869                         gb_backend_map = 0x66442200;
1870                         break;
1871                 case CHIP_JUNIPER:
1872                         gb_backend_map = 0x00006420;
1873                         break;
1874                 default:
1875                         gb_backend_map =
1876                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1877                                                                        rdev->config.evergreen.max_tile_pipes,
1878                                                                        rdev->config.evergreen.max_backends,
1879                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1880                                                                          rdev->config.evergreen.max_backends) &
1881                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1882                 }
1883         }
1884
1885         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1886          * not have bank info, so create a custom tiling dword.
1887          * bits 3:0   num_pipes
1888          * bits 7:4   num_banks
1889          * bits 11:8  group_size
1890          * bits 15:12 row_size
1891          */
1892         rdev->config.evergreen.tile_config = 0;
1893         switch (rdev->config.evergreen.max_tile_pipes) {
1894         case 1:
1895         default:
1896                 rdev->config.evergreen.tile_config |= (0 << 0);
1897                 break;
1898         case 2:
1899                 rdev->config.evergreen.tile_config |= (1 << 0);
1900                 break;
1901         case 4:
1902                 rdev->config.evergreen.tile_config |= (2 << 0);
1903                 break;
1904         case 8:
1905                 rdev->config.evergreen.tile_config |= (3 << 0);
1906                 break;
1907         }
1908         rdev->config.evergreen.tile_config |=
1909                 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1910         rdev->config.evergreen.tile_config |=
1911                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1912         rdev->config.evergreen.tile_config |=
1913                 ((gb_addr_config & 0x30000000) >> 28) << 12;
1914
1915         WREG32(GB_BACKEND_MAP, gb_backend_map);
1916         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1917         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1918         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1919
1920         evergreen_program_channel_remap(rdev);
1921
1922         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1923         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1924
1925         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1926                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1927                 u32 sp = cc_gc_shader_pipe_config;
1928                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1929
1930                 if (i == num_shader_engines) {
1931                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1932                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1933                 }
1934
1935                 WREG32(GRBM_GFX_INDEX, gfx);
1936                 WREG32(RLC_GFX_INDEX, gfx);
1937
1938                 WREG32(CC_RB_BACKEND_DISABLE, rb);
1939                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1940                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1941                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1942         }
1943
1944         grbm_gfx_index |= SE_BROADCAST_WRITES;
1945         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1946         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1947
1948         WREG32(CGTS_SYS_TCC_DISABLE, 0);
1949         WREG32(CGTS_TCC_DISABLE, 0);
1950         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1951         WREG32(CGTS_USER_TCC_DISABLE, 0);
1952
1953         /* set HW defaults for 3D engine */
1954         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1955                                      ROQ_IB2_START(0x2b)));
1956
1957         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1958
1959         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1960                              SYNC_GRADIENT |
1961                              SYNC_WALKER |
1962                              SYNC_ALIGNER));
1963
1964         sx_debug_1 = RREG32(SX_DEBUG_1);
1965         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1966         WREG32(SX_DEBUG_1, sx_debug_1);
1967
1968
1969         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1970         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1971         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1972         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1973
1974         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1975                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1976                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1977
1978         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1979                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1980                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1981
1982         WREG32(VGT_NUM_INSTANCES, 1);
1983         WREG32(SPI_CONFIG_CNTL, 0);
1984         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1985         WREG32(CP_PERFMON_CNTL, 0);
1986
1987         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1988                                   FETCH_FIFO_HIWATER(0x4) |
1989                                   DONE_FIFO_HIWATER(0xe0) |
1990                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
1991
1992         sq_config = RREG32(SQ_CONFIG);
1993         sq_config &= ~(PS_PRIO(3) |
1994                        VS_PRIO(3) |
1995                        GS_PRIO(3) |
1996                        ES_PRIO(3));
1997         sq_config |= (VC_ENABLE |
1998                       EXPORT_SRC_C |
1999                       PS_PRIO(0) |
2000                       VS_PRIO(1) |
2001                       GS_PRIO(2) |
2002                       ES_PRIO(3));
2003
2004         switch (rdev->family) {
2005         case CHIP_CEDAR:
2006         case CHIP_PALM:
2007         case CHIP_CAICOS:
2008                 /* no vertex cache */
2009                 sq_config &= ~VC_ENABLE;
2010                 break;
2011         default:
2012                 break;
2013         }
2014
2015         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2016
2017         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2018         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2019         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2020         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2021         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2022         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2023         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2024
2025         switch (rdev->family) {
2026         case CHIP_CEDAR:
2027         case CHIP_PALM:
2028                 ps_thread_count = 96;
2029                 break;
2030         default:
2031                 ps_thread_count = 128;
2032                 break;
2033         }
2034
2035         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2036         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2037         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2038         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2039         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2040         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2041
2042         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2043         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2044         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2045         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2046         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2047         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2048
2049         WREG32(SQ_CONFIG, sq_config);
2050         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2051         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2052         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2053         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2054         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2055         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2056         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2057         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2058         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2059         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2060
2061         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2062                                           FORCE_EOV_MAX_REZ_CNT(255)));
2063
2064         switch (rdev->family) {
2065         case CHIP_CEDAR:
2066         case CHIP_PALM:
2067         case CHIP_CAICOS:
2068                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2069                 break;
2070         default:
2071                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2072                 break;
2073         }
2074         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2075         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2076
2077         WREG32(VGT_GS_VERTEX_REUSE, 16);
2078         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2079
2080         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2081         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2082
2083         WREG32(CB_PERF_CTR0_SEL_0, 0);
2084         WREG32(CB_PERF_CTR0_SEL_1, 0);
2085         WREG32(CB_PERF_CTR1_SEL_0, 0);
2086         WREG32(CB_PERF_CTR1_SEL_1, 0);
2087         WREG32(CB_PERF_CTR2_SEL_0, 0);
2088         WREG32(CB_PERF_CTR2_SEL_1, 0);
2089         WREG32(CB_PERF_CTR3_SEL_0, 0);
2090         WREG32(CB_PERF_CTR3_SEL_1, 0);
2091
2092         /* clear render buffer base addresses */
2093         WREG32(CB_COLOR0_BASE, 0);
2094         WREG32(CB_COLOR1_BASE, 0);
2095         WREG32(CB_COLOR2_BASE, 0);
2096         WREG32(CB_COLOR3_BASE, 0);
2097         WREG32(CB_COLOR4_BASE, 0);
2098         WREG32(CB_COLOR5_BASE, 0);
2099         WREG32(CB_COLOR6_BASE, 0);
2100         WREG32(CB_COLOR7_BASE, 0);
2101         WREG32(CB_COLOR8_BASE, 0);
2102         WREG32(CB_COLOR9_BASE, 0);
2103         WREG32(CB_COLOR10_BASE, 0);
2104         WREG32(CB_COLOR11_BASE, 0);
2105
2106         /* set the shader const cache sizes to 0 */
2107         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2108                 WREG32(i, 0);
2109         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2110                 WREG32(i, 0);
2111
2112         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2113         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2114
2115         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2116
2117         udelay(50);
2118
2119 }
2120
2121 int evergreen_mc_init(struct radeon_device *rdev)
2122 {
2123         u32 tmp;
2124         int chansize, numchan;
2125
2126         /* Get VRAM informations */
2127         rdev->mc.vram_is_ddr = true;
2128         tmp = RREG32(MC_ARB_RAMCFG);
2129         if (tmp & CHANSIZE_OVERRIDE) {
2130                 chansize = 16;
2131         } else if (tmp & CHANSIZE_MASK) {
2132                 chansize = 64;
2133         } else {
2134                 chansize = 32;
2135         }
2136         tmp = RREG32(MC_SHARED_CHMAP);
2137         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2138         case 0:
2139         default:
2140                 numchan = 1;
2141                 break;
2142         case 1:
2143                 numchan = 2;
2144                 break;
2145         case 2:
2146                 numchan = 4;
2147                 break;
2148         case 3:
2149                 numchan = 8;
2150                 break;
2151         }
2152         rdev->mc.vram_width = numchan * chansize;
2153         /* Could aper size report 0 ? */
2154         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2155         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2156         /* Setup GPU memory space */
2157         if (rdev->flags & RADEON_IS_IGP) {
2158                 /* size in bytes on fusion */
2159                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2160                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2161         } else {
2162                 /* size in MB on evergreen */
2163                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2164                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2165         }
2166         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2167         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2168         r700_vram_gtt_location(rdev, &rdev->mc);
2169         radeon_update_bandwidth_info(rdev);
2170
2171         return 0;
2172 }
2173
2174 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2175 {
2176         u32 srbm_status;
2177         u32 grbm_status;
2178         u32 grbm_status_se0, grbm_status_se1;
2179         struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2180         int r;
2181
2182         srbm_status = RREG32(SRBM_STATUS);
2183         grbm_status = RREG32(GRBM_STATUS);
2184         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2185         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2186         if (!(grbm_status & GUI_ACTIVE)) {
2187                 r100_gpu_lockup_update(lockup, &rdev->cp);
2188                 return false;
2189         }
2190         /* force CP activities */
2191         r = radeon_ring_lock(rdev, 2);
2192         if (!r) {
2193                 /* PACKET2 NOP */
2194                 radeon_ring_write(rdev, 0x80000000);
2195                 radeon_ring_write(rdev, 0x80000000);
2196                 radeon_ring_unlock_commit(rdev);
2197         }
2198         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2199         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2200 }
2201
2202 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2203 {
2204         struct evergreen_mc_save save;
2205         u32 grbm_reset = 0;
2206
2207         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2208                 return 0;
2209
2210         dev_info(rdev->dev, "GPU softreset \n");
2211         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2212                 RREG32(GRBM_STATUS));
2213         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2214                 RREG32(GRBM_STATUS_SE0));
2215         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2216                 RREG32(GRBM_STATUS_SE1));
2217         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2218                 RREG32(SRBM_STATUS));
2219         evergreen_mc_stop(rdev, &save);
2220         if (evergreen_mc_wait_for_idle(rdev)) {
2221                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2222         }
2223         /* Disable CP parsing/prefetching */
2224         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2225
2226         /* reset all the gfx blocks */
2227         grbm_reset = (SOFT_RESET_CP |
2228                       SOFT_RESET_CB |
2229                       SOFT_RESET_DB |
2230                       SOFT_RESET_PA |
2231                       SOFT_RESET_SC |
2232                       SOFT_RESET_SPI |
2233                       SOFT_RESET_SH |
2234                       SOFT_RESET_SX |
2235                       SOFT_RESET_TC |
2236                       SOFT_RESET_TA |
2237                       SOFT_RESET_VC |
2238                       SOFT_RESET_VGT);
2239
2240         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2241         WREG32(GRBM_SOFT_RESET, grbm_reset);
2242         (void)RREG32(GRBM_SOFT_RESET);
2243         udelay(50);
2244         WREG32(GRBM_SOFT_RESET, 0);
2245         (void)RREG32(GRBM_SOFT_RESET);
2246         /* Wait a little for things to settle down */
2247         udelay(50);
2248         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2249                 RREG32(GRBM_STATUS));
2250         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2251                 RREG32(GRBM_STATUS_SE0));
2252         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2253                 RREG32(GRBM_STATUS_SE1));
2254         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2255                 RREG32(SRBM_STATUS));
2256         evergreen_mc_resume(rdev, &save);
2257         return 0;
2258 }
2259
2260 int evergreen_asic_reset(struct radeon_device *rdev)
2261 {
2262         return evergreen_gpu_soft_reset(rdev);
2263 }
2264
2265 /* Interrupts */
2266
2267 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2268 {
2269         switch (crtc) {
2270         case 0:
2271                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2272         case 1:
2273                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2274         case 2:
2275                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2276         case 3:
2277                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2278         case 4:
2279                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2280         case 5:
2281                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2282         default:
2283                 return 0;
2284         }
2285 }
2286
2287 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2288 {
2289         u32 tmp;
2290
2291         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2292         WREG32(GRBM_INT_CNTL, 0);
2293         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2294         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2295         if (!(rdev->flags & RADEON_IS_IGP)) {
2296                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2297                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2298                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2299                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2300         }
2301
2302         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2303         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2304         if (!(rdev->flags & RADEON_IS_IGP)) {
2305                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2306                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2307                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2308                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2309         }
2310
2311         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2312         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2313
2314         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2315         WREG32(DC_HPD1_INT_CONTROL, tmp);
2316         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2317         WREG32(DC_HPD2_INT_CONTROL, tmp);
2318         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2319         WREG32(DC_HPD3_INT_CONTROL, tmp);
2320         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2321         WREG32(DC_HPD4_INT_CONTROL, tmp);
2322         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2323         WREG32(DC_HPD5_INT_CONTROL, tmp);
2324         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2325         WREG32(DC_HPD6_INT_CONTROL, tmp);
2326
2327 }
2328
2329 int evergreen_irq_set(struct radeon_device *rdev)
2330 {
2331         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2332         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2333         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2334         u32 grbm_int_cntl = 0;
2335         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2336
2337         if (!rdev->irq.installed) {
2338                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2339                 return -EINVAL;
2340         }
2341         /* don't enable anything if the ih is disabled */
2342         if (!rdev->ih.enabled) {
2343                 r600_disable_interrupts(rdev);
2344                 /* force the active interrupt state to all disabled */
2345                 evergreen_disable_interrupt_state(rdev);
2346                 return 0;
2347         }
2348
2349         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2350         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2351         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2352         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2353         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2354         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2355
2356         if (rdev->irq.sw_int) {
2357                 DRM_DEBUG("evergreen_irq_set: sw int\n");
2358                 cp_int_cntl |= RB_INT_ENABLE;
2359                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2360         }
2361         if (rdev->irq.crtc_vblank_int[0] ||
2362             rdev->irq.pflip[0]) {
2363                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2364                 crtc1 |= VBLANK_INT_MASK;
2365         }
2366         if (rdev->irq.crtc_vblank_int[1] ||
2367             rdev->irq.pflip[1]) {
2368                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2369                 crtc2 |= VBLANK_INT_MASK;
2370         }
2371         if (rdev->irq.crtc_vblank_int[2] ||
2372             rdev->irq.pflip[2]) {
2373                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2374                 crtc3 |= VBLANK_INT_MASK;
2375         }
2376         if (rdev->irq.crtc_vblank_int[3] ||
2377             rdev->irq.pflip[3]) {
2378                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2379                 crtc4 |= VBLANK_INT_MASK;
2380         }
2381         if (rdev->irq.crtc_vblank_int[4] ||
2382             rdev->irq.pflip[4]) {
2383                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2384                 crtc5 |= VBLANK_INT_MASK;
2385         }
2386         if (rdev->irq.crtc_vblank_int[5] ||
2387             rdev->irq.pflip[5]) {
2388                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2389                 crtc6 |= VBLANK_INT_MASK;
2390         }
2391         if (rdev->irq.hpd[0]) {
2392                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2393                 hpd1 |= DC_HPDx_INT_EN;
2394         }
2395         if (rdev->irq.hpd[1]) {
2396                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2397                 hpd2 |= DC_HPDx_INT_EN;
2398         }
2399         if (rdev->irq.hpd[2]) {
2400                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2401                 hpd3 |= DC_HPDx_INT_EN;
2402         }
2403         if (rdev->irq.hpd[3]) {
2404                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2405                 hpd4 |= DC_HPDx_INT_EN;
2406         }
2407         if (rdev->irq.hpd[4]) {
2408                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2409                 hpd5 |= DC_HPDx_INT_EN;
2410         }
2411         if (rdev->irq.hpd[5]) {
2412                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2413                 hpd6 |= DC_HPDx_INT_EN;
2414         }
2415         if (rdev->irq.gui_idle) {
2416                 DRM_DEBUG("gui idle\n");
2417                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2418         }
2419
2420         WREG32(CP_INT_CNTL, cp_int_cntl);
2421         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2422
2423         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2424         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2425         if (!(rdev->flags & RADEON_IS_IGP)) {
2426                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2427                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2428                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2429                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2430         }
2431
2432         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2433         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2434         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2435         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2436         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2437         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2438
2439         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2440         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2441         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2442         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2443         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2444         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2445
2446         return 0;
2447 }
2448
2449 static inline void evergreen_irq_ack(struct radeon_device *rdev)
2450 {
2451         u32 tmp;
2452
2453         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2454         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2455         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2456         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2457         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2458         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2459         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2460         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2461         rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2462         rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2463         rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2464         rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2465
2466         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2467                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2468         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2469                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2470         if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2471                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2472         if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2473                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2474         if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2475                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2476         if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2477                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2478
2479         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2480                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2481         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2482                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2483
2484         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2485                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2486         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2487                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2488
2489         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2490                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2491         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2492                 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2493
2494         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2495                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2496         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2497                 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2498
2499         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2500                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2501         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2502                 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2503
2504         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2505                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2506         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2507                 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2508
2509         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2510                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2511                 tmp |= DC_HPDx_INT_ACK;
2512                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2513         }
2514         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2515                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2516                 tmp |= DC_HPDx_INT_ACK;
2517                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2518         }
2519         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2520                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2521                 tmp |= DC_HPDx_INT_ACK;
2522                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2523         }
2524         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2525                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2526                 tmp |= DC_HPDx_INT_ACK;
2527                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2528         }
2529         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2530                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2531                 tmp |= DC_HPDx_INT_ACK;
2532                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2533         }
2534         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2535                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2536                 tmp |= DC_HPDx_INT_ACK;
2537                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2538         }
2539 }
2540
2541 void evergreen_irq_disable(struct radeon_device *rdev)
2542 {
2543         r600_disable_interrupts(rdev);
2544         /* Wait and acknowledge irq */
2545         mdelay(1);
2546         evergreen_irq_ack(rdev);
2547         evergreen_disable_interrupt_state(rdev);
2548 }
2549
2550 static void evergreen_irq_suspend(struct radeon_device *rdev)
2551 {
2552         evergreen_irq_disable(rdev);
2553         r600_rlc_stop(rdev);
2554 }
2555
2556 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2557 {
2558         u32 wptr, tmp;
2559
2560         if (rdev->wb.enabled)
2561                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2562         else
2563                 wptr = RREG32(IH_RB_WPTR);
2564
2565         if (wptr & RB_OVERFLOW) {
2566                 /* When a ring buffer overflow happen start parsing interrupt
2567                  * from the last not overwritten vector (wptr + 16). Hopefully
2568                  * this should allow us to catchup.
2569                  */
2570                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2571                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2572                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2573                 tmp = RREG32(IH_RB_CNTL);
2574                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2575                 WREG32(IH_RB_CNTL, tmp);
2576         }
2577         return (wptr & rdev->ih.ptr_mask);
2578 }
2579
2580 int evergreen_irq_process(struct radeon_device *rdev)
2581 {
2582         u32 wptr = evergreen_get_ih_wptr(rdev);
2583         u32 rptr = rdev->ih.rptr;
2584         u32 src_id, src_data;
2585         u32 ring_index;
2586         unsigned long flags;
2587         bool queue_hotplug = false;
2588
2589         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2590         if (!rdev->ih.enabled)
2591                 return IRQ_NONE;
2592
2593         spin_lock_irqsave(&rdev->ih.lock, flags);
2594
2595         if (rptr == wptr) {
2596                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2597                 return IRQ_NONE;
2598         }
2599         if (rdev->shutdown) {
2600                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2601                 return IRQ_NONE;
2602         }
2603
2604 restart_ih:
2605         /* display interrupts */
2606         evergreen_irq_ack(rdev);
2607
2608         rdev->ih.wptr = wptr;
2609         while (rptr != wptr) {
2610                 /* wptr/rptr are in bytes! */
2611                 ring_index = rptr / 4;
2612                 src_id =  rdev->ih.ring[ring_index] & 0xff;
2613                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2614
2615                 switch (src_id) {
2616                 case 1: /* D1 vblank/vline */
2617                         switch (src_data) {
2618                         case 0: /* D1 vblank */
2619                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2620                                         if (rdev->irq.crtc_vblank_int[0]) {
2621                                                 drm_handle_vblank(rdev->ddev, 0);
2622                                                 rdev->pm.vblank_sync = true;
2623                                                 wake_up(&rdev->irq.vblank_queue);
2624                                         }
2625                                         if (rdev->irq.pflip[0])
2626                                                 radeon_crtc_handle_flip(rdev, 0);
2627                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2628                                         DRM_DEBUG("IH: D1 vblank\n");
2629                                 }
2630                                 break;
2631                         case 1: /* D1 vline */
2632                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2633                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2634                                         DRM_DEBUG("IH: D1 vline\n");
2635                                 }
2636                                 break;
2637                         default:
2638                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2639                                 break;
2640                         }
2641                         break;
2642                 case 2: /* D2 vblank/vline */
2643                         switch (src_data) {
2644                         case 0: /* D2 vblank */
2645                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2646                                         if (rdev->irq.crtc_vblank_int[1]) {
2647                                                 drm_handle_vblank(rdev->ddev, 1);
2648                                                 rdev->pm.vblank_sync = true;
2649                                                 wake_up(&rdev->irq.vblank_queue);
2650                                         }
2651                                         if (rdev->irq.pflip[1])
2652                                                 radeon_crtc_handle_flip(rdev, 1);
2653                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2654                                         DRM_DEBUG("IH: D2 vblank\n");
2655                                 }
2656                                 break;
2657                         case 1: /* D2 vline */
2658                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2659                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2660                                         DRM_DEBUG("IH: D2 vline\n");
2661                                 }
2662                                 break;
2663                         default:
2664                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2665                                 break;
2666                         }
2667                         break;
2668                 case 3: /* D3 vblank/vline */
2669                         switch (src_data) {
2670                         case 0: /* D3 vblank */
2671                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2672                                         if (rdev->irq.crtc_vblank_int[2]) {
2673                                                 drm_handle_vblank(rdev->ddev, 2);
2674                                                 rdev->pm.vblank_sync = true;
2675                                                 wake_up(&rdev->irq.vblank_queue);
2676                                         }
2677                                         if (rdev->irq.pflip[2])
2678                                                 radeon_crtc_handle_flip(rdev, 2);
2679                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2680                                         DRM_DEBUG("IH: D3 vblank\n");
2681                                 }
2682                                 break;
2683                         case 1: /* D3 vline */
2684                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2685                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2686                                         DRM_DEBUG("IH: D3 vline\n");
2687                                 }
2688                                 break;
2689                         default:
2690                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2691                                 break;
2692                         }
2693                         break;
2694                 case 4: /* D4 vblank/vline */
2695                         switch (src_data) {
2696                         case 0: /* D4 vblank */
2697                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2698                                         if (rdev->irq.crtc_vblank_int[3]) {
2699                                                 drm_handle_vblank(rdev->ddev, 3);
2700                                                 rdev->pm.vblank_sync = true;
2701                                                 wake_up(&rdev->irq.vblank_queue);
2702                                         }
2703                                         if (rdev->irq.pflip[3])
2704                                                 radeon_crtc_handle_flip(rdev, 3);
2705                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2706                                         DRM_DEBUG("IH: D4 vblank\n");
2707                                 }
2708                                 break;
2709                         case 1: /* D4 vline */
2710                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2711                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2712                                         DRM_DEBUG("IH: D4 vline\n");
2713                                 }
2714                                 break;
2715                         default:
2716                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2717                                 break;
2718                         }
2719                         break;
2720                 case 5: /* D5 vblank/vline */
2721                         switch (src_data) {
2722                         case 0: /* D5 vblank */
2723                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2724                                         if (rdev->irq.crtc_vblank_int[4]) {
2725                                                 drm_handle_vblank(rdev->ddev, 4);
2726                                                 rdev->pm.vblank_sync = true;
2727                                                 wake_up(&rdev->irq.vblank_queue);
2728                                         }
2729                                         if (rdev->irq.pflip[4])
2730                                                 radeon_crtc_handle_flip(rdev, 4);
2731                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2732                                         DRM_DEBUG("IH: D5 vblank\n");
2733                                 }
2734                                 break;
2735                         case 1: /* D5 vline */
2736                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2737                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2738                                         DRM_DEBUG("IH: D5 vline\n");
2739                                 }
2740                                 break;
2741                         default:
2742                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2743                                 break;
2744                         }
2745                         break;
2746                 case 6: /* D6 vblank/vline */
2747                         switch (src_data) {
2748                         case 0: /* D6 vblank */
2749                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2750                                         if (rdev->irq.crtc_vblank_int[5]) {
2751                                                 drm_handle_vblank(rdev->ddev, 5);
2752                                                 rdev->pm.vblank_sync = true;
2753                                                 wake_up(&rdev->irq.vblank_queue);
2754                                         }
2755                                         if (rdev->irq.pflip[5])
2756                                                 radeon_crtc_handle_flip(rdev, 5);
2757                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2758                                         DRM_DEBUG("IH: D6 vblank\n");
2759                                 }
2760                                 break;
2761                         case 1: /* D6 vline */
2762                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2763                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2764                                         DRM_DEBUG("IH: D6 vline\n");
2765                                 }
2766                                 break;
2767                         default:
2768                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2769                                 break;
2770                         }
2771                         break;
2772                 case 42: /* HPD hotplug */
2773                         switch (src_data) {
2774                         case 0:
2775                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2776                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2777                                         queue_hotplug = true;
2778                                         DRM_DEBUG("IH: HPD1\n");
2779                                 }
2780                                 break;
2781                         case 1:
2782                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2783                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2784                                         queue_hotplug = true;
2785                                         DRM_DEBUG("IH: HPD2\n");
2786                                 }
2787                                 break;
2788                         case 2:
2789                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2790                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2791                                         queue_hotplug = true;
2792                                         DRM_DEBUG("IH: HPD3\n");
2793                                 }
2794                                 break;
2795                         case 3:
2796                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2797                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2798                                         queue_hotplug = true;
2799                                         DRM_DEBUG("IH: HPD4\n");
2800                                 }
2801                                 break;
2802                         case 4:
2803                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2804                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2805                                         queue_hotplug = true;
2806                                         DRM_DEBUG("IH: HPD5\n");
2807                                 }
2808                                 break;
2809                         case 5:
2810                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2811                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2812                                         queue_hotplug = true;
2813                                         DRM_DEBUG("IH: HPD6\n");
2814                                 }
2815                                 break;
2816                         default:
2817                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2818                                 break;
2819                         }
2820                         break;
2821                 case 176: /* CP_INT in ring buffer */
2822                 case 177: /* CP_INT in IB1 */
2823                 case 178: /* CP_INT in IB2 */
2824                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2825                         radeon_fence_process(rdev);
2826                         break;
2827                 case 181: /* CP EOP event */
2828                         DRM_DEBUG("IH: CP EOP\n");
2829                         radeon_fence_process(rdev);
2830                         break;
2831                 case 233: /* GUI IDLE */
2832                         DRM_DEBUG("IH: CP EOP\n");
2833                         rdev->pm.gui_idle = true;
2834                         wake_up(&rdev->irq.idle_queue);
2835                         break;
2836                 default:
2837                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2838                         break;
2839                 }
2840
2841                 /* wptr/rptr are in bytes! */
2842                 rptr += 16;
2843                 rptr &= rdev->ih.ptr_mask;
2844         }
2845         /* make sure wptr hasn't changed while processing */
2846         wptr = evergreen_get_ih_wptr(rdev);
2847         if (wptr != rdev->ih.wptr)
2848                 goto restart_ih;
2849         if (queue_hotplug)
2850                 schedule_work(&rdev->hotplug_work);
2851         rdev->ih.rptr = rptr;
2852         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2853         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2854         return IRQ_HANDLED;
2855 }
2856
2857 static int evergreen_startup(struct radeon_device *rdev)
2858 {
2859         int r;
2860
2861         /* enable pcie gen2 link */
2862         if (!ASIC_IS_DCE5(rdev))
2863                 evergreen_pcie_gen2_enable(rdev);
2864
2865         if (ASIC_IS_DCE5(rdev)) {
2866                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2867                         r = ni_init_microcode(rdev);
2868                         if (r) {
2869                                 DRM_ERROR("Failed to load firmware!\n");
2870                                 return r;
2871                         }
2872                 }
2873                 r = btc_mc_load_microcode(rdev);
2874                 if (r) {
2875                         DRM_ERROR("Failed to load MC firmware!\n");
2876                         return r;
2877                 }
2878         } else {
2879                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2880                         r = r600_init_microcode(rdev);
2881                         if (r) {
2882                                 DRM_ERROR("Failed to load firmware!\n");
2883                                 return r;
2884                         }
2885                 }
2886         }
2887
2888         evergreen_mc_program(rdev);
2889         if (rdev->flags & RADEON_IS_AGP) {
2890                 evergreen_agp_enable(rdev);
2891         } else {
2892                 r = evergreen_pcie_gart_enable(rdev);
2893                 if (r)
2894                         return r;
2895         }
2896         evergreen_gpu_init(rdev);
2897
2898         r = evergreen_blit_init(rdev);
2899         if (r) {
2900                 evergreen_blit_fini(rdev);
2901                 rdev->asic->copy = NULL;
2902                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2903         }
2904         /* XXX: ontario has problems blitting to gart at the moment */
2905         if (rdev->family == CHIP_PALM) {
2906                 rdev->asic->copy = NULL;
2907                 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2908         }
2909
2910         /* allocate wb buffer */
2911         r = radeon_wb_init(rdev);
2912         if (r)
2913                 return r;
2914
2915         /* Enable IRQ */
2916         r = r600_irq_init(rdev);
2917         if (r) {
2918                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2919                 radeon_irq_kms_fini(rdev);
2920                 return r;
2921         }
2922         evergreen_irq_set(rdev);
2923
2924         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2925         if (r)
2926                 return r;
2927         r = evergreen_cp_load_microcode(rdev);
2928         if (r)
2929                 return r;
2930         r = evergreen_cp_resume(rdev);
2931         if (r)
2932                 return r;
2933
2934         return 0;
2935 }
2936
2937 int evergreen_resume(struct radeon_device *rdev)
2938 {
2939         int r;
2940
2941         /* reset the asic, the gfx blocks are often in a bad state
2942          * after the driver is unloaded or after a resume
2943          */
2944         if (radeon_asic_reset(rdev))
2945                 dev_warn(rdev->dev, "GPU reset failed !\n");
2946         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2947          * posting will perform necessary task to bring back GPU into good
2948          * shape.
2949          */
2950         /* post card */
2951         atom_asic_init(rdev->mode_info.atom_context);
2952
2953         r = evergreen_startup(rdev);
2954         if (r) {
2955                 DRM_ERROR("r600 startup failed on resume\n");
2956                 return r;
2957         }
2958
2959         r = r600_ib_test(rdev);
2960         if (r) {
2961                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2962                 return r;
2963         }
2964
2965         return r;
2966
2967 }
2968
2969 int evergreen_suspend(struct radeon_device *rdev)
2970 {
2971         int r;
2972
2973         /* FIXME: we should wait for ring to be empty */
2974         r700_cp_stop(rdev);
2975         rdev->cp.ready = false;
2976         evergreen_irq_suspend(rdev);
2977         radeon_wb_disable(rdev);
2978         evergreen_pcie_gart_disable(rdev);
2979
2980         /* unpin shaders bo */
2981         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2982         if (likely(r == 0)) {
2983                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2984                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2985         }
2986
2987         return 0;
2988 }
2989
2990 int evergreen_copy_blit(struct radeon_device *rdev,
2991                         uint64_t src_offset, uint64_t dst_offset,
2992                         unsigned num_pages, struct radeon_fence *fence)
2993 {
2994         int r;
2995
2996         mutex_lock(&rdev->r600_blit.mutex);
2997         rdev->r600_blit.vb_ib = NULL;
2998         r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2999         if (r) {
3000                 if (rdev->r600_blit.vb_ib)
3001                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
3002                 mutex_unlock(&rdev->r600_blit.mutex);
3003                 return r;
3004         }
3005         evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3006         evergreen_blit_done_copy(rdev, fence);
3007         mutex_unlock(&rdev->r600_blit.mutex);
3008         return 0;
3009 }
3010
3011 /* Plan is to move initialization in that function and use
3012  * helper function so that radeon_device_init pretty much
3013  * do nothing more than calling asic specific function. This
3014  * should also allow to remove a bunch of callback function
3015  * like vram_info.
3016  */
3017 int evergreen_init(struct radeon_device *rdev)
3018 {
3019         int r;
3020
3021         r = radeon_dummy_page_init(rdev);
3022         if (r)
3023                 return r;
3024         /* This don't do much */
3025         r = radeon_gem_init(rdev);
3026         if (r)
3027                 return r;
3028         /* Read BIOS */
3029         if (!radeon_get_bios(rdev)) {
3030                 if (ASIC_IS_AVIVO(rdev))
3031                         return -EINVAL;
3032         }
3033         /* Must be an ATOMBIOS */
3034         if (!rdev->is_atom_bios) {
3035                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3036                 return -EINVAL;
3037         }
3038         r = radeon_atombios_init(rdev);
3039         if (r)
3040                 return r;
3041         /* reset the asic, the gfx blocks are often in a bad state
3042          * after the driver is unloaded or after a resume
3043          */
3044         if (radeon_asic_reset(rdev))
3045                 dev_warn(rdev->dev, "GPU reset failed !\n");
3046         /* Post card if necessary */
3047         if (!radeon_card_posted(rdev)) {
3048                 if (!rdev->bios) {
3049                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3050                         return -EINVAL;
3051                 }
3052                 DRM_INFO("GPU not posted. posting now...\n");
3053                 atom_asic_init(rdev->mode_info.atom_context);
3054         }
3055         /* Initialize scratch registers */
3056         r600_scratch_init(rdev);
3057         /* Initialize surface registers */
3058         radeon_surface_init(rdev);
3059         /* Initialize clocks */
3060         radeon_get_clock_info(rdev->ddev);
3061         /* Fence driver */
3062         r = radeon_fence_driver_init(rdev);
3063         if (r)
3064                 return r;
3065         /* initialize AGP */
3066         if (rdev->flags & RADEON_IS_AGP) {
3067                 r = radeon_agp_init(rdev);
3068                 if (r)
3069                         radeon_agp_disable(rdev);
3070         }
3071         /* initialize memory controller */
3072         r = evergreen_mc_init(rdev);
3073         if (r)
3074                 return r;
3075         /* Memory manager */
3076         r = radeon_bo_init(rdev);
3077         if (r)
3078                 return r;
3079
3080         r = radeon_irq_kms_init(rdev);
3081         if (r)
3082                 return r;
3083
3084         rdev->cp.ring_obj = NULL;
3085         r600_ring_init(rdev, 1024 * 1024);
3086
3087         rdev->ih.ring_obj = NULL;
3088         r600_ih_ring_init(rdev, 64 * 1024);
3089
3090         r = r600_pcie_gart_init(rdev);
3091         if (r)
3092                 return r;
3093
3094         rdev->accel_working = true;
3095         r = evergreen_startup(rdev);
3096         if (r) {
3097                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3098                 r700_cp_fini(rdev);
3099                 r600_irq_fini(rdev);
3100                 radeon_wb_fini(rdev);
3101                 radeon_irq_kms_fini(rdev);
3102                 evergreen_pcie_gart_fini(rdev);
3103                 rdev->accel_working = false;
3104         }
3105         if (rdev->accel_working) {
3106                 r = radeon_ib_pool_init(rdev);
3107                 if (r) {
3108                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3109                         rdev->accel_working = false;
3110                 }
3111                 r = r600_ib_test(rdev);
3112                 if (r) {
3113                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3114                         rdev->accel_working = false;
3115                 }
3116         }
3117         return 0;
3118 }
3119
3120 void evergreen_fini(struct radeon_device *rdev)
3121 {
3122         evergreen_blit_fini(rdev);
3123         r700_cp_fini(rdev);
3124         r600_irq_fini(rdev);
3125         radeon_wb_fini(rdev);
3126         radeon_irq_kms_fini(rdev);
3127         evergreen_pcie_gart_fini(rdev);
3128         radeon_gem_fini(rdev);
3129         radeon_fence_driver_fini(rdev);
3130         radeon_agp_fini(rdev);
3131         radeon_bo_fini(rdev);
3132         radeon_atombios_fini(rdev);
3133         kfree(rdev->bios);
3134         rdev->bios = NULL;
3135         radeon_dummy_page_fini(rdev);
3136 }
3137
3138 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3139 {
3140         u32 link_width_cntl, speed_cntl;
3141
3142         if (radeon_pcie_gen2 == 0)
3143                 return;
3144
3145         if (rdev->flags & RADEON_IS_IGP)
3146                 return;
3147
3148         if (!(rdev->flags & RADEON_IS_PCIE))
3149                 return;
3150
3151         /* x2 cards have a special sequence */
3152         if (ASIC_IS_X2(rdev))
3153                 return;
3154
3155         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3156         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3157             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3158
3159                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3160                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3161                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3162
3163                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3164                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3165                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3166
3167                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3168                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3169                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3170
3171                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3172                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3173                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3174
3175                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3176                 speed_cntl |= LC_GEN2_EN_STRAP;
3177                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3178
3179         } else {
3180                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3181                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3182                 if (1)
3183                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3184                 else
3185                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3186                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3187         }
3188 }