2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "radeon_ucode.h"
32 #include <linux/seq_file.h>
34 #define MC_CG_ARB_FREQ_F0 0x0a
35 #define MC_CG_ARB_FREQ_F1 0x0b
36 #define MC_CG_ARB_FREQ_F2 0x0c
37 #define MC_CG_ARB_FREQ_F3 0x0d
39 #define SMC_RAM_END 0x40000
41 #define VOLTAGE_SCALE 4
42 #define VOLTAGE_VID_OFFSET_SCALE1 625
43 #define VOLTAGE_VID_OFFSET_SCALE2 100
45 static const struct ci_pt_defaults defaults_hawaii_xt =
47 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
48 { 0x84, 0x0, 0x0, 0x7F, 0x0, 0x0, 0x5A, 0x60, 0x51, 0x8E, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
49 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
52 static const struct ci_pt_defaults defaults_hawaii_pro =
54 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
55 { 0x93, 0x0, 0x0, 0x97, 0x0, 0x0, 0x6B, 0x60, 0x51, 0x95, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
56 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
59 static const struct ci_pt_defaults defaults_bonaire_xt =
61 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
62 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
63 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
66 static const struct ci_pt_defaults defaults_bonaire_pro =
68 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
69 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
70 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
73 static const struct ci_pt_defaults defaults_saturn_xt =
75 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
76 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
77 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
80 static const struct ci_pt_defaults defaults_saturn_pro =
82 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
83 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
84 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
87 static const struct ci_pt_config_reg didt_config_ci[] =
89 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
90 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
91 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
92 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
93 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
94 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
95 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
96 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
97 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
98 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
99 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
100 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
101 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
102 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
103 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
104 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
105 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
106 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
107 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
108 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
109 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
110 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
164 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
165 extern void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
167 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
168 u32 arb_freq_src, u32 arb_freq_dest);
169 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
170 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
171 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
172 u32 max_voltage_steps,
173 struct atom_voltage_table *voltage_table);
174 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
175 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
176 extern int ci_mc_load_microcode(struct radeon_device *rdev);
177 extern void cik_update_cg(struct radeon_device *rdev,
178 u32 block, bool enable);
180 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
181 struct atom_voltage_table_entry *voltage_table,
182 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
183 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
184 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
186 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
188 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
190 struct ci_power_info *pi = rdev->pm.dpm.priv;
195 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
197 struct ci_ps *ps = rps->ps_priv;
202 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
204 struct ci_power_info *pi = ci_get_pi(rdev);
206 switch (rdev->pdev->device) {
214 pi->powertune_defaults = &defaults_bonaire_xt;
220 pi->powertune_defaults = &defaults_saturn_xt;
224 pi->powertune_defaults = &defaults_hawaii_xt;
228 pi->powertune_defaults = &defaults_hawaii_pro;
238 pi->powertune_defaults = &defaults_bonaire_xt;
242 pi->dte_tj_offset = 0;
244 pi->caps_power_containment = true;
245 pi->caps_cac = false;
246 pi->caps_sq_ramping = false;
247 pi->caps_db_ramping = false;
248 pi->caps_td_ramping = false;
249 pi->caps_tcp_ramping = false;
251 if (pi->caps_power_containment) {
253 pi->enable_bapm_feature = true;
254 pi->enable_tdc_limit_feature = true;
255 pi->enable_pkg_pwr_tracking_feature = true;
259 static u8 ci_convert_to_vid(u16 vddc)
261 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
264 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
266 struct ci_power_info *pi = ci_get_pi(rdev);
267 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
268 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
269 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
272 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
274 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
276 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
277 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
280 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
281 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
282 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
283 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
284 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
286 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
287 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
293 static int ci_populate_vddc_vid(struct radeon_device *rdev)
295 struct ci_power_info *pi = ci_get_pi(rdev);
296 u8 *vid = pi->smc_powertune_table.VddCVid;
299 if (pi->vddc_voltage_table.count > 8)
302 for (i = 0; i < pi->vddc_voltage_table.count; i++)
303 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
308 static int ci_populate_svi_load_line(struct radeon_device *rdev)
310 struct ci_power_info *pi = ci_get_pi(rdev);
311 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
313 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
314 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
315 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
316 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
321 static int ci_populate_tdc_limit(struct radeon_device *rdev)
323 struct ci_power_info *pi = ci_get_pi(rdev);
324 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
327 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
328 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
329 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
330 pt_defaults->tdc_vddc_throttle_release_limit_perc;
331 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
336 static int ci_populate_dw8(struct radeon_device *rdev)
338 struct ci_power_info *pi = ci_get_pi(rdev);
339 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
342 ret = ci_read_smc_sram_dword(rdev,
343 SMU7_FIRMWARE_HEADER_LOCATION +
344 offsetof(SMU7_Firmware_Header, PmFuseTable) +
345 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
346 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
351 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
356 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
358 struct ci_power_info *pi = ci_get_pi(rdev);
359 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
360 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
363 min = max = hi_vid[0];
364 for (i = 0; i < 8; i++) {
365 if (0 != hi_vid[i]) {
372 if (0 != lo_vid[i]) {
380 if ((min == 0) || (max == 0))
382 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
383 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
388 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
390 struct ci_power_info *pi = ci_get_pi(rdev);
391 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
392 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
393 struct radeon_cac_tdp_table *cac_tdp_table =
394 rdev->pm.dpm.dyn_state.cac_tdp_table;
396 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
397 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
399 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
400 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
405 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
407 struct ci_power_info *pi = ci_get_pi(rdev);
408 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
409 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
410 struct radeon_cac_tdp_table *cac_tdp_table =
411 rdev->pm.dpm.dyn_state.cac_tdp_table;
412 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
417 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
418 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
420 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
421 dpm_table->GpuTjMax =
422 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
423 dpm_table->GpuTjHyst = 8;
425 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
428 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
429 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
431 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
432 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
435 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
436 def1 = pt_defaults->bapmti_r;
437 def2 = pt_defaults->bapmti_rc;
439 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
440 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
441 for (k = 0; k < SMU7_DTE_SINKS; k++) {
442 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
443 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
453 static int ci_populate_pm_base(struct radeon_device *rdev)
455 struct ci_power_info *pi = ci_get_pi(rdev);
456 u32 pm_fuse_table_offset;
459 if (pi->caps_power_containment) {
460 ret = ci_read_smc_sram_dword(rdev,
461 SMU7_FIRMWARE_HEADER_LOCATION +
462 offsetof(SMU7_Firmware_Header, PmFuseTable),
463 &pm_fuse_table_offset, pi->sram_end);
466 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
469 ret = ci_populate_vddc_vid(rdev);
472 ret = ci_populate_svi_load_line(rdev);
475 ret = ci_populate_tdc_limit(rdev);
478 ret = ci_populate_dw8(rdev);
481 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
484 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
487 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
488 (u8 *)&pi->smc_powertune_table,
489 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
497 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
499 struct ci_power_info *pi = ci_get_pi(rdev);
502 if (pi->caps_sq_ramping) {
503 data = RREG32_DIDT(DIDT_SQ_CTRL0);
505 data |= DIDT_CTRL_EN;
507 data &= ~DIDT_CTRL_EN;
508 WREG32_DIDT(DIDT_SQ_CTRL0, data);
511 if (pi->caps_db_ramping) {
512 data = RREG32_DIDT(DIDT_DB_CTRL0);
514 data |= DIDT_CTRL_EN;
516 data &= ~DIDT_CTRL_EN;
517 WREG32_DIDT(DIDT_DB_CTRL0, data);
520 if (pi->caps_td_ramping) {
521 data = RREG32_DIDT(DIDT_TD_CTRL0);
523 data |= DIDT_CTRL_EN;
525 data &= ~DIDT_CTRL_EN;
526 WREG32_DIDT(DIDT_TD_CTRL0, data);
529 if (pi->caps_tcp_ramping) {
530 data = RREG32_DIDT(DIDT_TCP_CTRL0);
532 data |= DIDT_CTRL_EN;
534 data &= ~DIDT_CTRL_EN;
535 WREG32_DIDT(DIDT_TCP_CTRL0, data);
539 static int ci_program_pt_config_registers(struct radeon_device *rdev,
540 const struct ci_pt_config_reg *cac_config_regs)
542 const struct ci_pt_config_reg *config_regs = cac_config_regs;
546 if (config_regs == NULL)
549 while (config_regs->offset != 0xFFFFFFFF) {
550 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
551 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
553 switch (config_regs->type) {
554 case CISLANDS_CONFIGREG_SMC_IND:
555 data = RREG32_SMC(config_regs->offset);
557 case CISLANDS_CONFIGREG_DIDT_IND:
558 data = RREG32_DIDT(config_regs->offset);
561 data = RREG32(config_regs->offset << 2);
565 data &= ~config_regs->mask;
566 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
569 switch (config_regs->type) {
570 case CISLANDS_CONFIGREG_SMC_IND:
571 WREG32_SMC(config_regs->offset, data);
573 case CISLANDS_CONFIGREG_DIDT_IND:
574 WREG32_DIDT(config_regs->offset, data);
577 WREG32(config_regs->offset << 2, data);
587 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
589 struct ci_power_info *pi = ci_get_pi(rdev);
592 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
593 pi->caps_td_ramping || pi->caps_tcp_ramping) {
594 cik_enter_rlc_safe_mode(rdev);
597 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
599 cik_exit_rlc_safe_mode(rdev);
604 ci_do_enable_didt(rdev, enable);
606 cik_exit_rlc_safe_mode(rdev);
612 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
614 struct ci_power_info *pi = ci_get_pi(rdev);
615 PPSMC_Result smc_result;
619 pi->power_containment_features = 0;
620 if (pi->caps_power_containment) {
621 if (pi->enable_bapm_feature) {
622 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
623 if (smc_result != PPSMC_Result_OK)
626 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
629 if (pi->enable_tdc_limit_feature) {
630 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
631 if (smc_result != PPSMC_Result_OK)
634 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
637 if (pi->enable_pkg_pwr_tracking_feature) {
638 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
639 if (smc_result != PPSMC_Result_OK) {
642 struct radeon_cac_tdp_table *cac_tdp_table =
643 rdev->pm.dpm.dyn_state.cac_tdp_table;
644 u32 default_pwr_limit =
645 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
647 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
649 ci_set_power_limit(rdev, default_pwr_limit);
654 if (pi->caps_power_containment && pi->power_containment_features) {
655 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
656 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
658 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
659 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
661 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
662 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
663 pi->power_containment_features = 0;
670 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
672 struct ci_power_info *pi = ci_get_pi(rdev);
673 PPSMC_Result smc_result;
678 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
679 if (smc_result != PPSMC_Result_OK) {
681 pi->cac_enabled = false;
683 pi->cac_enabled = true;
685 } else if (pi->cac_enabled) {
686 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
687 pi->cac_enabled = false;
694 static int ci_power_control_set_level(struct radeon_device *rdev)
696 struct ci_power_info *pi = ci_get_pi(rdev);
697 struct radeon_cac_tdp_table *cac_tdp_table =
698 rdev->pm.dpm.dyn_state.cac_tdp_table;
702 bool adjust_polarity = false; /* ??? */
704 if (pi->caps_power_containment &&
705 (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) {
706 adjust_percent = adjust_polarity ?
707 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
708 target_tdp = ((100 + adjust_percent) *
709 (s32)cac_tdp_table->configurable_tdp) / 100;
712 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
718 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
720 struct ci_power_info *pi = ci_get_pi(rdev);
722 if (pi->uvd_power_gated == gate)
725 pi->uvd_power_gated = gate;
727 ci_update_uvd_dpm(rdev, gate);
730 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
732 struct ci_power_info *pi = ci_get_pi(rdev);
733 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
734 u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
736 if (vblank_time < switch_limit)
743 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
744 struct radeon_ps *rps)
746 struct ci_ps *ps = ci_get_ps(rps);
747 struct ci_power_info *pi = ci_get_pi(rdev);
748 struct radeon_clock_and_voltage_limits *max_limits;
749 bool disable_mclk_switching;
751 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
754 if (rps->vce_active) {
755 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
756 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
762 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
763 ci_dpm_vblank_too_short(rdev))
764 disable_mclk_switching = true;
766 disable_mclk_switching = false;
768 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
769 pi->battery_state = true;
771 pi->battery_state = false;
773 if (rdev->pm.dpm.ac_power)
774 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
776 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
778 if (rdev->pm.dpm.ac_power == false) {
779 for (i = 0; i < ps->performance_level_count; i++) {
780 if (ps->performance_levels[i].mclk > max_limits->mclk)
781 ps->performance_levels[i].mclk = max_limits->mclk;
782 if (ps->performance_levels[i].sclk > max_limits->sclk)
783 ps->performance_levels[i].sclk = max_limits->sclk;
787 /* limit clocks to max supported clocks based on voltage dependency tables */
788 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
790 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
792 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
795 for (i = 0; i < ps->performance_level_count; i++) {
797 if (ps->performance_levels[i].sclk > max_sclk_vddc)
798 ps->performance_levels[i].sclk = max_sclk_vddc;
800 if (max_mclk_vddci) {
801 if (ps->performance_levels[i].mclk > max_mclk_vddci)
802 ps->performance_levels[i].mclk = max_mclk_vddci;
805 if (ps->performance_levels[i].mclk > max_mclk_vddc)
806 ps->performance_levels[i].mclk = max_mclk_vddc;
810 /* XXX validate the min clocks required for display */
812 if (disable_mclk_switching) {
813 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
814 sclk = ps->performance_levels[0].sclk;
816 mclk = ps->performance_levels[0].mclk;
817 sclk = ps->performance_levels[0].sclk;
820 if (rps->vce_active) {
821 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
822 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
823 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
824 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
827 ps->performance_levels[0].sclk = sclk;
828 ps->performance_levels[0].mclk = mclk;
830 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
831 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
833 if (disable_mclk_switching) {
834 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
835 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
837 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
838 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
842 static int ci_set_thermal_temperature_range(struct radeon_device *rdev,
843 int min_temp, int max_temp)
845 int low_temp = 0 * 1000;
846 int high_temp = 255 * 1000;
849 if (low_temp < min_temp)
851 if (high_temp > max_temp)
852 high_temp = max_temp;
853 if (high_temp < low_temp) {
854 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
858 tmp = RREG32_SMC(CG_THERMAL_INT);
859 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
860 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
861 CI_DIG_THERM_INTL(low_temp / 1000);
862 WREG32_SMC(CG_THERMAL_INT, tmp);
865 /* XXX: need to figure out how to handle this properly */
866 tmp = RREG32_SMC(CG_THERMAL_CTRL);
867 tmp &= DIG_THERM_DPM_MASK;
868 tmp |= DIG_THERM_DPM(high_temp / 1000);
869 WREG32_SMC(CG_THERMAL_CTRL, tmp);
876 static int ci_read_smc_soft_register(struct radeon_device *rdev,
877 u16 reg_offset, u32 *value)
879 struct ci_power_info *pi = ci_get_pi(rdev);
881 return ci_read_smc_sram_dword(rdev,
882 pi->soft_regs_start + reg_offset,
883 value, pi->sram_end);
887 static int ci_write_smc_soft_register(struct radeon_device *rdev,
888 u16 reg_offset, u32 value)
890 struct ci_power_info *pi = ci_get_pi(rdev);
892 return ci_write_smc_sram_dword(rdev,
893 pi->soft_regs_start + reg_offset,
894 value, pi->sram_end);
897 static void ci_init_fps_limits(struct radeon_device *rdev)
899 struct ci_power_info *pi = ci_get_pi(rdev);
900 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
906 table->FpsHighT = cpu_to_be16(tmp);
909 table->FpsLowT = cpu_to_be16(tmp);
913 static int ci_update_sclk_t(struct radeon_device *rdev)
915 struct ci_power_info *pi = ci_get_pi(rdev);
917 u32 low_sclk_interrupt_t = 0;
919 if (pi->caps_sclk_throttle_low_notification) {
920 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
922 ret = ci_copy_bytes_to_smc(rdev,
923 pi->dpm_table_start +
924 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
925 (u8 *)&low_sclk_interrupt_t,
926 sizeof(u32), pi->sram_end);
933 static void ci_get_leakage_voltages(struct radeon_device *rdev)
935 struct ci_power_info *pi = ci_get_pi(rdev);
936 u16 leakage_id, virtual_voltage_id;
940 pi->vddc_leakage.count = 0;
941 pi->vddci_leakage.count = 0;
943 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
944 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
945 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
946 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
948 if (vddc != 0 && vddc != virtual_voltage_id) {
949 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
950 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
951 pi->vddc_leakage.count++;
954 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
955 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
956 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
957 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
960 if (vddc != 0 && vddc != virtual_voltage_id) {
961 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
962 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
963 pi->vddc_leakage.count++;
965 if (vddci != 0 && vddci != virtual_voltage_id) {
966 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
967 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
968 pi->vddci_leakage.count++;
975 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
977 struct ci_power_info *pi = ci_get_pi(rdev);
978 bool want_thermal_protection;
979 enum radeon_dpm_event_src dpm_event_src;
985 want_thermal_protection = false;
987 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
988 want_thermal_protection = true;
989 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
991 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
992 want_thermal_protection = true;
993 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
995 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
996 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
997 want_thermal_protection = true;
998 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1002 if (want_thermal_protection) {
1004 /* XXX: need to figure out how to handle this properly */
1005 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1006 tmp &= DPM_EVENT_SRC_MASK;
1007 tmp |= DPM_EVENT_SRC(dpm_event_src);
1008 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1011 tmp = RREG32_SMC(GENERAL_PWRMGT);
1012 if (pi->thermal_protection)
1013 tmp &= ~THERMAL_PROTECTION_DIS;
1015 tmp |= THERMAL_PROTECTION_DIS;
1016 WREG32_SMC(GENERAL_PWRMGT, tmp);
1018 tmp = RREG32_SMC(GENERAL_PWRMGT);
1019 tmp |= THERMAL_PROTECTION_DIS;
1020 WREG32_SMC(GENERAL_PWRMGT, tmp);
1024 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1025 enum radeon_dpm_auto_throttle_src source,
1028 struct ci_power_info *pi = ci_get_pi(rdev);
1031 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1032 pi->active_auto_throttle_sources |= 1 << source;
1033 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1036 if (pi->active_auto_throttle_sources & (1 << source)) {
1037 pi->active_auto_throttle_sources &= ~(1 << source);
1038 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1043 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1045 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1046 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1049 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1051 struct ci_power_info *pi = ci_get_pi(rdev);
1052 PPSMC_Result smc_result;
1054 if (!pi->need_update_smu7_dpm_table)
1057 if ((!pi->sclk_dpm_key_disabled) &&
1058 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1059 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1060 if (smc_result != PPSMC_Result_OK)
1064 if ((!pi->mclk_dpm_key_disabled) &&
1065 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1066 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1067 if (smc_result != PPSMC_Result_OK)
1071 pi->need_update_smu7_dpm_table = 0;
1075 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1077 struct ci_power_info *pi = ci_get_pi(rdev);
1078 PPSMC_Result smc_result;
1081 if (!pi->sclk_dpm_key_disabled) {
1082 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1083 if (smc_result != PPSMC_Result_OK)
1087 if (!pi->mclk_dpm_key_disabled) {
1088 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1089 if (smc_result != PPSMC_Result_OK)
1092 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1094 WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1095 WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1096 WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1100 WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1101 WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1102 WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1105 if (!pi->sclk_dpm_key_disabled) {
1106 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1107 if (smc_result != PPSMC_Result_OK)
1111 if (!pi->mclk_dpm_key_disabled) {
1112 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1113 if (smc_result != PPSMC_Result_OK)
1121 static int ci_start_dpm(struct radeon_device *rdev)
1123 struct ci_power_info *pi = ci_get_pi(rdev);
1124 PPSMC_Result smc_result;
1128 tmp = RREG32_SMC(GENERAL_PWRMGT);
1129 tmp |= GLOBAL_PWRMGT_EN;
1130 WREG32_SMC(GENERAL_PWRMGT, tmp);
1132 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1133 tmp |= DYNAMIC_PM_EN;
1134 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1136 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1138 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1140 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1141 if (smc_result != PPSMC_Result_OK)
1144 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1148 if (!pi->pcie_dpm_key_disabled) {
1149 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1150 if (smc_result != PPSMC_Result_OK)
1157 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1159 struct ci_power_info *pi = ci_get_pi(rdev);
1160 PPSMC_Result smc_result;
1162 if (!pi->need_update_smu7_dpm_table)
1165 if ((!pi->sclk_dpm_key_disabled) &&
1166 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1167 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1168 if (smc_result != PPSMC_Result_OK)
1172 if ((!pi->mclk_dpm_key_disabled) &&
1173 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1174 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1175 if (smc_result != PPSMC_Result_OK)
1182 static int ci_stop_dpm(struct radeon_device *rdev)
1184 struct ci_power_info *pi = ci_get_pi(rdev);
1185 PPSMC_Result smc_result;
1189 tmp = RREG32_SMC(GENERAL_PWRMGT);
1190 tmp &= ~GLOBAL_PWRMGT_EN;
1191 WREG32_SMC(GENERAL_PWRMGT, tmp);
1193 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1194 tmp &= ~DYNAMIC_PM_EN;
1195 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1197 if (!pi->pcie_dpm_key_disabled) {
1198 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1199 if (smc_result != PPSMC_Result_OK)
1203 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1207 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1208 if (smc_result != PPSMC_Result_OK)
1214 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1216 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1219 tmp &= ~SCLK_PWRMGT_OFF;
1221 tmp |= SCLK_PWRMGT_OFF;
1222 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1226 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1229 struct ci_power_info *pi = ci_get_pi(rdev);
1230 struct radeon_cac_tdp_table *cac_tdp_table =
1231 rdev->pm.dpm.dyn_state.cac_tdp_table;
1235 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1237 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1239 ci_set_power_limit(rdev, power_limit);
1241 if (pi->caps_automatic_dc_transition) {
1243 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1245 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1252 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1253 PPSMC_Msg msg, u32 parameter)
1255 WREG32(SMC_MSG_ARG_0, parameter);
1256 return ci_send_msg_to_smc(rdev, msg);
1259 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1260 PPSMC_Msg msg, u32 *parameter)
1262 PPSMC_Result smc_result;
1264 smc_result = ci_send_msg_to_smc(rdev, msg);
1266 if ((smc_result == PPSMC_Result_OK) && parameter)
1267 *parameter = RREG32(SMC_MSG_ARG_0);
1272 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1274 struct ci_power_info *pi = ci_get_pi(rdev);
1276 if (!pi->sclk_dpm_key_disabled) {
1277 PPSMC_Result smc_result =
1278 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, n);
1279 if (smc_result != PPSMC_Result_OK)
1286 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1288 struct ci_power_info *pi = ci_get_pi(rdev);
1290 if (!pi->mclk_dpm_key_disabled) {
1291 PPSMC_Result smc_result =
1292 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_ForceState, n);
1293 if (smc_result != PPSMC_Result_OK)
1300 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1302 struct ci_power_info *pi = ci_get_pi(rdev);
1304 if (!pi->pcie_dpm_key_disabled) {
1305 PPSMC_Result smc_result =
1306 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1307 if (smc_result != PPSMC_Result_OK)
1314 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1316 struct ci_power_info *pi = ci_get_pi(rdev);
1318 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1319 PPSMC_Result smc_result =
1320 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1321 if (smc_result != PPSMC_Result_OK)
1328 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1331 PPSMC_Result smc_result =
1332 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1333 if (smc_result != PPSMC_Result_OK)
1338 static int ci_set_boot_state(struct radeon_device *rdev)
1340 return ci_enable_sclk_mclk_dpm(rdev, false);
1343 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1346 PPSMC_Result smc_result =
1347 ci_send_msg_to_smc_return_parameter(rdev,
1348 PPSMC_MSG_API_GetSclkFrequency,
1350 if (smc_result != PPSMC_Result_OK)
1356 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1359 PPSMC_Result smc_result =
1360 ci_send_msg_to_smc_return_parameter(rdev,
1361 PPSMC_MSG_API_GetMclkFrequency,
1363 if (smc_result != PPSMC_Result_OK)
1369 static void ci_dpm_start_smc(struct radeon_device *rdev)
1373 ci_program_jump_on_start(rdev);
1374 ci_start_smc_clock(rdev);
1376 for (i = 0; i < rdev->usec_timeout; i++) {
1377 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1382 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1385 ci_stop_smc_clock(rdev);
1388 static int ci_process_firmware_header(struct radeon_device *rdev)
1390 struct ci_power_info *pi = ci_get_pi(rdev);
1394 ret = ci_read_smc_sram_dword(rdev,
1395 SMU7_FIRMWARE_HEADER_LOCATION +
1396 offsetof(SMU7_Firmware_Header, DpmTable),
1397 &tmp, pi->sram_end);
1401 pi->dpm_table_start = tmp;
1403 ret = ci_read_smc_sram_dword(rdev,
1404 SMU7_FIRMWARE_HEADER_LOCATION +
1405 offsetof(SMU7_Firmware_Header, SoftRegisters),
1406 &tmp, pi->sram_end);
1410 pi->soft_regs_start = tmp;
1412 ret = ci_read_smc_sram_dword(rdev,
1413 SMU7_FIRMWARE_HEADER_LOCATION +
1414 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1415 &tmp, pi->sram_end);
1419 pi->mc_reg_table_start = tmp;
1421 ret = ci_read_smc_sram_dword(rdev,
1422 SMU7_FIRMWARE_HEADER_LOCATION +
1423 offsetof(SMU7_Firmware_Header, FanTable),
1424 &tmp, pi->sram_end);
1428 pi->fan_table_start = tmp;
1430 ret = ci_read_smc_sram_dword(rdev,
1431 SMU7_FIRMWARE_HEADER_LOCATION +
1432 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1433 &tmp, pi->sram_end);
1437 pi->arb_table_start = tmp;
1442 static void ci_read_clock_registers(struct radeon_device *rdev)
1444 struct ci_power_info *pi = ci_get_pi(rdev);
1446 pi->clock_registers.cg_spll_func_cntl =
1447 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1448 pi->clock_registers.cg_spll_func_cntl_2 =
1449 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1450 pi->clock_registers.cg_spll_func_cntl_3 =
1451 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1452 pi->clock_registers.cg_spll_func_cntl_4 =
1453 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1454 pi->clock_registers.cg_spll_spread_spectrum =
1455 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1456 pi->clock_registers.cg_spll_spread_spectrum_2 =
1457 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1458 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1459 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1460 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1461 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1462 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1463 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1464 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1465 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1466 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1469 static void ci_init_sclk_t(struct radeon_device *rdev)
1471 struct ci_power_info *pi = ci_get_pi(rdev);
1473 pi->low_sclk_interrupt_t = 0;
1476 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1479 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1482 tmp &= ~THERMAL_PROTECTION_DIS;
1484 tmp |= THERMAL_PROTECTION_DIS;
1485 WREG32_SMC(GENERAL_PWRMGT, tmp);
1488 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1490 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1492 tmp |= STATIC_PM_EN;
1494 WREG32_SMC(GENERAL_PWRMGT, tmp);
1498 static int ci_enter_ulp_state(struct radeon_device *rdev)
1501 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1508 static int ci_exit_ulp_state(struct radeon_device *rdev)
1512 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1516 for (i = 0; i < rdev->usec_timeout; i++) {
1517 if (RREG32(SMC_RESP_0) == 1)
1526 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1529 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1531 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1534 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1537 struct ci_power_info *pi = ci_get_pi(rdev);
1540 if (pi->caps_sclk_ds) {
1541 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1544 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1548 if (pi->caps_sclk_ds) {
1549 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1557 static void ci_program_display_gap(struct radeon_device *rdev)
1559 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1560 u32 pre_vbi_time_in_us;
1561 u32 frame_time_in_us;
1562 u32 ref_clock = rdev->clock.spll.reference_freq;
1563 u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1564 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1566 tmp &= ~DISP_GAP_MASK;
1567 if (rdev->pm.dpm.new_active_crtc_count > 0)
1568 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1570 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1571 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1573 if (refresh_rate == 0)
1575 if (vblank_time == 0xffffffff)
1577 frame_time_in_us = 1000000 / refresh_rate;
1578 pre_vbi_time_in_us =
1579 frame_time_in_us - 200 - vblank_time;
1580 tmp = pre_vbi_time_in_us * (ref_clock / 100);
1582 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1583 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1584 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1587 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1591 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1593 struct ci_power_info *pi = ci_get_pi(rdev);
1597 if (pi->caps_sclk_ss_support) {
1598 tmp = RREG32_SMC(GENERAL_PWRMGT);
1599 tmp |= DYN_SPREAD_SPECTRUM_EN;
1600 WREG32_SMC(GENERAL_PWRMGT, tmp);
1603 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1605 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
1607 tmp = RREG32_SMC(GENERAL_PWRMGT);
1608 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
1609 WREG32_SMC(GENERAL_PWRMGT, tmp);
1613 static void ci_program_sstp(struct radeon_device *rdev)
1615 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
1618 static void ci_enable_display_gap(struct radeon_device *rdev)
1620 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1622 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
1623 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1624 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
1626 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1629 static void ci_program_vc(struct radeon_device *rdev)
1633 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1634 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
1635 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1637 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
1638 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
1639 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
1640 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
1641 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
1642 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
1643 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
1644 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
1647 static void ci_clear_vc(struct radeon_device *rdev)
1651 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1652 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
1653 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1655 WREG32_SMC(CG_FTV_0, 0);
1656 WREG32_SMC(CG_FTV_1, 0);
1657 WREG32_SMC(CG_FTV_2, 0);
1658 WREG32_SMC(CG_FTV_3, 0);
1659 WREG32_SMC(CG_FTV_4, 0);
1660 WREG32_SMC(CG_FTV_5, 0);
1661 WREG32_SMC(CG_FTV_6, 0);
1662 WREG32_SMC(CG_FTV_7, 0);
1665 static int ci_upload_firmware(struct radeon_device *rdev)
1667 struct ci_power_info *pi = ci_get_pi(rdev);
1670 for (i = 0; i < rdev->usec_timeout; i++) {
1671 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
1674 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
1676 ci_stop_smc_clock(rdev);
1679 ret = ci_load_smc_ucode(rdev, pi->sram_end);
1685 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
1686 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
1687 struct atom_voltage_table *voltage_table)
1691 if (voltage_dependency_table == NULL)
1694 voltage_table->mask_low = 0;
1695 voltage_table->phase_delay = 0;
1697 voltage_table->count = voltage_dependency_table->count;
1698 for (i = 0; i < voltage_table->count; i++) {
1699 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
1700 voltage_table->entries[i].smio_low = 0;
1706 static int ci_construct_voltage_tables(struct radeon_device *rdev)
1708 struct ci_power_info *pi = ci_get_pi(rdev);
1711 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1712 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
1713 VOLTAGE_OBJ_GPIO_LUT,
1714 &pi->vddc_voltage_table);
1717 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1718 ret = ci_get_svi2_voltage_table(rdev,
1719 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
1720 &pi->vddc_voltage_table);
1725 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
1726 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
1727 &pi->vddc_voltage_table);
1729 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1730 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
1731 VOLTAGE_OBJ_GPIO_LUT,
1732 &pi->vddci_voltage_table);
1735 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1736 ret = ci_get_svi2_voltage_table(rdev,
1737 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
1738 &pi->vddci_voltage_table);
1743 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
1744 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
1745 &pi->vddci_voltage_table);
1747 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1748 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
1749 VOLTAGE_OBJ_GPIO_LUT,
1750 &pi->mvdd_voltage_table);
1753 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1754 ret = ci_get_svi2_voltage_table(rdev,
1755 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
1756 &pi->mvdd_voltage_table);
1761 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
1762 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
1763 &pi->mvdd_voltage_table);
1768 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
1769 struct atom_voltage_table_entry *voltage_table,
1770 SMU7_Discrete_VoltageLevel *smc_voltage_table)
1774 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
1775 &smc_voltage_table->StdVoltageHiSidd,
1776 &smc_voltage_table->StdVoltageLoSidd);
1779 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
1780 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
1783 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
1784 smc_voltage_table->StdVoltageHiSidd =
1785 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
1786 smc_voltage_table->StdVoltageLoSidd =
1787 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
1790 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
1791 SMU7_Discrete_DpmTable *table)
1793 struct ci_power_info *pi = ci_get_pi(rdev);
1796 table->VddcLevelCount = pi->vddc_voltage_table.count;
1797 for (count = 0; count < table->VddcLevelCount; count++) {
1798 ci_populate_smc_voltage_table(rdev,
1799 &pi->vddc_voltage_table.entries[count],
1800 &table->VddcLevel[count]);
1802 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1803 table->VddcLevel[count].Smio |=
1804 pi->vddc_voltage_table.entries[count].smio_low;
1806 table->VddcLevel[count].Smio = 0;
1808 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
1813 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
1814 SMU7_Discrete_DpmTable *table)
1817 struct ci_power_info *pi = ci_get_pi(rdev);
1819 table->VddciLevelCount = pi->vddci_voltage_table.count;
1820 for (count = 0; count < table->VddciLevelCount; count++) {
1821 ci_populate_smc_voltage_table(rdev,
1822 &pi->vddci_voltage_table.entries[count],
1823 &table->VddciLevel[count]);
1825 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1826 table->VddciLevel[count].Smio |=
1827 pi->vddci_voltage_table.entries[count].smio_low;
1829 table->VddciLevel[count].Smio = 0;
1831 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
1836 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
1837 SMU7_Discrete_DpmTable *table)
1839 struct ci_power_info *pi = ci_get_pi(rdev);
1842 table->MvddLevelCount = pi->mvdd_voltage_table.count;
1843 for (count = 0; count < table->MvddLevelCount; count++) {
1844 ci_populate_smc_voltage_table(rdev,
1845 &pi->mvdd_voltage_table.entries[count],
1846 &table->MvddLevel[count]);
1848 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1849 table->MvddLevel[count].Smio |=
1850 pi->mvdd_voltage_table.entries[count].smio_low;
1852 table->MvddLevel[count].Smio = 0;
1854 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
1859 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
1860 SMU7_Discrete_DpmTable *table)
1864 ret = ci_populate_smc_vddc_table(rdev, table);
1868 ret = ci_populate_smc_vddci_table(rdev, table);
1872 ret = ci_populate_smc_mvdd_table(rdev, table);
1879 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
1880 SMU7_Discrete_VoltageLevel *voltage)
1882 struct ci_power_info *pi = ci_get_pi(rdev);
1885 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
1886 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
1887 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
1888 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
1893 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
1900 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
1901 struct atom_voltage_table_entry *voltage_table,
1902 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
1905 bool voltage_found = false;
1906 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
1907 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
1909 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
1912 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
1913 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1914 if (voltage_table->value ==
1915 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1916 voltage_found = true;
1917 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1920 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1921 *std_voltage_lo_sidd =
1922 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1923 *std_voltage_hi_sidd =
1924 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1929 if (!voltage_found) {
1930 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1931 if (voltage_table->value <=
1932 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1933 voltage_found = true;
1934 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1937 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1938 *std_voltage_lo_sidd =
1939 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1940 *std_voltage_hi_sidd =
1941 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1951 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
1952 const struct radeon_phase_shedding_limits_table *limits,
1954 u32 *phase_shedding)
1958 *phase_shedding = 1;
1960 for (i = 0; i < limits->count; i++) {
1961 if (sclk < limits->entries[i].sclk) {
1962 *phase_shedding = i;
1968 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
1969 const struct radeon_phase_shedding_limits_table *limits,
1971 u32 *phase_shedding)
1975 *phase_shedding = 1;
1977 for (i = 0; i < limits->count; i++) {
1978 if (mclk < limits->entries[i].mclk) {
1979 *phase_shedding = i;
1985 static int ci_init_arb_table_index(struct radeon_device *rdev)
1987 struct ci_power_info *pi = ci_get_pi(rdev);
1991 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
1992 &tmp, pi->sram_end);
1997 tmp |= MC_CG_ARB_FREQ_F1 << 24;
1999 return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2003 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2004 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2005 u32 clock, u32 *voltage)
2009 if (allowed_clock_voltage_table->count == 0)
2012 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2013 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2014 *voltage = allowed_clock_voltage_table->entries[i].v;
2019 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2024 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2025 u32 sclk, u32 min_sclk_in_sr)
2029 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2030 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2035 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2036 tmp = sclk / (1 << i);
2037 if (tmp >= min || i == 0)
2044 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2046 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2049 static int ci_reset_to_default(struct radeon_device *rdev)
2051 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2055 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2059 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2061 if (tmp == MC_CG_ARB_FREQ_F0)
2064 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2067 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2070 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2076 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2078 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
2079 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2080 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2082 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2083 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2084 arb_regs->McArbBurstTime = (u8)burst_time;
2089 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2091 struct ci_power_info *pi = ci_get_pi(rdev);
2092 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2096 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2098 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2099 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2100 ret = ci_populate_memory_timing_parameters(rdev,
2101 pi->dpm_table.sclk_table.dpm_levels[i].value,
2102 pi->dpm_table.mclk_table.dpm_levels[j].value,
2103 &arb_regs.entries[i][j]);
2110 ret = ci_copy_bytes_to_smc(rdev,
2111 pi->arb_table_start,
2113 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2119 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2121 struct ci_power_info *pi = ci_get_pi(rdev);
2123 if (pi->need_update_smu7_dpm_table == 0)
2126 return ci_do_program_memory_timing_parameters(rdev);
2129 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2130 struct radeon_ps *radeon_boot_state)
2132 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2133 struct ci_power_info *pi = ci_get_pi(rdev);
2136 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2137 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2138 boot_state->performance_levels[0].sclk) {
2139 pi->smc_state_table.GraphicsBootLevel = level;
2144 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2145 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2146 boot_state->performance_levels[0].mclk) {
2147 pi->smc_state_table.MemoryBootLevel = level;
2153 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2158 for (i = dpm_table->count; i > 0; i--) {
2159 mask_value = mask_value << 1;
2160 if (dpm_table->dpm_levels[i-1].enabled)
2163 mask_value &= 0xFFFFFFFE;
2169 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2170 SMU7_Discrete_DpmTable *table)
2172 struct ci_power_info *pi = ci_get_pi(rdev);
2173 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2176 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2177 table->LinkLevel[i].PcieGenSpeed =
2178 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2179 table->LinkLevel[i].PcieLaneCount =
2180 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2181 table->LinkLevel[i].EnabledForActivity = 1;
2182 table->LinkLevel[i].DownT = cpu_to_be32(5);
2183 table->LinkLevel[i].UpT = cpu_to_be32(30);
2186 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2187 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2188 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2191 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2192 SMU7_Discrete_DpmTable *table)
2195 struct atom_clock_dividers dividers;
2198 table->UvdLevelCount =
2199 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2201 for (count = 0; count < table->UvdLevelCount; count++) {
2202 table->UvdLevel[count].VclkFrequency =
2203 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2204 table->UvdLevel[count].DclkFrequency =
2205 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2206 table->UvdLevel[count].MinVddc =
2207 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2208 table->UvdLevel[count].MinVddcPhases = 1;
2210 ret = radeon_atom_get_clock_dividers(rdev,
2211 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2212 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2216 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2218 ret = radeon_atom_get_clock_dividers(rdev,
2219 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2220 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2224 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2226 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2227 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2228 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2234 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2235 SMU7_Discrete_DpmTable *table)
2238 struct atom_clock_dividers dividers;
2241 table->VceLevelCount =
2242 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2244 for (count = 0; count < table->VceLevelCount; count++) {
2245 table->VceLevel[count].Frequency =
2246 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2247 table->VceLevel[count].MinVoltage =
2248 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2249 table->VceLevel[count].MinPhases = 1;
2251 ret = radeon_atom_get_clock_dividers(rdev,
2252 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2253 table->VceLevel[count].Frequency, false, ÷rs);
2257 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2259 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2260 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2267 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2268 SMU7_Discrete_DpmTable *table)
2271 struct atom_clock_dividers dividers;
2274 table->AcpLevelCount = (u8)
2275 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2277 for (count = 0; count < table->AcpLevelCount; count++) {
2278 table->AcpLevel[count].Frequency =
2279 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2280 table->AcpLevel[count].MinVoltage =
2281 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2282 table->AcpLevel[count].MinPhases = 1;
2284 ret = radeon_atom_get_clock_dividers(rdev,
2285 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2286 table->AcpLevel[count].Frequency, false, ÷rs);
2290 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2292 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2293 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2299 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2300 SMU7_Discrete_DpmTable *table)
2303 struct atom_clock_dividers dividers;
2306 table->SamuLevelCount =
2307 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2309 for (count = 0; count < table->SamuLevelCount; count++) {
2310 table->SamuLevel[count].Frequency =
2311 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2312 table->SamuLevel[count].MinVoltage =
2313 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2314 table->SamuLevel[count].MinPhases = 1;
2316 ret = radeon_atom_get_clock_dividers(rdev,
2317 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2318 table->SamuLevel[count].Frequency, false, ÷rs);
2322 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2324 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2325 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2331 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2333 SMU7_Discrete_MemoryLevel *mclk,
2337 struct ci_power_info *pi = ci_get_pi(rdev);
2338 u32 dll_cntl = pi->clock_registers.dll_cntl;
2339 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2340 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2341 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2342 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2343 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2344 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2345 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2346 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2347 struct atom_mpll_param mpll_param;
2350 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2354 mpll_func_cntl &= ~BWCTRL_MASK;
2355 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2357 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2358 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2359 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2361 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2362 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2364 if (pi->mem_gddr5) {
2365 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2366 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2367 YCLK_POST_DIV(mpll_param.post_div);
2370 if (pi->caps_mclk_ss_support) {
2371 struct radeon_atom_ss ss;
2374 u32 reference_clock = rdev->clock.mpll.reference_freq;
2377 freq_nom = memory_clock * 4;
2379 freq_nom = memory_clock * 2;
2381 tmp = (freq_nom / reference_clock);
2383 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2384 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2385 u32 clks = reference_clock * 5 / ss.rate;
2386 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2388 mpll_ss1 &= ~CLKV_MASK;
2389 mpll_ss1 |= CLKV(clkv);
2391 mpll_ss2 &= ~CLKS_MASK;
2392 mpll_ss2 |= CLKS(clks);
2396 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2397 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2400 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2402 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2404 mclk->MclkFrequency = memory_clock;
2405 mclk->MpllFuncCntl = mpll_func_cntl;
2406 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2407 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2408 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2409 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2410 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2411 mclk->DllCntl = dll_cntl;
2412 mclk->MpllSs1 = mpll_ss1;
2413 mclk->MpllSs2 = mpll_ss2;
2418 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2420 SMU7_Discrete_MemoryLevel *memory_level)
2422 struct ci_power_info *pi = ci_get_pi(rdev);
2426 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2427 ret = ci_get_dependency_volt_by_clk(rdev,
2428 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2429 memory_clock, &memory_level->MinVddc);
2434 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2435 ret = ci_get_dependency_volt_by_clk(rdev,
2436 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2437 memory_clock, &memory_level->MinVddci);
2442 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2443 ret = ci_get_dependency_volt_by_clk(rdev,
2444 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2445 memory_clock, &memory_level->MinMvdd);
2450 memory_level->MinVddcPhases = 1;
2452 if (pi->vddc_phase_shed_control)
2453 ci_populate_phase_value_based_on_mclk(rdev,
2454 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2456 &memory_level->MinVddcPhases);
2458 memory_level->EnabledForThrottle = 1;
2459 memory_level->EnabledForActivity = 1;
2460 memory_level->UpH = 0;
2461 memory_level->DownH = 100;
2462 memory_level->VoltageDownH = 0;
2463 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2465 memory_level->StutterEnable = false;
2466 memory_level->StrobeEnable = false;
2467 memory_level->EdcReadEnable = false;
2468 memory_level->EdcWriteEnable = false;
2469 memory_level->RttEnable = false;
2471 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2473 if (pi->mclk_stutter_mode_threshold &&
2474 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2475 (pi->uvd_enabled == false) &&
2476 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2477 (rdev->pm.dpm.new_active_crtc_count <= 2))
2478 memory_level->StutterEnable = true;
2480 if (pi->mclk_strobe_mode_threshold &&
2481 (memory_clock <= pi->mclk_strobe_mode_threshold))
2482 memory_level->StrobeEnable = 1;
2484 if (pi->mem_gddr5) {
2485 memory_level->StrobeRatio =
2486 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2487 if (pi->mclk_edc_enable_threshold &&
2488 (memory_clock > pi->mclk_edc_enable_threshold))
2489 memory_level->EdcReadEnable = true;
2491 if (pi->mclk_edc_wr_enable_threshold &&
2492 (memory_clock > pi->mclk_edc_wr_enable_threshold))
2493 memory_level->EdcWriteEnable = true;
2495 if (memory_level->StrobeEnable) {
2496 if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2497 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2498 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2500 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2502 dll_state_on = pi->dll_default_on;
2505 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2506 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2509 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2513 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2514 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2515 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2516 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2518 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2519 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2520 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2521 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2522 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2523 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2524 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2525 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2526 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2527 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2528 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2533 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2534 SMU7_Discrete_DpmTable *table)
2536 struct ci_power_info *pi = ci_get_pi(rdev);
2537 struct atom_clock_dividers dividers;
2538 SMU7_Discrete_VoltageLevel voltage_level;
2539 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2540 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2541 u32 dll_cntl = pi->clock_registers.dll_cntl;
2542 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2545 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2548 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2550 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2552 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2554 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2556 ret = radeon_atom_get_clock_dividers(rdev,
2557 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2558 table->ACPILevel.SclkFrequency, false, ÷rs);
2562 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2563 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2564 table->ACPILevel.DeepSleepDivId = 0;
2566 spll_func_cntl &= ~SPLL_PWRON;
2567 spll_func_cntl |= SPLL_RESET;
2569 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2570 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
2572 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2573 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2574 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2575 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
2576 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
2577 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2578 table->ACPILevel.CcPwrDynRm = 0;
2579 table->ACPILevel.CcPwrDynRm1 = 0;
2581 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
2582 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
2583 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
2584 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
2585 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
2586 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
2587 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
2588 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
2589 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
2590 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
2591 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
2593 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
2594 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
2596 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2598 table->MemoryACPILevel.MinVddci =
2599 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
2601 table->MemoryACPILevel.MinVddci =
2602 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
2605 if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
2606 table->MemoryACPILevel.MinMvdd = 0;
2608 table->MemoryACPILevel.MinMvdd =
2609 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
2611 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
2612 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2614 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
2616 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
2617 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
2618 table->MemoryACPILevel.MpllAdFuncCntl =
2619 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
2620 table->MemoryACPILevel.MpllDqFuncCntl =
2621 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
2622 table->MemoryACPILevel.MpllFuncCntl =
2623 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
2624 table->MemoryACPILevel.MpllFuncCntl_1 =
2625 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
2626 table->MemoryACPILevel.MpllFuncCntl_2 =
2627 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
2628 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
2629 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
2631 table->MemoryACPILevel.EnabledForThrottle = 0;
2632 table->MemoryACPILevel.EnabledForActivity = 0;
2633 table->MemoryACPILevel.UpH = 0;
2634 table->MemoryACPILevel.DownH = 100;
2635 table->MemoryACPILevel.VoltageDownH = 0;
2636 table->MemoryACPILevel.ActivityLevel =
2637 cpu_to_be16((u16)pi->mclk_activity_target);
2639 table->MemoryACPILevel.StutterEnable = false;
2640 table->MemoryACPILevel.StrobeEnable = false;
2641 table->MemoryACPILevel.EdcReadEnable = false;
2642 table->MemoryACPILevel.EdcWriteEnable = false;
2643 table->MemoryACPILevel.RttEnable = false;
2649 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
2651 struct ci_power_info *pi = ci_get_pi(rdev);
2652 struct ci_ulv_parm *ulv = &pi->ulv;
2654 if (ulv->supported) {
2656 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
2659 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
2666 static int ci_populate_ulv_level(struct radeon_device *rdev,
2667 SMU7_Discrete_Ulv *state)
2669 struct ci_power_info *pi = ci_get_pi(rdev);
2670 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
2672 state->CcPwrDynRm = 0;
2673 state->CcPwrDynRm1 = 0;
2675 if (ulv_voltage == 0) {
2676 pi->ulv.supported = false;
2680 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2681 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2682 state->VddcOffset = 0;
2685 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
2687 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2688 state->VddcOffsetVid = 0;
2690 state->VddcOffsetVid = (u8)
2691 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
2692 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2694 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
2696 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
2697 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
2698 state->VddcOffset = cpu_to_be16(state->VddcOffset);
2703 static int ci_calculate_sclk_params(struct radeon_device *rdev,
2705 SMU7_Discrete_GraphicsLevel *sclk)
2707 struct ci_power_info *pi = ci_get_pi(rdev);
2708 struct atom_clock_dividers dividers;
2709 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
2710 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
2711 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
2712 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2713 u32 reference_clock = rdev->clock.spll.reference_freq;
2714 u32 reference_divider;
2718 ret = radeon_atom_get_clock_dividers(rdev,
2719 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2720 engine_clock, false, ÷rs);
2724 reference_divider = 1 + dividers.ref_div;
2725 fbdiv = dividers.fb_div & 0x3FFFFFF;
2727 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2728 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2729 spll_func_cntl_3 |= SPLL_DITHEN;
2731 if (pi->caps_sclk_ss_support) {
2732 struct radeon_atom_ss ss;
2733 u32 vco_freq = engine_clock * dividers.post_div;
2735 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2736 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2737 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2738 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2740 cg_spll_spread_spectrum &= ~CLK_S_MASK;
2741 cg_spll_spread_spectrum |= CLK_S(clk_s);
2742 cg_spll_spread_spectrum |= SSEN;
2744 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2745 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2749 sclk->SclkFrequency = engine_clock;
2750 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2751 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2752 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2753 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
2754 sclk->SclkDid = (u8)dividers.post_divider;
2759 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
2761 u16 sclk_activity_level_t,
2762 SMU7_Discrete_GraphicsLevel *graphic_level)
2764 struct ci_power_info *pi = ci_get_pi(rdev);
2767 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
2771 ret = ci_get_dependency_volt_by_clk(rdev,
2772 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2773 engine_clock, &graphic_level->MinVddc);
2777 graphic_level->SclkFrequency = engine_clock;
2779 graphic_level->Flags = 0;
2780 graphic_level->MinVddcPhases = 1;
2782 if (pi->vddc_phase_shed_control)
2783 ci_populate_phase_value_based_on_sclk(rdev,
2784 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2786 &graphic_level->MinVddcPhases);
2788 graphic_level->ActivityLevel = sclk_activity_level_t;
2790 graphic_level->CcPwrDynRm = 0;
2791 graphic_level->CcPwrDynRm1 = 0;
2792 graphic_level->EnabledForActivity = 1;
2793 graphic_level->EnabledForThrottle = 1;
2794 graphic_level->UpH = 0;
2795 graphic_level->DownH = 0;
2796 graphic_level->VoltageDownH = 0;
2797 graphic_level->PowerThrottle = 0;
2799 if (pi->caps_sclk_ds)
2800 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
2802 CISLAND_MINIMUM_ENGINE_CLOCK);
2804 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2806 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
2807 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
2808 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
2809 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
2810 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
2811 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
2812 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
2813 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
2814 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
2815 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
2816 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
2821 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
2823 struct ci_power_info *pi = ci_get_pi(rdev);
2824 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2825 u32 level_array_address = pi->dpm_table_start +
2826 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
2827 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
2828 SMU7_MAX_LEVELS_GRAPHICS;
2829 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
2832 memset(levels, 0, level_array_size);
2834 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2835 ret = ci_populate_single_graphic_level(rdev,
2836 dpm_table->sclk_table.dpm_levels[i].value,
2837 (u16)pi->activity_target[i],
2838 &pi->smc_state_table.GraphicsLevel[i]);
2841 if (i == (dpm_table->sclk_table.count - 1))
2842 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
2843 PPSMC_DISPLAY_WATERMARK_HIGH;
2846 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
2847 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
2848 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2850 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2851 (u8 *)levels, level_array_size,
2859 static int ci_populate_ulv_state(struct radeon_device *rdev,
2860 SMU7_Discrete_Ulv *ulv_level)
2862 return ci_populate_ulv_level(rdev, ulv_level);
2865 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
2867 struct ci_power_info *pi = ci_get_pi(rdev);
2868 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2869 u32 level_array_address = pi->dpm_table_start +
2870 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
2871 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
2872 SMU7_MAX_LEVELS_MEMORY;
2873 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
2876 memset(levels, 0, level_array_size);
2878 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2879 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
2881 ret = ci_populate_single_memory_level(rdev,
2882 dpm_table->mclk_table.dpm_levels[i].value,
2883 &pi->smc_state_table.MemoryLevel[i]);
2888 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
2890 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
2891 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
2892 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2894 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
2895 PPSMC_DISPLAY_WATERMARK_HIGH;
2897 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2898 (u8 *)levels, level_array_size,
2906 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
2907 struct ci_single_dpm_table* dpm_table,
2912 dpm_table->count = count;
2913 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
2914 dpm_table->dpm_levels[i].enabled = false;
2917 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
2918 u32 index, u32 pcie_gen, u32 pcie_lanes)
2920 dpm_table->dpm_levels[index].value = pcie_gen;
2921 dpm_table->dpm_levels[index].param1 = pcie_lanes;
2922 dpm_table->dpm_levels[index].enabled = true;
2925 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
2927 struct ci_power_info *pi = ci_get_pi(rdev);
2929 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
2932 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
2933 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
2934 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
2935 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
2936 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
2937 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
2940 ci_reset_single_dpm_table(rdev,
2941 &pi->dpm_table.pcie_speed_table,
2942 SMU7_MAX_LEVELS_LINK);
2944 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
2945 pi->pcie_gen_powersaving.min,
2946 pi->pcie_lane_powersaving.min);
2947 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
2948 pi->pcie_gen_performance.min,
2949 pi->pcie_lane_performance.min);
2950 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
2951 pi->pcie_gen_powersaving.min,
2952 pi->pcie_lane_powersaving.max);
2953 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
2954 pi->pcie_gen_performance.min,
2955 pi->pcie_lane_performance.max);
2956 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
2957 pi->pcie_gen_powersaving.max,
2958 pi->pcie_lane_powersaving.max);
2959 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
2960 pi->pcie_gen_performance.max,
2961 pi->pcie_lane_performance.max);
2963 pi->dpm_table.pcie_speed_table.count = 6;
2968 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
2970 struct ci_power_info *pi = ci_get_pi(rdev);
2971 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
2972 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2973 struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
2974 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
2975 struct radeon_cac_leakage_table *std_voltage_table =
2976 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2979 if (allowed_sclk_vddc_table == NULL)
2981 if (allowed_sclk_vddc_table->count < 1)
2983 if (allowed_mclk_table == NULL)
2985 if (allowed_mclk_table->count < 1)
2988 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
2990 ci_reset_single_dpm_table(rdev,
2991 &pi->dpm_table.sclk_table,
2992 SMU7_MAX_LEVELS_GRAPHICS);
2993 ci_reset_single_dpm_table(rdev,
2994 &pi->dpm_table.mclk_table,
2995 SMU7_MAX_LEVELS_MEMORY);
2996 ci_reset_single_dpm_table(rdev,
2997 &pi->dpm_table.vddc_table,
2998 SMU7_MAX_LEVELS_VDDC);
2999 ci_reset_single_dpm_table(rdev,
3000 &pi->dpm_table.vddci_table,
3001 SMU7_MAX_LEVELS_VDDCI);
3002 ci_reset_single_dpm_table(rdev,
3003 &pi->dpm_table.mvdd_table,
3004 SMU7_MAX_LEVELS_MVDD);
3006 pi->dpm_table.sclk_table.count = 0;
3007 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3009 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3010 allowed_sclk_vddc_table->entries[i].clk)) {
3011 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3012 allowed_sclk_vddc_table->entries[i].clk;
3013 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true;
3014 pi->dpm_table.sclk_table.count++;
3018 pi->dpm_table.mclk_table.count = 0;
3019 for (i = 0; i < allowed_mclk_table->count; i++) {
3021 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3022 allowed_mclk_table->entries[i].clk)) {
3023 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3024 allowed_mclk_table->entries[i].clk;
3025 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true;
3026 pi->dpm_table.mclk_table.count++;
3030 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3031 pi->dpm_table.vddc_table.dpm_levels[i].value =
3032 allowed_sclk_vddc_table->entries[i].v;
3033 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3034 std_voltage_table->entries[i].leakage;
3035 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3037 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3039 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3040 if (allowed_mclk_table) {
3041 for (i = 0; i < allowed_mclk_table->count; i++) {
3042 pi->dpm_table.vddci_table.dpm_levels[i].value =
3043 allowed_mclk_table->entries[i].v;
3044 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3046 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3049 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3050 if (allowed_mclk_table) {
3051 for (i = 0; i < allowed_mclk_table->count; i++) {
3052 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3053 allowed_mclk_table->entries[i].v;
3054 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3056 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3059 ci_setup_default_pcie_tables(rdev);
3064 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3065 u32 value, u32 *boot_level)
3070 for(i = 0; i < table->count; i++) {
3071 if (value == table->dpm_levels[i].value) {
3080 static int ci_init_smc_table(struct radeon_device *rdev)
3082 struct ci_power_info *pi = ci_get_pi(rdev);
3083 struct ci_ulv_parm *ulv = &pi->ulv;
3084 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3085 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3088 ret = ci_setup_default_dpm_tables(rdev);
3092 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3093 ci_populate_smc_voltage_tables(rdev, table);
3095 ci_init_fps_limits(rdev);
3097 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3098 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3100 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3101 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3104 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3106 if (ulv->supported) {
3107 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3110 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3113 ret = ci_populate_all_graphic_levels(rdev);
3117 ret = ci_populate_all_memory_levels(rdev);
3121 ci_populate_smc_link_level(rdev, table);
3123 ret = ci_populate_smc_acpi_level(rdev, table);
3127 ret = ci_populate_smc_vce_level(rdev, table);
3131 ret = ci_populate_smc_acp_level(rdev, table);
3135 ret = ci_populate_smc_samu_level(rdev, table);
3139 ret = ci_do_program_memory_timing_parameters(rdev);
3143 ret = ci_populate_smc_uvd_level(rdev, table);
3147 table->UvdBootLevel = 0;
3148 table->VceBootLevel = 0;
3149 table->AcpBootLevel = 0;
3150 table->SamuBootLevel = 0;
3151 table->GraphicsBootLevel = 0;
3152 table->MemoryBootLevel = 0;
3154 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3155 pi->vbios_boot_state.sclk_bootup_value,
3156 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3158 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3159 pi->vbios_boot_state.mclk_bootup_value,
3160 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3162 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3163 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3164 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3166 ci_populate_smc_initial_state(rdev, radeon_boot_state);
3168 ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3172 table->UVDInterval = 1;
3173 table->VCEInterval = 1;
3174 table->ACPInterval = 1;
3175 table->SAMUInterval = 1;
3176 table->GraphicsVoltageChangeEnable = 1;
3177 table->GraphicsThermThrottleEnable = 1;
3178 table->GraphicsInterval = 1;
3179 table->VoltageInterval = 1;
3180 table->ThermalInterval = 1;
3181 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3182 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3183 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3184 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3185 table->MemoryVoltageChangeEnable = 1;
3186 table->MemoryInterval = 1;
3187 table->VoltageResponseTime = 0;
3188 table->VddcVddciDelta = 4000;
3189 table->PhaseResponseTime = 0;
3190 table->MemoryThermThrottleEnable = 1;
3191 table->PCIeBootLinkLevel = 0;
3192 table->PCIeGenInterval = 1;
3193 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3194 table->SVI2Enable = 1;
3196 table->SVI2Enable = 0;
3198 table->ThermGpio = 17;
3199 table->SclkStepSize = 0x4000;
3201 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3202 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3203 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3204 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3205 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3206 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3207 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3208 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3209 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3210 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3211 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3212 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3213 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3214 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3216 ret = ci_copy_bytes_to_smc(rdev,
3217 pi->dpm_table_start +
3218 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3219 (u8 *)&table->SystemFlags,
3220 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3228 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3229 struct ci_single_dpm_table *dpm_table,
3230 u32 low_limit, u32 high_limit)
3234 for (i = 0; i < dpm_table->count; i++) {
3235 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3236 (dpm_table->dpm_levels[i].value > high_limit))
3237 dpm_table->dpm_levels[i].enabled = false;
3239 dpm_table->dpm_levels[i].enabled = true;
3243 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3244 u32 speed_low, u32 lanes_low,
3245 u32 speed_high, u32 lanes_high)
3247 struct ci_power_info *pi = ci_get_pi(rdev);
3248 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3251 for (i = 0; i < pcie_table->count; i++) {
3252 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3253 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3254 (pcie_table->dpm_levels[i].value > speed_high) ||
3255 (pcie_table->dpm_levels[i].param1 > lanes_high))
3256 pcie_table->dpm_levels[i].enabled = false;
3258 pcie_table->dpm_levels[i].enabled = true;
3261 for (i = 0; i < pcie_table->count; i++) {
3262 if (pcie_table->dpm_levels[i].enabled) {
3263 for (j = i + 1; j < pcie_table->count; j++) {
3264 if (pcie_table->dpm_levels[j].enabled) {
3265 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3266 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3267 pcie_table->dpm_levels[j].enabled = false;
3274 static int ci_trim_dpm_states(struct radeon_device *rdev,
3275 struct radeon_ps *radeon_state)
3277 struct ci_ps *state = ci_get_ps(radeon_state);
3278 struct ci_power_info *pi = ci_get_pi(rdev);
3279 u32 high_limit_count;
3281 if (state->performance_level_count < 1)
3284 if (state->performance_level_count == 1)
3285 high_limit_count = 0;
3287 high_limit_count = 1;
3289 ci_trim_single_dpm_states(rdev,
3290 &pi->dpm_table.sclk_table,
3291 state->performance_levels[0].sclk,
3292 state->performance_levels[high_limit_count].sclk);
3294 ci_trim_single_dpm_states(rdev,
3295 &pi->dpm_table.mclk_table,
3296 state->performance_levels[0].mclk,
3297 state->performance_levels[high_limit_count].mclk);
3299 ci_trim_pcie_dpm_states(rdev,
3300 state->performance_levels[0].pcie_gen,
3301 state->performance_levels[0].pcie_lane,
3302 state->performance_levels[high_limit_count].pcie_gen,
3303 state->performance_levels[high_limit_count].pcie_lane);
3308 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3310 struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3311 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3312 struct radeon_clock_voltage_dependency_table *vddc_table =
3313 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3314 u32 requested_voltage = 0;
3317 if (disp_voltage_table == NULL)
3319 if (!disp_voltage_table->count)
3322 for (i = 0; i < disp_voltage_table->count; i++) {
3323 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3324 requested_voltage = disp_voltage_table->entries[i].v;
3327 for (i = 0; i < vddc_table->count; i++) {
3328 if (requested_voltage <= vddc_table->entries[i].v) {
3329 requested_voltage = vddc_table->entries[i].v;
3330 return (ci_send_msg_to_smc_with_parameter(rdev,
3331 PPSMC_MSG_VddC_Request,
3332 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3340 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3342 struct ci_power_info *pi = ci_get_pi(rdev);
3343 PPSMC_Result result;
3345 if (!pi->sclk_dpm_key_disabled) {
3346 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3347 result = ci_send_msg_to_smc_with_parameter(rdev,
3348 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3349 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3350 if (result != PPSMC_Result_OK)
3355 if (!pi->mclk_dpm_key_disabled) {
3356 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3357 result = ci_send_msg_to_smc_with_parameter(rdev,
3358 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3359 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3360 if (result != PPSMC_Result_OK)
3365 if (!pi->pcie_dpm_key_disabled) {
3366 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3367 result = ci_send_msg_to_smc_with_parameter(rdev,
3368 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3369 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3370 if (result != PPSMC_Result_OK)
3375 ci_apply_disp_minimum_voltage_request(rdev);
3380 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3381 struct radeon_ps *radeon_state)
3383 struct ci_power_info *pi = ci_get_pi(rdev);
3384 struct ci_ps *state = ci_get_ps(radeon_state);
3385 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3386 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3387 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3388 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3391 pi->need_update_smu7_dpm_table = 0;
3393 for (i = 0; i < sclk_table->count; i++) {
3394 if (sclk == sclk_table->dpm_levels[i].value)
3398 if (i >= sclk_table->count) {
3399 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3401 /* XXX check display min clock requirements */
3402 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK)
3403 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3406 for (i = 0; i < mclk_table->count; i++) {
3407 if (mclk == mclk_table->dpm_levels[i].value)
3411 if (i >= mclk_table->count)
3412 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3414 if (rdev->pm.dpm.current_active_crtc_count !=
3415 rdev->pm.dpm.new_active_crtc_count)
3416 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3419 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3420 struct radeon_ps *radeon_state)
3422 struct ci_power_info *pi = ci_get_pi(rdev);
3423 struct ci_ps *state = ci_get_ps(radeon_state);
3424 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3425 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3426 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3429 if (!pi->need_update_smu7_dpm_table)
3432 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3433 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3435 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3436 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3438 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3439 ret = ci_populate_all_graphic_levels(rdev);
3444 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3445 ret = ci_populate_all_memory_levels(rdev);
3453 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3455 struct ci_power_info *pi = ci_get_pi(rdev);
3456 const struct radeon_clock_and_voltage_limits *max_limits;
3459 if (rdev->pm.dpm.ac_power)
3460 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3462 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3465 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3467 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3468 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3469 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3471 if (!pi->caps_uvd_dpm)
3476 ci_send_msg_to_smc_with_parameter(rdev,
3477 PPSMC_MSG_UVDDPM_SetEnabledMask,
3478 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3480 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3481 pi->uvd_enabled = true;
3482 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3483 ci_send_msg_to_smc_with_parameter(rdev,
3484 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3485 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3488 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3489 pi->uvd_enabled = false;
3490 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3491 ci_send_msg_to_smc_with_parameter(rdev,
3492 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3493 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3497 return (ci_send_msg_to_smc(rdev, enable ?
3498 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3502 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3504 struct ci_power_info *pi = ci_get_pi(rdev);
3505 const struct radeon_clock_and_voltage_limits *max_limits;
3508 if (rdev->pm.dpm.ac_power)
3509 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3511 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3514 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3515 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3516 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3517 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3519 if (!pi->caps_vce_dpm)
3524 ci_send_msg_to_smc_with_parameter(rdev,
3525 PPSMC_MSG_VCEDPM_SetEnabledMask,
3526 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3529 return (ci_send_msg_to_smc(rdev, enable ?
3530 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3535 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3537 struct ci_power_info *pi = ci_get_pi(rdev);
3538 const struct radeon_clock_and_voltage_limits *max_limits;
3541 if (rdev->pm.dpm.ac_power)
3542 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3544 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3547 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3548 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3549 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3550 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3552 if (!pi->caps_samu_dpm)
3557 ci_send_msg_to_smc_with_parameter(rdev,
3558 PPSMC_MSG_SAMUDPM_SetEnabledMask,
3559 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
3561 return (ci_send_msg_to_smc(rdev, enable ?
3562 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
3566 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
3568 struct ci_power_info *pi = ci_get_pi(rdev);
3569 const struct radeon_clock_and_voltage_limits *max_limits;
3572 if (rdev->pm.dpm.ac_power)
3573 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3575 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3578 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
3579 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3580 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3581 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
3583 if (!pi->caps_acp_dpm)
3588 ci_send_msg_to_smc_with_parameter(rdev,
3589 PPSMC_MSG_ACPDPM_SetEnabledMask,
3590 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
3593 return (ci_send_msg_to_smc(rdev, enable ?
3594 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
3599 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
3601 struct ci_power_info *pi = ci_get_pi(rdev);
3605 if (pi->caps_uvd_dpm ||
3606 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
3607 pi->smc_state_table.UvdBootLevel = 0;
3609 pi->smc_state_table.UvdBootLevel =
3610 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
3612 tmp = RREG32_SMC(DPM_TABLE_475);
3613 tmp &= ~UvdBootLevel_MASK;
3614 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
3615 WREG32_SMC(DPM_TABLE_475, tmp);
3618 return ci_enable_uvd_dpm(rdev, !gate);
3621 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
3624 u32 min_evclk = 30000; /* ??? */
3625 struct radeon_vce_clock_voltage_dependency_table *table =
3626 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3628 for (i = 0; i < table->count; i++) {
3629 if (table->entries[i].evclk >= min_evclk)
3633 return table->count - 1;
3636 static int ci_update_vce_dpm(struct radeon_device *rdev,
3637 struct radeon_ps *radeon_new_state,
3638 struct radeon_ps *radeon_current_state)
3640 struct ci_power_info *pi = ci_get_pi(rdev);
3644 if (radeon_current_state->evclk != radeon_new_state->evclk) {
3645 if (radeon_new_state->evclk) {
3646 /* turn the clocks on when encoding */
3647 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
3649 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
3650 tmp = RREG32_SMC(DPM_TABLE_475);
3651 tmp &= ~VceBootLevel_MASK;
3652 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
3653 WREG32_SMC(DPM_TABLE_475, tmp);
3655 ret = ci_enable_vce_dpm(rdev, true);
3657 /* turn the clocks off when not encoding */
3658 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
3660 ret = ci_enable_vce_dpm(rdev, false);
3667 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
3669 return ci_enable_samu_dpm(rdev, gate);
3672 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
3674 struct ci_power_info *pi = ci_get_pi(rdev);
3678 pi->smc_state_table.AcpBootLevel = 0;
3680 tmp = RREG32_SMC(DPM_TABLE_475);
3681 tmp &= ~AcpBootLevel_MASK;
3682 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
3683 WREG32_SMC(DPM_TABLE_475, tmp);
3686 return ci_enable_acp_dpm(rdev, !gate);
3690 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
3691 struct radeon_ps *radeon_state)
3693 struct ci_power_info *pi = ci_get_pi(rdev);
3696 ret = ci_trim_dpm_states(rdev, radeon_state);
3700 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3701 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
3702 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3703 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
3704 pi->last_mclk_dpm_enable_mask =
3705 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3706 if (pi->uvd_enabled) {
3707 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
3708 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3710 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
3711 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
3716 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
3721 while ((level_mask & (1 << level)) == 0)
3728 int ci_dpm_force_performance_level(struct radeon_device *rdev,
3729 enum radeon_dpm_forced_level level)
3731 struct ci_power_info *pi = ci_get_pi(rdev);
3732 PPSMC_Result smc_result;
3736 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3737 if ((!pi->sclk_dpm_key_disabled) &&
3738 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3740 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
3744 ret = ci_dpm_force_state_sclk(rdev, levels);
3747 for (i = 0; i < rdev->usec_timeout; i++) {
3748 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3749 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3756 if ((!pi->mclk_dpm_key_disabled) &&
3757 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3759 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3763 ret = ci_dpm_force_state_mclk(rdev, levels);
3766 for (i = 0; i < rdev->usec_timeout; i++) {
3767 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3768 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3775 if ((!pi->pcie_dpm_key_disabled) &&
3776 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3778 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
3782 ret = ci_dpm_force_state_pcie(rdev, level);
3785 for (i = 0; i < rdev->usec_timeout; i++) {
3786 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3787 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3794 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3795 if ((!pi->sclk_dpm_key_disabled) &&
3796 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3797 levels = ci_get_lowest_enabled_level(rdev,
3798 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3799 ret = ci_dpm_force_state_sclk(rdev, levels);
3802 for (i = 0; i < rdev->usec_timeout; i++) {
3803 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3804 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3810 if ((!pi->mclk_dpm_key_disabled) &&
3811 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3812 levels = ci_get_lowest_enabled_level(rdev,
3813 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3814 ret = ci_dpm_force_state_mclk(rdev, levels);
3817 for (i = 0; i < rdev->usec_timeout; i++) {
3818 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3819 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3825 if ((!pi->pcie_dpm_key_disabled) &&
3826 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3827 levels = ci_get_lowest_enabled_level(rdev,
3828 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3829 ret = ci_dpm_force_state_pcie(rdev, levels);
3832 for (i = 0; i < rdev->usec_timeout; i++) {
3833 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3834 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3840 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3841 if (!pi->sclk_dpm_key_disabled) {
3842 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel);
3843 if (smc_result != PPSMC_Result_OK)
3846 if (!pi->mclk_dpm_key_disabled) {
3847 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_NoForcedLevel);
3848 if (smc_result != PPSMC_Result_OK)
3851 if (!pi->pcie_dpm_key_disabled) {
3852 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_UnForceLevel);
3853 if (smc_result != PPSMC_Result_OK)
3858 rdev->pm.dpm.forced_level = level;
3863 static int ci_set_mc_special_registers(struct radeon_device *rdev,
3864 struct ci_mc_reg_table *table)
3866 struct ci_power_info *pi = ci_get_pi(rdev);
3870 for (i = 0, j = table->last; i < table->last; i++) {
3871 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3873 switch(table->mc_reg_address[i].s1 << 2) {
3875 temp_reg = RREG32(MC_PMG_CMD_EMRS);
3876 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
3877 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3878 for (k = 0; k < table->num_entries; k++) {
3879 table->mc_reg_table_entry[k].mc_data[j] =
3880 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3883 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3886 temp_reg = RREG32(MC_PMG_CMD_MRS);
3887 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
3888 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3889 for (k = 0; k < table->num_entries; k++) {
3890 table->mc_reg_table_entry[k].mc_data[j] =
3891 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3893 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3896 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3899 if (!pi->mem_gddr5) {
3900 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
3901 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
3902 for (k = 0; k < table->num_entries; k++) {
3903 table->mc_reg_table_entry[k].mc_data[j] =
3904 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3907 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3911 case MC_SEQ_RESERVE_M:
3912 temp_reg = RREG32(MC_PMG_CMD_MRS1);
3913 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
3914 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3915 for (k = 0; k < table->num_entries; k++) {
3916 table->mc_reg_table_entry[k].mc_data[j] =
3917 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3920 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3934 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
3939 case MC_SEQ_RAS_TIMING >> 2:
3940 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
3942 case MC_SEQ_DLL_STBY >> 2:
3943 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
3945 case MC_SEQ_G5PDX_CMD0 >> 2:
3946 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
3948 case MC_SEQ_G5PDX_CMD1 >> 2:
3949 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
3951 case MC_SEQ_G5PDX_CTRL >> 2:
3952 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
3954 case MC_SEQ_CAS_TIMING >> 2:
3955 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
3957 case MC_SEQ_MISC_TIMING >> 2:
3958 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
3960 case MC_SEQ_MISC_TIMING2 >> 2:
3961 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
3963 case MC_SEQ_PMG_DVS_CMD >> 2:
3964 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
3966 case MC_SEQ_PMG_DVS_CTL >> 2:
3967 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
3969 case MC_SEQ_RD_CTL_D0 >> 2:
3970 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
3972 case MC_SEQ_RD_CTL_D1 >> 2:
3973 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
3975 case MC_SEQ_WR_CTL_D0 >> 2:
3976 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
3978 case MC_SEQ_WR_CTL_D1 >> 2:
3979 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
3981 case MC_PMG_CMD_EMRS >> 2:
3982 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3984 case MC_PMG_CMD_MRS >> 2:
3985 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3987 case MC_PMG_CMD_MRS1 >> 2:
3988 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3990 case MC_SEQ_PMG_TIMING >> 2:
3991 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
3993 case MC_PMG_CMD_MRS2 >> 2:
3994 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
3996 case MC_SEQ_WR_CTL_2 >> 2:
3997 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
4007 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4011 for (i = 0; i < table->last; i++) {
4012 for (j = 1; j < table->num_entries; j++) {
4013 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4014 table->mc_reg_table_entry[j].mc_data[i]) {
4015 table->valid_flag |= 1 << i;
4022 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4027 for (i = 0; i < table->last; i++) {
4028 table->mc_reg_address[i].s0 =
4029 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4030 address : table->mc_reg_address[i].s1;
4034 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4035 struct ci_mc_reg_table *ci_table)
4039 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4041 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4044 for (i = 0; i < table->last; i++)
4045 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4047 ci_table->last = table->last;
4049 for (i = 0; i < table->num_entries; i++) {
4050 ci_table->mc_reg_table_entry[i].mclk_max =
4051 table->mc_reg_table_entry[i].mclk_max;
4052 for (j = 0; j < table->last; j++)
4053 ci_table->mc_reg_table_entry[i].mc_data[j] =
4054 table->mc_reg_table_entry[i].mc_data[j];
4056 ci_table->num_entries = table->num_entries;
4061 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4063 struct ci_power_info *pi = ci_get_pi(rdev);
4064 struct atom_mc_reg_table *table;
4065 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4066 u8 module_index = rv770_get_memory_module_index(rdev);
4069 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4073 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4074 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4075 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4076 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4077 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4078 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4079 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4080 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4081 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4082 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4083 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4084 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4085 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4086 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4087 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4088 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4089 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4090 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4091 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4092 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4094 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4098 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4102 ci_set_s0_mc_reg_index(ci_table);
4104 ret = ci_set_mc_special_registers(rdev, ci_table);
4108 ci_set_valid_flag(ci_table);
4116 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4117 SMU7_Discrete_MCRegisters *mc_reg_table)
4119 struct ci_power_info *pi = ci_get_pi(rdev);
4122 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4123 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4124 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4126 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4127 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4132 mc_reg_table->last = (u8)i;
4137 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4138 SMU7_Discrete_MCRegisterSet *data,
4139 u32 num_entries, u32 valid_flag)
4143 for (i = 0, j = 0; j < num_entries; j++) {
4144 if (valid_flag & (1 << j)) {
4145 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4151 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4152 const u32 memory_clock,
4153 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4155 struct ci_power_info *pi = ci_get_pi(rdev);
4158 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4159 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4163 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4166 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4167 mc_reg_table_data, pi->mc_reg_table.last,
4168 pi->mc_reg_table.valid_flag);
4171 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4172 SMU7_Discrete_MCRegisters *mc_reg_table)
4174 struct ci_power_info *pi = ci_get_pi(rdev);
4177 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4178 ci_convert_mc_reg_table_entry_to_smc(rdev,
4179 pi->dpm_table.mclk_table.dpm_levels[i].value,
4180 &mc_reg_table->data[i]);
4183 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4185 struct ci_power_info *pi = ci_get_pi(rdev);
4188 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4190 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4193 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4195 return ci_copy_bytes_to_smc(rdev,
4196 pi->mc_reg_table_start,
4197 (u8 *)&pi->smc_mc_reg_table,
4198 sizeof(SMU7_Discrete_MCRegisters),
4202 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4204 struct ci_power_info *pi = ci_get_pi(rdev);
4206 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4209 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4211 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4213 return ci_copy_bytes_to_smc(rdev,
4214 pi->mc_reg_table_start +
4215 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4216 (u8 *)&pi->smc_mc_reg_table.data[0],
4217 sizeof(SMU7_Discrete_MCRegisterSet) *
4218 pi->dpm_table.mclk_table.count,
4222 static void ci_enable_voltage_control(struct radeon_device *rdev)
4224 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4226 tmp |= VOLT_PWRMGT_EN;
4227 WREG32_SMC(GENERAL_PWRMGT, tmp);
4230 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4231 struct radeon_ps *radeon_state)
4233 struct ci_ps *state = ci_get_ps(radeon_state);
4235 u16 pcie_speed, max_speed = 0;
4237 for (i = 0; i < state->performance_level_count; i++) {
4238 pcie_speed = state->performance_levels[i].pcie_gen;
4239 if (max_speed < pcie_speed)
4240 max_speed = pcie_speed;
4246 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4250 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4251 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4253 return (u16)speed_cntl;
4256 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4260 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4261 link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4263 switch (link_width) {
4264 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4266 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4268 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4270 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4272 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4273 /* not actually supported */
4275 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4276 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4282 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4283 struct radeon_ps *radeon_new_state,
4284 struct radeon_ps *radeon_current_state)
4286 struct ci_power_info *pi = ci_get_pi(rdev);
4287 enum radeon_pcie_gen target_link_speed =
4288 ci_get_maximum_link_speed(rdev, radeon_new_state);
4289 enum radeon_pcie_gen current_link_speed;
4291 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4292 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4294 current_link_speed = pi->force_pcie_gen;
4296 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4297 pi->pspp_notify_required = false;
4298 if (target_link_speed > current_link_speed) {
4299 switch (target_link_speed) {
4301 case RADEON_PCIE_GEN3:
4302 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4304 pi->force_pcie_gen = RADEON_PCIE_GEN2;
4305 if (current_link_speed == RADEON_PCIE_GEN2)
4307 case RADEON_PCIE_GEN2:
4308 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4312 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4316 if (target_link_speed < current_link_speed)
4317 pi->pspp_notify_required = true;
4321 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4322 struct radeon_ps *radeon_new_state,
4323 struct radeon_ps *radeon_current_state)
4325 struct ci_power_info *pi = ci_get_pi(rdev);
4326 enum radeon_pcie_gen target_link_speed =
4327 ci_get_maximum_link_speed(rdev, radeon_new_state);
4330 if (pi->pspp_notify_required) {
4331 if (target_link_speed == RADEON_PCIE_GEN3)
4332 request = PCIE_PERF_REQ_PECI_GEN3;
4333 else if (target_link_speed == RADEON_PCIE_GEN2)
4334 request = PCIE_PERF_REQ_PECI_GEN2;
4336 request = PCIE_PERF_REQ_PECI_GEN1;
4338 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4339 (ci_get_current_pcie_speed(rdev) > 0))
4343 radeon_acpi_pcie_performance_request(rdev, request, false);
4348 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4350 struct ci_power_info *pi = ci_get_pi(rdev);
4351 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4352 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4353 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4354 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4355 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4356 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4358 if (allowed_sclk_vddc_table == NULL)
4360 if (allowed_sclk_vddc_table->count < 1)
4362 if (allowed_mclk_vddc_table == NULL)
4364 if (allowed_mclk_vddc_table->count < 1)
4366 if (allowed_mclk_vddci_table == NULL)
4368 if (allowed_mclk_vddci_table->count < 1)
4371 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4372 pi->max_vddc_in_pp_table =
4373 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4375 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4376 pi->max_vddci_in_pp_table =
4377 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4379 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4380 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4381 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4382 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4383 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4384 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4385 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4386 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4391 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4393 struct ci_power_info *pi = ci_get_pi(rdev);
4394 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4397 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4398 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4399 *vddc = leakage_table->actual_voltage[leakage_index];
4405 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4407 struct ci_power_info *pi = ci_get_pi(rdev);
4408 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4411 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4412 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4413 *vddci = leakage_table->actual_voltage[leakage_index];
4419 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4420 struct radeon_clock_voltage_dependency_table *table)
4425 for (i = 0; i < table->count; i++)
4426 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4430 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4431 struct radeon_clock_voltage_dependency_table *table)
4436 for (i = 0; i < table->count; i++)
4437 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4441 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4442 struct radeon_vce_clock_voltage_dependency_table *table)
4447 for (i = 0; i < table->count; i++)
4448 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4452 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4453 struct radeon_uvd_clock_voltage_dependency_table *table)
4458 for (i = 0; i < table->count; i++)
4459 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4463 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
4464 struct radeon_phase_shedding_limits_table *table)
4469 for (i = 0; i < table->count; i++)
4470 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
4474 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
4475 struct radeon_clock_and_voltage_limits *table)
4478 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
4479 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
4483 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
4484 struct radeon_cac_leakage_table *table)
4489 for (i = 0; i < table->count; i++)
4490 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
4494 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
4497 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4498 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
4499 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4500 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
4501 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4502 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
4503 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
4504 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
4505 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4506 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
4507 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4508 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
4509 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4510 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
4511 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4512 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
4513 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
4514 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
4515 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4516 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
4517 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4518 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
4519 ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
4520 &rdev->pm.dpm.dyn_state.cac_leakage_table);
4524 static void ci_get_memory_type(struct radeon_device *rdev)
4526 struct ci_power_info *pi = ci_get_pi(rdev);
4529 tmp = RREG32(MC_SEQ_MISC0);
4531 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
4532 MC_SEQ_MISC0_GDDR5_VALUE)
4533 pi->mem_gddr5 = true;
4535 pi->mem_gddr5 = false;
4539 static void ci_update_current_ps(struct radeon_device *rdev,
4540 struct radeon_ps *rps)
4542 struct ci_ps *new_ps = ci_get_ps(rps);
4543 struct ci_power_info *pi = ci_get_pi(rdev);
4545 pi->current_rps = *rps;
4546 pi->current_ps = *new_ps;
4547 pi->current_rps.ps_priv = &pi->current_ps;
4550 static void ci_update_requested_ps(struct radeon_device *rdev,
4551 struct radeon_ps *rps)
4553 struct ci_ps *new_ps = ci_get_ps(rps);
4554 struct ci_power_info *pi = ci_get_pi(rdev);
4556 pi->requested_rps = *rps;
4557 pi->requested_ps = *new_ps;
4558 pi->requested_rps.ps_priv = &pi->requested_ps;
4561 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
4563 struct ci_power_info *pi = ci_get_pi(rdev);
4564 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
4565 struct radeon_ps *new_ps = &requested_ps;
4567 ci_update_requested_ps(rdev, new_ps);
4569 ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
4574 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
4576 struct ci_power_info *pi = ci_get_pi(rdev);
4577 struct radeon_ps *new_ps = &pi->requested_rps;
4579 ci_update_current_ps(rdev, new_ps);
4583 void ci_dpm_setup_asic(struct radeon_device *rdev)
4587 r = ci_mc_load_microcode(rdev);
4589 DRM_ERROR("Failed to load MC firmware!\n");
4590 ci_read_clock_registers(rdev);
4591 ci_get_memory_type(rdev);
4592 ci_enable_acpi_power_management(rdev);
4593 ci_init_sclk_t(rdev);
4596 int ci_dpm_enable(struct radeon_device *rdev)
4598 struct ci_power_info *pi = ci_get_pi(rdev);
4599 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4602 if (ci_is_smc_running(rdev))
4604 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
4605 ci_enable_voltage_control(rdev);
4606 ret = ci_construct_voltage_tables(rdev);
4608 DRM_ERROR("ci_construct_voltage_tables failed\n");
4612 if (pi->caps_dynamic_ac_timing) {
4613 ret = ci_initialize_mc_reg_table(rdev);
4615 pi->caps_dynamic_ac_timing = false;
4618 ci_enable_spread_spectrum(rdev, true);
4619 if (pi->thermal_protection)
4620 ci_enable_thermal_protection(rdev, true);
4621 ci_program_sstp(rdev);
4622 ci_enable_display_gap(rdev);
4623 ci_program_vc(rdev);
4624 ret = ci_upload_firmware(rdev);
4626 DRM_ERROR("ci_upload_firmware failed\n");
4629 ret = ci_process_firmware_header(rdev);
4631 DRM_ERROR("ci_process_firmware_header failed\n");
4634 ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
4636 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
4639 ret = ci_init_smc_table(rdev);
4641 DRM_ERROR("ci_init_smc_table failed\n");
4644 ret = ci_init_arb_table_index(rdev);
4646 DRM_ERROR("ci_init_arb_table_index failed\n");
4649 if (pi->caps_dynamic_ac_timing) {
4650 ret = ci_populate_initial_mc_reg_table(rdev);
4652 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
4656 ret = ci_populate_pm_base(rdev);
4658 DRM_ERROR("ci_populate_pm_base failed\n");
4661 ci_dpm_start_smc(rdev);
4662 ci_enable_vr_hot_gpio_interrupt(rdev);
4663 ret = ci_notify_smc_display_change(rdev, false);
4665 DRM_ERROR("ci_notify_smc_display_change failed\n");
4668 ci_enable_sclk_control(rdev, true);
4669 ret = ci_enable_ulv(rdev, true);
4671 DRM_ERROR("ci_enable_ulv failed\n");
4674 ret = ci_enable_ds_master_switch(rdev, true);
4676 DRM_ERROR("ci_enable_ds_master_switch failed\n");
4679 ret = ci_start_dpm(rdev);
4681 DRM_ERROR("ci_start_dpm failed\n");
4684 ret = ci_enable_didt(rdev, true);
4686 DRM_ERROR("ci_enable_didt failed\n");
4689 ret = ci_enable_smc_cac(rdev, true);
4691 DRM_ERROR("ci_enable_smc_cac failed\n");
4694 ret = ci_enable_power_containment(rdev, true);
4696 DRM_ERROR("ci_enable_power_containment failed\n");
4700 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
4702 ci_update_current_ps(rdev, boot_ps);
4707 int ci_dpm_late_enable(struct radeon_device *rdev)
4711 if (rdev->irq.installed &&
4712 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
4714 PPSMC_Result result;
4716 ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
4718 DRM_ERROR("ci_set_thermal_temperature_range failed\n");
4721 rdev->irq.dpm_thermal = true;
4722 radeon_irq_set(rdev);
4724 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
4726 if (result != PPSMC_Result_OK)
4727 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
4731 ci_dpm_powergate_uvd(rdev, true);
4736 void ci_dpm_disable(struct radeon_device *rdev)
4738 struct ci_power_info *pi = ci_get_pi(rdev);
4739 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4741 ci_dpm_powergate_uvd(rdev, false);
4743 if (!ci_is_smc_running(rdev))
4746 if (pi->thermal_protection)
4747 ci_enable_thermal_protection(rdev, false);
4748 ci_enable_power_containment(rdev, false);
4749 ci_enable_smc_cac(rdev, false);
4750 ci_enable_didt(rdev, false);
4751 ci_enable_spread_spectrum(rdev, false);
4752 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
4754 ci_enable_ds_master_switch(rdev, true);
4755 ci_enable_ulv(rdev, false);
4757 ci_reset_to_default(rdev);
4758 ci_dpm_stop_smc(rdev);
4759 ci_force_switch_to_arb_f0(rdev);
4761 ci_update_current_ps(rdev, boot_ps);
4764 int ci_dpm_set_power_state(struct radeon_device *rdev)
4766 struct ci_power_info *pi = ci_get_pi(rdev);
4767 struct radeon_ps *new_ps = &pi->requested_rps;
4768 struct radeon_ps *old_ps = &pi->current_rps;
4771 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
4772 if (pi->pcie_performance_request)
4773 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
4774 ret = ci_freeze_sclk_mclk_dpm(rdev);
4776 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
4779 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
4781 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
4784 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
4786 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
4790 ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
4792 DRM_ERROR("ci_update_vce_dpm failed\n");
4796 ret = ci_update_sclk_t(rdev);
4798 DRM_ERROR("ci_update_sclk_t failed\n");
4801 if (pi->caps_dynamic_ac_timing) {
4802 ret = ci_update_and_upload_mc_reg_table(rdev);
4804 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
4808 ret = ci_program_memory_timing_parameters(rdev);
4810 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
4813 ret = ci_unfreeze_sclk_mclk_dpm(rdev);
4815 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
4818 ret = ci_upload_dpm_level_enable_mask(rdev);
4820 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
4823 if (pi->pcie_performance_request)
4824 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
4829 int ci_dpm_power_control_set_level(struct radeon_device *rdev)
4831 return ci_power_control_set_level(rdev);
4834 void ci_dpm_reset_asic(struct radeon_device *rdev)
4836 ci_set_boot_state(rdev);
4839 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
4841 ci_program_display_gap(rdev);
4845 struct _ATOM_POWERPLAY_INFO info;
4846 struct _ATOM_POWERPLAY_INFO_V2 info_2;
4847 struct _ATOM_POWERPLAY_INFO_V3 info_3;
4848 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
4849 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
4850 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
4853 union pplib_clock_info {
4854 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
4855 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
4856 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
4857 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
4858 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
4859 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
4862 union pplib_power_state {
4863 struct _ATOM_PPLIB_STATE v1;
4864 struct _ATOM_PPLIB_STATE_V2 v2;
4867 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
4868 struct radeon_ps *rps,
4869 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
4872 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
4873 rps->class = le16_to_cpu(non_clock_info->usClassification);
4874 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
4876 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
4877 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
4878 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
4884 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
4885 rdev->pm.dpm.boot_ps = rps;
4886 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
4887 rdev->pm.dpm.uvd_ps = rps;
4890 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
4891 struct radeon_ps *rps, int index,
4892 union pplib_clock_info *clock_info)
4894 struct ci_power_info *pi = ci_get_pi(rdev);
4895 struct ci_ps *ps = ci_get_ps(rps);
4896 struct ci_pl *pl = &ps->performance_levels[index];
4898 ps->performance_level_count = index + 1;
4900 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
4901 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
4902 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
4903 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
4905 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
4907 pi->vbios_boot_state.pcie_gen_bootup_value,
4908 clock_info->ci.ucPCIEGen);
4909 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
4910 pi->vbios_boot_state.pcie_lane_bootup_value,
4911 le16_to_cpu(clock_info->ci.usPCIELane));
4913 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
4914 pi->acpi_pcie_gen = pl->pcie_gen;
4917 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
4918 pi->ulv.supported = true;
4920 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
4923 /* patch up boot state */
4924 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
4925 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
4926 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
4927 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
4928 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
4931 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
4932 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
4933 pi->use_pcie_powersaving_levels = true;
4934 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
4935 pi->pcie_gen_powersaving.max = pl->pcie_gen;
4936 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
4937 pi->pcie_gen_powersaving.min = pl->pcie_gen;
4938 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
4939 pi->pcie_lane_powersaving.max = pl->pcie_lane;
4940 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
4941 pi->pcie_lane_powersaving.min = pl->pcie_lane;
4943 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
4944 pi->use_pcie_performance_levels = true;
4945 if (pi->pcie_gen_performance.max < pl->pcie_gen)
4946 pi->pcie_gen_performance.max = pl->pcie_gen;
4947 if (pi->pcie_gen_performance.min > pl->pcie_gen)
4948 pi->pcie_gen_performance.min = pl->pcie_gen;
4949 if (pi->pcie_lane_performance.max < pl->pcie_lane)
4950 pi->pcie_lane_performance.max = pl->pcie_lane;
4951 if (pi->pcie_lane_performance.min > pl->pcie_lane)
4952 pi->pcie_lane_performance.min = pl->pcie_lane;
4959 static int ci_parse_power_table(struct radeon_device *rdev)
4961 struct radeon_mode_info *mode_info = &rdev->mode_info;
4962 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
4963 union pplib_power_state *power_state;
4964 int i, j, k, non_clock_array_index, clock_array_index;
4965 union pplib_clock_info *clock_info;
4966 struct _StateArray *state_array;
4967 struct _ClockInfoArray *clock_info_array;
4968 struct _NonClockInfoArray *non_clock_info_array;
4969 union power_info *power_info;
4970 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
4973 u8 *power_state_offset;
4976 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
4977 &frev, &crev, &data_offset))
4979 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
4981 state_array = (struct _StateArray *)
4982 (mode_info->atom_context->bios + data_offset +
4983 le16_to_cpu(power_info->pplib.usStateArrayOffset));
4984 clock_info_array = (struct _ClockInfoArray *)
4985 (mode_info->atom_context->bios + data_offset +
4986 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
4987 non_clock_info_array = (struct _NonClockInfoArray *)
4988 (mode_info->atom_context->bios + data_offset +
4989 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
4991 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
4992 state_array->ucNumEntries, GFP_KERNEL);
4993 if (!rdev->pm.dpm.ps)
4995 power_state_offset = (u8 *)state_array->states;
4996 for (i = 0; i < state_array->ucNumEntries; i++) {
4998 power_state = (union pplib_power_state *)power_state_offset;
4999 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5000 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5001 &non_clock_info_array->nonClockInfo[non_clock_array_index];
5002 if (!rdev->pm.power_state[i].clock_info)
5004 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5006 kfree(rdev->pm.dpm.ps);
5009 rdev->pm.dpm.ps[i].ps_priv = ps;
5010 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5012 non_clock_info_array->ucEntrySize);
5014 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5015 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5016 clock_array_index = idx[j];
5017 if (clock_array_index >= clock_info_array->ucNumEntries)
5019 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5021 clock_info = (union pplib_clock_info *)
5022 ((u8 *)&clock_info_array->clockInfo[0] +
5023 (clock_array_index * clock_info_array->ucEntrySize));
5024 ci_parse_pplib_clock_info(rdev,
5025 &rdev->pm.dpm.ps[i], k,
5029 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5031 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5033 /* fill in the vce power states */
5034 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5036 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5037 clock_info = (union pplib_clock_info *)
5038 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5039 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5040 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5041 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5042 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5043 rdev->pm.dpm.vce_states[i].sclk = sclk;
5044 rdev->pm.dpm.vce_states[i].mclk = mclk;
5050 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5051 struct ci_vbios_boot_state *boot_state)
5053 struct radeon_mode_info *mode_info = &rdev->mode_info;
5054 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5055 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5059 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5060 &frev, &crev, &data_offset)) {
5062 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5064 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5065 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5066 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5067 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5068 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5069 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5070 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5077 void ci_dpm_fini(struct radeon_device *rdev)
5081 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5082 kfree(rdev->pm.dpm.ps[i].ps_priv);
5084 kfree(rdev->pm.dpm.ps);
5085 kfree(rdev->pm.dpm.priv);
5086 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5087 r600_free_extended_power_table(rdev);
5090 int ci_dpm_init(struct radeon_device *rdev)
5092 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5093 u16 data_offset, size;
5095 struct ci_power_info *pi;
5099 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5102 rdev->pm.dpm.priv = pi;
5104 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5106 pi->sys_pcie_mask = 0;
5108 pi->sys_pcie_mask = mask;
5109 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5111 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5112 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5113 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5114 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5116 pi->pcie_lane_performance.max = 0;
5117 pi->pcie_lane_performance.min = 16;
5118 pi->pcie_lane_powersaving.max = 0;
5119 pi->pcie_lane_powersaving.min = 16;
5121 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5127 ret = r600_get_platform_caps(rdev);
5133 ret = r600_parse_extended_power_table(rdev);
5139 ret = ci_parse_power_table(rdev);
5145 pi->dll_default_on = false;
5146 pi->sram_end = SMC_RAM_END;
5148 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5149 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5150 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5151 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5152 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5153 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5154 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5155 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5157 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5159 pi->sclk_dpm_key_disabled = 0;
5160 pi->mclk_dpm_key_disabled = 0;
5161 pi->pcie_dpm_key_disabled = 0;
5163 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5164 if ((rdev->pdev->device == 0x6658) &&
5165 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5166 pi->mclk_dpm_key_disabled = 1;
5169 pi->caps_sclk_ds = true;
5171 pi->mclk_strobe_mode_threshold = 40000;
5172 pi->mclk_stutter_mode_threshold = 40000;
5173 pi->mclk_edc_enable_threshold = 40000;
5174 pi->mclk_edc_wr_enable_threshold = 40000;
5176 ci_initialize_powertune_defaults(rdev);
5178 pi->caps_fps = false;
5180 pi->caps_sclk_throttle_low_notification = false;
5182 pi->caps_uvd_dpm = true;
5183 pi->caps_vce_dpm = true;
5185 ci_get_leakage_voltages(rdev);
5186 ci_patch_dependency_tables_with_leakage(rdev);
5187 ci_set_private_data_variables_based_on_pptable(rdev);
5189 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5190 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5191 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5195 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5196 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5197 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5198 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5199 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5200 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5201 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5202 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5203 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5205 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5206 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5207 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5209 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5210 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5211 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5212 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5214 if (rdev->family == CHIP_HAWAII) {
5215 pi->thermal_temp_setting.temperature_low = 94500;
5216 pi->thermal_temp_setting.temperature_high = 95000;
5217 pi->thermal_temp_setting.temperature_shutdown = 104000;
5219 pi->thermal_temp_setting.temperature_low = 99500;
5220 pi->thermal_temp_setting.temperature_high = 100000;
5221 pi->thermal_temp_setting.temperature_shutdown = 104000;
5224 pi->uvd_enabled = false;
5226 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5227 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5228 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5229 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5230 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5231 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5232 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5234 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5235 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5236 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5237 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5238 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5240 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5243 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5244 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5245 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5246 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5247 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5249 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5252 pi->vddc_phase_shed_control = true;
5254 #if defined(CONFIG_ACPI)
5255 pi->pcie_performance_request =
5256 radeon_acpi_is_pcie_performance_request_supported(rdev);
5258 pi->pcie_performance_request = false;
5261 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5262 &frev, &crev, &data_offset)) {
5263 pi->caps_sclk_ss_support = true;
5264 pi->caps_mclk_ss_support = true;
5265 pi->dynamic_ss = true;
5267 pi->caps_sclk_ss_support = false;
5268 pi->caps_mclk_ss_support = false;
5269 pi->dynamic_ss = true;
5272 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5273 pi->thermal_protection = true;
5275 pi->thermal_protection = false;
5277 pi->caps_dynamic_ac_timing = true;
5279 pi->uvd_power_gated = false;
5281 /* make sure dc limits are valid */
5282 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5283 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5284 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5285 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5290 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5293 u32 sclk = ci_get_average_sclk_freq(rdev);
5294 u32 mclk = ci_get_average_mclk_freq(rdev);
5296 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
5300 void ci_dpm_print_power_state(struct radeon_device *rdev,
5301 struct radeon_ps *rps)
5303 struct ci_ps *ps = ci_get_ps(rps);
5307 r600_dpm_print_class_info(rps->class, rps->class2);
5308 r600_dpm_print_cap_info(rps->caps);
5309 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5310 for (i = 0; i < ps->performance_level_count; i++) {
5311 pl = &ps->performance_levels[i];
5312 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5313 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5315 r600_dpm_print_ps_status(rdev, rps);
5318 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5320 struct ci_power_info *pi = ci_get_pi(rdev);
5321 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5324 return requested_state->performance_levels[0].sclk;
5326 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5329 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5331 struct ci_power_info *pi = ci_get_pi(rdev);
5332 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5335 return requested_state->performance_levels[0].mclk;
5337 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;