drivers/gpu/drm/radeon/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *          Jerome Glisse
  26  */
  27 #include <drm/drmP.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33 #include <drm/drm_dp_helper.h>
  34
  35 /* move these to drm_dp_helper.c/h */
  36 #define DP_LINK_CONFIGURATION_SIZE 9
  37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  38
  39 static char *voltage_names[] = {
  40         "0.4V", "0.6V", "0.8V", "1.2V"
  41 };
  42 static char *pre_emph_names[] = {
  43         "0dB", "3.5dB", "6dB", "9.5dB"
  44 };
  45
  46 /***** radeon AUX functions *****/
  47
  48 /* Atom needs data in little endian format
  49  * so swap as appropriate when copying data to
  50  * or from atom. Note that atom operates on
  51  * dw units.
  52  */
  53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
  54 {
  55 #ifdef __BIG_ENDIAN
  56         u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
  57         u32 *dst32, *src32;
  58         int i;
  59
  60         memcpy(src_tmp, src, num_bytes);
  61         src32 = (u32 *)src_tmp;
  62         dst32 = (u32 *)dst_tmp;
  63         if (to_le) {
  64                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  65                         dst32[i] = cpu_to_le32(src32[i]);
  66                 memcpy(dst, dst_tmp, num_bytes);
  67         } else {
  68                 u8 dws = num_bytes & ~3;
  69                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  70                         dst32[i] = le32_to_cpu(src32[i]);
  71                 memcpy(dst, dst_tmp, dws);
  72                 if (num_bytes % 4) {
  73                         for (i = 0; i < (num_bytes % 4); i++)
  74                                 dst[dws+i] = dst_tmp[dws+i];
  75                 }
  76         }
  77 #else
  78         memcpy(dst, src, num_bytes);
  79 #endif
  80 }
  81
  82 union aux_channel_transaction {
  83         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  84         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  85 };
  86
  87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
  88                                  u8 *send, int send_bytes,
  89                                  u8 *recv, int recv_size,
  90                                  u8 delay, u8 *ack)
  91 {
  92         struct drm_device *dev = chan->dev;
  93         struct radeon_device *rdev = dev->dev_private;
  94         union aux_channel_transaction args;
  95         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  96         unsigned char *base;
  97         int recv_bytes;
  98
  99         memset(&args, 0, sizeof(args));
 100
 101         base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
 102
 103         radeon_atom_copy_swap(base, send, send_bytes, true);
 104
 105         args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
 106         args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
 107         args.v1.ucDataOutLen = 0;
 108         args.v1.ucChannelID = chan->rec.i2c_id;
 109         args.v1.ucDelay = delay / 10;
 110         if (ASIC_IS_DCE4(rdev))
 111                 args.v2.ucHPD_ID = chan->rec.hpd;
 112
 113         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 114
 115         *ack = args.v1.ucReplyStatus;
 116
 117         /* timeout */
 118         if (args.v1.ucReplyStatus == 1) {
 119                 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
 120                 return -ETIMEDOUT;
 121         }
 122
 123         /* flags not zero */
 124         if (args.v1.ucReplyStatus == 2) {
 125                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
 126                 return -EBUSY;
 127         }
 128
 129         /* error */
 130         if (args.v1.ucReplyStatus == 3) {
 131                 DRM_DEBUG_KMS("dp_aux_ch error\n");
 132                 return -EIO;
 133         }
 134
 135         recv_bytes = args.v1.ucDataOutLen;
 136         if (recv_bytes > recv_size)
 137                 recv_bytes = recv_size;
 138
 139         if (recv && recv_size)
 140                 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
 141
 142         return recv_bytes;
 143 }
 144
 145 #define BARE_ADDRESS_SIZE 3
 146 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
 147
 148 static ssize_t
 149 radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 150 {
 151         struct radeon_i2c_chan *chan =
 152                 container_of(aux, struct radeon_i2c_chan, aux);
 153         int ret;
 154         u8 tx_buf[20];
 155         size_t tx_size;
 156         u8 ack, delay = 0;
 157
 158         if (WARN_ON(msg->size > 16))
 159                 return -E2BIG;
 160
 161         tx_buf[0] = msg->address & 0xff;
 162         tx_buf[1] = msg->address >> 8;
 163         tx_buf[2] = msg->request << 4;
 164         tx_buf[3] = msg->size ? (msg->size - 1) : 0;
 165
 166         switch (msg->request & ~DP_AUX_I2C_MOT) {
 167         case DP_AUX_NATIVE_WRITE:
 168         case DP_AUX_I2C_WRITE:
 169                 /* tx_size needs to be 4 even for bare address packets since the atom
 170                  * table needs the info in tx_buf[3].
 171                  */
 172                 tx_size = HEADER_SIZE + msg->size;
 173                 if (msg->size == 0)
 174                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 175                 else
 176                         tx_buf[3] |= tx_size << 4;
 177                 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
 178                 ret = radeon_process_aux_ch(chan,
 179                                             tx_buf, tx_size, NULL, 0, delay, &ack);
 180                 if (ret >= 0)
 181                         /* Return payload size. */
 182                         ret = msg->size;
 183                 break;
 184         case DP_AUX_NATIVE_READ:
 185         case DP_AUX_I2C_READ:
 186                 /* tx_size needs to be 4 even for bare address packets since the atom
 187                  * table needs the info in tx_buf[3].
 188                  */
 189                 tx_size = HEADER_SIZE;
 190                 if (msg->size == 0)
 191                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 192                 else
 193                         tx_buf[3] |= tx_size << 4;
 194                 ret = radeon_process_aux_ch(chan,
 195                                             tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
 196                 break;
 197         default:
 198                 ret = -EINVAL;
 199                 break;
 200         }
 201
 202         if (ret >= 0)
 203                 msg->reply = ack >> 4;
 204
 205         return ret;
 206 }
 207
 208 void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
 209 {
 210         int ret;
 211
 212         radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
 213         radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer;
 214         ret = drm_dp_aux_register_i2c_bus(&radeon_connector->ddc_bus->aux);
 215         if (!ret)
 216                 radeon_connector->ddc_bus->has_aux = true;
 217
 218         WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret);
 219 }
 220
 221 /***** general DP utility functions *****/
 222
 223 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
 224 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPHASIS_9_5
 225
 226 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
 227                                 int lane_count,
 228                                 u8 train_set[4])
 229 {
 230         u8 v = 0;
 231         u8 p = 0;
 232         int lane;
 233
 234         for (lane = 0; lane < lane_count; lane++) {
 235                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 236                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 237
 238                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 239                           lane,
 240                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 241                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 242
 243                 if (this_v > v)
 244                         v = this_v;
 245                 if (this_p > p)
 246                         p = this_p;
 247         }
 248
 249         if (v >= DP_VOLTAGE_MAX)
 250                 v |= DP_TRAIN_MAX_SWING_REACHED;
 251
 252         if (p >= DP_PRE_EMPHASIS_MAX)
 253                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 254
 255         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 256                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 257                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 258
 259         for (lane = 0; lane < 4; lane++)
 260                 train_set[lane] = v | p;
 261 }
 262
 263 /* convert bits per color to bits per pixel */
 264 /* get bpc from the EDID */
 265 static int convert_bpc_to_bpp(int bpc)
 266 {
 267         if (bpc == 0)
 268                 return 24;
 269         else
 270                 return bpc * 3;
 271 }
 272
 273 /* get the max pix clock supported by the link rate and lane num */
 274 static int dp_get_max_dp_pix_clock(int link_rate,
 275                                    int lane_num,
 276                                    int bpp)
 277 {
 278         return (link_rate * lane_num * 8) / bpp;
 279 }
 280
 281 /***** radeon specific DP functions *****/
 282
 283 /* First get the min lane# when low rate is used according to pixel clock
 284  * (prefer low rate), second check max lane# supported by DP panel,
 285  * if the max lane# < low rate lane# then use max lane# instead.
 286  */
 287 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
 288                                         u8 dpcd[DP_DPCD_SIZE],
 289                                         int pix_clock)
 290 {
 291         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 292         int max_link_rate = drm_dp_max_link_rate(dpcd);
 293         int max_lane_num = drm_dp_max_lane_count(dpcd);
 294         int lane_num;
 295         int max_dp_pix_clock;
 296
 297         for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
 298                 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
 299                 if (pix_clock <= max_dp_pix_clock)
 300                         break;
 301         }
 302
 303         return lane_num;
 304 }
 305
 306 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
 307                                        u8 dpcd[DP_DPCD_SIZE],
 308                                        int pix_clock)
 309 {
 310         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 311         int lane_num, max_pix_clock;
 312
 313         if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 314             ENCODER_OBJECT_ID_NUTMEG)
 315                 return 270000;
 316
 317         lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
 318         max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
 319         if (pix_clock <= max_pix_clock)
 320                 return 162000;
 321         max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
 322         if (pix_clock <= max_pix_clock)
 323                 return 270000;
 324         if (radeon_connector_is_dp12_capable(connector)) {
 325                 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
 326                 if (pix_clock <= max_pix_clock)
 327                         return 540000;
 328         }
 329
 330         return drm_dp_max_link_rate(dpcd);
 331 }
 332
 333 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
 334                                     int action, int dp_clock,
 335                                     u8 ucconfig, u8 lane_num)
 336 {
 337         DP_ENCODER_SERVICE_PARAMETERS args;
 338         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 339
 340         memset(&args, 0, sizeof(args));
 341         args.ucLinkClock = dp_clock / 10;
 342         args.ucConfig = ucconfig;
 343         args.ucAction = action;
 344         args.ucLaneNum = lane_num;
 345         args.ucStatus = 0;
 346
 347         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 348         return args.ucStatus;
 349 }
 350
 351 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
 352 {
 353         struct drm_device *dev = radeon_connector->base.dev;
 354         struct radeon_device *rdev = dev->dev_private;
 355
 356         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 357                                          radeon_connector->ddc_bus->rec.i2c_id, 0);
 358 }
 359
 360 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
 361 {
 362         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 363         u8 buf[3];
 364
 365         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 366                 return;
 367
 368         if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3))
 369                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
 370                               buf[0], buf[1], buf[2]);
 371
 372         if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3))
 373                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
 374                               buf[0], buf[1], buf[2]);
 375 }
 376
 377 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
 378 {
 379         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 380         u8 msg[DP_DPCD_SIZE];
 381         int ret, i;
 382
 383         ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
 384                                DP_DPCD_SIZE);
 385         if (ret > 0) {
 386                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
 387                 DRM_DEBUG_KMS("DPCD: ");
 388                 for (i = 0; i < DP_DPCD_SIZE; i++)
 389                         DRM_DEBUG_KMS("%02x ", msg[i]);
 390                 DRM_DEBUG_KMS("\n");
 391
 392                 radeon_dp_probe_oui(radeon_connector);
 393
 394                 return true;
 395         }
 396         dig_connector->dpcd[0] = 0;
 397         return false;
 398 }
 399
 400 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 401                              struct drm_connector *connector)
 402 {
 403         struct drm_device *dev = encoder->dev;
 404         struct radeon_device *rdev = dev->dev_private;
 405         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 406         struct radeon_connector_atom_dig *dig_connector;
 407         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 408         u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
 409         u8 tmp;
 410
 411         if (!ASIC_IS_DCE4(rdev))
 412                 return panel_mode;
 413
 414         if (!radeon_connector->con_priv)
 415                 return panel_mode;
 416
 417         dig_connector = radeon_connector->con_priv;
 418
 419         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 420                 /* DP bridge chips */
 421                 drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
 422                                   DP_EDP_CONFIGURATION_CAP, &tmp);
 423                 if (tmp & 1)
 424                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 425                 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
 426                          (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
 427                         panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 428                 else
 429                         panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 430         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 431                 /* eDP */
 432                 drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
 433                                   DP_EDP_CONFIGURATION_CAP, &tmp);
 434                 if (tmp & 1)
 435                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 436         }
 437
 438         return panel_mode;
 439 }
 440
 441 void radeon_dp_set_link_config(struct drm_connector *connector,
 442                                const struct drm_display_mode *mode)
 443 {
 444         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 445         struct radeon_connector_atom_dig *dig_connector;
 446
 447         if (!radeon_connector->con_priv)
 448                 return;
 449         dig_connector = radeon_connector->con_priv;
 450
 451         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 452             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 453                 dig_connector->dp_clock =
 454                         radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 455                 dig_connector->dp_lane_count =
 456                         radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
 457         }
 458 }
 459
 460 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 461                                 struct drm_display_mode *mode)
 462 {
 463         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 464         struct radeon_connector_atom_dig *dig_connector;
 465         int dp_clock;
 466
 467         if (!radeon_connector->con_priv)
 468                 return MODE_CLOCK_HIGH;
 469         dig_connector = radeon_connector->con_priv;
 470
 471         dp_clock =
 472                 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 473
 474         if ((dp_clock == 540000) &&
 475             (!radeon_connector_is_dp12_capable(connector)))
 476                 return MODE_CLOCK_HIGH;
 477
 478         return MODE_OK;
 479 }
 480
 481 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
 482 {
 483         u8 link_status[DP_LINK_STATUS_SIZE];
 484         struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 485
 486         if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
 487             <= 0)
 488                 return false;
 489         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
 490                 return false;
 491         return true;
 492 }
 493
 494 void radeon_dp_set_rx_power_state(struct drm_connector *connector,
 495                                   u8 power_state)
 496 {
 497         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 498         struct radeon_connector_atom_dig *dig_connector;
 499
 500         if (!radeon_connector->con_priv)
 501                 return;
 502
 503         dig_connector = radeon_connector->con_priv;
 504
 505         /* power up/down the sink */
 506         if (dig_connector->dpcd[0] >= 0x11) {
 507                 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
 508                                    DP_SET_POWER, power_state);
 509                 usleep_range(1000, 2000);
 510         }
 511 }
 512
 513
 514 struct radeon_dp_link_train_info {
 515         struct radeon_device *rdev;
 516         struct drm_encoder *encoder;
 517         struct drm_connector *connector;
 518         int enc_id;
 519         int dp_clock;
 520         int dp_lane_count;
 521         bool tp3_supported;
 522         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 523         u8 train_set[4];
 524         u8 link_status[DP_LINK_STATUS_SIZE];
 525         u8 tries;
 526         bool use_dpencoder;
 527         struct drm_dp_aux *aux;
 528 };
 529
 530 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
 531 {
 532         /* set the initial vs/emph on the source */
 533         atombios_dig_transmitter_setup(dp_info->encoder,
 534                                        ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 535                                        0, dp_info->train_set[0]); /* sets all lanes at once */
 536
 537         /* set the vs/emph on the sink */
 538         drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
 539                           dp_info->train_set, dp_info->dp_lane_count);
 540 }
 541
 542 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
 543 {
 544         int rtp = 0;
 545
 546         /* set training pattern on the source */
 547         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
 548                 switch (tp) {
 549                 case DP_TRAINING_PATTERN_1:
 550                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 551                         break;
 552                 case DP_TRAINING_PATTERN_2:
 553                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 554                         break;
 555                 case DP_TRAINING_PATTERN_3:
 556                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 557                         break;
 558                 }
 559                 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
 560         } else {
 561                 switch (tp) {
 562                 case DP_TRAINING_PATTERN_1:
 563                         rtp = 0;
 564                         break;
 565                 case DP_TRAINING_PATTERN_2:
 566                         rtp = 1;
 567                         break;
 568                 }
 569                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 570                                           dp_info->dp_clock, dp_info->enc_id, rtp);
 571         }
 572
 573         /* enable training pattern on the sink */
 574         drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
 575 }
 576
 577 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 578 {
 579         struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
 580         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 581         u8 tmp;
 582
 583         /* power up the sink */
 584         radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
 585
 586         /* possibly enable downspread on the sink */
 587         if (dp_info->dpcd[3] & 0x1)
 588                 drm_dp_dpcd_writeb(dp_info->aux,
 589                                    DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 590         else
 591                 drm_dp_dpcd_writeb(dp_info->aux,
 592                                    DP_DOWNSPREAD_CTRL, 0);
 593
 594         if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
 595             (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
 596                 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
 597         }
 598
 599         /* set the lane count on the sink */
 600         tmp = dp_info->dp_lane_count;
 601         if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
 602                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 603         drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
 604
 605         /* set the link rate on the sink */
 606         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
 607         drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
 608
 609         /* start training on the source */
 610         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 611                 atombios_dig_encoder_setup(dp_info->encoder,
 612                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 613         else
 614                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
 615                                           dp_info->dp_clock, dp_info->enc_id, 0);
 616
 617         /* disable the training pattern on the sink */
 618         drm_dp_dpcd_writeb(dp_info->aux,
 619                            DP_TRAINING_PATTERN_SET,
 620                            DP_TRAINING_PATTERN_DISABLE);
 621
 622         return 0;
 623 }
 624
 625 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
 626 {
 627         udelay(400);
 628
 629         /* disable the training pattern on the sink */
 630         drm_dp_dpcd_writeb(dp_info->aux,
 631                            DP_TRAINING_PATTERN_SET,
 632                            DP_TRAINING_PATTERN_DISABLE);
 633
 634         /* disable the training pattern on the source */
 635         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 636                 atombios_dig_encoder_setup(dp_info->encoder,
 637                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 638         else
 639                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
 640                                           dp_info->dp_clock, dp_info->enc_id, 0);
 641
 642         return 0;
 643 }
 644
 645 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
 646 {
 647         bool clock_recovery;
 648         u8 voltage;
 649         int i;
 650
 651         radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 652         memset(dp_info->train_set, 0, 4);
 653         radeon_dp_update_vs_emph(dp_info);
 654
 655         udelay(400);
 656
 657         /* clock recovery loop */
 658         clock_recovery = false;
 659         dp_info->tries = 0;
 660         voltage = 0xff;
 661         while (1) {
 662                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
 663
 664                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 665                                                  dp_info->link_status) <= 0) {
 666                         DRM_ERROR("displayport link status failed\n");
 667                         break;
 668                 }
 669
 670                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 671                         clock_recovery = true;
 672                         break;
 673                 }
 674
 675                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 676                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 677                                 break;
 678                 }
 679                 if (i == dp_info->dp_lane_count) {
 680                         DRM_ERROR("clock recovery reached max voltage\n");
 681                         break;
 682                 }
 683
 684                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 685                         ++dp_info->tries;
 686                         if (dp_info->tries == 5) {
 687                                 DRM_ERROR("clock recovery tried 5 times\n");
 688                                 break;
 689                         }
 690                 } else
 691                         dp_info->tries = 0;
 692
 693                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 694
 695                 /* Compute new train_set as requested by sink */
 696                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 697
 698                 radeon_dp_update_vs_emph(dp_info);
 699         }
 700         if (!clock_recovery) {
 701                 DRM_ERROR("clock recovery failed\n");
 702                 return -1;
 703         } else {
 704                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 705                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 706                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 707                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 708                 return 0;
 709         }
 710 }
 711
 712 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
 713 {
 714         bool channel_eq;
 715
 716         if (dp_info->tp3_supported)
 717                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 718         else
 719                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 720
 721         /* channel equalization loop */
 722         dp_info->tries = 0;
 723         channel_eq = false;
 724         while (1) {
 725                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
 726
 727                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 728                                                  dp_info->link_status) <= 0) {
 729                         DRM_ERROR("displayport link status failed\n");
 730                         break;
 731                 }
 732
 733                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 734                         channel_eq = true;
 735                         break;
 736                 }
 737
 738                 /* Try 5 times */
 739                 if (dp_info->tries > 5) {
 740                         DRM_ERROR("channel eq failed: 5 tries\n");
 741                         break;
 742                 }
 743
 744                 /* Compute new train_set as requested by sink */
 745                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 746
 747                 radeon_dp_update_vs_emph(dp_info);
 748                 dp_info->tries++;
 749         }
 750
 751         if (!channel_eq) {
 752                 DRM_ERROR("channel eq failed\n");
 753                 return -1;
 754         } else {
 755                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 756                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 757                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 758                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 759                 return 0;
 760         }
 761 }
 762
 763 void radeon_dp_link_train(struct drm_encoder *encoder,
 764                           struct drm_connector *connector)
 765 {
 766         struct drm_device *dev = encoder->dev;
 767         struct radeon_device *rdev = dev->dev_private;
 768         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 769         struct radeon_encoder_atom_dig *dig;
 770         struct radeon_connector *radeon_connector;
 771         struct radeon_connector_atom_dig *dig_connector;
 772         struct radeon_dp_link_train_info dp_info;
 773         int index;
 774         u8 tmp, frev, crev;
 775
 776         if (!radeon_encoder->enc_priv)
 777                 return;
 778         dig = radeon_encoder->enc_priv;
 779
 780         radeon_connector = to_radeon_connector(connector);
 781         if (!radeon_connector->con_priv)
 782                 return;
 783         dig_connector = radeon_connector->con_priv;
 784
 785         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 786             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 787                 return;
 788
 789         /* DPEncoderService newer than 1.1 can't program properly the
 790          * training pattern. When facing such version use the
 791          * DIGXEncoderControl (X== 1 | 2)
 792          */
 793         dp_info.use_dpencoder = true;
 794         index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 795         if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
 796                 if (crev > 1) {
 797                         dp_info.use_dpencoder = false;
 798                 }
 799         }
 800
 801         dp_info.enc_id = 0;
 802         if (dig->dig_encoder)
 803                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
 804         else
 805                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
 806         if (dig->linkb)
 807                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
 808         else
 809                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
 810
 811         drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp);
 812         if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
 813                 dp_info.tp3_supported = true;
 814         else
 815                 dp_info.tp3_supported = false;
 816
 817         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
 818         dp_info.rdev = rdev;
 819         dp_info.encoder = encoder;
 820         dp_info.connector = connector;
 821         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 822         dp_info.dp_clock = dig_connector->dp_clock;
 823         dp_info.aux = &radeon_connector->ddc_bus->aux;
 824
 825         if (radeon_dp_link_train_init(&dp_info))
 826                 goto done;
 827         if (radeon_dp_link_train_cr(&dp_info))
 828                 goto done;
 829         if (radeon_dp_link_train_ce(&dp_info))
 830                 goto done;
 831 done:
 832         if (radeon_dp_link_train_finish(&dp_info))
 833                 return;
 834 }