2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include <drm/drm_fixed.h>
32 #include "atom-bits.h"
34 static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
45 memset(&args, 0, sizeof(args));
47 args.usOverscanRight = 0;
48 args.usOverscanLeft = 0;
49 args.usOverscanBottom = 0;
50 args.usOverscanTop = 0;
51 args.ucCRTC = radeon_crtc->crtc_id;
53 switch (radeon_crtc->rmx_type) {
55 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
56 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
57 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
58 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
59 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
66 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
67 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
69 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
70 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
72 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
76 args.usOverscanRight = 0;
77 args.usOverscanLeft = 0;
78 args.usOverscanBottom = 0;
79 args.usOverscanTop = 0;
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
85 static void atombios_scaler_setup(struct drm_crtc *crtc)
87 struct drm_device *dev = crtc->dev;
88 struct radeon_device *rdev = dev->dev_private;
89 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
90 ENABLE_SCALER_PS_ALLOCATION args;
91 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
93 /* fixme - fill in enc_priv for atom dac */
94 enum radeon_tv_std tv_std = TV_STD_NTSC;
95 bool is_tv = false, is_cv = false;
96 struct drm_encoder *encoder;
98 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
101 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
103 if (encoder->crtc == crtc) {
104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
105 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
106 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
107 tv_std = tv_dac->tv_std;
113 memset(&args, 0, sizeof(args));
115 args.ucScaler = radeon_crtc->crtc_id;
121 args.ucTVStandard = ATOM_TV_NTSC;
124 args.ucTVStandard = ATOM_TV_PAL;
127 args.ucTVStandard = ATOM_TV_PALM;
130 args.ucTVStandard = ATOM_TV_PAL60;
133 args.ucTVStandard = ATOM_TV_NTSCJ;
135 case TV_STD_SCART_PAL:
136 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
139 args.ucTVStandard = ATOM_TV_SECAM;
142 args.ucTVStandard = ATOM_TV_PALCN;
145 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
147 args.ucTVStandard = ATOM_TV_CV;
148 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
150 switch (radeon_crtc->rmx_type) {
152 args.ucEnable = ATOM_SCALER_EXPANSION;
155 args.ucEnable = ATOM_SCALER_CENTER;
158 args.ucEnable = ATOM_SCALER_EXPANSION;
161 if (ASIC_IS_AVIVO(rdev))
162 args.ucEnable = ATOM_SCALER_DISABLE;
164 args.ucEnable = ATOM_SCALER_CENTER;
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
170 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
171 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
175 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
178 struct drm_device *dev = crtc->dev;
179 struct radeon_device *rdev = dev->dev_private;
181 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
182 ENABLE_CRTC_PS_ALLOCATION args;
184 memset(&args, 0, sizeof(args));
186 args.ucCRTC = radeon_crtc->crtc_id;
187 args.ucEnable = lock;
189 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
192 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
194 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
197 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
198 ENABLE_CRTC_PS_ALLOCATION args;
200 memset(&args, 0, sizeof(args));
202 args.ucCRTC = radeon_crtc->crtc_id;
203 args.ucEnable = state;
205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
208 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
210 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
211 struct drm_device *dev = crtc->dev;
212 struct radeon_device *rdev = dev->dev_private;
213 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
214 ENABLE_CRTC_PS_ALLOCATION args;
216 memset(&args, 0, sizeof(args));
218 args.ucCRTC = radeon_crtc->crtc_id;
219 args.ucEnable = state;
221 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
224 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 struct drm_device *dev = crtc->dev;
228 struct radeon_device *rdev = dev->dev_private;
229 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
230 BLANK_CRTC_PS_ALLOCATION args;
232 memset(&args, 0, sizeof(args));
234 args.ucCRTC = radeon_crtc->crtc_id;
235 args.ucBlanking = state;
237 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
240 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
242 struct drm_device *dev = crtc->dev;
243 struct radeon_device *rdev = dev->dev_private;
244 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
247 case DRM_MODE_DPMS_ON:
248 radeon_crtc->enabled = true;
249 /* adjust pm to dpms changes BEFORE enabling crtcs */
250 radeon_pm_compute_clocks(rdev);
251 atombios_enable_crtc(crtc, ATOM_ENABLE);
252 if (ASIC_IS_DCE3(rdev))
253 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
254 atombios_blank_crtc(crtc, ATOM_DISABLE);
255 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
256 radeon_crtc_load_lut(crtc);
258 case DRM_MODE_DPMS_STANDBY:
259 case DRM_MODE_DPMS_SUSPEND:
260 case DRM_MODE_DPMS_OFF:
261 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
262 atombios_blank_crtc(crtc, ATOM_ENABLE);
263 if (ASIC_IS_DCE3(rdev))
264 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
265 atombios_enable_crtc(crtc, ATOM_DISABLE);
266 radeon_crtc->enabled = false;
267 /* adjust pm to dpms changes AFTER disabling crtcs */
268 radeon_pm_compute_clocks(rdev);
274 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
275 struct drm_display_mode *mode)
277 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
278 struct drm_device *dev = crtc->dev;
279 struct radeon_device *rdev = dev->dev_private;
280 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
281 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
284 memset(&args, 0, sizeof(args));
285 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
286 args.usH_Blanking_Time =
287 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
288 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
289 args.usV_Blanking_Time =
290 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
291 args.usH_SyncOffset =
292 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
294 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
295 args.usV_SyncOffset =
296 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
298 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
299 /*args.ucH_Border = mode->hborder;*/
300 /*args.ucV_Border = mode->vborder;*/
302 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
303 misc |= ATOM_VSYNC_POLARITY;
304 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
305 misc |= ATOM_HSYNC_POLARITY;
306 if (mode->flags & DRM_MODE_FLAG_CSYNC)
307 misc |= ATOM_COMPOSITESYNC;
308 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
309 misc |= ATOM_INTERLACE;
310 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
311 misc |= ATOM_DOUBLE_CLOCK_MODE;
313 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
314 args.ucCRTC = radeon_crtc->crtc_id;
316 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
319 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
320 struct drm_display_mode *mode)
322 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
323 struct drm_device *dev = crtc->dev;
324 struct radeon_device *rdev = dev->dev_private;
325 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
326 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
329 memset(&args, 0, sizeof(args));
330 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
331 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
332 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
334 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
335 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
336 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
337 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
339 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
341 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
342 misc |= ATOM_VSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
344 misc |= ATOM_HSYNC_POLARITY;
345 if (mode->flags & DRM_MODE_FLAG_CSYNC)
346 misc |= ATOM_COMPOSITESYNC;
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
348 misc |= ATOM_INTERLACE;
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
350 misc |= ATOM_DOUBLE_CLOCK_MODE;
352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
353 args.ucCRTC = radeon_crtc->crtc_id;
355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
358 static void atombios_disable_ss(struct drm_crtc *crtc)
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
365 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) {
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
378 case ATOM_PPLL_INVALID:
381 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) {
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
394 case ATOM_PPLL_INVALID:
401 union atom_enable_ss {
402 ENABLE_LVDS_SS_PARAMETERS legacy;
403 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
406 static void atombios_enable_ss(struct drm_crtc *crtc)
408 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
409 struct drm_device *dev = crtc->dev;
410 struct radeon_device *rdev = dev->dev_private;
411 struct drm_encoder *encoder = NULL;
412 struct radeon_encoder *radeon_encoder = NULL;
413 struct radeon_encoder_atom_dig *dig = NULL;
414 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
415 union atom_enable_ss args;
416 uint16_t percentage = 0;
417 uint8_t type = 0, step = 0, delay = 0, range = 0;
419 /* XXX add ss support for DCE4 */
420 if (ASIC_IS_DCE4(rdev))
423 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
424 if (encoder->crtc == crtc) {
425 radeon_encoder = to_radeon_encoder(encoder);
426 /* only enable spread spectrum on LVDS */
427 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
428 dig = radeon_encoder->enc_priv;
429 if (dig && dig->ss) {
430 percentage = dig->ss->percentage;
431 type = dig->ss->type;
432 step = dig->ss->step;
433 delay = dig->ss->delay;
434 range = dig->ss->range;
446 memset(&args, 0, sizeof(args));
447 if (ASIC_IS_AVIVO(rdev)) {
448 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
449 args.v1.ucSpreadSpectrumType = type;
450 args.v1.ucSpreadSpectrumStep = step;
451 args.v1.ucSpreadSpectrumDelay = delay;
452 args.v1.ucSpreadSpectrumRange = range;
453 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
454 args.v1.ucEnable = ATOM_ENABLE;
456 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
457 args.legacy.ucSpreadSpectrumType = type;
458 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
459 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
460 args.legacy.ucEnable = ATOM_ENABLE;
462 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
465 union adjust_pixel_clock {
466 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
467 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
470 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
471 struct drm_display_mode *mode,
472 struct radeon_pll *pll)
474 struct drm_device *dev = crtc->dev;
475 struct radeon_device *rdev = dev->dev_private;
476 struct drm_encoder *encoder = NULL;
477 struct radeon_encoder *radeon_encoder = NULL;
478 u32 adjusted_clock = mode->clock;
479 int encoder_mode = 0;
481 /* reset the pll flags */
484 /* select the PLL algo */
485 if (ASIC_IS_AVIVO(rdev)) {
486 if (radeon_new_pll == 0)
487 pll->algo = PLL_ALGO_LEGACY;
489 pll->algo = PLL_ALGO_NEW;
491 if (radeon_new_pll == 1)
492 pll->algo = PLL_ALGO_NEW;
494 pll->algo = PLL_ALGO_LEGACY;
497 if (ASIC_IS_AVIVO(rdev)) {
498 if ((rdev->family == CHIP_RS600) ||
499 (rdev->family == CHIP_RS690) ||
500 (rdev->family == CHIP_RS740))
501 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
502 RADEON_PLL_PREFER_CLOSEST_LOWER);
504 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
505 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
507 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
509 pll->flags |= RADEON_PLL_LEGACY;
511 if (mode->clock > 200000) /* range limits??? */
512 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
514 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
518 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
519 if (encoder->crtc == crtc) {
520 radeon_encoder = to_radeon_encoder(encoder);
521 encoder_mode = atombios_get_encoder_mode(encoder);
522 if (ASIC_IS_AVIVO(rdev)) {
523 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
524 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
525 adjusted_clock = mode->clock * 2;
526 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
527 pll->algo = PLL_ALGO_LEGACY;
528 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
531 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
532 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
533 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
534 pll->flags |= RADEON_PLL_USE_REF_DIV;
540 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
541 * accordingly based on the encoder/transmitter to work around
542 * special hw requirements.
544 if (ASIC_IS_DCE3(rdev)) {
545 union adjust_pixel_clock args;
549 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
550 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
552 return adjusted_clock;
554 memset(&args, 0, sizeof(args));
561 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
562 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
563 args.v1.ucEncodeMode = encoder_mode;
565 atom_execute_table(rdev->mode_info.atom_context,
566 index, (uint32_t *)&args);
567 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
570 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
571 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
572 args.v3.sInput.ucEncodeMode = encoder_mode;
573 args.v3.sInput.ucDispPllConfig = 0;
574 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
575 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
577 if (encoder_mode == ATOM_ENCODER_MODE_DP)
578 args.v3.sInput.ucDispPllConfig |=
579 DISPPLL_CONFIG_COHERENT_MODE;
581 if (dig->coherent_mode)
582 args.v3.sInput.ucDispPllConfig |=
583 DISPPLL_CONFIG_COHERENT_MODE;
584 if (mode->clock > 165000)
585 args.v3.sInput.ucDispPllConfig |=
586 DISPPLL_CONFIG_DUAL_LINK;
588 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
589 /* may want to enable SS on DP/eDP eventually */
590 /*args.v3.sInput.ucDispPllConfig |=
591 DISPPLL_CONFIG_SS_ENABLE;*/
592 if (encoder_mode == ATOM_ENCODER_MODE_DP)
593 args.v3.sInput.ucDispPllConfig |=
594 DISPPLL_CONFIG_COHERENT_MODE;
596 if (mode->clock > 165000)
597 args.v3.sInput.ucDispPllConfig |=
598 DISPPLL_CONFIG_DUAL_LINK;
601 atom_execute_table(rdev->mode_info.atom_context,
602 index, (uint32_t *)&args);
603 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
604 if (args.v3.sOutput.ucRefDiv) {
605 pll->flags |= RADEON_PLL_USE_REF_DIV;
606 pll->reference_div = args.v3.sOutput.ucRefDiv;
608 if (args.v3.sOutput.ucPostDiv) {
609 pll->flags |= RADEON_PLL_USE_POST_DIV;
610 pll->post_div = args.v3.sOutput.ucPostDiv;
614 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
615 return adjusted_clock;
619 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
620 return adjusted_clock;
623 return adjusted_clock;
626 union set_pixel_clock {
627 SET_PIXEL_CLOCK_PS_ALLOCATION base;
628 PIXEL_CLOCK_PARAMETERS v1;
629 PIXEL_CLOCK_PARAMETERS_V2 v2;
630 PIXEL_CLOCK_PARAMETERS_V3 v3;
631 PIXEL_CLOCK_PARAMETERS_V5 v5;
634 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
636 struct drm_device *dev = crtc->dev;
637 struct radeon_device *rdev = dev->dev_private;
640 union set_pixel_clock args;
642 memset(&args, 0, sizeof(args));
644 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
645 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
653 /* if the default dcpll clock is specified,
654 * SetPixelClock provides the dividers
656 args.v5.ucCRTC = ATOM_CRTC_INVALID;
657 args.v5.usPixelClock = rdev->clock.default_dispclk;
658 args.v5.ucPpll = ATOM_DCPLL;
661 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
666 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
669 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
672 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
683 struct drm_device *dev = crtc->dev;
684 struct radeon_device *rdev = dev->dev_private;
686 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
687 union set_pixel_clock args;
689 memset(&args, 0, sizeof(args));
691 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
699 if (clock == ATOM_DISABLE)
701 args.v1.usPixelClock = cpu_to_le16(clock / 10);
702 args.v1.usRefDiv = cpu_to_le16(ref_div);
703 args.v1.usFbDiv = cpu_to_le16(fb_div);
704 args.v1.ucFracFbDiv = frac_fb_div;
705 args.v1.ucPostDiv = post_div;
706 args.v1.ucPpll = pll_id;
707 args.v1.ucCRTC = crtc_id;
708 args.v1.ucRefDivSrc = 1;
711 args.v2.usPixelClock = cpu_to_le16(clock / 10);
712 args.v2.usRefDiv = cpu_to_le16(ref_div);
713 args.v2.usFbDiv = cpu_to_le16(fb_div);
714 args.v2.ucFracFbDiv = frac_fb_div;
715 args.v2.ucPostDiv = post_div;
716 args.v2.ucPpll = pll_id;
717 args.v2.ucCRTC = crtc_id;
718 args.v2.ucRefDivSrc = 1;
721 args.v3.usPixelClock = cpu_to_le16(clock / 10);
722 args.v3.usRefDiv = cpu_to_le16(ref_div);
723 args.v3.usFbDiv = cpu_to_le16(fb_div);
724 args.v3.ucFracFbDiv = frac_fb_div;
725 args.v3.ucPostDiv = post_div;
726 args.v3.ucPpll = pll_id;
727 args.v3.ucMiscInfo = (pll_id << 2);
728 args.v3.ucTransmitterId = encoder_id;
729 args.v3.ucEncoderMode = encoder_mode;
732 args.v5.ucCRTC = crtc_id;
733 args.v5.usPixelClock = cpu_to_le16(clock / 10);
734 args.v5.ucRefDiv = ref_div;
735 args.v5.usFbDiv = cpu_to_le16(fb_div);
736 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
737 args.v5.ucPostDiv = post_div;
738 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
739 args.v5.ucTransmitterID = encoder_id;
740 args.v5.ucEncoderMode = encoder_mode;
741 args.v5.ucPpll = pll_id;
744 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
749 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
753 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
756 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
758 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
759 struct drm_device *dev = crtc->dev;
760 struct radeon_device *rdev = dev->dev_private;
761 struct drm_encoder *encoder = NULL;
762 struct radeon_encoder *radeon_encoder = NULL;
763 u32 pll_clock = mode->clock;
764 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
765 struct radeon_pll *pll;
767 int encoder_mode = 0;
769 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
770 if (encoder->crtc == crtc) {
771 radeon_encoder = to_radeon_encoder(encoder);
772 encoder_mode = atombios_get_encoder_mode(encoder);
780 switch (radeon_crtc->pll_id) {
782 pll = &rdev->clock.p1pll;
785 pll = &rdev->clock.p2pll;
788 case ATOM_PPLL_INVALID:
790 pll = &rdev->clock.dcpll;
794 /* adjust pixel clock as needed */
795 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
797 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
798 &ref_div, &post_div);
800 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
801 encoder_mode, radeon_encoder->encoder_id, mode->clock,
802 ref_div, fb_div, frac_fb_div, post_div);
806 static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
807 struct drm_framebuffer *old_fb)
809 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
810 struct drm_device *dev = crtc->dev;
811 struct radeon_device *rdev = dev->dev_private;
812 struct radeon_framebuffer *radeon_fb;
813 struct drm_gem_object *obj;
814 struct radeon_bo *rbo;
815 uint64_t fb_location;
816 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
821 DRM_DEBUG("No FB bound\n");
825 radeon_fb = to_radeon_framebuffer(crtc->fb);
827 /* Pin framebuffer & get tilling informations */
828 obj = radeon_fb->obj;
829 rbo = obj->driver_private;
830 r = radeon_bo_reserve(rbo, false);
831 if (unlikely(r != 0))
833 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
834 if (unlikely(r != 0)) {
835 radeon_bo_unreserve(rbo);
838 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
839 radeon_bo_unreserve(rbo);
841 switch (crtc->fb->bits_per_pixel) {
843 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
844 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
847 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
848 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
851 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
852 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
856 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
857 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
860 DRM_ERROR("Unsupported screen depth %d\n",
861 crtc->fb->bits_per_pixel);
865 if (tiling_flags & RADEON_TILING_MACRO)
866 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
867 else if (tiling_flags & RADEON_TILING_MICRO)
868 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
870 switch (radeon_crtc->crtc_id) {
872 WREG32(AVIVO_D1VGA_CONTROL, 0);
875 WREG32(AVIVO_D2VGA_CONTROL, 0);
878 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
881 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
884 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
887 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
893 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
894 upper_32_bits(fb_location));
895 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
896 upper_32_bits(fb_location));
897 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
898 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
899 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
900 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
901 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
903 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
904 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
905 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
906 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
907 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
908 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
910 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
911 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
912 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
914 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
915 crtc->mode.vdisplay);
918 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
920 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
921 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
923 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
924 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
925 EVERGREEN_INTERLEAVE_EN);
927 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
929 if (old_fb && old_fb != crtc->fb) {
930 radeon_fb = to_radeon_framebuffer(old_fb);
931 rbo = radeon_fb->obj->driver_private;
932 r = radeon_bo_reserve(rbo, false);
933 if (unlikely(r != 0))
935 radeon_bo_unpin(rbo);
936 radeon_bo_unreserve(rbo);
939 /* Bytes per pixel may have changed */
940 radeon_bandwidth_update(rdev);
945 static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
946 struct drm_framebuffer *old_fb)
948 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
949 struct drm_device *dev = crtc->dev;
950 struct radeon_device *rdev = dev->dev_private;
951 struct radeon_framebuffer *radeon_fb;
952 struct drm_gem_object *obj;
953 struct radeon_bo *rbo;
954 uint64_t fb_location;
955 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
960 DRM_DEBUG("No FB bound\n");
964 radeon_fb = to_radeon_framebuffer(crtc->fb);
966 /* Pin framebuffer & get tilling informations */
967 obj = radeon_fb->obj;
968 rbo = obj->driver_private;
969 r = radeon_bo_reserve(rbo, false);
970 if (unlikely(r != 0))
972 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
973 if (unlikely(r != 0)) {
974 radeon_bo_unreserve(rbo);
977 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
978 radeon_bo_unreserve(rbo);
980 switch (crtc->fb->bits_per_pixel) {
983 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
984 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
988 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
989 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
993 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
994 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
999 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1000 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1003 DRM_ERROR("Unsupported screen depth %d\n",
1004 crtc->fb->bits_per_pixel);
1008 if (rdev->family >= CHIP_R600) {
1009 if (tiling_flags & RADEON_TILING_MACRO)
1010 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1011 else if (tiling_flags & RADEON_TILING_MICRO)
1012 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1014 if (tiling_flags & RADEON_TILING_MACRO)
1015 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1017 if (tiling_flags & RADEON_TILING_MICRO)
1018 fb_format |= AVIVO_D1GRPH_TILED;
1021 if (radeon_crtc->crtc_id == 0)
1022 WREG32(AVIVO_D1VGA_CONTROL, 0);
1024 WREG32(AVIVO_D2VGA_CONTROL, 0);
1026 if (rdev->family >= CHIP_RV770) {
1027 if (radeon_crtc->crtc_id) {
1028 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
1029 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
1031 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
1032 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
1035 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1037 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1038 radeon_crtc->crtc_offset, (u32) fb_location);
1039 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1041 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1042 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1043 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1044 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1045 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
1046 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
1048 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
1049 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1050 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1052 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1053 crtc->mode.vdisplay);
1056 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1058 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1059 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1061 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1062 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1063 AVIVO_D1MODE_INTERLEAVE_EN);
1065 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1067 if (old_fb && old_fb != crtc->fb) {
1068 radeon_fb = to_radeon_framebuffer(old_fb);
1069 rbo = radeon_fb->obj->driver_private;
1070 r = radeon_bo_reserve(rbo, false);
1071 if (unlikely(r != 0))
1073 radeon_bo_unpin(rbo);
1074 radeon_bo_unreserve(rbo);
1077 /* Bytes per pixel may have changed */
1078 radeon_bandwidth_update(rdev);
1083 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1084 struct drm_framebuffer *old_fb)
1086 struct drm_device *dev = crtc->dev;
1087 struct radeon_device *rdev = dev->dev_private;
1089 if (ASIC_IS_DCE4(rdev))
1090 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1091 else if (ASIC_IS_AVIVO(rdev))
1092 return avivo_crtc_set_base(crtc, x, y, old_fb);
1094 return radeon_crtc_set_base(crtc, x, y, old_fb);
1097 /* properly set additional regs when using atombios */
1098 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1100 struct drm_device *dev = crtc->dev;
1101 struct radeon_device *rdev = dev->dev_private;
1102 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1103 u32 disp_merge_cntl;
1105 switch (radeon_crtc->crtc_id) {
1107 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1108 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1109 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1112 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1113 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1114 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1115 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1116 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1121 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1123 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1124 struct drm_device *dev = crtc->dev;
1125 struct radeon_device *rdev = dev->dev_private;
1126 struct drm_encoder *test_encoder;
1127 struct drm_crtc *test_crtc;
1128 uint32_t pll_in_use = 0;
1130 if (ASIC_IS_DCE4(rdev)) {
1131 /* if crtc is driving DP and we have an ext clock, use that */
1132 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1133 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1134 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1135 if (rdev->clock.dp_extclk)
1136 return ATOM_PPLL_INVALID;
1141 /* otherwise, pick one of the plls */
1142 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1143 struct radeon_crtc *radeon_test_crtc;
1145 if (crtc == test_crtc)
1148 radeon_test_crtc = to_radeon_crtc(test_crtc);
1149 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1150 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1151 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1153 if (!(pll_in_use & 1))
1157 return radeon_crtc->crtc_id;
1161 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1162 struct drm_display_mode *mode,
1163 struct drm_display_mode *adjusted_mode,
1164 int x, int y, struct drm_framebuffer *old_fb)
1166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1167 struct drm_device *dev = crtc->dev;
1168 struct radeon_device *rdev = dev->dev_private;
1170 /* TODO color tiling */
1172 atombios_disable_ss(crtc);
1173 /* always set DCPLL */
1174 if (ASIC_IS_DCE4(rdev))
1175 atombios_crtc_set_dcpll(crtc);
1176 atombios_crtc_set_pll(crtc, adjusted_mode);
1177 atombios_enable_ss(crtc);
1179 if (ASIC_IS_DCE4(rdev))
1180 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1181 else if (ASIC_IS_AVIVO(rdev))
1182 atombios_crtc_set_timing(crtc, adjusted_mode);
1184 atombios_crtc_set_timing(crtc, adjusted_mode);
1185 if (radeon_crtc->crtc_id == 0)
1186 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1187 radeon_legacy_atom_fixup(crtc);
1189 atombios_crtc_set_base(crtc, x, y, old_fb);
1190 atombios_overscan_setup(crtc, mode, adjusted_mode);
1191 atombios_scaler_setup(crtc);
1195 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1196 struct drm_display_mode *mode,
1197 struct drm_display_mode *adjusted_mode)
1199 struct drm_device *dev = crtc->dev;
1200 struct radeon_device *rdev = dev->dev_private;
1202 /* adjust pm to upcoming mode change */
1203 radeon_pm_compute_clocks(rdev);
1205 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1210 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1212 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1215 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1217 atombios_lock_crtc(crtc, ATOM_ENABLE);
1218 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1221 static void atombios_crtc_commit(struct drm_crtc *crtc)
1223 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1224 atombios_lock_crtc(crtc, ATOM_DISABLE);
1227 static void atombios_crtc_disable(struct drm_crtc *crtc)
1229 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1230 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1232 switch (radeon_crtc->pll_id) {
1235 /* disable the ppll */
1236 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1237 0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1242 radeon_crtc->pll_id = -1;
1245 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1246 .dpms = atombios_crtc_dpms,
1247 .mode_fixup = atombios_crtc_mode_fixup,
1248 .mode_set = atombios_crtc_mode_set,
1249 .mode_set_base = atombios_crtc_set_base,
1250 .prepare = atombios_crtc_prepare,
1251 .commit = atombios_crtc_commit,
1252 .load_lut = radeon_crtc_load_lut,
1253 .disable = atombios_crtc_disable,
1256 void radeon_atombios_init_crtc(struct drm_device *dev,
1257 struct radeon_crtc *radeon_crtc)
1259 struct radeon_device *rdev = dev->dev_private;
1261 if (ASIC_IS_DCE4(rdev)) {
1262 switch (radeon_crtc->crtc_id) {
1265 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1268 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1271 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1274 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1277 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1280 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1284 if (radeon_crtc->crtc_id == 1)
1285 radeon_crtc->crtc_offset =
1286 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1288 radeon_crtc->crtc_offset = 0;
1290 radeon_crtc->pll_id = -1;
1291 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);