2 * Copyright 2010 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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26 #include "nouveau_drv.h"
27 #include "nouveau_bios.h"
28 #include "nouveau_pm.h"
30 static u32 read_clk(struct drm_device *, int, bool);
31 static u32 read_pll(struct drm_device *, int, u32);
34 read_vco(struct drm_device *dev, int clk)
36 u32 sctl = nv_rd32(dev, 0x4120 + (clk * 4));
37 if ((sctl & 0x00000030) != 0x00000030)
38 return read_pll(dev, 0x41, 0x00e820);
39 return read_pll(dev, 0x42, 0x00e8a0);
43 read_clk(struct drm_device *dev, int clk, bool ignore_en)
47 /* refclk for the 0xe8xx plls always 27KHz */
51 sctl = nv_rd32(dev, 0x4120 + (clk * 4));
52 if (!ignore_en && !(sctl & 0x00000100))
55 switch (sctl & 0x00003000) {
59 if (sctl & 0x00000040)
63 sclk = read_vco(dev, clk);
64 sdiv = ((sctl & 0x003f0000) >> 16) + 2;
65 return (sclk * 2) / sdiv;
72 read_pll(struct drm_device *dev, int clk, u32 pll)
74 u32 ctrl = nv_rd32(dev, pll + 0);
75 u32 sclk, P = 1, N = 1, M = 1;
77 if (!(ctrl & 0x00000008)) {
78 u32 coef = nv_rd32(dev, pll + 4);
79 M = (coef & 0x000000ff) >> 0;
80 N = (coef & 0x0000ff00) >> 8;
81 P = (coef & 0x003f0000) >> 16;
83 /* not post-divider on these.. */
84 if ((pll & 0x00ff00) == 0x00e800)
87 sclk = read_clk(dev, 0x00 + clk, false);
89 sclk = read_clk(dev, 0x10 + clk, false);
92 return sclk * N / (M * P);
101 calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg)
103 struct pll_lims limits;
104 u32 oclk, sclk, sdiv;
111 NV_DEBUG(dev, "no clock for 0x%04x/0x%02x\n", pll, clk);
117 reg->clk = 0x00000100;
120 reg->clk = 0x00002100;
123 reg->clk = 0x00002140;
126 sclk = read_vco(dev, clk);
127 sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
128 /* if the clock has a PLL attached, and we can get a within
129 * [-2, 3) MHz of a divider, we'll disable the PLL and use
130 * the divider instead.
132 * divider can go as low as 2, limited here because NVIDIA
133 * and the VBIOS on my NVA8 seem to prefer using the PLL
134 * for 810MHz - is there a good reason?
137 oclk = (sclk * 2) / sdiv;
139 if (!pll || (diff >= -2000 && diff < 3000)) {
140 reg->clk = (((sdiv - 2) << 16) | 0x00003100);
146 NV_ERROR(dev, "bad freq %02x: %d %d\n", clk, khz, sclk);
153 ret = get_pll_limits(dev, pll, &limits);
157 limits.refclk = read_clk(dev, clk - 0x10, true);
161 ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P);
163 reg->clk = nv_rd32(dev, 0x4120 + (clk * 4));
164 reg->pll = (P << 16) | (N << 8) | M;
170 prog_pll(struct drm_device *dev, int clk, u32 pll, struct creg *reg)
172 const u32 src0 = 0x004120 + (clk * 4);
173 const u32 src1 = 0x004160 + (clk * 4);
174 const u32 ctrl = pll + 0;
175 const u32 coef = pll + 4;
178 if (!reg->clk && !reg->pll) {
179 NV_DEBUG(dev, "no clock for %02x\n", clk);
183 cntl = nv_rd32(dev, ctrl) & 0xfffffff2;
185 nv_mask(dev, src0, 0x00000101, 0x00000101);
186 nv_wr32(dev, coef, reg->pll);
187 nv_wr32(dev, ctrl, cntl | 0x00000015);
188 nv_mask(dev, src1, 0x00000100, 0x00000000);
189 nv_mask(dev, src1, 0x00000001, 0x00000000);
191 nv_mask(dev, src1, 0x003f3141, 0x00000101 | reg->clk);
192 nv_wr32(dev, ctrl, cntl | 0x0000001d);
193 nv_mask(dev, ctrl, 0x00000001, 0x00000000);
194 nv_mask(dev, src0, 0x00000100, 0x00000000);
195 nv_mask(dev, src0, 0x00000001, 0x00000000);
200 prog_clk(struct drm_device *dev, int clk, struct creg *reg)
203 NV_DEBUG(dev, "no clock for %02x\n", clk);
207 nv_mask(dev, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | reg->clk);
211 nva3_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
213 perflvl->core = read_pll(dev, 0x00, 0x4200);
214 perflvl->shader = read_pll(dev, 0x01, 0x4220);
215 perflvl->memory = read_pll(dev, 0x02, 0x4000);
216 perflvl->unka0 = read_clk(dev, 0x20, false);
217 perflvl->vdec = read_clk(dev, 0x21, false);
218 perflvl->daemon = read_clk(dev, 0x25, false);
219 perflvl->copy = perflvl->core;
223 struct nva3_pm_state {
232 nva3_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
234 struct nva3_pm_state *info;
237 info = kzalloc(sizeof(*info), GFP_KERNEL);
239 return ERR_PTR(-ENOMEM);
241 ret = calc_clk(dev, 0x10, 0x4200, perflvl->core, &info->nclk);
245 ret = calc_clk(dev, 0x11, 0x4220, perflvl->shader, &info->sclk);
249 ret = calc_clk(dev, 0x12, 0x4000, perflvl->memory, &info->mclk);
253 ret = calc_clk(dev, 0x20, 0x0000, perflvl->unka0, &info->unka0);
257 ret = calc_clk(dev, 0x21, 0x0000, perflvl->vdec, &info->vdec);
270 nva3_pm_grcp_idle(void *data)
272 struct drm_device *dev = data;
274 if (!(nv_rd32(dev, 0x400304) & 0x00000001))
276 if (nv_rd32(dev, 0x400308) == 0x0050001c)
282 nva3_pm_clocks_set(struct drm_device *dev, void *pre_state)
284 struct drm_nouveau_private *dev_priv = dev->dev_private;
285 struct nva3_pm_state *info = pre_state;
288 /* prevent any new grctx switches from starting */
289 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
290 nv_wr32(dev, 0x400324, 0x00000000);
291 nv_wr32(dev, 0x400328, 0x0050001c); /* wait flag 0x1c */
292 /* wait for any pending grctx switches to complete */
293 if (!nv_wait_cb(dev, nva3_pm_grcp_idle, dev)) {
294 NV_ERROR(dev, "pm: ctxprog didn't go idle\n");
298 nv_mask(dev, 0x002504, 0x00000001, 0x00000001);
299 if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010)) {
300 NV_ERROR(dev, "pm: fifo didn't go idle\n");
304 prog_pll(dev, 0x00, 0x004200, &info->nclk);
305 prog_pll(dev, 0x01, 0x004220, &info->sclk);
306 prog_clk(dev, 0x20, &info->unka0);
307 prog_clk(dev, 0x21, &info->vdec);
309 nv_wr32(dev, 0x100210, 0);
310 nv_wr32(dev, 0x1002dc, 1);
311 nv_wr32(dev, 0x004018, 0x00001000);
312 prog_pll(dev, 0x02, 0x004000, &info->mclk);
313 if (nv_rd32(dev, 0x4000) & 0x00000008)
314 nv_wr32(dev, 0x004018, 0x1000d000);
316 nv_wr32(dev, 0x004018, 0x10005000);
317 nv_wr32(dev, 0x1002dc, 0);
318 nv_wr32(dev, 0x100210, 0x80000000);
322 nv_mask(dev, 0x002504, 0x00000001, 0x00000000);
323 /* restore ctxprog to normal */
324 nv_wr32(dev, 0x400324, 0x00000000);
325 nv_wr32(dev, 0x400328, 0x0070009c); /* set flag 0x1c */
326 /* unblock it if necessary */
327 if (nv_rd32(dev, 0x400308) == 0x0050001c)
328 nv_mask(dev, 0x400824, 0x10000000, 0x10000000);
329 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);