2 * Copyright (C) 2008 Maarten Maathuis.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <drm/drm_crtc_helper.h>
30 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
31 #include "nouveau_reg.h"
32 #include "nouveau_drm.h"
33 #include "nouveau_dma.h"
34 #include "nouveau_encoder.h"
35 #include "nouveau_connector.h"
36 #include "nouveau_crtc.h"
37 #include "nv50_display.h"
39 #include <subdev/timer.h>
42 nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_output *dcb, u8 lane)
44 struct nouveau_drm *drm = nouveau_drm(dev);
45 static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
46 static const u8 nv50[] = { 16, 8, 0, 24 };
47 if (nv_device(drm->device)->chipset == 0xaf)
53 nv50_sor_dp_train_set(struct drm_device *dev, struct dcb_output *dcb, u8 pattern)
55 struct nouveau_device *device = nouveau_dev(dev);
56 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
57 nv_mask(device, NV50_SOR_DP_CTRL(or, link), 0x0f000000, pattern << 24);
61 nv50_sor_dp_train_adj(struct drm_device *dev, struct dcb_output *dcb,
62 u8 lane, u8 swing, u8 preem)
64 struct nouveau_device *device = nouveau_dev(dev);
65 struct nouveau_drm *drm = nouveau_drm(dev);
66 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
67 u32 shift = nv50_sor_dp_lane_map(dev, dcb, lane);
68 u32 mask = 0x000000ff << shift;
69 u8 *table, *entry, *config;
71 table = nouveau_dp_bios_data(dev, dcb, &entry);
72 if (!table || (table[0] != 0x20 && table[0] != 0x21)) {
73 NV_ERROR(drm, "PDISP: unsupported DP table for chipset\n");
77 config = entry + table[4];
78 while (config[0] != swing || config[1] != preem) {
80 if (config >= entry + table[4] + entry[4] * table[5])
84 nv_mask(device, NV50_SOR_DP_UNK118(or, link), mask, config[2] << shift);
85 nv_mask(device, NV50_SOR_DP_UNK120(or, link), mask, config[3] << shift);
86 nv_mask(device, NV50_SOR_DP_UNK130(or, link), 0x0000ff00, config[4] << 8);
90 nv50_sor_dp_link_set(struct drm_device *dev, struct dcb_output *dcb, int crtc,
91 int link_nr, u32 link_bw, bool enhframe)
93 struct nouveau_device *device = nouveau_dev(dev);
94 struct nouveau_drm *drm = nouveau_drm(dev);
95 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
96 u32 dpctrl = nv_rd32(device, NV50_SOR_DP_CTRL(or, link)) & ~0x001f4000;
97 u32 clksor = nv_rd32(device, 0x614300 + (or * 0x800)) & ~0x000c0000;
98 u8 *table, *entry, mask;
101 table = nouveau_dp_bios_data(dev, dcb, &entry);
102 if (!table || (table[0] != 0x20 && table[0] != 0x21)) {
103 NV_ERROR(drm, "PDISP: unsupported DP table for chipset\n");
107 entry = ROMPTR(dev, entry[10]);
109 while (link_bw < ROM16(entry[0]) * 10)
112 nouveau_bios_run_init_table(dev, ROM16(entry[2]), dcb, crtc);
115 dpctrl |= ((1 << link_nr) - 1) << 16;
117 dpctrl |= 0x00004000;
119 if (link_bw > 162000)
120 clksor |= 0x00040000;
122 nv_wr32(device, 0x614300 + (or * 0x800), clksor);
123 nv_wr32(device, NV50_SOR_DP_CTRL(or, link), dpctrl);
126 for (i = 0; i < link_nr; i++)
127 mask |= 1 << (nv50_sor_dp_lane_map(dev, dcb, i) >> 3);
128 nv_mask(device, NV50_SOR_DP_UNK130(or, link), 0x0000000f, mask);
132 nv50_sor_dp_link_get(struct drm_device *dev, u32 or, u32 link, u32 *nr, u32 *bw)
134 struct nouveau_device *device = nouveau_dev(dev);
135 u32 dpctrl = nv_rd32(device, NV50_SOR_DP_CTRL(or, link)) & 0x000f0000;
136 u32 clksor = nv_rd32(device, 0x614300 + (or * 0x800));
137 if (clksor & 0x000c0000)
142 if (dpctrl > 0x00030000) *nr = 4;
143 else if (dpctrl > 0x00010000) *nr = 2;
148 nv50_sor_dp_calc_tu(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
150 struct nouveau_device *device = nouveau_dev(dev);
151 struct nouveau_drm *drm = nouveau_drm(dev);
152 const u32 symbol = 100000;
153 int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
154 int TU, VTUi, VTUf, VTUa;
155 u64 link_data_rate, link_ratio, unk;
156 u32 best_diff = 64 * symbol;
157 u32 link_nr, link_bw, r;
159 /* calculate packed data rate for each lane */
160 nv50_sor_dp_link_get(dev, or, link, &link_nr, &link_bw);
161 link_data_rate = (clk * bpp / 8) / link_nr;
163 /* calculate ratio of packed data rate to link symbol rate */
164 link_ratio = link_data_rate * symbol;
165 r = do_div(link_ratio, link_bw);
167 for (TU = 64; TU >= 32; TU--) {
168 /* calculate average number of valid symbols in each TU */
169 u32 tu_valid = link_ratio * TU;
172 /* find a hw representation for the fraction.. */
173 VTUi = tu_valid / symbol;
174 calc = VTUi * symbol;
175 diff = tu_valid - calc;
177 if (diff >= (symbol / 2)) {
178 VTUf = symbol / (symbol - diff);
179 if (symbol - (VTUf * diff))
184 calc += symbol - (symbol / VTUf);
192 VTUf = min((int)(symbol / diff), 15);
193 calc += symbol / VTUf;
196 diff = calc - tu_valid;
198 /* no remainder, but the hw doesn't like the fractional
199 * part to be zero. decrement the integer part and
200 * have the fraction add a whole symbol back
207 if (diff < best_diff) {
219 NV_ERROR(drm, "DP: unable to find suitable config\n");
223 /* XXX close to vbios numbers, but not right */
224 unk = (symbol - link_ratio) * bestTU;
226 r = do_div(unk, symbol);
227 r = do_div(unk, symbol);
230 nv_mask(device, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
231 nv_mask(device, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
237 nv50_sor_disconnect(struct drm_encoder *encoder)
239 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
240 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
241 struct drm_device *dev = encoder->dev;
242 struct nouveau_channel *evo = nv50_display(dev)->master;
245 if (!nv_encoder->crtc)
247 nv50_crtc_blank(nouveau_crtc(nv_encoder->crtc), true);
249 NV_DEBUG(drm, "Disconnecting SOR %d\n", nv_encoder->or);
251 ret = RING_SPACE(evo, 4);
253 NV_ERROR(drm, "no space while disconnecting SOR\n");
256 BEGIN_NV04(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1);
258 BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1);
261 nouveau_hdmi_mode_set(encoder, NULL);
263 nv_encoder->crtc = NULL;
264 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
268 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
270 struct nouveau_device *device = nouveau_dev(encoder->dev);
271 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
272 struct drm_device *dev = encoder->dev;
273 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
274 struct drm_encoder *enc;
276 int or = nv_encoder->or;
278 NV_DEBUG(drm, "or %d type %d mode %d\n", or, nv_encoder->dcb->type, mode);
280 nv_encoder->last_dpms = mode;
281 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
282 struct nouveau_encoder *nvenc = nouveau_encoder(enc);
284 if (nvenc == nv_encoder ||
285 (nvenc->dcb->type != DCB_OUTPUT_TMDS &&
286 nvenc->dcb->type != DCB_OUTPUT_LVDS &&
287 nvenc->dcb->type != DCB_OUTPUT_DP) ||
288 nvenc->dcb->or != nv_encoder->dcb->or)
291 if (nvenc->last_dpms == DRM_MODE_DPMS_ON)
295 /* wait for it to be done */
296 if (!nv_wait(device, NV50_PDISPLAY_SOR_DPMS_CTRL(or),
297 NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING, 0)) {
298 NV_ERROR(drm, "timeout: SOR_DPMS_CTRL_PENDING(%d) == 0\n", or);
299 NV_ERROR(drm, "SOR_DPMS_CTRL(%d) = 0x%08x\n", or,
300 nv_rd32(device, NV50_PDISPLAY_SOR_DPMS_CTRL(or)));
303 val = nv_rd32(device, NV50_PDISPLAY_SOR_DPMS_CTRL(or));
305 if (mode == DRM_MODE_DPMS_ON)
306 val |= NV50_PDISPLAY_SOR_DPMS_CTRL_ON;
308 val &= ~NV50_PDISPLAY_SOR_DPMS_CTRL_ON;
310 nv_wr32(device, NV50_PDISPLAY_SOR_DPMS_CTRL(or), val |
311 NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING);
312 if (!nv_wait(device, NV50_PDISPLAY_SOR_DPMS_STATE(or),
313 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
314 NV_ERROR(drm, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", or);
315 NV_ERROR(drm, "SOR_DPMS_STATE(%d) = 0x%08x\n", or,
316 nv_rd32(device, NV50_PDISPLAY_SOR_DPMS_STATE(or)));
319 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
320 struct dp_train_func func = {
321 .link_set = nv50_sor_dp_link_set,
322 .train_set = nv50_sor_dp_train_set,
323 .train_adj = nv50_sor_dp_train_adj
326 nouveau_dp_dpms(encoder, mode, nv_encoder->dp.datarate, &func);
331 nv50_sor_save(struct drm_encoder *encoder)
333 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
334 NV_ERROR(drm, "!!\n");
338 nv50_sor_restore(struct drm_encoder *encoder)
340 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
341 NV_ERROR(drm, "!!\n");
345 nv50_sor_mode_fixup(struct drm_encoder *encoder,
346 const struct drm_display_mode *mode,
347 struct drm_display_mode *adjusted_mode)
349 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
350 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
351 struct nouveau_connector *connector;
353 NV_DEBUG(drm, "or %d\n", nv_encoder->or);
355 connector = nouveau_encoder_connector_get(nv_encoder);
357 NV_ERROR(drm, "Encoder has no connector\n");
361 if (connector->scaling_mode != DRM_MODE_SCALE_NONE &&
362 connector->native_mode)
363 drm_mode_copy(adjusted_mode, connector->native_mode);
369 nv50_sor_prepare(struct drm_encoder *encoder)
371 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
372 nv50_sor_disconnect(encoder);
373 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
374 /* avoid race between link training and supervisor intr */
375 nv50_display_sync(encoder->dev);
380 nv50_sor_commit(struct drm_encoder *encoder)
385 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
386 struct drm_display_mode *mode)
388 struct nouveau_channel *evo = nv50_display(encoder->dev)->master;
389 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
390 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
391 struct nouveau_crtc *crtc = nouveau_crtc(encoder->crtc);
392 struct nouveau_connector *nv_connector;
393 uint32_t mode_ctl = 0;
396 NV_DEBUG(drm, "or %d type %d -> crtc %d\n",
397 nv_encoder->or, nv_encoder->dcb->type, crtc->index);
398 nv_encoder->crtc = encoder->crtc;
400 switch (nv_encoder->dcb->type) {
401 case DCB_OUTPUT_TMDS:
402 if (nv_encoder->dcb->sorconf.link & 1) {
403 if (mode->clock < 165000)
410 nouveau_hdmi_mode_set(encoder, mode);
413 nv_connector = nouveau_encoder_connector_get(nv_encoder);
414 if (nv_connector && nv_connector->base.display_info.bpc == 6) {
415 nv_encoder->dp.datarate = mode->clock * 18 / 8;
416 mode_ctl |= 0x00020000;
418 nv_encoder->dp.datarate = mode->clock * 24 / 8;
419 mode_ctl |= 0x00050000;
422 if (nv_encoder->dcb->sorconf.link & 1)
423 mode_ctl |= 0x00000800;
425 mode_ctl |= 0x00000900;
431 if (crtc->index == 1)
432 mode_ctl |= NV50_EVO_SOR_MODE_CTRL_CRTC1;
434 mode_ctl |= NV50_EVO_SOR_MODE_CTRL_CRTC0;
436 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
437 mode_ctl |= NV50_EVO_SOR_MODE_CTRL_NHSYNC;
439 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
440 mode_ctl |= NV50_EVO_SOR_MODE_CTRL_NVSYNC;
442 nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
444 ret = RING_SPACE(evo, 2);
446 NV_ERROR(drm, "no space while connecting SOR\n");
447 nv_encoder->crtc = NULL;
450 BEGIN_NV04(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1);
451 OUT_RING(evo, mode_ctl);
454 static struct drm_crtc *
455 nv50_sor_crtc_get(struct drm_encoder *encoder)
457 return nouveau_encoder(encoder)->crtc;
460 static const struct drm_encoder_helper_funcs nv50_sor_helper_funcs = {
461 .dpms = nv50_sor_dpms,
462 .save = nv50_sor_save,
463 .restore = nv50_sor_restore,
464 .mode_fixup = nv50_sor_mode_fixup,
465 .prepare = nv50_sor_prepare,
466 .commit = nv50_sor_commit,
467 .mode_set = nv50_sor_mode_set,
468 .get_crtc = nv50_sor_crtc_get,
470 .disable = nv50_sor_disconnect
474 nv50_sor_destroy(struct drm_encoder *encoder)
476 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
477 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
481 drm_encoder_cleanup(encoder);
486 static const struct drm_encoder_funcs nv50_sor_encoder_funcs = {
487 .destroy = nv50_sor_destroy,
491 nv50_sor_create(struct drm_connector *connector, struct dcb_output *entry)
493 struct nouveau_encoder *nv_encoder = NULL;
494 struct drm_device *dev = connector->dev;
495 struct nouveau_drm *drm = nouveau_drm(dev);
496 struct drm_encoder *encoder;
501 switch (entry->type) {
502 case DCB_OUTPUT_TMDS:
504 type = DRM_MODE_ENCODER_TMDS;
506 case DCB_OUTPUT_LVDS:
507 type = DRM_MODE_ENCODER_LVDS;
513 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
516 encoder = to_drm_encoder(nv_encoder);
518 nv_encoder->dcb = entry;
519 nv_encoder->or = ffs(entry->or) - 1;
520 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
522 drm_encoder_init(dev, encoder, &nv50_sor_encoder_funcs, type);
523 drm_encoder_helper_add(encoder, &nv50_sor_helper_funcs);
525 encoder->possible_crtcs = entry->heads;
526 encoder->possible_clones = 0;
528 drm_mode_connector_attach_encoder(connector, encoder);