2 * Copyright 2009 Marcin KoĆcielnicki
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #define CP_FLAG_CLEAR 0
25 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
26 #define CP_FLAG_SWAP_DIRECTION_LOAD 0
27 #define CP_FLAG_SWAP_DIRECTION_SAVE 1
28 #define CP_FLAG_UNK01 ((0 * 32) + 1)
29 #define CP_FLAG_UNK01_CLEAR 0
30 #define CP_FLAG_UNK01_SET 1
31 #define CP_FLAG_UNK03 ((0 * 32) + 3)
32 #define CP_FLAG_UNK03_CLEAR 0
33 #define CP_FLAG_UNK03_SET 1
34 #define CP_FLAG_USER_SAVE ((0 * 32) + 5)
35 #define CP_FLAG_USER_SAVE_NOT_PENDING 0
36 #define CP_FLAG_USER_SAVE_PENDING 1
37 #define CP_FLAG_USER_LOAD ((0 * 32) + 6)
38 #define CP_FLAG_USER_LOAD_NOT_PENDING 0
39 #define CP_FLAG_USER_LOAD_PENDING 1
40 #define CP_FLAG_UNK0B ((0 * 32) + 0xb)
41 #define CP_FLAG_UNK0B_CLEAR 0
42 #define CP_FLAG_UNK0B_SET 1
43 #define CP_FLAG_UNK1D ((0 * 32) + 0x1d)
44 #define CP_FLAG_UNK1D_CLEAR 0
45 #define CP_FLAG_UNK1D_SET 1
46 #define CP_FLAG_UNK20 ((1 * 32) + 0)
47 #define CP_FLAG_UNK20_CLEAR 0
48 #define CP_FLAG_UNK20_SET 1
49 #define CP_FLAG_STATUS ((2 * 32) + 0)
50 #define CP_FLAG_STATUS_BUSY 0
51 #define CP_FLAG_STATUS_IDLE 1
52 #define CP_FLAG_AUTO_SAVE ((2 * 32) + 4)
53 #define CP_FLAG_AUTO_SAVE_NOT_PENDING 0
54 #define CP_FLAG_AUTO_SAVE_PENDING 1
55 #define CP_FLAG_AUTO_LOAD ((2 * 32) + 5)
56 #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
57 #define CP_FLAG_AUTO_LOAD_PENDING 1
58 #define CP_FLAG_NEWCTX ((2 * 32) + 10)
59 #define CP_FLAG_NEWCTX_BUSY 0
60 #define CP_FLAG_NEWCTX_DONE 1
61 #define CP_FLAG_XFER ((2 * 32) + 11)
62 #define CP_FLAG_XFER_IDLE 0
63 #define CP_FLAG_XFER_BUSY 1
64 #define CP_FLAG_ALWAYS ((2 * 32) + 13)
65 #define CP_FLAG_ALWAYS_FALSE 0
66 #define CP_FLAG_ALWAYS_TRUE 1
67 #define CP_FLAG_INTR ((2 * 32) + 15)
68 #define CP_FLAG_INTR_NOT_PENDING 0
69 #define CP_FLAG_INTR_PENDING 1
71 #define CP_CTX 0x00100000
72 #define CP_CTX_COUNT 0x000f0000
73 #define CP_CTX_COUNT_SHIFT 16
74 #define CP_CTX_REG 0x00003fff
75 #define CP_LOAD_SR 0x00200000
76 #define CP_LOAD_SR_VALUE 0x000fffff
77 #define CP_BRA 0x00400000
78 #define CP_BRA_IP 0x0001ff00
79 #define CP_BRA_IP_SHIFT 8
80 #define CP_BRA_IF_CLEAR 0x00000080
81 #define CP_BRA_FLAG 0x0000007f
82 #define CP_WAIT 0x00500000
83 #define CP_WAIT_SET 0x00000080
84 #define CP_WAIT_FLAG 0x0000007f
85 #define CP_SET 0x00700000
86 #define CP_SET_1 0x00000080
87 #define CP_SET_FLAG 0x0000007f
88 #define CP_NEWCTX 0x00600004
89 #define CP_NEXT_TO_SWAP 0x00600005
90 #define CP_SET_CONTEXT_POINTER 0x00600006
91 #define CP_SET_XFER_POINTER 0x00600007
92 #define CP_ENABLE 0x00600009
93 #define CP_END 0x0060000c
94 #define CP_NEXT_TO_CURRENT 0x0060000d
95 #define CP_DISABLE1 0x0090ffff
96 #define CP_DISABLE2 0x0091ffff
97 #define CP_XFER_1 0x008000ff
98 #define CP_XFER_2 0x008800ff
99 #define CP_SEEK_1 0x00c000ff
100 #define CP_SEEK_2 0x00c800ff
103 #include "nouveau_drv.h"
104 #include "nouveau_grctx.h"
107 * This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's
108 * the GPU itself that does context-switching, but it needs a special
109 * microcode to do it. And it's the driver's task to supply this microcode,
110 * further known as ctxprog, as well as the initial context values, known
113 * Without ctxprog, you cannot switch contexts. Not even in software, since
114 * the majority of context [xfer strands] isn't accessible directly. You're
115 * stuck with a single channel, and you also suffer all the problems resulting
116 * from missing ctxvals, since you cannot load them.
118 * Without ctxvals, you're stuck with PGRAPH's default context. It's enough to
119 * run 2d operations, but trying to utilise 3d or CUDA will just lock you up,
120 * since you don't have... some sort of needed setup.
122 * Nouveau will just disable acceleration if not given ctxprog + ctxvals, since
123 * it's too much hassle to handle no-ctxprog as a special case.
129 * The ctxprog is written in its own kind of microcode, with very small and
130 * crappy set of available commands. You upload it to a small [512 insns]
131 * area of memory on PGRAPH, and it'll be run when PFIFO wants PGRAPH to
132 * switch channel. or when the driver explicitely requests it. Stuff visible
133 * to ctxprog consists of: PGRAPH MMIO registers, PGRAPH context strands,
134 * the per-channel context save area in VRAM [known as ctxvals or grctx],
135 * 4 flags registers, a scratch register, two grctx pointers, plus many
136 * random poorly-understood details.
138 * When ctxprog runs, it's supposed to check what operations are asked of it,
139 * save old context if requested, optionally reset PGRAPH and switch to the
140 * new channel, and load the new context. Context consists of three major
141 * parts: subset of MMIO registers and two "xfer areas".
145 * - document unimplemented bits compared to nvidia
146 * - NVAx: make a TP subroutine, use it.
147 * - use 0x4008fc instead of 0x1540?
160 static void nv50_graph_construct_mmio(struct nouveau_grctx *ctx);
161 static void nv50_graph_construct_xfer1(struct nouveau_grctx *ctx);
162 static void nv50_graph_construct_xfer2(struct nouveau_grctx *ctx);
164 /* Main function: construct the ctxprog skeleton, call the other functions. */
167 nv50_grctx_init(struct nouveau_grctx *ctx)
169 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
171 switch (dev_priv->chipset) {
186 NV_ERROR(ctx->dev, "I don't know how to make a ctxprog for "
187 "your NV%x card.\n", dev_priv->chipset);
188 NV_ERROR(ctx->dev, "Disabling acceleration. Please contact "
192 /* decide whether we're loading/unloading the context */
193 cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
194 cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);
196 cp_name(ctx, cp_check_load);
197 cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);
198 cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);
199 cp_bra (ctx, ALWAYS, TRUE, cp_exit);
201 /* setup for context load */
202 cp_name(ctx, cp_setup_auto_load);
203 cp_out (ctx, CP_DISABLE1);
204 cp_out (ctx, CP_DISABLE2);
205 cp_out (ctx, CP_ENABLE);
206 cp_out (ctx, CP_NEXT_TO_SWAP);
207 cp_set (ctx, UNK01, SET);
208 cp_name(ctx, cp_setup_load);
209 cp_out (ctx, CP_NEWCTX);
210 cp_wait(ctx, NEWCTX, BUSY);
211 cp_set (ctx, UNK1D, CLEAR);
212 cp_set (ctx, SWAP_DIRECTION, LOAD);
213 cp_bra (ctx, UNK0B, SET, cp_prepare_exit);
214 cp_bra (ctx, ALWAYS, TRUE, cp_swap_state);
216 /* setup for context save */
217 cp_name(ctx, cp_setup_save);
218 cp_set (ctx, UNK1D, SET);
219 cp_wait(ctx, STATUS, BUSY);
220 cp_wait(ctx, INTR, PENDING);
221 cp_bra (ctx, STATUS, BUSY, cp_setup_save);
222 cp_set (ctx, UNK01, SET);
223 cp_set (ctx, SWAP_DIRECTION, SAVE);
225 /* general PGRAPH state */
226 cp_name(ctx, cp_swap_state);
227 cp_set (ctx, UNK03, SET);
228 cp_pos (ctx, 0x00004/4);
229 cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */
230 cp_pos (ctx, 0x00100/4);
231 nv50_graph_construct_mmio(ctx);
232 nv50_graph_construct_xfer1(ctx);
233 nv50_graph_construct_xfer2(ctx);
235 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load);
237 cp_set (ctx, UNK20, SET);
238 cp_set (ctx, SWAP_DIRECTION, SAVE); /* no idea why this is needed, but fixes at least one lockup. */
239 cp_lsr (ctx, ctx->ctxvals_base);
240 cp_out (ctx, CP_SET_XFER_POINTER);
242 cp_out (ctx, CP_SEEK_1);
243 cp_out (ctx, CP_XFER_1);
244 cp_wait(ctx, XFER, BUSY);
246 /* pre-exit state updates */
247 cp_name(ctx, cp_prepare_exit);
248 cp_set (ctx, UNK01, CLEAR);
249 cp_set (ctx, UNK03, CLEAR);
250 cp_set (ctx, UNK1D, CLEAR);
252 cp_bra (ctx, USER_SAVE, PENDING, cp_exit);
253 cp_out (ctx, CP_NEXT_TO_CURRENT);
255 cp_name(ctx, cp_exit);
256 cp_set (ctx, USER_SAVE, NOT_PENDING);
257 cp_set (ctx, USER_LOAD, NOT_PENDING);
258 cp_out (ctx, CP_END);
259 ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */
265 * Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which
266 * registers to save/restore and the default values for them.
270 nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
272 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
275 uint32_t units = nv_rd32 (ctx->dev, 0x1540);
278 cp_ctx(ctx, 0x400808, 7);
279 gr_def(ctx, 0x400814, 0x00000030);
280 cp_ctx(ctx, 0x400834, 0x32);
281 if (dev_priv->chipset == 0x50) {
282 gr_def(ctx, 0x400834, 0xff400040);
283 gr_def(ctx, 0x400838, 0xfff00080);
284 gr_def(ctx, 0x40083c, 0xfff70090);
285 gr_def(ctx, 0x400840, 0xffe806a8);
287 gr_def(ctx, 0x400844, 0x00000002);
288 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
289 gr_def(ctx, 0x400894, 0x00001000);
290 gr_def(ctx, 0x4008e8, 0x00000003);
291 gr_def(ctx, 0x4008ec, 0x00001000);
292 if (dev_priv->chipset == 0x50)
293 cp_ctx(ctx, 0x400908, 0xb);
294 else if (dev_priv->chipset < 0xa0)
295 cp_ctx(ctx, 0x400908, 0xc);
297 cp_ctx(ctx, 0x400908, 0xe);
299 if (dev_priv->chipset >= 0xa0)
300 cp_ctx(ctx, 0x400b00, 0x1);
301 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) {
302 cp_ctx(ctx, 0x400b10, 0x1);
303 gr_def(ctx, 0x400b10, 0x0001629d);
304 cp_ctx(ctx, 0x400b20, 0x1);
305 gr_def(ctx, 0x400b20, 0x0001629d);
309 cp_ctx(ctx, 0x400c08, 0x2);
310 gr_def(ctx, 0x400c08, 0x0000fe0c);
313 if (dev_priv->chipset < 0xa0) {
314 cp_ctx(ctx, 0x401008, 0x4);
315 gr_def(ctx, 0x401014, 0x00001000);
316 } else if (dev_priv->chipset == 0xa0 || dev_priv->chipset >= 0xaa) {
317 cp_ctx(ctx, 0x401008, 0x5);
318 gr_def(ctx, 0x401018, 0x00001000);
320 cp_ctx(ctx, 0x401008, 0x5);
321 gr_def(ctx, 0x401018, 0x00004000);
325 cp_ctx(ctx, 0x401400, 0x8);
326 cp_ctx(ctx, 0x401424, 0x3);
327 if (dev_priv->chipset == 0x50)
328 gr_def(ctx, 0x40142c, 0x0001fd87);
330 gr_def(ctx, 0x40142c, 0x00000187);
331 cp_ctx(ctx, 0x401540, 0x5);
332 gr_def(ctx, 0x401550, 0x00001018);
334 /* 1800: STREAMOUT */
335 cp_ctx(ctx, 0x401814, 0x1);
336 gr_def(ctx, 0x401814, 0x000000ff);
337 if (dev_priv->chipset == 0x50) {
338 cp_ctx(ctx, 0x40181c, 0xe);
339 gr_def(ctx, 0x401850, 0x00000004);
340 } else if (dev_priv->chipset < 0xa0) {
341 cp_ctx(ctx, 0x40181c, 0xf);
342 gr_def(ctx, 0x401854, 0x00000004);
344 cp_ctx(ctx, 0x40181c, 0x13);
345 gr_def(ctx, 0x401864, 0x00000004);
349 cp_ctx(ctx, 0x401c00, 0x1);
350 switch (dev_priv->chipset) {
352 gr_def(ctx, 0x401c00, 0x0001005f);
357 gr_def(ctx, 0x401c00, 0x044d00df);
365 gr_def(ctx, 0x401c00, 0x042500df);
369 gr_def(ctx, 0x401c00, 0x142500df);
374 cp_ctx(ctx, 0x402400, 0x1);
375 if (dev_priv->chipset == 0x50)
376 cp_ctx(ctx, 0x402408, 0x1);
378 cp_ctx(ctx, 0x402408, 0x2);
379 gr_def(ctx, 0x402408, 0x00000600);
382 cp_ctx(ctx, 0x402800, 0x1);
383 if (dev_priv->chipset == 0x50)
384 gr_def(ctx, 0x402800, 0x00000006);
387 cp_ctx(ctx, 0x402c08, 0x6);
388 if (dev_priv->chipset != 0x50)
389 gr_def(ctx, 0x402c14, 0x01000000);
390 gr_def(ctx, 0x402c18, 0x000000ff);
391 if (dev_priv->chipset == 0x50)
392 cp_ctx(ctx, 0x402ca0, 0x1);
394 cp_ctx(ctx, 0x402ca0, 0x2);
395 if (dev_priv->chipset < 0xa0)
396 gr_def(ctx, 0x402ca0, 0x00000400);
397 else if (dev_priv->chipset == 0xa0 || dev_priv->chipset >= 0xaa)
398 gr_def(ctx, 0x402ca0, 0x00000800);
400 gr_def(ctx, 0x402ca0, 0x00000400);
401 cp_ctx(ctx, 0x402cac, 0x4);
404 cp_ctx(ctx, 0x403004, 0x1);
405 gr_def(ctx, 0x403004, 0x00000001);
408 if (dev_priv->chipset >= 0xa0) {
409 cp_ctx(ctx, 0x403404, 0x1);
410 gr_def(ctx, 0x403404, 0x00000001);
414 cp_ctx(ctx, 0x405000, 0x1);
415 switch (dev_priv->chipset) {
417 gr_def(ctx, 0x405000, 0x00300080);
425 gr_def(ctx, 0x405000, 0x000e0080);
432 gr_def(ctx, 0x405000, 0x00000080);
435 cp_ctx(ctx, 0x405014, 0x1);
436 gr_def(ctx, 0x405014, 0x00000004);
437 cp_ctx(ctx, 0x40501c, 0x1);
438 cp_ctx(ctx, 0x405024, 0x1);
439 cp_ctx(ctx, 0x40502c, 0x1);
441 /* 5400 or maybe 4800 */
442 if (dev_priv->chipset == 0x50) {
444 cp_ctx(ctx, 0x405400, 0xea);
445 } else if (dev_priv->chipset < 0x94) {
447 cp_ctx(ctx, 0x405400, 0xcb);
448 } else if (dev_priv->chipset < 0xa0) {
450 cp_ctx(ctx, 0x405400, 0xcc);
451 } else if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) {
453 cp_ctx(ctx, 0x404800, 0xda);
456 cp_ctx(ctx, 0x405400, 0xd4);
458 gr_def(ctx, offset + 0x0c, 0x00000002);
459 gr_def(ctx, offset + 0x10, 0x00000001);
460 if (dev_priv->chipset >= 0x94)
462 gr_def(ctx, offset + 0x1c, 0x00000001);
463 gr_def(ctx, offset + 0x20, 0x00000100);
464 gr_def(ctx, offset + 0x38, 0x00000002);
465 gr_def(ctx, offset + 0x3c, 0x00000001);
466 gr_def(ctx, offset + 0x40, 0x00000001);
467 gr_def(ctx, offset + 0x50, 0x00000001);
468 gr_def(ctx, offset + 0x54, 0x003fffff);
469 gr_def(ctx, offset + 0x58, 0x00001fff);
470 gr_def(ctx, offset + 0x60, 0x00000001);
471 gr_def(ctx, offset + 0x64, 0x00000001);
472 gr_def(ctx, offset + 0x6c, 0x00000001);
473 gr_def(ctx, offset + 0x70, 0x00000001);
474 gr_def(ctx, offset + 0x74, 0x00000001);
475 gr_def(ctx, offset + 0x78, 0x00000004);
476 gr_def(ctx, offset + 0x7c, 0x00000001);
477 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
479 gr_def(ctx, offset + 0x80, 0x00000001);
480 gr_def(ctx, offset + 0x84, 0x00000001);
481 gr_def(ctx, offset + 0x88, 0x00000007);
482 gr_def(ctx, offset + 0x8c, 0x00000001);
483 gr_def(ctx, offset + 0x90, 0x00000007);
484 gr_def(ctx, offset + 0x94, 0x00000001);
485 gr_def(ctx, offset + 0x98, 0x00000001);
486 gr_def(ctx, offset + 0x9c, 0x00000001);
487 if (dev_priv->chipset == 0x50) {
488 gr_def(ctx, offset + 0xb0, 0x00000001);
489 gr_def(ctx, offset + 0xb4, 0x00000001);
490 gr_def(ctx, offset + 0xbc, 0x00000001);
491 gr_def(ctx, offset + 0xc0, 0x0000000a);
492 gr_def(ctx, offset + 0xd0, 0x00000040);
493 gr_def(ctx, offset + 0xd8, 0x00000002);
494 gr_def(ctx, offset + 0xdc, 0x00000100);
495 gr_def(ctx, offset + 0xe0, 0x00000001);
496 gr_def(ctx, offset + 0xe4, 0x00000100);
497 gr_def(ctx, offset + 0x100, 0x00000001);
498 gr_def(ctx, offset + 0x124, 0x00000004);
499 gr_def(ctx, offset + 0x13c, 0x00000001);
500 gr_def(ctx, offset + 0x140, 0x00000100);
501 gr_def(ctx, offset + 0x148, 0x00000001);
502 gr_def(ctx, offset + 0x154, 0x00000100);
503 gr_def(ctx, offset + 0x158, 0x00000001);
504 gr_def(ctx, offset + 0x15c, 0x00000100);
505 gr_def(ctx, offset + 0x164, 0x00000001);
506 gr_def(ctx, offset + 0x170, 0x00000100);
507 gr_def(ctx, offset + 0x174, 0x00000001);
508 gr_def(ctx, offset + 0x17c, 0x00000001);
509 gr_def(ctx, offset + 0x188, 0x00000002);
510 gr_def(ctx, offset + 0x190, 0x00000001);
511 gr_def(ctx, offset + 0x198, 0x00000001);
512 gr_def(ctx, offset + 0x1ac, 0x00000003);
515 gr_def(ctx, offset + 0xb0, 0x00000001);
516 gr_def(ctx, offset + 0xb4, 0x00000100);
517 gr_def(ctx, offset + 0xbc, 0x00000001);
518 gr_def(ctx, offset + 0xc8, 0x00000100);
519 gr_def(ctx, offset + 0xcc, 0x00000001);
520 gr_def(ctx, offset + 0xd0, 0x00000100);
521 gr_def(ctx, offset + 0xd8, 0x00000001);
522 gr_def(ctx, offset + 0xe4, 0x00000100);
524 gr_def(ctx, offset + 0xf8, 0x00000004);
525 gr_def(ctx, offset + 0xfc, 0x00000070);
526 gr_def(ctx, offset + 0x100, 0x00000080);
527 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
529 gr_def(ctx, offset + 0x114, 0x0000000c);
530 if (dev_priv->chipset == 0x50)
532 gr_def(ctx, offset + 0x11c, 0x00000008);
533 gr_def(ctx, offset + 0x120, 0x00000014);
534 if (dev_priv->chipset == 0x50) {
535 gr_def(ctx, offset + 0x124, 0x00000026);
538 gr_def(ctx, offset + 0x128, 0x00000029);
539 gr_def(ctx, offset + 0x12c, 0x00000027);
540 gr_def(ctx, offset + 0x130, 0x00000026);
541 gr_def(ctx, offset + 0x134, 0x00000008);
542 gr_def(ctx, offset + 0x138, 0x00000004);
543 gr_def(ctx, offset + 0x13c, 0x00000027);
545 gr_def(ctx, offset + 0x148, 0x00000001);
546 gr_def(ctx, offset + 0x14c, 0x00000002);
547 gr_def(ctx, offset + 0x150, 0x00000003);
548 gr_def(ctx, offset + 0x154, 0x00000004);
549 gr_def(ctx, offset + 0x158, 0x00000005);
550 gr_def(ctx, offset + 0x15c, 0x00000006);
551 gr_def(ctx, offset + 0x160, 0x00000007);
552 gr_def(ctx, offset + 0x164, 0x00000001);
553 gr_def(ctx, offset + 0x1a8, 0x000000cf);
554 if (dev_priv->chipset == 0x50)
556 gr_def(ctx, offset + 0x1d8, 0x00000080);
557 gr_def(ctx, offset + 0x1dc, 0x00000004);
558 gr_def(ctx, offset + 0x1e0, 0x00000004);
559 if (dev_priv->chipset == 0x50)
562 gr_def(ctx, offset + 0x1e4, 0x00000003);
563 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) {
564 gr_def(ctx, offset + 0x1ec, 0x00000003);
567 gr_def(ctx, offset + 0x1e8, 0x00000001);
568 if (dev_priv->chipset == 0x50)
570 gr_def(ctx, offset + 0x1f4, 0x00000012);
571 gr_def(ctx, offset + 0x1f8, 0x00000010);
572 gr_def(ctx, offset + 0x1fc, 0x0000000c);
573 gr_def(ctx, offset + 0x200, 0x00000001);
574 gr_def(ctx, offset + 0x210, 0x00000004);
575 gr_def(ctx, offset + 0x214, 0x00000002);
576 gr_def(ctx, offset + 0x218, 0x00000004);
577 if (dev_priv->chipset >= 0xa0)
579 gr_def(ctx, offset + 0x224, 0x003fffff);
580 gr_def(ctx, offset + 0x228, 0x00001fff);
581 if (dev_priv->chipset == 0x50)
583 else if (dev_priv->chipset >= 0xa0) {
584 gr_def(ctx, offset + 0x250, 0x00000001);
585 gr_def(ctx, offset + 0x254, 0x00000001);
586 gr_def(ctx, offset + 0x258, 0x00000002);
589 gr_def(ctx, offset + 0x250, 0x00000004);
590 gr_def(ctx, offset + 0x254, 0x00000014);
591 gr_def(ctx, offset + 0x258, 0x00000001);
592 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
594 gr_def(ctx, offset + 0x264, 0x00000002);
595 if (dev_priv->chipset >= 0xa0)
597 gr_def(ctx, offset + 0x270, 0x00000001);
598 gr_def(ctx, offset + 0x278, 0x00000002);
599 gr_def(ctx, offset + 0x27c, 0x00001000);
600 if (dev_priv->chipset == 0x50)
603 gr_def(ctx, offset + 0x280, 0x00000e00);
604 gr_def(ctx, offset + 0x284, 0x00001000);
605 gr_def(ctx, offset + 0x288, 0x00001e00);
607 gr_def(ctx, offset + 0x290, 0x00000001);
608 gr_def(ctx, offset + 0x294, 0x00000001);
609 gr_def(ctx, offset + 0x298, 0x00000001);
610 gr_def(ctx, offset + 0x29c, 0x00000001);
611 gr_def(ctx, offset + 0x2a0, 0x00000001);
612 gr_def(ctx, offset + 0x2b0, 0x00000200);
613 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) {
614 gr_def(ctx, offset + 0x2b4, 0x00000200);
617 if (dev_priv->chipset < 0xa0) {
618 gr_def(ctx, offset + 0x2b8, 0x00000001);
619 gr_def(ctx, offset + 0x2bc, 0x00000070);
620 gr_def(ctx, offset + 0x2c0, 0x00000080);
621 gr_def(ctx, offset + 0x2cc, 0x00000001);
622 gr_def(ctx, offset + 0x2d0, 0x00000070);
623 gr_def(ctx, offset + 0x2d4, 0x00000080);
625 gr_def(ctx, offset + 0x2b8, 0x00000001);
626 gr_def(ctx, offset + 0x2bc, 0x000000f0);
627 gr_def(ctx, offset + 0x2c0, 0x000000ff);
628 gr_def(ctx, offset + 0x2cc, 0x00000001);
629 gr_def(ctx, offset + 0x2d0, 0x000000f0);
630 gr_def(ctx, offset + 0x2d4, 0x000000ff);
631 gr_def(ctx, offset + 0x2dc, 0x00000009);
634 gr_def(ctx, offset + 0x2e4, 0x00000001);
635 gr_def(ctx, offset + 0x2e8, 0x000000cf);
636 gr_def(ctx, offset + 0x2f0, 0x00000001);
637 gr_def(ctx, offset + 0x300, 0x000000cf);
638 gr_def(ctx, offset + 0x308, 0x00000002);
639 gr_def(ctx, offset + 0x310, 0x00000001);
640 gr_def(ctx, offset + 0x318, 0x00000001);
641 gr_def(ctx, offset + 0x320, 0x000000cf);
642 gr_def(ctx, offset + 0x324, 0x000000cf);
643 gr_def(ctx, offset + 0x328, 0x00000001);
646 if (dev_priv->chipset == 0x50)
647 cp_ctx(ctx, 0x4063e0, 0x1);
650 if (dev_priv->chipset < 0x90) {
651 cp_ctx(ctx, 0x406814, 0x2b);
652 gr_def(ctx, 0x406818, 0x00000f80);
653 gr_def(ctx, 0x406860, 0x007f0080);
654 gr_def(ctx, 0x40689c, 0x007f0080);
656 cp_ctx(ctx, 0x406814, 0x4);
657 if (dev_priv->chipset == 0x98)
658 gr_def(ctx, 0x406818, 0x00000f80);
660 gr_def(ctx, 0x406818, 0x00001f80);
661 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
662 gr_def(ctx, 0x40681c, 0x00000030);
663 cp_ctx(ctx, 0x406830, 0x3);
666 /* 7000: per-ROP group state */
667 for (i = 0; i < 8; i++) {
668 if (units & (1<<(i+16))) {
669 cp_ctx(ctx, 0x407000 + (i<<8), 3);
670 if (dev_priv->chipset == 0x50)
671 gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820);
672 else if (dev_priv->chipset != 0xa5)
673 gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821);
675 gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821);
676 gr_def(ctx, 0x407004 + (i<<8), 0x89058001);
678 if (dev_priv->chipset == 0x50) {
679 cp_ctx(ctx, 0x407010 + (i<<8), 1);
680 } else if (dev_priv->chipset < 0xa0) {
681 cp_ctx(ctx, 0x407010 + (i<<8), 2);
682 gr_def(ctx, 0x407010 + (i<<8), 0x00001000);
683 gr_def(ctx, 0x407014 + (i<<8), 0x0000001f);
685 cp_ctx(ctx, 0x407010 + (i<<8), 3);
686 gr_def(ctx, 0x407010 + (i<<8), 0x00001000);
687 if (dev_priv->chipset != 0xa5)
688 gr_def(ctx, 0x407014 + (i<<8), 0x000000ff);
690 gr_def(ctx, 0x407014 + (i<<8), 0x000001ff);
693 cp_ctx(ctx, 0x407080 + (i<<8), 4);
694 if (dev_priv->chipset != 0xa5)
695 gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa);
697 gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa);
698 if (dev_priv->chipset == 0x50)
699 gr_def(ctx, 0x407084 + (i<<8), 0x000000c0);
701 gr_def(ctx, 0x407084 + (i<<8), 0x400000c0);
702 gr_def(ctx, 0x407088 + (i<<8), 0xb7892080);
704 if (dev_priv->chipset < 0xa0)
705 cp_ctx(ctx, 0x407094 + (i<<8), 1);
706 else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa)
707 cp_ctx(ctx, 0x407094 + (i<<8), 3);
709 cp_ctx(ctx, 0x407094 + (i<<8), 4);
710 gr_def(ctx, 0x4070a0 + (i<<8), 1);
715 cp_ctx(ctx, 0x407c00, 0x3);
716 if (dev_priv->chipset < 0x90)
717 gr_def(ctx, 0x407c00, 0x00010040);
718 else if (dev_priv->chipset < 0xa0)
719 gr_def(ctx, 0x407c00, 0x00390040);
721 gr_def(ctx, 0x407c00, 0x003d0040);
722 gr_def(ctx, 0x407c08, 0x00000022);
723 if (dev_priv->chipset >= 0xa0) {
724 cp_ctx(ctx, 0x407c10, 0x3);
725 cp_ctx(ctx, 0x407c20, 0x1);
726 cp_ctx(ctx, 0x407c2c, 0x1);
729 if (dev_priv->chipset < 0xa0) {
730 cp_ctx(ctx, 0x407d00, 0x9);
732 cp_ctx(ctx, 0x407d00, 0x15);
734 if (dev_priv->chipset == 0x98)
735 gr_def(ctx, 0x407d08, 0x00380040);
737 if (dev_priv->chipset < 0x90)
738 gr_def(ctx, 0x407d08, 0x00010040);
739 else if (dev_priv->chipset < 0xa0)
740 gr_def(ctx, 0x407d08, 0x00390040);
742 gr_def(ctx, 0x407d08, 0x003d0040);
743 gr_def(ctx, 0x407d0c, 0x00000022);
746 /* 8000+: per-TP state */
747 for (i = 0; i < 10; i++) {
748 if (units & (1<<i)) {
749 if (dev_priv->chipset < 0xa0)
750 base = 0x408000 + (i<<12);
752 base = 0x408000 + (i<<11);
753 if (dev_priv->chipset < 0xa0)
754 offset = base + 0xc00;
756 offset = base + 0x80;
757 cp_ctx(ctx, offset + 0x00, 1);
758 gr_def(ctx, offset + 0x00, 0x0000ff0a);
759 cp_ctx(ctx, offset + 0x08, 1);
762 for (j = 0; j < (dev_priv->chipset < 0xa0 ? 2 : 4); j++) {
763 if (!(units & (1 << (j+24)))) continue;
764 if (dev_priv->chipset < 0xa0)
765 offset = base + 0x200 + (j<<7);
767 offset = base + 0x100 + (j<<7);
768 cp_ctx(ctx, offset, 0x20);
769 gr_def(ctx, offset + 0x00, 0x01800000);
770 gr_def(ctx, offset + 0x04, 0x00160000);
771 gr_def(ctx, offset + 0x08, 0x01800000);
772 gr_def(ctx, offset + 0x18, 0x0003ffff);
773 switch (dev_priv->chipset) {
775 gr_def(ctx, offset + 0x1c, 0x00080000);
778 gr_def(ctx, offset + 0x1c, 0x00880000);
781 gr_def(ctx, offset + 0x1c, 0x008c0000);
786 gr_def(ctx, offset + 0x1c, 0x118c0000);
789 gr_def(ctx, offset + 0x1c, 0x10880000);
793 gr_def(ctx, offset + 0x1c, 0x310c0000);
798 gr_def(ctx, offset + 0x1c, 0x300c0000);
801 gr_def(ctx, offset + 0x40, 0x00010401);
802 if (dev_priv->chipset == 0x50)
803 gr_def(ctx, offset + 0x48, 0x00000040);
805 gr_def(ctx, offset + 0x48, 0x00000078);
806 gr_def(ctx, offset + 0x50, 0x000000bf);
807 gr_def(ctx, offset + 0x58, 0x00001210);
808 if (dev_priv->chipset == 0x50)
809 gr_def(ctx, offset + 0x5c, 0x00000080);
811 gr_def(ctx, offset + 0x5c, 0x08000080);
812 if (dev_priv->chipset >= 0xa0)
813 gr_def(ctx, offset + 0x68, 0x0000003e);
816 if (dev_priv->chipset < 0xa0)
817 cp_ctx(ctx, base + 0x300, 0x4);
819 cp_ctx(ctx, base + 0x300, 0x5);
820 if (dev_priv->chipset == 0x50)
821 gr_def(ctx, base + 0x304, 0x00007070);
822 else if (dev_priv->chipset < 0xa0)
823 gr_def(ctx, base + 0x304, 0x00027070);
824 else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa)
825 gr_def(ctx, base + 0x304, 0x01127070);
827 gr_def(ctx, base + 0x304, 0x05127070);
829 if (dev_priv->chipset < 0xa0)
830 cp_ctx(ctx, base + 0x318, 1);
832 cp_ctx(ctx, base + 0x320, 1);
833 if (dev_priv->chipset == 0x50)
834 gr_def(ctx, base + 0x318, 0x0003ffff);
835 else if (dev_priv->chipset < 0xa0)
836 gr_def(ctx, base + 0x318, 0x03ffffff);
838 gr_def(ctx, base + 0x320, 0x07ffffff);
840 if (dev_priv->chipset < 0xa0)
841 cp_ctx(ctx, base + 0x324, 5);
843 cp_ctx(ctx, base + 0x328, 4);
845 if (dev_priv->chipset < 0xa0) {
846 cp_ctx(ctx, base + 0x340, 9);
847 offset = base + 0x340;
848 } else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) {
849 cp_ctx(ctx, base + 0x33c, 0xb);
850 offset = base + 0x344;
852 cp_ctx(ctx, base + 0x33c, 0xd);
853 offset = base + 0x344;
855 gr_def(ctx, offset + 0x0, 0x00120407);
856 gr_def(ctx, offset + 0x4, 0x05091507);
857 if (dev_priv->chipset == 0x84)
858 gr_def(ctx, offset + 0x8, 0x05100202);
860 gr_def(ctx, offset + 0x8, 0x05010202);
861 gr_def(ctx, offset + 0xc, 0x00030201);
863 cp_ctx(ctx, base + 0x400, 2);
864 gr_def(ctx, base + 0x404, 0x00000040);
865 cp_ctx(ctx, base + 0x40c, 2);
866 gr_def(ctx, base + 0x40c, 0x0d0c0b0a);
867 gr_def(ctx, base + 0x410, 0x00141210);
869 if (dev_priv->chipset < 0xa0)
870 offset = base + 0x800;
872 offset = base + 0x500;
873 cp_ctx(ctx, offset, 6);
874 gr_def(ctx, offset + 0x0, 0x000001f0);
875 gr_def(ctx, offset + 0x4, 0x00000001);
876 gr_def(ctx, offset + 0x8, 0x00000003);
877 if (dev_priv->chipset == 0x50 || dev_priv->chipset >= 0xaa)
878 gr_def(ctx, offset + 0xc, 0x00008000);
879 gr_def(ctx, offset + 0x14, 0x00039e00);
880 cp_ctx(ctx, offset + 0x1c, 2);
881 if (dev_priv->chipset == 0x50)
882 gr_def(ctx, offset + 0x1c, 0x00000040);
884 gr_def(ctx, offset + 0x1c, 0x00000100);
885 gr_def(ctx, offset + 0x20, 0x00003800);
887 if (dev_priv->chipset >= 0xa0) {
888 cp_ctx(ctx, base + 0x54c, 2);
889 if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa)
890 gr_def(ctx, base + 0x54c, 0x003fe006);
892 gr_def(ctx, base + 0x54c, 0x003fe007);
893 gr_def(ctx, base + 0x550, 0x003fe000);
896 if (dev_priv->chipset < 0xa0)
897 offset = base + 0xa00;
899 offset = base + 0x680;
900 cp_ctx(ctx, offset, 1);
901 gr_def(ctx, offset, 0x00404040);
903 if (dev_priv->chipset < 0xa0)
904 offset = base + 0xe00;
906 offset = base + 0x700;
907 cp_ctx(ctx, offset, 2);
908 if (dev_priv->chipset < 0xa0)
909 gr_def(ctx, offset, 0x0077f005);
910 else if (dev_priv->chipset == 0xa5)
911 gr_def(ctx, offset, 0x6cf7f007);
912 else if (dev_priv->chipset == 0xa8)
913 gr_def(ctx, offset, 0x6cfff007);
914 else if (dev_priv->chipset == 0xac)
915 gr_def(ctx, offset, 0x0cfff007);
917 gr_def(ctx, offset, 0x0cf7f007);
918 if (dev_priv->chipset == 0x50)
919 gr_def(ctx, offset + 0x4, 0x00007fff);
920 else if (dev_priv->chipset < 0xa0)
921 gr_def(ctx, offset + 0x4, 0x003f7fff);
923 gr_def(ctx, offset + 0x4, 0x02bf7fff);
924 cp_ctx(ctx, offset + 0x2c, 1);
925 if (dev_priv->chipset == 0x50) {
926 cp_ctx(ctx, offset + 0x50, 9);
927 gr_def(ctx, offset + 0x54, 0x000003ff);
928 gr_def(ctx, offset + 0x58, 0x00000003);
929 gr_def(ctx, offset + 0x5c, 0x00000003);
930 gr_def(ctx, offset + 0x60, 0x000001ff);
931 gr_def(ctx, offset + 0x64, 0x0000001f);
932 gr_def(ctx, offset + 0x68, 0x0000000f);
933 gr_def(ctx, offset + 0x6c, 0x0000000f);
934 } else if(dev_priv->chipset < 0xa0) {
935 cp_ctx(ctx, offset + 0x50, 1);
936 cp_ctx(ctx, offset + 0x70, 1);
938 cp_ctx(ctx, offset + 0x50, 1);
939 cp_ctx(ctx, offset + 0x60, 5);
946 * xfer areas. These are a pain.
948 * There are 2 xfer areas: the first one is big and contains all sorts of
949 * stuff, the second is small and contains some per-TP context.
951 * Each area is split into 8 "strands". The areas, when saved to grctx,
952 * are made of 8-word blocks. Each block contains a single word from
953 * each strand. The strands are independent of each other, their
954 * addresses are unrelated to each other, and data in them is closely
955 * packed together. The strand layout varies a bit between cards: here
956 * and there, a single word is thrown out in the middle and the whole
957 * strand is offset by a bit from corresponding one on another chipset.
958 * For this reason, addresses of stuff in strands are almost useless.
959 * Knowing sequence of stuff and size of gaps between them is much more
960 * useful, and that's how we build the strands in our generator.
962 * NVA0 takes this mess to a whole new level by cutting the old strands
963 * into a few dozen pieces [known as genes], rearranging them randomly,
964 * and putting them back together to make new strands. Hopefully these
965 * genes correspond more or less directly to the same PGRAPH subunits
966 * as in 400040 register.
968 * The most common value in default context is 0, and when the genes
969 * are separated by 0's, gene bounduaries are quite speculative...
970 * some of them can be clearly deduced, others can be guessed, and yet
971 * others won't be resolved without figuring out the real meaning of
972 * given ctxval. For the same reason, ending point of each strand
973 * is unknown. Except for strand 0, which is the longest strand and
974 * its end corresponds to end of the whole xfer.
976 * An unsolved mystery is the seek instruction: it takes an argument
977 * in bits 8-18, and that argument is clearly the place in strands to
978 * seek to... but the offsets don't seem to correspond to offsets as
979 * seen in grctx. Perhaps there's another, real, not randomly-changing
980 * addressing in strands, and the xfer insn just happens to skip over
981 * the unused bits? NV10-NV30 PIPE comes to mind...
983 * As far as I know, there's no way to access the xfer areas directly
984 * without the help of ctxprog.
988 xf_emit(struct nouveau_grctx *ctx, int num, uint32_t val) {
990 if (val && ctx->mode == NOUVEAU_GRCTX_VALS)
991 for (i = 0; i < num; i++)
992 nv_wo32(ctx->dev, ctx->data, ctx->ctxvals_pos + (i << 3), val);
993 ctx->ctxvals_pos += num << 3;
996 /* Gene declarations... */
998 static void nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx);
999 static void nv50_graph_construct_gene_unk1(struct nouveau_grctx *ctx);
1000 static void nv50_graph_construct_gene_unk2(struct nouveau_grctx *ctx);
1001 static void nv50_graph_construct_gene_unk3(struct nouveau_grctx *ctx);
1002 static void nv50_graph_construct_gene_unk4(struct nouveau_grctx *ctx);
1003 static void nv50_graph_construct_gene_unk5(struct nouveau_grctx *ctx);
1004 static void nv50_graph_construct_gene_unk6(struct nouveau_grctx *ctx);
1005 static void nv50_graph_construct_gene_unk7(struct nouveau_grctx *ctx);
1006 static void nv50_graph_construct_gene_unk8(struct nouveau_grctx *ctx);
1007 static void nv50_graph_construct_gene_unk9(struct nouveau_grctx *ctx);
1008 static void nv50_graph_construct_gene_unk10(struct nouveau_grctx *ctx);
1009 static void nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx);
1010 static void nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx);
1013 nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
1015 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1019 uint32_t units = nv_rd32 (ctx->dev, 0x1540);
1021 offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
1022 ctx->ctxvals_base = offset;
1024 if (dev_priv->chipset < 0xa0) {
1026 ctx->ctxvals_pos = offset;
1027 switch (dev_priv->chipset) {
1029 xf_emit(ctx, 0x99, 0);
1033 xf_emit(ctx, 0x384, 0);
1039 xf_emit(ctx, 0x380, 0);
1042 nv50_graph_construct_gene_m2mf (ctx);
1043 switch (dev_priv->chipset) {
1048 xf_emit(ctx, 0x4c4, 0);
1053 xf_emit(ctx, 0x984, 0);
1056 nv50_graph_construct_gene_unk5(ctx);
1057 if (dev_priv->chipset == 0x50)
1058 xf_emit(ctx, 0xa, 0);
1060 xf_emit(ctx, 0xb, 0);
1061 nv50_graph_construct_gene_unk4(ctx);
1062 nv50_graph_construct_gene_unk3(ctx);
1063 if ((ctx->ctxvals_pos-offset)/8 > size)
1064 size = (ctx->ctxvals_pos-offset)/8;
1067 ctx->ctxvals_pos = offset + 0x1;
1068 nv50_graph_construct_gene_unk6(ctx);
1069 nv50_graph_construct_gene_unk7(ctx);
1070 nv50_graph_construct_gene_unk8(ctx);
1071 switch (dev_priv->chipset) {
1074 xf_emit(ctx, 0xfb, 0);
1077 xf_emit(ctx, 0xd3, 0);
1081 xf_emit(ctx, 0xab, 0);
1085 xf_emit(ctx, 0x6b, 0);
1088 xf_emit(ctx, 2, 0x4e3bfdf);
1090 xf_emit(ctx, 1, 0x0fac6881);
1091 xf_emit(ctx, 0xb, 0);
1092 xf_emit(ctx, 2, 0x4e3bfdf);
1093 if ((ctx->ctxvals_pos-offset)/8 > size)
1094 size = (ctx->ctxvals_pos-offset)/8;
1097 ctx->ctxvals_pos = offset + 0x2;
1098 switch (dev_priv->chipset) {
1101 xf_emit(ctx, 0xa80, 0);
1104 xf_emit(ctx, 0xa7e, 0);
1108 xf_emit(ctx, 0xa7c, 0);
1112 xf_emit(ctx, 0xa7a, 0);
1115 xf_emit(ctx, 1, 0x3fffff);
1117 xf_emit(ctx, 1, 0x1fff);
1118 xf_emit(ctx, 0xe, 0);
1119 nv50_graph_construct_gene_unk9(ctx);
1120 nv50_graph_construct_gene_unk2(ctx);
1121 nv50_graph_construct_gene_unk1(ctx);
1122 nv50_graph_construct_gene_unk10(ctx);
1123 if ((ctx->ctxvals_pos-offset)/8 > size)
1124 size = (ctx->ctxvals_pos-offset)/8;
1126 /* Strand 3: per-ROP group state */
1127 ctx->ctxvals_pos = offset + 3;
1128 for (i = 0; i < 6; i++)
1129 if (units & (1 << (i + 16)))
1130 nv50_graph_construct_gene_ropc(ctx);
1131 if ((ctx->ctxvals_pos-offset)/8 > size)
1132 size = (ctx->ctxvals_pos-offset)/8;
1134 /* Strands 4-7: per-TP state */
1135 for (i = 0; i < 4; i++) {
1136 ctx->ctxvals_pos = offset + 4 + i;
1137 if (units & (1 << (2 * i)))
1138 nv50_graph_construct_xfer_tp(ctx);
1139 if (units & (1 << (2 * i + 1)))
1140 nv50_graph_construct_xfer_tp(ctx);
1141 if ((ctx->ctxvals_pos-offset)/8 > size)
1142 size = (ctx->ctxvals_pos-offset)/8;
1146 ctx->ctxvals_pos = offset;
1147 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1148 xf_emit(ctx, 0x385, 0);
1150 xf_emit(ctx, 0x384, 0);
1151 nv50_graph_construct_gene_m2mf(ctx);
1152 xf_emit(ctx, 0x950, 0);
1153 nv50_graph_construct_gene_unk10(ctx);
1154 xf_emit(ctx, 1, 0x0fac6881);
1155 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) {
1159 nv50_graph_construct_gene_unk8(ctx);
1160 if (dev_priv->chipset == 0xa0)
1161 xf_emit(ctx, 0x189, 0);
1162 else if (dev_priv->chipset < 0xa8)
1163 xf_emit(ctx, 0x99, 0);
1164 else if (dev_priv->chipset == 0xaa)
1165 xf_emit(ctx, 0x65, 0);
1167 xf_emit(ctx, 0x6d, 0);
1168 nv50_graph_construct_gene_unk9(ctx);
1169 if ((ctx->ctxvals_pos-offset)/8 > size)
1170 size = (ctx->ctxvals_pos-offset)/8;
1173 ctx->ctxvals_pos = offset + 1;
1174 nv50_graph_construct_gene_unk1(ctx);
1175 if ((ctx->ctxvals_pos-offset)/8 > size)
1176 size = (ctx->ctxvals_pos-offset)/8;
1179 ctx->ctxvals_pos = offset + 2;
1180 if (dev_priv->chipset == 0xa0) {
1181 nv50_graph_construct_gene_unk2(ctx);
1183 xf_emit(ctx, 0x36, 0);
1184 nv50_graph_construct_gene_unk5(ctx);
1185 if ((ctx->ctxvals_pos-offset)/8 > size)
1186 size = (ctx->ctxvals_pos-offset)/8;
1189 ctx->ctxvals_pos = offset + 3;
1192 nv50_graph_construct_gene_unk6(ctx);
1193 if ((ctx->ctxvals_pos-offset)/8 > size)
1194 size = (ctx->ctxvals_pos-offset)/8;
1197 ctx->ctxvals_pos = offset + 4;
1198 if (dev_priv->chipset == 0xa0)
1199 xf_emit(ctx, 0xa80, 0);
1201 xf_emit(ctx, 0xa7a, 0);
1202 xf_emit(ctx, 1, 0x3fffff);
1204 xf_emit(ctx, 1, 0x1fff);
1205 if ((ctx->ctxvals_pos-offset)/8 > size)
1206 size = (ctx->ctxvals_pos-offset)/8;
1209 ctx->ctxvals_pos = offset + 5;
1211 xf_emit(ctx, 1, 0x0fac6881);
1212 xf_emit(ctx, 0xb, 0);
1213 xf_emit(ctx, 2, 0x4e3bfdf);
1215 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1216 xf_emit(ctx, 1, 0x11);
1218 xf_emit(ctx, 2, 0x4e3bfdf);
1220 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1221 xf_emit(ctx, 1, 0x11);
1223 for (i = 0; i < 8; i++)
1224 if (units & (1<<(i+16)))
1225 nv50_graph_construct_gene_ropc(ctx);
1226 if ((ctx->ctxvals_pos-offset)/8 > size)
1227 size = (ctx->ctxvals_pos-offset)/8;
1230 ctx->ctxvals_pos = offset + 6;
1231 nv50_graph_construct_gene_unk3(ctx);
1232 xf_emit(ctx, 0xb, 0);
1233 nv50_graph_construct_gene_unk4(ctx);
1234 nv50_graph_construct_gene_unk7(ctx);
1235 if (units & (1 << 0))
1236 nv50_graph_construct_xfer_tp(ctx);
1237 if (units & (1 << 1))
1238 nv50_graph_construct_xfer_tp(ctx);
1239 if (units & (1 << 2))
1240 nv50_graph_construct_xfer_tp(ctx);
1241 if (units & (1 << 3))
1242 nv50_graph_construct_xfer_tp(ctx);
1243 if ((ctx->ctxvals_pos-offset)/8 > size)
1244 size = (ctx->ctxvals_pos-offset)/8;
1247 ctx->ctxvals_pos = offset + 7;
1248 if (dev_priv->chipset == 0xa0) {
1249 if (units & (1 << 4))
1250 nv50_graph_construct_xfer_tp(ctx);
1251 if (units & (1 << 5))
1252 nv50_graph_construct_xfer_tp(ctx);
1253 if (units & (1 << 6))
1254 nv50_graph_construct_xfer_tp(ctx);
1255 if (units & (1 << 7))
1256 nv50_graph_construct_xfer_tp(ctx);
1257 if (units & (1 << 8))
1258 nv50_graph_construct_xfer_tp(ctx);
1259 if (units & (1 << 9))
1260 nv50_graph_construct_xfer_tp(ctx);
1262 nv50_graph_construct_gene_unk2(ctx);
1264 if ((ctx->ctxvals_pos-offset)/8 > size)
1265 size = (ctx->ctxvals_pos-offset)/8;
1268 ctx->ctxvals_pos = offset + size * 8;
1269 ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f;
1270 cp_lsr (ctx, offset);
1271 cp_out (ctx, CP_SET_XFER_POINTER);
1273 cp_out (ctx, CP_SEEK_1);
1274 cp_out (ctx, CP_XFER_1);
1275 cp_wait(ctx, XFER, BUSY);
1279 * non-trivial demagiced parts of ctx init go here
1283 nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx)
1286 xf_emit (ctx, 1, 0); /* DMA_NOTIFY instance >> 4 */
1287 xf_emit (ctx, 1, 0); /* DMA_BUFFER_IN instance >> 4 */
1288 xf_emit (ctx, 1, 0); /* DMA_BUFFER_OUT instance >> 4 */
1289 xf_emit (ctx, 1, 0); /* OFFSET_IN */
1290 xf_emit (ctx, 1, 0); /* OFFSET_OUT */
1291 xf_emit (ctx, 1, 0); /* PITCH_IN */
1292 xf_emit (ctx, 1, 0); /* PITCH_OUT */
1293 xf_emit (ctx, 1, 0); /* LINE_LENGTH */
1294 xf_emit (ctx, 1, 0); /* LINE_COUNT */
1295 xf_emit (ctx, 1, 0x21); /* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */
1296 xf_emit (ctx, 1, 1); /* LINEAR_IN */
1297 xf_emit (ctx, 1, 0x2); /* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */
1298 xf_emit (ctx, 1, 0x100); /* TILING_PITCH_IN */
1299 xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_IN */
1300 xf_emit (ctx, 1, 1); /* TILING_DEPTH_IN */
1301 xf_emit (ctx, 1, 0); /* TILING_POSITION_IN_Z */
1302 xf_emit (ctx, 1, 0); /* TILING_POSITION_IN */
1303 xf_emit (ctx, 1, 1); /* LINEAR_OUT */
1304 xf_emit (ctx, 1, 0x2); /* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */
1305 xf_emit (ctx, 1, 0x100); /* TILING_PITCH_OUT */
1306 xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_OUT */
1307 xf_emit (ctx, 1, 1); /* TILING_DEPTH_OUT */
1308 xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT_Z */
1309 xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT */
1310 xf_emit (ctx, 1, 0); /* OFFSET_IN_HIGH */
1311 xf_emit (ctx, 1, 0); /* OFFSET_OUT_HIGH */
1315 nv50_graph_construct_gene_unk1(struct nouveau_grctx *ctx)
1317 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1318 /* end of area 2 on pre-NVA0, area 1 on NVAx */
1321 xf_emit(ctx, 1, 0x80);
1323 xf_emit(ctx, 1, 0x80c14);
1325 if (dev_priv->chipset == 0x50)
1326 xf_emit(ctx, 1, 0x3ff);
1328 xf_emit(ctx, 1, 0x7ff);
1329 switch (dev_priv->chipset) {
1335 xf_emit(ctx, 0x542, 0);
1341 xf_emit(ctx, 0x942, 0);
1344 xf_emit(ctx, 0x2042, 0);
1348 xf_emit(ctx, 0x842, 0);
1353 xf_emit(ctx, 1, 0x80);
1357 xf_emit(ctx, 1, 0x27);
1359 xf_emit(ctx, 1, 0x26);
1364 nv50_graph_construct_gene_unk10(struct nouveau_grctx *ctx)
1366 /* end of area 2 on pre-NVA0, area 1 on NVAx */
1367 xf_emit(ctx, 0x10, 0x04000000);
1368 xf_emit(ctx, 0x24, 0);
1369 xf_emit(ctx, 2, 0x04e3bfdf);
1371 xf_emit(ctx, 1, 0x1fe21);
1375 nv50_graph_construct_gene_unk2(struct nouveau_grctx *ctx)
1377 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1378 /* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */
1379 if (dev_priv->chipset != 0x50) {
1381 xf_emit(ctx, 1, 0x80c14);
1383 xf_emit(ctx, 1, 0x804);
1386 xf_emit(ctx, 1, 0x8100c12);
1391 xf_emit(ctx, 1, 0x10);
1392 if (dev_priv->chipset == 0x50)
1396 xf_emit(ctx, 1, 0x804);
1398 xf_emit(ctx, 1, 0x1a);
1399 if (dev_priv->chipset != 0x50)
1400 xf_emit(ctx, 1, 0x7f);
1403 xf_emit(ctx, 1, 0x80c14);
1405 xf_emit(ctx, 1, 0x8100c12);
1408 xf_emit(ctx, 1, 0x10);
1411 xf_emit(ctx, 1, 0x8100c12);
1413 if (dev_priv->chipset == 0x50)
1414 xf_emit(ctx, 1, 0x3ff);
1416 xf_emit(ctx, 1, 0x7ff);
1417 xf_emit(ctx, 1, 0x80c14);
1418 xf_emit(ctx, 0x38, 0);
1421 xf_emit(ctx, 1, 0x10);
1422 xf_emit(ctx, 0x38, 0);
1423 xf_emit(ctx, 2, 0x88);
1426 xf_emit(ctx, 0x16, 0);
1427 xf_emit(ctx, 1, 0x26);
1429 xf_emit(ctx, 1, 0x3f800000);
1430 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1434 xf_emit(ctx, 1, 0x1a);
1435 xf_emit(ctx, 1, 0x10);
1436 if (dev_priv->chipset != 0x50)
1437 xf_emit(ctx, 0x28, 0);
1439 xf_emit(ctx, 0x25, 0);
1440 xf_emit(ctx, 1, 0x52);
1442 xf_emit(ctx, 1, 0x26);
1446 xf_emit(ctx, 1, 0x1a);
1448 xf_emit(ctx, 1, 0x00ffff00);
1453 nv50_graph_construct_gene_unk3(struct nouveau_grctx *ctx)
1455 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1456 /* end of area 0 on pre-NVA0, beginning of area 6 on NVAx */
1457 xf_emit(ctx, 1, 0x3f);
1458 xf_emit(ctx, 0xa, 0);
1460 xf_emit(ctx, 2, 0x04000000);
1465 if (dev_priv->chipset == 0x50)
1466 xf_emit(ctx, 0x10, 0);
1468 xf_emit(ctx, 0x11, 0);
1470 xf_emit(ctx, 1, 0x1001);
1471 xf_emit(ctx, 4, 0xffff);
1472 xf_emit(ctx, 0x20, 0);
1473 xf_emit(ctx, 0x10, 0x3f800000);
1474 xf_emit(ctx, 1, 0x10);
1475 if (dev_priv->chipset == 0x50)
1484 nv50_graph_construct_gene_unk4(struct nouveau_grctx *ctx)
1486 /* middle of area 0 on pre-NVA0, middle of area 6 on NVAx */
1487 xf_emit(ctx, 2, 0x04000000);
1489 xf_emit(ctx, 1, 0x80);
1491 xf_emit(ctx, 1, 0x80);
1496 nv50_graph_construct_gene_unk5(struct nouveau_grctx *ctx)
1498 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1499 /* middle of area 0 on pre-NVA0 [after m2mf], end of area 2 on NVAx */
1501 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1502 xf_emit(ctx, 0x1c4d, 0);
1504 xf_emit(ctx, 0x1c4b, 0);
1506 xf_emit(ctx, 1, 0x8100c12);
1507 if (dev_priv->chipset != 0x50)
1510 xf_emit(ctx, 1, 0x8100c12);
1512 xf_emit(ctx, 1, 0x80c14);
1514 if (dev_priv->chipset >= 0xa0)
1516 xf_emit(ctx, 1, 0x80c14);
1518 xf_emit(ctx, 1, 0x8100c12);
1519 xf_emit(ctx, 1, 0x27);
1522 xf_emit(ctx, 0x3c1, 0);
1524 xf_emit(ctx, 0x16, 0);
1525 xf_emit(ctx, 1, 0x8100c12);
1530 nv50_graph_construct_gene_unk6(struct nouveau_grctx *ctx)
1532 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1533 /* beginning of area 1 on pre-NVA0 [after m2mf], area 3 on NVAx */
1535 xf_emit(ctx, 1, 0xf);
1536 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1540 xf_emit(ctx, 1, 0x20);
1541 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1542 xf_emit(ctx, 0x11, 0);
1543 else if (dev_priv->chipset >= 0xa0)
1544 xf_emit(ctx, 0xf, 0);
1546 xf_emit(ctx, 0xe, 0);
1547 xf_emit(ctx, 1, 0x1a);
1548 xf_emit(ctx, 0xd, 0);
1554 if (dev_priv->chipset == 0x50)
1555 xf_emit(ctx, 1, 0x3ff);
1557 xf_emit(ctx, 1, 0x7ff);
1558 if (dev_priv->chipset == 0xa8)
1559 xf_emit(ctx, 1, 0x1e00);
1560 xf_emit(ctx, 0xc, 0);
1561 xf_emit(ctx, 1, 0xf);
1562 if (dev_priv->chipset == 0x50)
1563 xf_emit(ctx, 0x125, 0);
1564 else if (dev_priv->chipset < 0xa0)
1565 xf_emit(ctx, 0x126, 0);
1566 else if (dev_priv->chipset == 0xa0 || dev_priv->chipset >= 0xaa)
1567 xf_emit(ctx, 0x124, 0);
1569 xf_emit(ctx, 0x1f7, 0);
1570 xf_emit(ctx, 1, 0xf);
1571 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1576 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1577 xf_emit(ctx, 0xa1, 0);
1579 xf_emit(ctx, 0x5a, 0);
1580 xf_emit(ctx, 1, 0xf);
1581 if (dev_priv->chipset < 0xa0)
1582 xf_emit(ctx, 0x834, 0);
1583 else if (dev_priv->chipset == 0xa0)
1584 xf_emit(ctx, 0x1873, 0);
1585 else if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1586 xf_emit(ctx, 0x8ba, 0);
1588 xf_emit(ctx, 0x833, 0);
1589 xf_emit(ctx, 1, 0xf);
1590 xf_emit(ctx, 0xf, 0);
1594 nv50_graph_construct_gene_unk7(struct nouveau_grctx *ctx)
1596 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1597 /* middle of area 1 on pre-NVA0 [after m2mf], middle of area 6 on NVAx */
1599 if (dev_priv->chipset == 0x50)
1605 xf_emit(ctx, 2, 0x100);
1606 xf_emit(ctx, 1, 0x11);
1613 xf_emit(ctx, 1, 0xcf);
1623 xf_emit(ctx, 1, 0x15);
1625 xf_emit(ctx, 1, 0x4444480);
1626 xf_emit(ctx, 0x37, 0);
1630 nv50_graph_construct_gene_unk8(struct nouveau_grctx *ctx)
1632 /* middle of area 1 on pre-NVA0 [after m2mf], middle of area 0 on NVAx */
1634 xf_emit(ctx, 1, 0x8100c12);
1636 xf_emit(ctx, 1, 0x100);
1638 xf_emit(ctx, 1, 0x10001);
1640 xf_emit(ctx, 1, 0x10001);
1642 xf_emit(ctx, 1, 0x10001);
1649 nv50_graph_construct_gene_unk9(struct nouveau_grctx *ctx)
1651 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1652 /* middle of area 2 on pre-NVA0 [after m2mf], end of area 0 on NVAx */
1653 xf_emit(ctx, 1, 0x3f800000);
1656 xf_emit(ctx, 1, 0x1a);
1659 xf_emit(ctx, 0x12, 0);
1660 xf_emit(ctx, 1, 0x00ffff00);
1662 xf_emit(ctx, 1, 0xf);
1664 xf_emit(ctx, 1, 0x0fac6881);
1665 xf_emit(ctx, 1, 0x11);
1666 xf_emit(ctx, 0xf, 0);
1669 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1671 else if (dev_priv->chipset >= 0xa0)
1675 xf_emit(ctx, 2, 0x04000000);
1678 xf_emit(ctx, 1, 0x52);
1679 if (dev_priv->chipset == 0x50) {
1680 xf_emit(ctx, 0x13, 0);
1684 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1685 xf_emit(ctx, 0x11, 0);
1687 xf_emit(ctx, 0x10, 0);
1689 xf_emit(ctx, 0x10, 0x3f800000);
1690 xf_emit(ctx, 1, 0x10);
1691 xf_emit(ctx, 0x26, 0);
1692 xf_emit(ctx, 1, 0x8100c12);
1697 xf_emit(ctx, 4, 0xffff);
1698 if (dev_priv->chipset != 0x50)
1700 if (dev_priv->chipset < 0xa0)
1701 xf_emit(ctx, 0x1f, 0);
1702 else if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1703 xf_emit(ctx, 0xc, 0);
1706 xf_emit(ctx, 1, 0x00ffff00);
1707 xf_emit(ctx, 1, 0x1a);
1708 if (dev_priv->chipset != 0x50) {
1712 if (dev_priv->chipset < 0xa0)
1713 xf_emit(ctx, 0x26, 0);
1715 xf_emit(ctx, 0x3c, 0);
1716 xf_emit(ctx, 1, 0x102);
1719 if (dev_priv->chipset >= 0xa0)
1723 if (dev_priv->chipset == 0x50)
1724 xf_emit(ctx, 1, 0x3ff);
1726 xf_emit(ctx, 1, 0x7ff);
1728 xf_emit(ctx, 1, 0x102);
1731 xf_emit(ctx, 0x2c, 0);
1735 nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
1737 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1739 if (dev_priv->chipset == 0x50) {
1740 magic2 = 0x00003e60;
1741 } else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) {
1742 magic2 = 0x001ffe67;
1744 magic2 = 0x00087e67;
1749 xf_emit(ctx, 1, magic2);
1751 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1754 if (dev_priv->chipset >= 0xa0 && dev_priv->chipset < 0xaa)
1755 xf_emit(ctx, 1, 0x15);
1758 xf_emit(ctx, 1, 0x10);
1762 if (dev_priv->chipset == 0x86 || dev_priv->chipset == 0x92 || dev_priv->chipset == 0x98 || dev_priv->chipset >= 0xa0) {
1764 xf_emit(ctx, 1, 0x400);
1765 xf_emit(ctx, 1, 0x300);
1766 xf_emit(ctx, 1, 0x1001);
1767 if (dev_priv->chipset != 0xa0) {
1768 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1771 xf_emit(ctx, 1, 0x15);
1779 xf_emit(ctx, 1, 0x10);
1782 xf_emit(ctx, 0x13, 0);
1783 xf_emit(ctx, 1, 0x10);
1784 xf_emit(ctx, 0x10, 0);
1785 xf_emit(ctx, 0x10, 0x3f800000);
1786 xf_emit(ctx, 0x19, 0);
1787 xf_emit(ctx, 1, 0x10);
1789 xf_emit(ctx, 1, 0x3f);
1796 if (dev_priv->chipset >= 0xa0) {
1798 xf_emit(ctx, 1, 0x1001);
1799 xf_emit(ctx, 0xb, 0);
1801 xf_emit(ctx, 0xc, 0);
1803 xf_emit(ctx, 1, 0x11);
1805 xf_emit(ctx, 1, 0xf);
1807 xf_emit(ctx, 1, 0x11);
1808 if (dev_priv->chipset == 0x50)
1818 xf_emit(ctx, 1, magic2);
1820 xf_emit(ctx, 1, 0x0fac6881);
1821 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) {
1823 xf_emit(ctx, 0x18, 1);
1832 xf_emit(ctx, 0x16, 0);
1834 if (dev_priv->chipset >= 0xa0)
1835 xf_emit(ctx, 0x1b, 0);
1837 xf_emit(ctx, 0x15, 0);
1844 if (dev_priv->chipset >= 0xa0)
1848 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) {
1849 xf_emit(ctx, 0x10, 1);
1851 xf_emit(ctx, 0x10, 1);
1856 xf_emit(ctx, 1, 0x11);
1858 xf_emit(ctx, 0x5b, 0);
1862 nv50_graph_construct_xfer_tp_x1(struct nouveau_grctx *ctx)
1864 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1866 if (dev_priv->chipset == 0x50)
1868 else if (dev_priv->chipset == 0x86 || dev_priv->chipset == 0x98 || dev_priv->chipset >= 0xa8)
1874 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1875 xf_emit(ctx, 0x24, 0);
1876 else if (dev_priv->chipset >= 0xa0)
1877 xf_emit(ctx, 0x14, 0);
1879 xf_emit(ctx, 0x15, 0);
1881 if (dev_priv->chipset >= 0xa0)
1882 xf_emit(ctx, 1, 0x03020100);
1884 xf_emit(ctx, 1, 0x00608080);
1889 xf_emit(ctx, 1, 0x80);
1891 xf_emit(ctx, 1, magic3);
1893 xf_emit(ctx, 0x24, 0);
1895 xf_emit(ctx, 1, 0x80);
1897 xf_emit(ctx, 1, 0x03020100);
1900 xf_emit(ctx, 1, magic3);
1907 if (dev_priv->chipset == 0x94 || dev_priv->chipset == 0x96)
1908 xf_emit(ctx, 0x1024, 0);
1909 else if (dev_priv->chipset < 0xa0)
1910 xf_emit(ctx, 0xa24, 0);
1911 else if (dev_priv->chipset == 0xa0 || dev_priv->chipset >= 0xaa)
1912 xf_emit(ctx, 0x214, 0);
1914 xf_emit(ctx, 0x414, 0);
1921 nv50_graph_construct_xfer_tp_x2(struct nouveau_grctx *ctx)
1923 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1925 if (dev_priv->chipset == 0x50) {
1927 magic2 = 0x00003e60;
1928 } else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) {
1930 magic2 = 0x001ffe67;
1933 magic2 = 0x00087e67;
1936 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1938 xf_emit(ctx, 0xc, 0);
1939 xf_emit(ctx, 1, 0xf);
1940 xf_emit(ctx, 0xb, 0);
1942 xf_emit(ctx, 4, 0xffff);
1950 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) {
1953 } else if (dev_priv->chipset >= 0xa0)
1955 xf_emit(ctx, 0xa, 0);
1960 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) {
1962 xf_emit(ctx, 0x18, 1);
1971 xf_emit(ctx, 1, 0x11);
1973 xf_emit(ctx, 1, 0x0fac6881);
1977 xf_emit(ctx, 1, 0x11);
1980 xf_emit(ctx, 3, 0xcf);
1981 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
1983 xf_emit(ctx, 0xa, 0);
1991 xf_emit(ctx, 1, 0x11);
1993 xf_emit(ctx, 1, 0x0fac6881);
1994 xf_emit(ctx, 1, 0xf);
1996 xf_emit(ctx, 1, magic2);
1998 xf_emit(ctx, 1, 0x11);
1999 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
2003 if(dev_priv->chipset == 0x50)
2011 xf_emit(ctx, 1, 0x11);
2013 xf_emit(ctx, 1, 0x0fac6881);
2015 xf_emit(ctx, 1, 0x11);
2022 xf_emit(ctx, 1, magic1);
2028 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
2030 xf_emit(ctx, 0x28, 0);
2032 xf_emit(ctx, 1, 0x11);
2034 xf_emit(ctx, 1, 0x0fac6881);
2035 xf_emit(ctx, 8, 0x400);
2036 xf_emit(ctx, 8, 0x300);
2038 xf_emit(ctx, 1, 0xf);
2040 xf_emit(ctx, 1, 0x20);
2041 xf_emit(ctx, 1, 0x11);
2042 xf_emit(ctx, 1, 0x100);
2046 xf_emit(ctx, 1, 0x40);
2047 xf_emit(ctx, 1, 0x100);
2051 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
2053 xf_emit(ctx, 1, magic2);
2056 xf_emit(ctx, 1, 0x0fac6881);
2063 xf_emit(ctx, 1, 0x400);
2064 xf_emit(ctx, 1, 0x300);
2065 xf_emit(ctx, 1, 0x1001);
2066 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
2070 xf_emit(ctx, 1, 0x11);
2072 xf_emit(ctx, 1, 0x0fac6881);
2073 xf_emit(ctx, 1, 0xf);
2074 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) {
2075 xf_emit(ctx, 0x15, 0);
2079 xf_emit(ctx, 0x17, 0);
2080 if (dev_priv->chipset >= 0xa0)
2081 xf_emit(ctx, 1, 0x0fac6881);
2082 xf_emit(ctx, 1, magic2);
2084 xf_emit(ctx, 1, 0x11);
2090 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
2094 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
2096 else if (dev_priv->chipset != 0x50)
2101 nv50_graph_construct_xfer_tp_x3(struct nouveau_grctx *ctx)
2103 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2108 if (dev_priv->chipset == 0x50)
2112 xf_emit(ctx, 1, 0x2a712488);
2114 xf_emit(ctx, 1, 0x4085c000);
2115 xf_emit(ctx, 1, 0x40);
2116 xf_emit(ctx, 1, 0x100);
2117 xf_emit(ctx, 1, 0x10100);
2118 xf_emit(ctx, 1, 0x02800000);
2122 nv50_graph_construct_xfer_tp_x4(struct nouveau_grctx *ctx)
2124 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2125 xf_emit(ctx, 2, 0x04e3bfdf);
2128 xf_emit(ctx, 1, 0x00ffff00);
2129 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
2134 xf_emit(ctx, 1, 0x00ffff00);
2139 xf_emit(ctx, 1, 0x30201000);
2140 xf_emit(ctx, 1, 0x70605040);
2141 xf_emit(ctx, 1, 0xb8a89888);
2142 xf_emit(ctx, 1, 0xf8e8d8c8);
2144 xf_emit(ctx, 1, 0x1a);
2148 nv50_graph_construct_xfer_tp_x5(struct nouveau_grctx *ctx)
2150 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2152 xf_emit(ctx, 1, 0xfac6881);
2159 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
2160 xf_emit(ctx, 0xb, 0);
2162 xf_emit(ctx, 0xa, 0);
2164 xf_emit(ctx, 1, 0x11);
2166 xf_emit(ctx, 1, 0xfac6881);
2167 xf_emit(ctx, 1, 0xf);
2169 xf_emit(ctx, 1, 0x11);
2171 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) {
2176 xf_emit(ctx, 0xb, 0);
2181 nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx)
2183 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2184 if (dev_priv->chipset < 0xa0) {
2185 nv50_graph_construct_xfer_tp_x1(ctx);
2186 nv50_graph_construct_xfer_tp_x2(ctx);
2187 nv50_graph_construct_xfer_tp_x3(ctx);
2188 if (dev_priv->chipset == 0x50)
2189 xf_emit(ctx, 0xf, 0);
2191 xf_emit(ctx, 0x12, 0);
2192 nv50_graph_construct_xfer_tp_x4(ctx);
2194 nv50_graph_construct_xfer_tp_x3(ctx);
2195 if (dev_priv->chipset < 0xaa)
2196 xf_emit(ctx, 0xc, 0);
2198 xf_emit(ctx, 0xa, 0);
2199 nv50_graph_construct_xfer_tp_x2(ctx);
2200 nv50_graph_construct_xfer_tp_x5(ctx);
2201 nv50_graph_construct_xfer_tp_x4(ctx);
2202 nv50_graph_construct_xfer_tp_x1(ctx);
2207 nv50_graph_construct_xfer_tp2(struct nouveau_grctx *ctx)
2209 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2211 if (dev_priv->chipset == 0x98 || dev_priv->chipset == 0xaa)
2213 else if (dev_priv->chipset < 0xa0 || dev_priv->chipset >= 0xa8)
2217 for (i = 0; i < mpcnt; i++) {
2219 xf_emit(ctx, 1, 0x80);
2220 xf_emit(ctx, 1, 0x80007004);
2221 xf_emit(ctx, 1, 0x04000400);
2222 if (dev_priv->chipset >= 0xa0)
2223 xf_emit(ctx, 1, 0xc0);
2224 xf_emit(ctx, 1, 0x1000);
2226 if (dev_priv->chipset == 0x86 || dev_priv->chipset == 0x98 || dev_priv->chipset >= 0xa8) {
2227 xf_emit(ctx, 1, 0xe00);
2228 xf_emit(ctx, 1, 0x1e00);
2232 if (dev_priv->chipset == 0x50)
2233 xf_emit(ctx, 2, 0x1000);
2238 if (dev_priv->chipset >= 0xaa)
2239 xf_emit(ctx, 0xb, 0);
2240 else if (dev_priv->chipset >= 0xa0)
2241 xf_emit(ctx, 0xc, 0);
2243 xf_emit(ctx, 0xa, 0);
2245 xf_emit(ctx, 1, 0x08100c12);
2247 if (dev_priv->chipset >= 0xa0) {
2248 xf_emit(ctx, 1, 0x1fe21);
2251 xf_emit(ctx, 4, 0xffff);
2253 xf_emit(ctx, 2, 0x10001);
2256 xf_emit(ctx, 1, 0x1fe21);
2258 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
2261 xf_emit(ctx, 1, 0x08100c12);
2265 xf_emit(ctx, 1, 0x11);
2267 xf_emit(ctx, 1, 0xfac6881);
2269 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa)
2279 if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) {
2281 xf_emit(ctx, 0x10, 1);
2283 xf_emit(ctx, 0x18, 1);
2287 if (dev_priv->chipset == 0x50)
2288 xf_emit(ctx, 0x3a0, 0);
2289 else if (dev_priv->chipset < 0x94)
2290 xf_emit(ctx, 0x3a2, 0);
2291 else if (dev_priv->chipset == 0x98 || dev_priv->chipset == 0xaa)
2292 xf_emit(ctx, 0x39f, 0);
2294 xf_emit(ctx, 0x3a3, 0);
2295 xf_emit(ctx, 1, 0x11);
2298 xf_emit(ctx, 0x2d, 0);
2302 nv50_graph_construct_xfer2(struct nouveau_grctx *ctx)
2304 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2307 uint32_t units = nv_rd32 (ctx->dev, 0x1540);
2310 offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
2312 if (dev_priv->chipset < 0xa0) {
2313 for (i = 0; i < 8; i++) {
2314 ctx->ctxvals_pos = offset + i;
2316 xf_emit(ctx, 1, 0x08100c12);
2317 if (units & (1 << i))
2318 nv50_graph_construct_xfer_tp2(ctx);
2319 if ((ctx->ctxvals_pos-offset)/8 > size)
2320 size = (ctx->ctxvals_pos-offset)/8;
2323 /* Strand 0: TPs 0, 1 */
2324 ctx->ctxvals_pos = offset;
2325 xf_emit(ctx, 1, 0x08100c12);
2326 if (units & (1 << 0))
2327 nv50_graph_construct_xfer_tp2(ctx);
2328 if (units & (1 << 1))
2329 nv50_graph_construct_xfer_tp2(ctx);
2330 if ((ctx->ctxvals_pos-offset)/8 > size)
2331 size = (ctx->ctxvals_pos-offset)/8;
2333 /* Strand 0: TPs 2, 3 */
2334 ctx->ctxvals_pos = offset + 1;
2335 if (units & (1 << 2))
2336 nv50_graph_construct_xfer_tp2(ctx);
2337 if (units & (1 << 3))
2338 nv50_graph_construct_xfer_tp2(ctx);
2339 if ((ctx->ctxvals_pos-offset)/8 > size)
2340 size = (ctx->ctxvals_pos-offset)/8;
2342 /* Strand 0: TPs 4, 5, 6 */
2343 ctx->ctxvals_pos = offset + 2;
2344 if (units & (1 << 4))
2345 nv50_graph_construct_xfer_tp2(ctx);
2346 if (units & (1 << 5))
2347 nv50_graph_construct_xfer_tp2(ctx);
2348 if (units & (1 << 6))
2349 nv50_graph_construct_xfer_tp2(ctx);
2350 if ((ctx->ctxvals_pos-offset)/8 > size)
2351 size = (ctx->ctxvals_pos-offset)/8;
2353 /* Strand 0: TPs 7, 8, 9 */
2354 ctx->ctxvals_pos = offset + 3;
2355 if (units & (1 << 7))
2356 nv50_graph_construct_xfer_tp2(ctx);
2357 if (units & (1 << 8))
2358 nv50_graph_construct_xfer_tp2(ctx);
2359 if (units & (1 << 9))
2360 nv50_graph_construct_xfer_tp2(ctx);
2361 if ((ctx->ctxvals_pos-offset)/8 > size)
2362 size = (ctx->ctxvals_pos-offset)/8;
2364 ctx->ctxvals_pos = offset + size * 8;
2365 ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f;
2366 cp_lsr (ctx, offset);
2367 cp_out (ctx, CP_SET_XFER_POINTER);
2369 cp_out (ctx, CP_SEEK_2);
2370 cp_out (ctx, CP_XFER_2);
2371 cp_wait(ctx, XFER, BUSY);