drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "nv50_display.h"
  28 #include "nouveau_crtc.h"
  29 #include "nouveau_encoder.h"
  30 #include "nouveau_connector.h"
  31 #include "nouveau_fb.h"
  32 #include "nouveau_fbcon.h"
  33 #include "drm_crtc_helper.h"
  34
  35 static void
  36 nv50_evo_channel_del(struct nouveau_channel **pchan)
  37 {
  38         struct nouveau_channel *chan = *pchan;
  39
  40         if (!chan)
  41                 return;
  42         *pchan = NULL;
  43
  44         nouveau_gpuobj_channel_takedown(chan);
  45         nouveau_bo_unmap(chan->pushbuf_bo);
  46         nouveau_bo_ref(NULL, &chan->pushbuf_bo);
  47
  48         if (chan->user)
  49                 iounmap(chan->user);
  50
  51         kfree(chan);
  52 }
  53
  54 static int
  55 nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
  56                     uint32_t tile_flags, uint32_t magic_flags,
  57                     uint32_t offset, uint32_t limit)
  58 {
  59         struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
  60         struct drm_device *dev = evo->dev;
  61         struct nouveau_gpuobj *obj = NULL;
  62         int ret;
  63
  64         ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
  65         if (ret)
  66                 return ret;
  67         obj->engine = NVOBJ_ENGINE_DISPLAY;
  68
  69         ret = nouveau_gpuobj_ref_add(dev, evo, name, obj, NULL);
  70         if (ret) {
  71                 nouveau_gpuobj_del(dev, &obj);
  72                 return ret;
  73         }
  74
  75         nv_wo32(dev, obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
  76         nv_wo32(dev, obj, 1, limit);
  77         nv_wo32(dev, obj, 2, offset);
  78         nv_wo32(dev, obj, 3, 0x00000000);
  79         nv_wo32(dev, obj, 4, 0x00000000);
  80         if (dev_priv->card_type < NV_C0)
  81                 nv_wo32(dev, obj, 5, 0x00010000);
  82         else
  83                 nv_wo32(dev, obj, 5, 0x00020000);
  84         dev_priv->engine.instmem.flush(dev);
  85
  86         return 0;
  87 }
  88
  89 static int
  90 nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
  91 {
  92         struct drm_nouveau_private *dev_priv = dev->dev_private;
  93         struct nouveau_channel *chan;
  94         int ret;
  95
  96         chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
  97         if (!chan)
  98                 return -ENOMEM;
  99         *pchan = chan;
 100
 101         chan->id = -1;
 102         chan->dev = dev;
 103         chan->user_get = 4;
 104         chan->user_put = 0;
 105
 106         INIT_LIST_HEAD(&chan->ramht_refs);
 107
 108         ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32768, 0x1000,
 109                                      NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
 110         if (ret) {
 111                 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
 112                 nv50_evo_channel_del(pchan);
 113                 return ret;
 114         }
 115
 116         ret = drm_mm_init(&chan->ramin_heap,
 117                           chan->ramin->gpuobj->im_pramin->start, 32768);
 118         if (ret) {
 119                 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
 120                 nv50_evo_channel_del(pchan);
 121                 return ret;
 122         }
 123
 124         ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 4096, 16,
 125                                      0, &chan->ramht);
 126         if (ret) {
 127                 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
 128                 nv50_evo_channel_del(pchan);
 129                 return ret;
 130         }
 131
 132         if (dev_priv->chipset != 0x50) {
 133                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
 134                                           0, 0xffffffff);
 135                 if (ret) {
 136                         nv50_evo_channel_del(pchan);
 137                         return ret;
 138                 }
 139
 140
 141                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
 142                                           0, 0xffffffff);
 143                 if (ret) {
 144                         nv50_evo_channel_del(pchan);
 145                         return ret;
 146                 }
 147         }
 148
 149         ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
 150                                   0, dev_priv->vram_size);
 151         if (ret) {
 152                 nv50_evo_channel_del(pchan);
 153                 return ret;
 154         }
 155
 156         ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
 157                              false, true, &chan->pushbuf_bo);
 158         if (ret == 0)
 159                 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
 160         if (ret) {
 161                 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
 162                 nv50_evo_channel_del(pchan);
 163                 return ret;
 164         }
 165
 166         ret = nouveau_bo_map(chan->pushbuf_bo);
 167         if (ret) {
 168                 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
 169                 nv50_evo_channel_del(pchan);
 170                 return ret;
 171         }
 172
 173         chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
 174                                         NV50_PDISPLAY_USER(0), PAGE_SIZE);
 175         if (!chan->user) {
 176                 NV_ERROR(dev, "Error mapping EVO control regs.\n");
 177                 nv50_evo_channel_del(pchan);
 178                 return -ENOMEM;
 179         }
 180
 181         return 0;
 182 }
 183
 184 int
 185 nv50_display_early_init(struct drm_device *dev)
 186 {
 187         return 0;
 188 }
 189
 190 void
 191 nv50_display_late_takedown(struct drm_device *dev)
 192 {
 193 }
 194
 195 int
 196 nv50_display_init(struct drm_device *dev)
 197 {
 198         struct drm_nouveau_private *dev_priv = dev->dev_private;
 199         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 200         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 201         struct nouveau_channel *evo = dev_priv->evo;
 202         struct drm_connector *connector;
 203         uint32_t val, ram_amount;
 204         uint64_t start;
 205         int ret, i;
 206
 207         NV_DEBUG_KMS(dev, "\n");
 208
 209         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
 210         /*
 211          * I think the 0x006101XX range is some kind of main control area
 212          * that enables things.
 213          */
 214         /* CRTC? */
 215         for (i = 0; i < 2; i++) {
 216                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
 217                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
 218                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
 219                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
 220                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
 221                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
 222                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
 223                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
 224         }
 225         /* DAC */
 226         for (i = 0; i < 3; i++) {
 227                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
 228                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
 229         }
 230         /* SOR */
 231         for (i = 0; i < 4; i++) {
 232                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
 233                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
 234         }
 235         /* Something not yet in use, tv-out maybe. */
 236         for (i = 0; i < 3; i++) {
 237                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
 238                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
 239         }
 240
 241         for (i = 0; i < 3; i++) {
 242                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 243                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 244                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 245         }
 246
 247         /* This used to be in crtc unblank, but seems out of place there. */
 248         nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
 249         /* RAM is clamped to 256 MiB. */
 250         ram_amount = dev_priv->vram_size;
 251         NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
 252         if (ram_amount > 256*1024*1024)
 253                 ram_amount = 256*1024*1024;
 254         nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
 255         nv_wr32(dev, NV50_PDISPLAY_UNK_388, 0x150000);
 256         nv_wr32(dev, NV50_PDISPLAY_UNK_38C, 0);
 257
 258         /* The precise purpose is unknown, i suspect it has something to do
 259          * with text mode.
 260          */
 261         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
 262                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
 263                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
 264                 if (!nv_wait(0x006194e8, 2, 0)) {
 265                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
 266                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
 267                                                 nv_rd32(dev, 0x6194e8));
 268                         return -EBUSY;
 269                 }
 270         }
 271
 272         /* taken from nv bug #12637, attempts to un-wedge the hw if it's
 273          * stuck in some unspecified state
 274          */
 275         start = ptimer->read(dev);
 276         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
 277         while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
 278                 if ((val & 0x9f0000) == 0x20000)
 279                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 280                                                         val | 0x800000);
 281
 282                 if ((val & 0x3f0000) == 0x30000)
 283                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 284                                                         val | 0x200000);
 285
 286                 if (ptimer->read(dev) - start > 1000000000ULL) {
 287                         NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
 288                         NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
 289                         return -EBUSY;
 290                 }
 291         }
 292
 293         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
 294         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
 295         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x40000000, 0x40000000)) {
 296                 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
 297                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
 298                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
 299                 return -EBUSY;
 300         }
 301
 302         for (i = 0; i < 2; i++) {
 303                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 304                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 305                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 306                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 307                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 308                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 309                         return -EBUSY;
 310                 }
 311
 312                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 313                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 314                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 315                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 316                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 317                         NV_ERROR(dev, "timeout: "
 318                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 319                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 320                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 321                         return -EBUSY;
 322                 }
 323         }
 324
 325         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9);
 326
 327         /* initialise fifo */
 328         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
 329                 ((evo->pushbuf_bo->bo.mem.mm_node->start << PAGE_SHIFT) >> 8) |
 330                 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
 331                 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
 332         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
 333         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
 334         if (!nv_wait(0x610200, 0x80000000, 0x00000000)) {
 335                 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
 336                 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
 337                 return -EBUSY;
 338         }
 339         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 340                 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
 341                  NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
 342         nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
 343         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
 344                 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
 345         nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
 346
 347         evo->dma.max = (4096/4) - 2;
 348         evo->dma.put = 0;
 349         evo->dma.cur = evo->dma.put;
 350         evo->dma.free = evo->dma.max - evo->dma.cur;
 351
 352         ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
 353         if (ret)
 354                 return ret;
 355
 356         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
 357                 OUT_RING(evo, 0);
 358
 359         ret = RING_SPACE(evo, 11);
 360         if (ret)
 361                 return ret;
 362         BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
 363         OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 364         OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
 365         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
 366         OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
 367         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
 368         OUT_RING(evo, 0);
 369         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
 370         OUT_RING(evo, 0);
 371         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
 372         OUT_RING(evo, 0);
 373         FIRE_RING(evo);
 374         if (!nv_wait(0x640004, 0xffffffff, evo->dma.put << 2))
 375                 NV_ERROR(dev, "evo pushbuf stalled\n");
 376
 377         /* enable clock change interrupts. */
 378         nv_wr32(dev, 0x610028, 0x00010001);
 379         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
 380                                              NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
 381                                              NV50_PDISPLAY_INTR_EN_CLK_UNK40));
 382
 383         /* enable hotplug interrupts */
 384         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 385                 struct nouveau_connector *conn = nouveau_connector(connector);
 386
 387                 if (conn->dcb->gpio_tag == 0xff)
 388                         continue;
 389
 390                 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
 391         }
 392
 393         return 0;
 394 }
 395
 396 static int nv50_display_disable(struct drm_device *dev)
 397 {
 398         struct drm_nouveau_private *dev_priv = dev->dev_private;
 399         struct drm_crtc *drm_crtc;
 400         int ret, i;
 401
 402         NV_DEBUG_KMS(dev, "\n");
 403
 404         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 405                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 406
 407                 nv50_crtc_blank(crtc, true);
 408         }
 409
 410         ret = RING_SPACE(dev_priv->evo, 2);
 411         if (ret == 0) {
 412                 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
 413                 OUT_RING(dev_priv->evo, 0);
 414         }
 415         FIRE_RING(dev_priv->evo);
 416
 417         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 418          * cleaning up?
 419          */
 420         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 421                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 422                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 423
 424                 if (!crtc->base.enabled)
 425                         continue;
 426
 427                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
 428                 if (!nv_wait(NV50_PDISPLAY_INTR_1, mask, mask)) {
 429                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
 430                                       "0x%08x\n", mask, mask);
 431                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
 432                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
 433                 }
 434         }
 435
 436         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
 437         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
 438         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
 439                 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
 440                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
 441                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
 442         }
 443
 444         for (i = 0; i < 3; i++) {
 445                 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_STATE(i),
 446                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 447                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 448                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 449                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 450                 }
 451         }
 452
 453         /* disable interrupts. */
 454         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
 455
 456         /* disable hotplug interrupts */
 457         nv_wr32(dev, 0xe054, 0xffffffff);
 458         nv_wr32(dev, 0xe050, 0x00000000);
 459         if (dev_priv->chipset >= 0x90) {
 460                 nv_wr32(dev, 0xe074, 0xffffffff);
 461                 nv_wr32(dev, 0xe070, 0x00000000);
 462         }
 463         return 0;
 464 }
 465
 466 int nv50_display_create(struct drm_device *dev)
 467 {
 468         struct drm_nouveau_private *dev_priv = dev->dev_private;
 469         struct dcb_table *dcb = &dev_priv->vbios.dcb;
 470         struct drm_connector *connector, *ct;
 471         int ret, i;
 472
 473         NV_DEBUG_KMS(dev, "\n");
 474
 475         /* init basic kernel modesetting */
 476         drm_mode_config_init(dev);
 477
 478         /* Initialise some optional connector properties. */
 479         drm_mode_create_scaling_mode_property(dev);
 480         drm_mode_create_dithering_property(dev);
 481
 482         dev->mode_config.min_width = 0;
 483         dev->mode_config.min_height = 0;
 484
 485         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
 486
 487         dev->mode_config.max_width = 8192;
 488         dev->mode_config.max_height = 8192;
 489
 490         dev->mode_config.fb_base = dev_priv->fb_phys;
 491
 492         /* Create EVO channel */
 493         ret = nv50_evo_channel_new(dev, &dev_priv->evo);
 494         if (ret) {
 495                 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
 496                 return ret;
 497         }
 498
 499         /* Create CRTC objects */
 500         for (i = 0; i < 2; i++)
 501                 nv50_crtc_create(dev, i);
 502
 503         /* We setup the encoders from the BIOS table */
 504         for (i = 0 ; i < dcb->entries; i++) {
 505                 struct dcb_entry *entry = &dcb->entry[i];
 506
 507                 if (entry->location != DCB_LOC_ON_CHIP) {
 508                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
 509                                 entry->type, ffs(entry->or) - 1);
 510                         continue;
 511                 }
 512
 513                 connector = nouveau_connector_create(dev, entry->connector);
 514                 if (IS_ERR(connector))
 515                         continue;
 516
 517                 switch (entry->type) {
 518                 case OUTPUT_TMDS:
 519                 case OUTPUT_LVDS:
 520                 case OUTPUT_DP:
 521                         nv50_sor_create(connector, entry);
 522                         break;
 523                 case OUTPUT_ANALOG:
 524                         nv50_dac_create(connector, entry);
 525                         break;
 526                 default:
 527                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
 528                         continue;
 529                 }
 530         }
 531
 532         list_for_each_entry_safe(connector, ct,
 533                                  &dev->mode_config.connector_list, head) {
 534                 if (!connector->encoder_ids[0]) {
 535                         NV_WARN(dev, "%s has no encoders, removing\n",
 536                                 drm_get_connector_name(connector));
 537                         connector->funcs->destroy(connector);
 538                 }
 539         }
 540
 541         ret = nv50_display_init(dev);
 542         if (ret) {
 543                 nv50_display_destroy(dev);
 544                 return ret;
 545         }
 546
 547         return 0;
 548 }
 549
 550 void
 551 nv50_display_destroy(struct drm_device *dev)
 552 {
 553         struct drm_nouveau_private *dev_priv = dev->dev_private;
 554
 555         NV_DEBUG_KMS(dev, "\n");
 556
 557         drm_mode_config_cleanup(dev);
 558
 559         nv50_display_disable(dev);
 560         nv50_evo_channel_del(&dev_priv->evo);
 561 }
 562
 563 static u16
 564 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
 565                            u32 mc, int pxclk)
 566 {
 567         struct drm_nouveau_private *dev_priv = dev->dev_private;
 568         struct nouveau_connector *nv_connector = NULL;
 569         struct drm_encoder *encoder;
 570         struct nvbios *bios = &dev_priv->vbios;
 571         u32 script = 0, or;
 572
 573         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 574                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 575
 576                 if (nv_encoder->dcb != dcb)
 577                         continue;
 578
 579                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 580                 break;
 581         }
 582
 583         or = ffs(dcb->or) - 1;
 584         switch (dcb->type) {
 585         case OUTPUT_LVDS:
 586                 script = (mc >> 8) & 0xf;
 587                 if (bios->fp_no_ddc) {
 588                         if (bios->fp.dual_link)
 589                                 script |= 0x0100;
 590                         if (bios->fp.if_is_24bit)
 591                                 script |= 0x0200;
 592                 } else {
 593                         if (pxclk >= bios->fp.duallink_transition_clk) {
 594                                 script |= 0x0100;
 595                                 if (bios->fp.strapless_is_24bit & 2)
 596                                         script |= 0x0200;
 597                         } else
 598                         if (bios->fp.strapless_is_24bit & 1)
 599                                 script |= 0x0200;
 600
 601                         if (nv_connector && nv_connector->edid &&
 602                             (nv_connector->edid->revision >= 4) &&
 603                             (nv_connector->edid->input & 0x70) >= 0x20)
 604                                 script |= 0x0200;
 605                 }
 606
 607                 if (nouveau_uscript_lvds >= 0) {
 608                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 609                                      "for output LVDS-%d\n", script,
 610                                      nouveau_uscript_lvds, or);
 611                         script = nouveau_uscript_lvds;
 612                 }
 613                 break;
 614         case OUTPUT_TMDS:
 615                 script = (mc >> 8) & 0xf;
 616                 if (pxclk >= 165000)
 617                         script |= 0x0100;
 618
 619                 if (nouveau_uscript_tmds >= 0) {
 620                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 621                                      "for output TMDS-%d\n", script,
 622                                      nouveau_uscript_tmds, or);
 623                         script = nouveau_uscript_tmds;
 624                 }
 625                 break;
 626         case OUTPUT_DP:
 627                 script = (mc >> 8) & 0xf;
 628                 break;
 629         case OUTPUT_ANALOG:
 630                 script = 0xff;
 631                 break;
 632         default:
 633                 NV_ERROR(dev, "modeset on unsupported output type!\n");
 634                 break;
 635         }
 636
 637         return script;
 638 }
 639
 640 static void
 641 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
 642 {
 643         struct drm_nouveau_private *dev_priv = dev->dev_private;
 644         struct nouveau_channel *chan;
 645         struct list_head *entry, *tmp;
 646
 647         list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
 648                 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
 649
 650                 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
 651                                                 chan->nvsw.vblsem_rval);
 652                 list_del(&chan->nvsw.vbl_wait);
 653         }
 654 }
 655
 656 static void
 657 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
 658 {
 659         intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 660
 661         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
 662                 nv50_display_vblank_crtc_handler(dev, 0);
 663
 664         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
 665                 nv50_display_vblank_crtc_handler(dev, 1);
 666
 667         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
 668                      NV50_PDISPLAY_INTR_EN) & ~intr);
 669         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
 670 }
 671
 672 static void
 673 nv50_display_unk10_handler(struct drm_device *dev)
 674 {
 675         struct drm_nouveau_private *dev_priv = dev->dev_private;
 676         u32 unk30 = nv_rd32(dev, 0x610030), mc;
 677         int i, crtc, or, type = OUTPUT_ANY;
 678
 679         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 680         dev_priv->evo_irq.dcb = NULL;
 681
 682         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
 683
 684         /* Determine which CRTC we're dealing with, only 1 ever will be
 685          * signalled at the same time with the current nouveau code.
 686          */
 687         crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
 688         if (crtc < 0)
 689                 goto ack;
 690
 691         /* Nothing needs to be done for the encoder */
 692         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 693         if (crtc < 0)
 694                 goto ack;
 695
 696         /* Find which encoder was connected to the CRTC */
 697         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 698                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
 699                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 700                 if (!(mc & (1 << crtc)))
 701                         continue;
 702
 703                 switch ((mc & 0x00000f00) >> 8) {
 704                 case 0: type = OUTPUT_ANALOG; break;
 705                 case 1: type = OUTPUT_TV; break;
 706                 default:
 707                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 708                         goto ack;
 709                 }
 710
 711                 or = i;
 712         }
 713
 714         for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
 715                 if (dev_priv->chipset  < 0x90 ||
 716                     dev_priv->chipset == 0x92 ||
 717                     dev_priv->chipset == 0xa0)
 718                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
 719                 else
 720                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
 721
 722                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 723                 if (!(mc & (1 << crtc)))
 724                         continue;
 725
 726                 switch ((mc & 0x00000f00) >> 8) {
 727                 case 0: type = OUTPUT_LVDS; break;
 728                 case 1: type = OUTPUT_TMDS; break;
 729                 case 2: type = OUTPUT_TMDS; break;
 730                 case 5: type = OUTPUT_TMDS; break;
 731                 case 8: type = OUTPUT_DP; break;
 732                 case 9: type = OUTPUT_DP; break;
 733                 default:
 734                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 735                         goto ack;
 736                 }
 737
 738                 or = i;
 739         }
 740
 741         /* There was no encoder to disable */
 742         if (type == OUTPUT_ANY)
 743                 goto ack;
 744
 745         /* Disable the encoder */
 746         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 747                 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
 748
 749                 if (dcb->type == type && (dcb->or & (1 << or))) {
 750                         nouveau_bios_run_display_table(dev, dcb, 0, -1);
 751                         dev_priv->evo_irq.dcb = dcb;
 752                         goto ack;
 753                 }
 754         }
 755
 756         NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 757 ack:
 758         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 759         nv_wr32(dev, 0x610030, 0x80000000);
 760 }
 761
 762 static void
 763 nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
 764 {
 765         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 766         struct drm_encoder *encoder;
 767         uint32_t tmp, unk0 = 0, unk1 = 0;
 768
 769         if (dcb->type != OUTPUT_DP)
 770                 return;
 771
 772         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 773                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 774
 775                 if (nv_encoder->dcb == dcb) {
 776                         unk0 = nv_encoder->dp.unk0;
 777                         unk1 = nv_encoder->dp.unk1;
 778                         break;
 779                 }
 780         }
 781
 782         if (unk0 || unk1) {
 783                 tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 784                 tmp &= 0xfffffe03;
 785                 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
 786
 787                 tmp  = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
 788                 tmp &= 0xfef080c0;
 789                 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
 790         }
 791 }
 792
 793 static void
 794 nv50_display_unk20_handler(struct drm_device *dev)
 795 {
 796         struct drm_nouveau_private *dev_priv = dev->dev_private;
 797         u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc;
 798         struct dcb_entry *dcb;
 799         int i, crtc, or, type = OUTPUT_ANY;
 800
 801         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 802         dcb = dev_priv->evo_irq.dcb;
 803         if (dcb) {
 804                 nouveau_bios_run_display_table(dev, dcb, 0, -2);
 805                 dev_priv->evo_irq.dcb = NULL;
 806         }
 807
 808         /* CRTC clock change requested? */
 809         crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
 810         if (crtc >= 0) {
 811                 pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
 812                 pclk &= 0x003fffff;
 813
 814                 nv50_crtc_set_clock(dev, crtc, pclk);
 815
 816                 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
 817                 tmp &= ~0x000000f;
 818                 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
 819         }
 820
 821         /* Nothing needs to be done for the encoder */
 822         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 823         if (crtc < 0)
 824                 goto ack;
 825         pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
 826
 827         /* Find which encoder is connected to the CRTC */
 828         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 829                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
 830                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 831                 if (!(mc & (1 << crtc)))
 832                         continue;
 833
 834                 switch ((mc & 0x00000f00) >> 8) {
 835                 case 0: type = OUTPUT_ANALOG; break;
 836                 case 1: type = OUTPUT_TV; break;
 837                 default:
 838                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 839                         goto ack;
 840                 }
 841
 842                 or = i;
 843         }
 844
 845         for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
 846                 if (dev_priv->chipset  < 0x90 ||
 847                     dev_priv->chipset == 0x92 ||
 848                     dev_priv->chipset == 0xa0)
 849                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
 850                 else
 851                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
 852
 853                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 854                 if (!(mc & (1 << crtc)))
 855                         continue;
 856
 857                 switch ((mc & 0x00000f00) >> 8) {
 858                 case 0: type = OUTPUT_LVDS; break;
 859                 case 1: type = OUTPUT_TMDS; break;
 860                 case 2: type = OUTPUT_TMDS; break;
 861                 case 5: type = OUTPUT_TMDS; break;
 862                 case 8: type = OUTPUT_DP; break;
 863                 case 9: type = OUTPUT_DP; break;
 864                 default:
 865                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 866                         goto ack;
 867                 }
 868
 869                 or = i;
 870         }
 871
 872         if (type == OUTPUT_ANY)
 873                 goto ack;
 874
 875         /* Enable the encoder */
 876         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 877                 dcb = &dev_priv->vbios.dcb.entry[i];
 878                 if (dcb->type == type && (dcb->or & (1 << or)))
 879                         break;
 880         }
 881
 882         if (i == dev_priv->vbios.dcb.entries) {
 883                 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 884                 goto ack;
 885         }
 886
 887         script = nv50_display_script_select(dev, dcb, mc, pclk);
 888         nouveau_bios_run_display_table(dev, dcb, script, pclk);
 889
 890         nv50_display_unk20_dp_hack(dev, dcb);
 891
 892         if (dcb->type != OUTPUT_ANALOG) {
 893                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 894                 tmp &= ~0x00000f0f;
 895                 if (script & 0x0100)
 896                         tmp |= 0x00000101;
 897                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 898         } else {
 899                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 900         }
 901
 902         dev_priv->evo_irq.dcb = dcb;
 903         dev_priv->evo_irq.pclk = pclk;
 904         dev_priv->evo_irq.script = script;
 905
 906 ack:
 907         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 908         nv_wr32(dev, 0x610030, 0x80000000);
 909 }
 910
 911 /* If programming a TMDS output on a SOR that can also be configured for
 912  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
 913  *
 914  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
 915  * the VBIOS scripts on at least one board I have only switch it off on
 916  * link 0, causing a blank display if the output has previously been
 917  * programmed for DisplayPort.
 918  */
 919 static void
 920 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
 921 {
 922         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 923         struct drm_encoder *encoder;
 924         u32 tmp;
 925
 926         if (dcb->type != OUTPUT_TMDS)
 927                 return;
 928
 929         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 930                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 931
 932                 if (nv_encoder->dcb->type == OUTPUT_DP &&
 933                     nv_encoder->dcb->or & (1 << or)) {
 934                         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 935                         tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
 936                         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 937                         break;
 938                 }
 939         }
 940 }
 941
 942 static void
 943 nv50_display_unk40_handler(struct drm_device *dev)
 944 {
 945         struct drm_nouveau_private *dev_priv = dev->dev_private;
 946         struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
 947         u16 script = dev_priv->evo_irq.script;
 948         u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
 949
 950         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 951         dev_priv->evo_irq.dcb = NULL;
 952         if (!dcb)
 953                 goto ack;
 954
 955         nouveau_bios_run_display_table(dev, dcb, script, -pclk);
 956         nv50_display_unk40_dp_set_tmds(dev, dcb);
 957
 958 ack:
 959         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 960         nv_wr32(dev, 0x610030, 0x80000000);
 961         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
 962 }
 963
 964 void
 965 nv50_display_irq_handler_bh(struct work_struct *work)
 966 {
 967         struct drm_nouveau_private *dev_priv =
 968                 container_of(work, struct drm_nouveau_private, irq_work);
 969         struct drm_device *dev = dev_priv->dev;
 970
 971         for (;;) {
 972                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 973                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 974
 975                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 976
 977                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 978                         nv50_display_unk10_handler(dev);
 979                 else
 980                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 981                         nv50_display_unk20_handler(dev);
 982                 else
 983                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 984                         nv50_display_unk40_handler(dev);
 985                 else
 986                         break;
 987         }
 988
 989         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
 990 }
 991
 992 static void
 993 nv50_display_error_handler(struct drm_device *dev)
 994 {
 995         uint32_t addr, data;
 996
 997         nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
 998         addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
 999         data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
1000
1001         NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
1002                  0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
1003
1004         nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
1005 }
1006
1007 void
1008 nv50_display_irq_hotplug_bh(struct work_struct *work)
1009 {
1010         struct drm_nouveau_private *dev_priv =
1011                 container_of(work, struct drm_nouveau_private, hpd_work);
1012         struct drm_device *dev = dev_priv->dev;
1013         struct drm_connector *connector;
1014         const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
1015         uint32_t unplug_mask, plug_mask, change_mask;
1016         uint32_t hpd0, hpd1 = 0;
1017
1018         hpd0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
1019         if (dev_priv->chipset >= 0x90)
1020                 hpd1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
1021
1022         plug_mask   = (hpd0 & 0x0000ffff) | (hpd1 << 16);
1023         unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
1024         change_mask = plug_mask | unplug_mask;
1025
1026         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1027                 struct drm_encoder_helper_funcs *helper;
1028                 struct nouveau_connector *nv_connector =
1029                         nouveau_connector(connector);
1030                 struct nouveau_encoder *nv_encoder;
1031                 struct dcb_gpio_entry *gpio;
1032                 uint32_t reg;
1033                 bool plugged;
1034
1035                 if (!nv_connector->dcb)
1036                         continue;
1037
1038                 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
1039                 if (!gpio || !(change_mask & (1 << gpio->line)))
1040                         continue;
1041
1042                 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
1043                 plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
1044                 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
1045                         drm_get_connector_name(connector)) ;
1046
1047                 if (!connector->encoder || !connector->encoder->crtc ||
1048                     !connector->encoder->crtc->enabled)
1049                         continue;
1050                 nv_encoder = nouveau_encoder(connector->encoder);
1051                 helper = connector->encoder->helper_private;
1052
1053                 if (nv_encoder->dcb->type != OUTPUT_DP)
1054                         continue;
1055
1056                 if (plugged)
1057                         helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
1058                 else
1059                         helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
1060         }
1061
1062         nv_wr32(dev, 0xe054, nv_rd32(dev, 0xe054));
1063         if (dev_priv->chipset >= 0x90)
1064                 nv_wr32(dev, 0xe074, nv_rd32(dev, 0xe074));
1065
1066         drm_helper_hpd_irq_event(dev);
1067 }
1068
1069 void
1070 nv50_display_irq_handler(struct drm_device *dev)
1071 {
1072         struct drm_nouveau_private *dev_priv = dev->dev_private;
1073         uint32_t delayed = 0;
1074
1075         if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
1076                 if (!work_pending(&dev_priv->hpd_work))
1077                         queue_work(dev_priv->wq, &dev_priv->hpd_work);
1078         }
1079
1080         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
1081                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
1082                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
1083                 uint32_t clock;
1084
1085                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
1086
1087                 if (!intr0 && !(intr1 & ~delayed))
1088                         break;
1089
1090                 if (intr0 & 0x00010000) {
1091                         nv50_display_error_handler(dev);
1092                         intr0 &= ~0x00010000;
1093                 }
1094
1095                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1096                         nv50_display_vblank_handler(dev, intr1);
1097                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1098                 }
1099
1100                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1101                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1102                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
1103                 if (clock) {
1104                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1105                         if (!work_pending(&dev_priv->irq_work))
1106                                 queue_work(dev_priv->wq, &dev_priv->irq_work);
1107                         delayed |= clock;
1108                         intr1 &= ~clock;
1109                 }
1110
1111                 if (intr0) {
1112                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1113                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1114                 }
1115
1116                 if (intr1) {
1117                         NV_ERROR(dev,
1118                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1119                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1120                 }
1121         }
1122 }
1123