drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "nv50_display.h"
  28 #include "nouveau_crtc.h"
  29 #include "nouveau_encoder.h"
  30 #include "nouveau_connector.h"
  31 #include "nouveau_fb.h"
  32 #include "nouveau_fbcon.h"
  33 #include "nouveau_ramht.h"
  34 #include "drm_crtc_helper.h"
  35
  36 static void nv50_display_isr(struct drm_device *);
  37
  38 static inline int
  39 nv50_sor_nr(struct drm_device *dev)
  40 {
  41         struct drm_nouveau_private *dev_priv = dev->dev_private;
  42
  43         if (dev_priv->chipset  < 0x90 ||
  44             dev_priv->chipset == 0x92 ||
  45             dev_priv->chipset == 0xa0)
  46                 return 2;
  47
  48         return 4;
  49 }
  50
  51 int
  52 nv50_display_early_init(struct drm_device *dev)
  53 {
  54         return 0;
  55 }
  56
  57 void
  58 nv50_display_late_takedown(struct drm_device *dev)
  59 {
  60 }
  61
  62 int
  63 nv50_display_init(struct drm_device *dev)
  64 {
  65         struct drm_nouveau_private *dev_priv = dev->dev_private;
  66         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
  67         struct drm_connector *connector;
  68         struct nouveau_channel *evo;
  69         int ret, i;
  70         u32 val;
  71
  72         NV_DEBUG_KMS(dev, "\n");
  73
  74         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
  75
  76         /*
  77          * I think the 0x006101XX range is some kind of main control area
  78          * that enables things.
  79          */
  80         /* CRTC? */
  81         for (i = 0; i < 2; i++) {
  82                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
  83                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
  84                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
  85                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
  86                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
  87                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
  88                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
  89                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
  90         }
  91
  92         /* DAC */
  93         for (i = 0; i < 3; i++) {
  94                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
  95                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
  96         }
  97
  98         /* SOR */
  99         for (i = 0; i < nv50_sor_nr(dev); i++) {
 100                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
 101                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
 102         }
 103
 104         /* EXT */
 105         for (i = 0; i < 3; i++) {
 106                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
 107                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
 108         }
 109
 110         for (i = 0; i < 3; i++) {
 111                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 112                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 113                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 114         }
 115
 116         /* The precise purpose is unknown, i suspect it has something to do
 117          * with text mode.
 118          */
 119         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
 120                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
 121                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
 122                 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
 123                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
 124                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
 125                                                 nv_rd32(dev, 0x6194e8));
 126                         return -EBUSY;
 127                 }
 128         }
 129
 130         for (i = 0; i < 2; i++) {
 131                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 132                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 133                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 134                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 135                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 136                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 137                         return -EBUSY;
 138                 }
 139
 140                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 141                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 142                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 143                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 144                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 145                         NV_ERROR(dev, "timeout: "
 146                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 147                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 148                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 149                         return -EBUSY;
 150                 }
 151         }
 152
 153         nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
 154         nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
 155         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
 156         nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
 157         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1,
 158                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
 159                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
 160                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
 161
 162         /* enable hotplug interrupts */
 163         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 164                 struct nouveau_connector *conn = nouveau_connector(connector);
 165
 166                 if (conn->dcb->gpio_tag == 0xff)
 167                         continue;
 168
 169                 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
 170         }
 171
 172         ret = nv50_evo_init(dev);
 173         if (ret)
 174                 return ret;
 175         evo = dev_priv->evo;
 176
 177         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
 178
 179         ret = RING_SPACE(evo, 11);
 180         if (ret)
 181                 return ret;
 182         BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
 183         OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 184         OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
 185         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
 186         OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
 187         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
 188         OUT_RING(evo, 0);
 189         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
 190         OUT_RING(evo, 0);
 191         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
 192         OUT_RING(evo, 0);
 193         FIRE_RING(evo);
 194         if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2))
 195                 NV_ERROR(dev, "evo pushbuf stalled\n");
 196
 197
 198         return 0;
 199 }
 200
 201 static int nv50_display_disable(struct drm_device *dev)
 202 {
 203         struct drm_nouveau_private *dev_priv = dev->dev_private;
 204         struct drm_crtc *drm_crtc;
 205         int ret, i;
 206
 207         NV_DEBUG_KMS(dev, "\n");
 208
 209         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 210                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 211
 212                 nv50_crtc_blank(crtc, true);
 213         }
 214
 215         ret = RING_SPACE(dev_priv->evo, 2);
 216         if (ret == 0) {
 217                 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
 218                 OUT_RING(dev_priv->evo, 0);
 219         }
 220         FIRE_RING(dev_priv->evo);
 221
 222         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 223          * cleaning up?
 224          */
 225         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 226                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 227                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 228
 229                 if (!crtc->base.enabled)
 230                         continue;
 231
 232                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
 233                 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
 234                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
 235                                       "0x%08x\n", mask, mask);
 236                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
 237                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
 238                 }
 239         }
 240
 241         nv50_evo_fini(dev);
 242
 243         for (i = 0; i < 3; i++) {
 244                 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
 245                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 246                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 247                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 248                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 249                 }
 250         }
 251
 252         /* disable interrupts. */
 253         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
 254
 255         /* disable hotplug interrupts */
 256         nv_wr32(dev, 0xe054, 0xffffffff);
 257         nv_wr32(dev, 0xe050, 0x00000000);
 258         if (dev_priv->chipset >= 0x90) {
 259                 nv_wr32(dev, 0xe074, 0xffffffff);
 260                 nv_wr32(dev, 0xe070, 0x00000000);
 261         }
 262         return 0;
 263 }
 264
 265 int nv50_display_create(struct drm_device *dev)
 266 {
 267         struct drm_nouveau_private *dev_priv = dev->dev_private;
 268         struct dcb_table *dcb = &dev_priv->vbios.dcb;
 269         struct drm_connector *connector, *ct;
 270         int ret, i;
 271
 272         NV_DEBUG_KMS(dev, "\n");
 273
 274         /* init basic kernel modesetting */
 275         drm_mode_config_init(dev);
 276
 277         /* Initialise some optional connector properties. */
 278         drm_mode_create_scaling_mode_property(dev);
 279         drm_mode_create_dithering_property(dev);
 280
 281         dev->mode_config.min_width = 0;
 282         dev->mode_config.min_height = 0;
 283
 284         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
 285
 286         dev->mode_config.max_width = 8192;
 287         dev->mode_config.max_height = 8192;
 288
 289         dev->mode_config.fb_base = dev_priv->fb_phys;
 290
 291         /* Create CRTC objects */
 292         for (i = 0; i < 2; i++)
 293                 nv50_crtc_create(dev, i);
 294
 295         /* We setup the encoders from the BIOS table */
 296         for (i = 0 ; i < dcb->entries; i++) {
 297                 struct dcb_entry *entry = &dcb->entry[i];
 298
 299                 if (entry->location != DCB_LOC_ON_CHIP) {
 300                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
 301                                 entry->type, ffs(entry->or) - 1);
 302                         continue;
 303                 }
 304
 305                 connector = nouveau_connector_create(dev, entry->connector);
 306                 if (IS_ERR(connector))
 307                         continue;
 308
 309                 switch (entry->type) {
 310                 case OUTPUT_TMDS:
 311                 case OUTPUT_LVDS:
 312                 case OUTPUT_DP:
 313                         nv50_sor_create(connector, entry);
 314                         break;
 315                 case OUTPUT_ANALOG:
 316                         nv50_dac_create(connector, entry);
 317                         break;
 318                 default:
 319                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
 320                         continue;
 321                 }
 322         }
 323
 324         list_for_each_entry_safe(connector, ct,
 325                                  &dev->mode_config.connector_list, head) {
 326                 if (!connector->encoder_ids[0]) {
 327                         NV_WARN(dev, "%s has no encoders, removing\n",
 328                                 drm_get_connector_name(connector));
 329                         connector->funcs->destroy(connector);
 330                 }
 331         }
 332
 333         INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh);
 334         nouveau_irq_register(dev, 26, nv50_display_isr);
 335
 336         ret = nv50_display_init(dev);
 337         if (ret) {
 338                 nv50_display_destroy(dev);
 339                 return ret;
 340         }
 341
 342         return 0;
 343 }
 344
 345 void
 346 nv50_display_destroy(struct drm_device *dev)
 347 {
 348         struct drm_nouveau_private *dev_priv = dev->dev_private;
 349
 350         NV_DEBUG_KMS(dev, "\n");
 351
 352         drm_mode_config_cleanup(dev);
 353
 354         nv50_display_disable(dev);
 355         nouveau_irq_unregister(dev, 26);
 356         flush_work_sync(&dev_priv->irq_work);
 357 }
 358
 359 static u16
 360 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
 361                            u32 mc, int pxclk)
 362 {
 363         struct drm_nouveau_private *dev_priv = dev->dev_private;
 364         struct nouveau_connector *nv_connector = NULL;
 365         struct drm_encoder *encoder;
 366         struct nvbios *bios = &dev_priv->vbios;
 367         u32 script = 0, or;
 368
 369         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 370                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 371
 372                 if (nv_encoder->dcb != dcb)
 373                         continue;
 374
 375                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 376                 break;
 377         }
 378
 379         or = ffs(dcb->or) - 1;
 380         switch (dcb->type) {
 381         case OUTPUT_LVDS:
 382                 script = (mc >> 8) & 0xf;
 383                 if (bios->fp_no_ddc) {
 384                         if (bios->fp.dual_link)
 385                                 script |= 0x0100;
 386                         if (bios->fp.if_is_24bit)
 387                                 script |= 0x0200;
 388                 } else {
 389                         if (pxclk >= bios->fp.duallink_transition_clk) {
 390                                 script |= 0x0100;
 391                                 if (bios->fp.strapless_is_24bit & 2)
 392                                         script |= 0x0200;
 393                         } else
 394                         if (bios->fp.strapless_is_24bit & 1)
 395                                 script |= 0x0200;
 396
 397                         if (nv_connector && nv_connector->edid &&
 398                             (nv_connector->edid->revision >= 4) &&
 399                             (nv_connector->edid->input & 0x70) >= 0x20)
 400                                 script |= 0x0200;
 401                 }
 402
 403                 if (nouveau_uscript_lvds >= 0) {
 404                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 405                                      "for output LVDS-%d\n", script,
 406                                      nouveau_uscript_lvds, or);
 407                         script = nouveau_uscript_lvds;
 408                 }
 409                 break;
 410         case OUTPUT_TMDS:
 411                 script = (mc >> 8) & 0xf;
 412                 if (pxclk >= 165000)
 413                         script |= 0x0100;
 414
 415                 if (nouveau_uscript_tmds >= 0) {
 416                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 417                                      "for output TMDS-%d\n", script,
 418                                      nouveau_uscript_tmds, or);
 419                         script = nouveau_uscript_tmds;
 420                 }
 421                 break;
 422         case OUTPUT_DP:
 423                 script = (mc >> 8) & 0xf;
 424                 break;
 425         case OUTPUT_ANALOG:
 426                 script = 0xff;
 427                 break;
 428         default:
 429                 NV_ERROR(dev, "modeset on unsupported output type!\n");
 430                 break;
 431         }
 432
 433         return script;
 434 }
 435
 436 static void
 437 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
 438 {
 439         struct drm_nouveau_private *dev_priv = dev->dev_private;
 440         struct nouveau_channel *chan, *tmp;
 441
 442         list_for_each_entry_safe(chan, tmp, &dev_priv->vbl_waiting,
 443                                  nvsw.vbl_wait) {
 444                 if (chan->nvsw.vblsem_head != crtc)
 445                         continue;
 446
 447                 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
 448                                                 chan->nvsw.vblsem_rval);
 449                 list_del(&chan->nvsw.vbl_wait);
 450                 drm_vblank_put(dev, crtc);
 451         }
 452
 453         drm_handle_vblank(dev, crtc);
 454 }
 455
 456 static void
 457 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
 458 {
 459         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
 460                 nv50_display_vblank_crtc_handler(dev, 0);
 461
 462         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
 463                 nv50_display_vblank_crtc_handler(dev, 1);
 464
 465         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_VBLANK_CRTC);
 466 }
 467
 468 static void
 469 nv50_display_unk10_handler(struct drm_device *dev)
 470 {
 471         struct drm_nouveau_private *dev_priv = dev->dev_private;
 472         u32 unk30 = nv_rd32(dev, 0x610030), mc;
 473         int i, crtc, or, type = OUTPUT_ANY;
 474
 475         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 476         dev_priv->evo_irq.dcb = NULL;
 477
 478         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
 479
 480         /* Determine which CRTC we're dealing with, only 1 ever will be
 481          * signalled at the same time with the current nouveau code.
 482          */
 483         crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
 484         if (crtc < 0)
 485                 goto ack;
 486
 487         /* Nothing needs to be done for the encoder */
 488         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 489         if (crtc < 0)
 490                 goto ack;
 491
 492         /* Find which encoder was connected to the CRTC */
 493         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 494                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
 495                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 496                 if (!(mc & (1 << crtc)))
 497                         continue;
 498
 499                 switch ((mc & 0x00000f00) >> 8) {
 500                 case 0: type = OUTPUT_ANALOG; break;
 501                 case 1: type = OUTPUT_TV; break;
 502                 default:
 503                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 504                         goto ack;
 505                 }
 506
 507                 or = i;
 508         }
 509
 510         for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 511                 if (dev_priv->chipset  < 0x90 ||
 512                     dev_priv->chipset == 0x92 ||
 513                     dev_priv->chipset == 0xa0)
 514                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
 515                 else
 516                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
 517
 518                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 519                 if (!(mc & (1 << crtc)))
 520                         continue;
 521
 522                 switch ((mc & 0x00000f00) >> 8) {
 523                 case 0: type = OUTPUT_LVDS; break;
 524                 case 1: type = OUTPUT_TMDS; break;
 525                 case 2: type = OUTPUT_TMDS; break;
 526                 case 5: type = OUTPUT_TMDS; break;
 527                 case 8: type = OUTPUT_DP; break;
 528                 case 9: type = OUTPUT_DP; break;
 529                 default:
 530                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 531                         goto ack;
 532                 }
 533
 534                 or = i;
 535         }
 536
 537         /* There was no encoder to disable */
 538         if (type == OUTPUT_ANY)
 539                 goto ack;
 540
 541         /* Disable the encoder */
 542         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 543                 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
 544
 545                 if (dcb->type == type && (dcb->or & (1 << or))) {
 546                         nouveau_bios_run_display_table(dev, dcb, 0, -1);
 547                         dev_priv->evo_irq.dcb = dcb;
 548                         goto ack;
 549                 }
 550         }
 551
 552         NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 553 ack:
 554         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 555         nv_wr32(dev, 0x610030, 0x80000000);
 556 }
 557
 558 static void
 559 nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
 560 {
 561         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 562         struct drm_encoder *encoder;
 563         uint32_t tmp, unk0 = 0, unk1 = 0;
 564
 565         if (dcb->type != OUTPUT_DP)
 566                 return;
 567
 568         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 569                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 570
 571                 if (nv_encoder->dcb == dcb) {
 572                         unk0 = nv_encoder->dp.unk0;
 573                         unk1 = nv_encoder->dp.unk1;
 574                         break;
 575                 }
 576         }
 577
 578         if (unk0 || unk1) {
 579                 tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 580                 tmp &= 0xfffffe03;
 581                 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
 582
 583                 tmp  = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
 584                 tmp &= 0xfef080c0;
 585                 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
 586         }
 587 }
 588
 589 static void
 590 nv50_display_unk20_handler(struct drm_device *dev)
 591 {
 592         struct drm_nouveau_private *dev_priv = dev->dev_private;
 593         u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0;
 594         struct dcb_entry *dcb;
 595         int i, crtc, or, type = OUTPUT_ANY;
 596
 597         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 598         dcb = dev_priv->evo_irq.dcb;
 599         if (dcb) {
 600                 nouveau_bios_run_display_table(dev, dcb, 0, -2);
 601                 dev_priv->evo_irq.dcb = NULL;
 602         }
 603
 604         /* CRTC clock change requested? */
 605         crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
 606         if (crtc >= 0) {
 607                 pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
 608                 pclk &= 0x003fffff;
 609
 610                 nv50_crtc_set_clock(dev, crtc, pclk);
 611
 612                 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
 613                 tmp &= ~0x000000f;
 614                 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
 615         }
 616
 617         /* Nothing needs to be done for the encoder */
 618         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 619         if (crtc < 0)
 620                 goto ack;
 621         pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
 622
 623         /* Find which encoder is connected to the CRTC */
 624         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 625                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
 626                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 627                 if (!(mc & (1 << crtc)))
 628                         continue;
 629
 630                 switch ((mc & 0x00000f00) >> 8) {
 631                 case 0: type = OUTPUT_ANALOG; break;
 632                 case 1: type = OUTPUT_TV; break;
 633                 default:
 634                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 635                         goto ack;
 636                 }
 637
 638                 or = i;
 639         }
 640
 641         for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 642                 if (dev_priv->chipset  < 0x90 ||
 643                     dev_priv->chipset == 0x92 ||
 644                     dev_priv->chipset == 0xa0)
 645                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
 646                 else
 647                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
 648
 649                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 650                 if (!(mc & (1 << crtc)))
 651                         continue;
 652
 653                 switch ((mc & 0x00000f00) >> 8) {
 654                 case 0: type = OUTPUT_LVDS; break;
 655                 case 1: type = OUTPUT_TMDS; break;
 656                 case 2: type = OUTPUT_TMDS; break;
 657                 case 5: type = OUTPUT_TMDS; break;
 658                 case 8: type = OUTPUT_DP; break;
 659                 case 9: type = OUTPUT_DP; break;
 660                 default:
 661                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 662                         goto ack;
 663                 }
 664
 665                 or = i;
 666         }
 667
 668         if (type == OUTPUT_ANY)
 669                 goto ack;
 670
 671         /* Enable the encoder */
 672         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 673                 dcb = &dev_priv->vbios.dcb.entry[i];
 674                 if (dcb->type == type && (dcb->or & (1 << or)))
 675                         break;
 676         }
 677
 678         if (i == dev_priv->vbios.dcb.entries) {
 679                 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 680                 goto ack;
 681         }
 682
 683         script = nv50_display_script_select(dev, dcb, mc, pclk);
 684         nouveau_bios_run_display_table(dev, dcb, script, pclk);
 685
 686         nv50_display_unk20_dp_hack(dev, dcb);
 687
 688         if (dcb->type != OUTPUT_ANALOG) {
 689                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 690                 tmp &= ~0x00000f0f;
 691                 if (script & 0x0100)
 692                         tmp |= 0x00000101;
 693                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 694         } else {
 695                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 696         }
 697
 698         dev_priv->evo_irq.dcb = dcb;
 699         dev_priv->evo_irq.pclk = pclk;
 700         dev_priv->evo_irq.script = script;
 701
 702 ack:
 703         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 704         nv_wr32(dev, 0x610030, 0x80000000);
 705 }
 706
 707 /* If programming a TMDS output on a SOR that can also be configured for
 708  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
 709  *
 710  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
 711  * the VBIOS scripts on at least one board I have only switch it off on
 712  * link 0, causing a blank display if the output has previously been
 713  * programmed for DisplayPort.
 714  */
 715 static void
 716 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
 717 {
 718         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 719         struct drm_encoder *encoder;
 720         u32 tmp;
 721
 722         if (dcb->type != OUTPUT_TMDS)
 723                 return;
 724
 725         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 726                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 727
 728                 if (nv_encoder->dcb->type == OUTPUT_DP &&
 729                     nv_encoder->dcb->or & (1 << or)) {
 730                         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 731                         tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
 732                         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 733                         break;
 734                 }
 735         }
 736 }
 737
 738 static void
 739 nv50_display_unk40_handler(struct drm_device *dev)
 740 {
 741         struct drm_nouveau_private *dev_priv = dev->dev_private;
 742         struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
 743         u16 script = dev_priv->evo_irq.script;
 744         u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
 745
 746         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 747         dev_priv->evo_irq.dcb = NULL;
 748         if (!dcb)
 749                 goto ack;
 750
 751         nouveau_bios_run_display_table(dev, dcb, script, -pclk);
 752         nv50_display_unk40_dp_set_tmds(dev, dcb);
 753
 754 ack:
 755         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 756         nv_wr32(dev, 0x610030, 0x80000000);
 757         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
 758 }
 759
 760 void
 761 nv50_display_irq_handler_bh(struct work_struct *work)
 762 {
 763         struct drm_nouveau_private *dev_priv =
 764                 container_of(work, struct drm_nouveau_private, irq_work);
 765         struct drm_device *dev = dev_priv->dev;
 766
 767         for (;;) {
 768                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 769                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 770
 771                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 772
 773                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 774                         nv50_display_unk10_handler(dev);
 775                 else
 776                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 777                         nv50_display_unk20_handler(dev);
 778                 else
 779                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 780                         nv50_display_unk40_handler(dev);
 781                 else
 782                         break;
 783         }
 784
 785         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
 786 }
 787
 788 static void
 789 nv50_display_error_handler(struct drm_device *dev)
 790 {
 791         u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
 792         u32 addr, data;
 793         int chid;
 794
 795         for (chid = 0; chid < 5; chid++) {
 796                 if (!(channels & (1 << chid)))
 797                         continue;
 798
 799                 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
 800                 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid));
 801                 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid));
 802                 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x "
 803                               "(0x%04x 0x%02x)\n", chid,
 804                          addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
 805
 806                 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
 807         }
 808 }
 809
 810 static void
 811 nv50_display_isr(struct drm_device *dev)
 812 {
 813         struct drm_nouveau_private *dev_priv = dev->dev_private;
 814         uint32_t delayed = 0;
 815
 816         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
 817                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 818                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 819                 uint32_t clock;
 820
 821                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
 822
 823                 if (!intr0 && !(intr1 & ~delayed))
 824                         break;
 825
 826                 if (intr0 & 0x001f0000) {
 827                         nv50_display_error_handler(dev);
 828                         intr0 &= ~0x001f0000;
 829                 }
 830
 831                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
 832                         nv50_display_vblank_handler(dev, intr1);
 833                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 834                 }
 835
 836                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
 837                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
 838                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
 839                 if (clock) {
 840                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
 841                         if (!work_pending(&dev_priv->irq_work))
 842                                 schedule_work(&dev_priv->irq_work);
 843                         delayed |= clock;
 844                         intr1 &= ~clock;
 845                 }
 846
 847                 if (intr0) {
 848                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
 849                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
 850                 }
 851
 852                 if (intr1) {
 853                         NV_ERROR(dev,
 854                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
 855                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
 856                 }
 857         }
 858 }