2 * Copyright (C) 2008 Maarten Maathuis.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "drm_crtc_helper.h"
31 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
32 #include "nouveau_reg.h"
33 #include "nouveau_drv.h"
34 #include "nouveau_hw.h"
35 #include "nouveau_encoder.h"
36 #include "nouveau_crtc.h"
37 #include "nouveau_fb.h"
38 #include "nouveau_connector.h"
39 #include "nv50_display.h"
42 nv50_crtc_lut_load(struct drm_crtc *crtc)
44 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
45 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
48 NV_DEBUG_KMS(crtc->dev, "\n");
50 for (i = 0; i < 256; i++) {
51 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0);
52 writew(nv_crtc->lut.g[i] >> 2, lut + 8*i + 2);
53 writew(nv_crtc->lut.b[i] >> 2, lut + 8*i + 4);
56 if (nv_crtc->lut.depth == 30) {
57 writew(nv_crtc->lut.r[i - 1] >> 2, lut + 8*i + 0);
58 writew(nv_crtc->lut.g[i - 1] >> 2, lut + 8*i + 2);
59 writew(nv_crtc->lut.b[i - 1] >> 2, lut + 8*i + 4);
64 nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
66 struct drm_device *dev = nv_crtc->base.dev;
67 struct drm_nouveau_private *dev_priv = dev->dev_private;
68 struct nouveau_channel *evo = dev_priv->evo;
69 int index = nv_crtc->index, ret;
71 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
72 NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked");
75 nv_crtc->cursor.hide(nv_crtc, false);
77 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5);
79 NV_ERROR(dev, "no space while blanking crtc\n");
82 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
83 OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK);
85 if (dev_priv->chipset != 0x50) {
86 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
87 OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE);
90 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
91 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
93 if (nv_crtc->cursor.visible)
94 nv_crtc->cursor.show(nv_crtc, false);
96 nv_crtc->cursor.hide(nv_crtc, false);
98 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8);
100 NV_ERROR(dev, "no space while unblanking crtc\n");
103 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
104 OUT_RING(evo, nv_crtc->lut.depth == 8 ?
105 NV50_EVO_CRTC_CLUT_MODE_OFF :
106 NV50_EVO_CRTC_CLUT_MODE_ON);
107 OUT_RING(evo, (nv_crtc->lut.nvbo->bo.mem.mm_node->start <<
109 if (dev_priv->chipset != 0x50) {
110 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
111 OUT_RING(evo, NvEvoVRAM);
114 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2);
115 OUT_RING(evo, nv_crtc->fb.offset >> 8);
117 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
118 if (dev_priv->chipset != 0x50)
119 if (nv_crtc->fb.tile_flags == 0x7a00)
120 OUT_RING(evo, NvEvoFB32);
122 if (nv_crtc->fb.tile_flags == 0x7000)
123 OUT_RING(evo, NvEvoFB16);
125 OUT_RING(evo, NvEvoVRAM);
127 OUT_RING(evo, NvEvoVRAM);
130 nv_crtc->fb.blanked = blanked;
135 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
137 struct drm_device *dev = nv_crtc->base.dev;
138 struct drm_nouveau_private *dev_priv = dev->dev_private;
139 struct nouveau_channel *evo = dev_priv->evo;
142 NV_DEBUG_KMS(dev, "\n");
144 ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
146 NV_ERROR(dev, "no space while setting dither\n");
150 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DITHER_CTRL), 1);
152 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_ON);
154 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_OFF);
157 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
165 struct nouveau_connector *
166 nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
168 struct drm_device *dev = nv_crtc->base.dev;
169 struct drm_connector *connector;
170 struct drm_crtc *crtc = to_drm_crtc(nv_crtc);
172 /* The safest approach is to find an encoder with the right crtc, that
173 * is also linked to a connector. */
174 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
175 if (connector->encoder)
176 if (connector->encoder->crtc == crtc)
177 return nouveau_connector(connector);
184 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
186 struct nouveau_connector *nv_connector =
187 nouveau_crtc_connector_get(nv_crtc);
188 struct drm_device *dev = nv_crtc->base.dev;
189 struct drm_nouveau_private *dev_priv = dev->dev_private;
190 struct nouveau_channel *evo = dev_priv->evo;
191 struct drm_display_mode *native_mode = NULL;
192 struct drm_display_mode *mode = &nv_crtc->base.mode;
193 uint32_t outX, outY, horiz, vert;
196 NV_DEBUG_KMS(dev, "\n");
198 switch (scaling_mode) {
199 case DRM_MODE_SCALE_NONE:
202 if (!nv_connector || !nv_connector->native_mode) {
203 NV_ERROR(dev, "No native mode, forcing panel scaling\n");
204 scaling_mode = DRM_MODE_SCALE_NONE;
206 native_mode = nv_connector->native_mode;
211 switch (scaling_mode) {
212 case DRM_MODE_SCALE_ASPECT:
213 horiz = (native_mode->hdisplay << 19) / mode->hdisplay;
214 vert = (native_mode->vdisplay << 19) / mode->vdisplay;
217 outX = (mode->hdisplay * horiz) >> 19;
218 outY = (mode->vdisplay * horiz) >> 19;
220 outX = (mode->hdisplay * vert) >> 19;
221 outY = (mode->vdisplay * vert) >> 19;
224 case DRM_MODE_SCALE_FULLSCREEN:
225 outX = native_mode->hdisplay;
226 outY = native_mode->vdisplay;
228 case DRM_MODE_SCALE_CENTER:
229 case DRM_MODE_SCALE_NONE:
231 outX = mode->hdisplay;
232 outY = mode->vdisplay;
236 ret = RING_SPACE(evo, update ? 7 : 5);
240 /* Got a better name for SCALER_ACTIVE? */
241 /* One day i've got to really figure out why this is needed. */
242 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1);
243 if ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ||
244 (mode->flags & DRM_MODE_FLAG_INTERLACE) ||
245 mode->hdisplay != outX || mode->vdisplay != outY) {
246 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_ACTIVE);
248 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_INACTIVE);
251 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2);
252 OUT_RING(evo, outY << 16 | outX);
253 OUT_RING(evo, outY << 16 | outX);
256 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
265 nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
267 struct drm_nouveau_private *dev_priv = dev->dev_private;
269 uint32_t reg, reg1, reg2;
270 int ret, N1, M1, N2, M2, P;
272 if (dev_priv->chipset < NV_C0)
273 reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head);
275 reg = 0x614140 + (head * 0x800);
277 ret = get_pll_limits(dev, reg, &pll);
281 if (pll.vco2.maxfreq) {
282 ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P);
286 NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",
287 pclk, ret, N1, M1, N2, M2, P);
289 reg1 = nv_rd32(dev, reg + 4) & 0xff00ff00;
290 reg2 = nv_rd32(dev, reg + 8) & 0x8000ff00;
291 nv_wr32(dev, reg, 0x10000611);
292 nv_wr32(dev, reg + 4, reg1 | (M1 << 16) | N1);
293 nv_wr32(dev, reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
295 if (dev_priv->chipset < NV_C0) {
296 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
300 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
301 pclk, ret, N1, N2, M1, P);
303 reg1 = nv_rd32(dev, reg + 4) & 0xffc00000;
304 nv_wr32(dev, reg, 0x50000610);
305 nv_wr32(dev, reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
306 nv_wr32(dev, reg + 8, N2);
308 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
312 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
313 pclk, ret, N1, N2, M1, P);
315 nv_mask(dev, reg + 0x0c, 0x00000000, 0x00000100);
316 nv_wr32(dev, reg + 0x04, (P << 16) | (N1 << 8) | M1);
317 nv_wr32(dev, reg + 0x10, N2 << 16);
324 nv50_crtc_destroy(struct drm_crtc *crtc)
326 struct drm_device *dev;
327 struct nouveau_crtc *nv_crtc;
333 nv_crtc = nouveau_crtc(crtc);
335 NV_DEBUG_KMS(dev, "\n");
337 drm_crtc_cleanup(&nv_crtc->base);
339 nv50_cursor_fini(nv_crtc);
341 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
342 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
343 kfree(nv_crtc->mode);
348 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
349 uint32_t buffer_handle, uint32_t width, uint32_t height)
351 struct drm_device *dev = crtc->dev;
352 struct drm_nouveau_private *dev_priv = dev->dev_private;
353 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
354 struct nouveau_bo *cursor = NULL;
355 struct drm_gem_object *gem;
358 if (width != 64 || height != 64)
361 if (!buffer_handle) {
362 nv_crtc->cursor.hide(nv_crtc, true);
366 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
369 cursor = nouveau_gem_object(gem);
371 ret = nouveau_bo_map(cursor);
375 /* The simple will do for now. */
376 for (i = 0; i < 64 * 64; i++)
377 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, nouveau_bo_rd32(cursor, i));
379 nouveau_bo_unmap(cursor);
381 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset -
382 dev_priv->vm_vram_base);
383 nv_crtc->cursor.show(nv_crtc, true);
386 drm_gem_object_unreference_unlocked(gem);
391 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
393 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
395 nv_crtc->cursor.set_pos(nv_crtc, x, y);
400 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
401 uint32_t start, uint32_t size)
403 int end = (start + size > 256) ? 256 : start + size, i;
404 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
406 for (i = start; i < end; i++) {
407 nv_crtc->lut.r[i] = r[i];
408 nv_crtc->lut.g[i] = g[i];
409 nv_crtc->lut.b[i] = b[i];
412 /* We need to know the depth before we upload, but it's possible to
413 * get called before a framebuffer is bound. If this is the case,
414 * mark the lut values as dirty by setting depth==0, and it'll be
415 * uploaded on the first mode_set_base()
417 if (!nv_crtc->base.fb) {
418 nv_crtc->lut.depth = 0;
422 nv50_crtc_lut_load(crtc);
426 nv50_crtc_save(struct drm_crtc *crtc)
428 NV_ERROR(crtc->dev, "!!\n");
432 nv50_crtc_restore(struct drm_crtc *crtc)
434 NV_ERROR(crtc->dev, "!!\n");
437 static const struct drm_crtc_funcs nv50_crtc_funcs = {
438 .save = nv50_crtc_save,
439 .restore = nv50_crtc_restore,
440 .cursor_set = nv50_crtc_cursor_set,
441 .cursor_move = nv50_crtc_cursor_move,
442 .gamma_set = nv50_crtc_gamma_set,
443 .set_config = drm_crtc_helper_set_config,
444 .destroy = nv50_crtc_destroy,
448 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
453 nv50_crtc_prepare(struct drm_crtc *crtc)
455 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
456 struct drm_device *dev = crtc->dev;
458 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
460 nv50_crtc_blank(nv_crtc, true);
464 nv50_crtc_commit(struct drm_crtc *crtc)
466 struct drm_device *dev = crtc->dev;
467 struct drm_nouveau_private *dev_priv = dev->dev_private;
468 struct nouveau_channel *evo = dev_priv->evo;
469 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
472 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
474 nv50_crtc_blank(nv_crtc, false);
476 ret = RING_SPACE(evo, 2);
478 NV_ERROR(dev, "no space while committing crtc\n");
481 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
487 nv50_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
488 struct drm_display_mode *adjusted_mode)
494 nv50_crtc_do_mode_set_base(struct drm_crtc *crtc,
495 struct drm_framebuffer *passed_fb,
496 int x, int y, bool update, bool atomic)
498 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
499 struct drm_device *dev = nv_crtc->base.dev;
500 struct drm_nouveau_private *dev_priv = dev->dev_private;
501 struct nouveau_channel *evo = dev_priv->evo;
502 struct drm_framebuffer *drm_fb = nv_crtc->base.fb;
503 struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
506 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
508 /* If atomic, we want to switch to the fb we were passed, so
509 * now we update pointers to do that. (We don't pin; just
510 * assume we're already pinned and update the base address.)
514 fb = nouveau_framebuffer(passed_fb);
517 /* If not atomic, we can go ahead and pin, and unpin the
518 * old fb we were passed.
520 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
525 struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb);
526 nouveau_bo_unpin(ofb->nvbo);
530 switch (drm_fb->depth) {
532 format = NV50_EVO_CRTC_FB_DEPTH_8;
535 format = NV50_EVO_CRTC_FB_DEPTH_15;
538 format = NV50_EVO_CRTC_FB_DEPTH_16;
542 format = NV50_EVO_CRTC_FB_DEPTH_24;
545 format = NV50_EVO_CRTC_FB_DEPTH_30;
548 NV_ERROR(dev, "unknown depth %d\n", drm_fb->depth);
552 nv_crtc->fb.offset = fb->nvbo->bo.offset - dev_priv->vm_vram_base;
553 nv_crtc->fb.tile_flags = fb->nvbo->tile_flags;
554 nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8;
555 if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) {
556 ret = RING_SPACE(evo, 2);
560 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1);
561 if (nv_crtc->fb.tile_flags == 0x7a00)
562 OUT_RING(evo, NvEvoFB32);
564 if (nv_crtc->fb.tile_flags == 0x7000)
565 OUT_RING(evo, NvEvoFB16);
567 OUT_RING(evo, NvEvoVRAM);
570 ret = RING_SPACE(evo, 12);
574 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5);
575 OUT_RING(evo, nv_crtc->fb.offset >> 8);
577 OUT_RING(evo, (drm_fb->height << 16) | drm_fb->width);
578 if (!nv_crtc->fb.tile_flags) {
579 OUT_RING(evo, drm_fb->pitch | (1 << 20));
581 OUT_RING(evo, ((drm_fb->pitch / 4) << 4) |
582 fb->nvbo->tile_mode);
584 if (dev_priv->chipset == 0x50)
585 OUT_RING(evo, (fb->nvbo->tile_flags << 8) | format);
587 OUT_RING(evo, format);
589 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1);
590 OUT_RING(evo, fb->base.depth == 8 ?
591 NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON);
593 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1);
594 OUT_RING(evo, NV50_EVO_CRTC_COLOR_CTRL_COLOR);
595 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1);
596 OUT_RING(evo, (y << 16) | x);
598 if (nv_crtc->lut.depth != fb->base.depth) {
599 nv_crtc->lut.depth = fb->base.depth;
600 nv50_crtc_lut_load(crtc);
604 ret = RING_SPACE(evo, 2);
607 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
616 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
617 struct drm_display_mode *adjusted_mode, int x, int y,
618 struct drm_framebuffer *old_fb)
620 struct drm_device *dev = crtc->dev;
621 struct drm_nouveau_private *dev_priv = dev->dev_private;
622 struct nouveau_channel *evo = dev_priv->evo;
623 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
624 struct nouveau_connector *nv_connector = NULL;
625 uint32_t hsync_dur, vsync_dur, hsync_start_to_end, vsync_start_to_end;
626 uint32_t hunk1, vunk1, vunk2a, vunk2b;
629 /* Find the connector attached to this CRTC */
630 nv_connector = nouveau_crtc_connector_get(nv_crtc);
632 *nv_crtc->mode = *adjusted_mode;
634 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
636 hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
637 vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
638 hsync_start_to_end = adjusted_mode->htotal - adjusted_mode->hsync_start;
639 vsync_start_to_end = adjusted_mode->vtotal - adjusted_mode->vsync_start;
640 /* I can't give this a proper name, anyone else can? */
641 hunk1 = adjusted_mode->htotal -
642 adjusted_mode->hsync_start + adjusted_mode->hdisplay;
643 vunk1 = adjusted_mode->vtotal -
644 adjusted_mode->vsync_start + adjusted_mode->vdisplay;
645 /* Another strange value, this time only for interlaced adjusted_modes. */
646 vunk2a = 2 * adjusted_mode->vtotal -
647 adjusted_mode->vsync_start + adjusted_mode->vdisplay;
648 vunk2b = adjusted_mode->vtotal -
649 adjusted_mode->vsync_start + adjusted_mode->vtotal;
651 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
653 vsync_start_to_end /= 2;
658 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
659 vsync_start_to_end -= 1;
666 ret = RING_SPACE(evo, 17);
670 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLOCK), 2);
671 OUT_RING(evo, adjusted_mode->clock | 0x800000);
672 OUT_RING(evo, (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 0);
674 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DISPLAY_START), 5);
676 OUT_RING(evo, (adjusted_mode->vtotal << 16) | adjusted_mode->htotal);
677 OUT_RING(evo, (vsync_dur - 1) << 16 | (hsync_dur - 1));
678 OUT_RING(evo, (vsync_start_to_end - 1) << 16 |
679 (hsync_start_to_end - 1));
680 OUT_RING(evo, (vunk1 - 1) << 16 | (hunk1 - 1));
682 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
683 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK0824), 1);
684 OUT_RING(evo, (vunk2b - 1) << 16 | (vunk2a - 1));
690 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1);
693 /* This is the actual resolution of the mode. */
694 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1);
695 OUT_RING(evo, (mode->vdisplay << 16) | mode->hdisplay);
696 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CENTER_OFFSET), 1);
697 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CENTER_OFFSET_VAL(0, 0));
699 nv_crtc->set_dither(nv_crtc, nv_connector->use_dithering, false);
700 nv_crtc->set_scale(nv_crtc, nv_connector->scaling_mode, false);
702 return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false, false);
706 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
707 struct drm_framebuffer *old_fb)
709 return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, true, false);
713 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
714 struct drm_framebuffer *fb,
717 return nv50_crtc_do_mode_set_base(crtc, fb, x, y, true, true);
720 static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = {
721 .dpms = nv50_crtc_dpms,
722 .prepare = nv50_crtc_prepare,
723 .commit = nv50_crtc_commit,
724 .mode_fixup = nv50_crtc_mode_fixup,
725 .mode_set = nv50_crtc_mode_set,
726 .mode_set_base = nv50_crtc_mode_set_base,
727 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
728 .load_lut = nv50_crtc_lut_load,
732 nv50_crtc_create(struct drm_device *dev, int index)
734 struct nouveau_crtc *nv_crtc = NULL;
737 NV_DEBUG_KMS(dev, "\n");
739 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
743 nv_crtc->mode = kzalloc(sizeof(*nv_crtc->mode), GFP_KERNEL);
744 if (!nv_crtc->mode) {
749 /* Default CLUT parameters, will be activated on the hw upon
752 for (i = 0; i < 256; i++) {
753 nv_crtc->lut.r[i] = i << 8;
754 nv_crtc->lut.g[i] = i << 8;
755 nv_crtc->lut.b[i] = i << 8;
757 nv_crtc->lut.depth = 0;
759 ret = nouveau_bo_new(dev, NULL, 4096, 0x100, TTM_PL_FLAG_VRAM,
760 0, 0x0000, false, true, &nv_crtc->lut.nvbo);
762 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
764 ret = nouveau_bo_map(nv_crtc->lut.nvbo);
766 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
770 kfree(nv_crtc->mode);
775 nv_crtc->index = index;
777 /* set function pointers */
778 nv_crtc->set_dither = nv50_crtc_set_dither;
779 nv_crtc->set_scale = nv50_crtc_set_scale;
781 drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs);
782 drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs);
783 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
785 ret = nouveau_bo_new(dev, NULL, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
786 0, 0x0000, false, true, &nv_crtc->cursor.nvbo);
788 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
790 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
792 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
795 nv50_cursor_init(nv_crtc);