drivers/gpu/drm/nouveau/nv40_fifo.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "nouveau_drv.h"
  29 #include "nouveau_drm.h"
  30 #include "nouveau_ramht.h"
  31
  32 #define NV40_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV40_RAMFC__SIZE))
  33 #define NV40_RAMFC__SIZE 128
  34
  35 int
  36 nv40_fifo_create_context(struct nouveau_channel *chan)
  37 {
  38         struct drm_device *dev = chan->dev;
  39         struct drm_nouveau_private *dev_priv = dev->dev_private;
  40         uint32_t fc = NV40_RAMFC(chan->id);
  41         unsigned long flags;
  42         int ret;
  43
  44         ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0,
  45                                       NV40_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC |
  46                                       NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
  47         if (ret)
  48                 return ret;
  49
  50         chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
  51                              NV40_USER(chan->id), PAGE_SIZE);
  52         if (!chan->user)
  53                 return -ENOMEM;
  54
  55         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
  56
  57         nv_wi32(dev, fc +  0, chan->pushbuf_base);
  58         nv_wi32(dev, fc +  4, chan->pushbuf_base);
  59         nv_wi32(dev, fc + 12, chan->pushbuf->pinst >> 4);
  60         nv_wi32(dev, fc + 24, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
  61                               NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
  62                               NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
  63 #ifdef __BIG_ENDIAN
  64                               NV_PFIFO_CACHE1_BIG_ENDIAN |
  65 #endif
  66                               0x30000000 /* no idea.. */);
  67         nv_wi32(dev, fc + 60, 0x0001FFFF);
  68
  69         /* enable the fifo dma operation */
  70         nv_wr32(dev, NV04_PFIFO_MODE,
  71                 nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
  72
  73         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
  74         return 0;
  75 }
  76
  77 static void
  78 nv40_fifo_do_load_context(struct drm_device *dev, int chid)
  79 {
  80         struct drm_nouveau_private *dev_priv = dev->dev_private;
  81         uint32_t fc = NV40_RAMFC(chid), tmp, tmp2;
  82
  83         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
  84         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
  85         nv_wr32(dev, NV10_PFIFO_CACHE1_REF_CNT, nv_ri32(dev, fc + 8));
  86         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, nv_ri32(dev, fc + 12));
  87         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, nv_ri32(dev, fc + 16));
  88         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 20));
  89
  90         /* No idea what 0x2058 is.. */
  91         tmp   = nv_ri32(dev, fc + 24);
  92         tmp2  = nv_rd32(dev, 0x2058) & 0xFFF;
  93         tmp2 |= (tmp & 0x30000000);
  94         nv_wr32(dev, 0x2058, tmp2);
  95         tmp  &= ~0x30000000;
  96         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, tmp);
  97
  98         nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 28));
  99         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 32));
 100         nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE, nv_ri32(dev, fc + 36));
 101         tmp = nv_ri32(dev, fc + 40);
 102         nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, tmp);
 103         nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, nv_ri32(dev, fc + 44));
 104         nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, nv_ri32(dev, fc + 48));
 105         nv_wr32(dev, NV10_PFIFO_CACHE1_DMA_SUBROUTINE, nv_ri32(dev, fc + 52));
 106         nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, nv_ri32(dev, fc + 56));
 107
 108         /* Don't clobber the TIMEOUT_ENABLED flag when restoring from RAMFC */
 109         tmp  = nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF;
 110         tmp |= nv_ri32(dev, fc + 60) & 0x1FFFF;
 111         nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, tmp);
 112
 113         nv_wr32(dev, 0x32e4, nv_ri32(dev, fc + 64));
 114         /* NVIDIA does this next line twice... */
 115         nv_wr32(dev, 0x32e8, nv_ri32(dev, fc + 68));
 116         nv_wr32(dev, 0x2088, nv_ri32(dev, fc + 76));
 117         nv_wr32(dev, 0x3300, nv_ri32(dev, fc + 80));
 118
 119         nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
 120         nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
 121 }
 122
 123 int
 124 nv40_fifo_load_context(struct nouveau_channel *chan)
 125 {
 126         struct drm_device *dev = chan->dev;
 127         uint32_t tmp;
 128
 129         nv40_fifo_do_load_context(dev, chan->id);
 130
 131         /* Set channel active, and in DMA mode */
 132         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
 133                      NV40_PFIFO_CACHE1_PUSH1_DMA | chan->id);
 134         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
 135
 136         /* Reset DMA_CTL_AT_INFO to INVALID */
 137         tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
 138         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 139
 140         return 0;
 141 }
 142
 143 int
 144 nv40_fifo_unload_context(struct drm_device *dev)
 145 {
 146         struct drm_nouveau_private *dev_priv = dev->dev_private;
 147         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 148         uint32_t fc, tmp;
 149         int chid;
 150
 151         chid = pfifo->channel_id(dev);
 152         if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
 153                 return 0;
 154         fc = NV40_RAMFC(chid);
 155
 156         nv_wi32(dev, fc + 0, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
 157         nv_wi32(dev, fc + 4, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
 158         nv_wi32(dev, fc + 8, nv_rd32(dev, NV10_PFIFO_CACHE1_REF_CNT));
 159         nv_wi32(dev, fc + 12, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE));
 160         nv_wi32(dev, fc + 16, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT));
 161         nv_wi32(dev, fc + 20, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
 162         tmp  = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH);
 163         tmp |= nv_rd32(dev, 0x2058) & 0x30000000;
 164         nv_wi32(dev, fc + 24, tmp);
 165         nv_wi32(dev, fc + 28, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
 166         nv_wi32(dev, fc + 32, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
 167         nv_wi32(dev, fc + 36, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
 168         tmp = nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
 169         nv_wi32(dev, fc + 40, tmp);
 170         nv_wi32(dev, fc + 44, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
 171         nv_wi32(dev, fc + 48, nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE));
 172         /* NVIDIA read 0x3228 first, then write DMA_GET here.. maybe something
 173          * more involved depending on the value of 0x3228?
 174          */
 175         nv_wi32(dev, fc + 52, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
 176         nv_wi32(dev, fc + 56, nv_rd32(dev, NV40_PFIFO_GRCTX_INSTANCE));
 177         nv_wi32(dev, fc + 60, nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & 0x1ffff);
 178         /* No idea what the below is for exactly, ripped from a mmio-trace */
 179         nv_wi32(dev, fc + 64, nv_rd32(dev, NV40_PFIFO_UNK32E4));
 180         /* NVIDIA do this next line twice.. bug? */
 181         nv_wi32(dev, fc + 68, nv_rd32(dev, 0x32e8));
 182         nv_wi32(dev, fc + 76, nv_rd32(dev, 0x2088));
 183         nv_wi32(dev, fc + 80, nv_rd32(dev, 0x3300));
 184 #if 0 /* no real idea which is PUT/GET in UNK_48.. */
 185         tmp  = nv_rd32(dev, NV04_PFIFO_CACHE1_GET);
 186         tmp |= (nv_rd32(dev, NV04_PFIFO_CACHE1_PUT) << 16);
 187         nv_wi32(dev, fc + 72, tmp);
 188 #endif
 189
 190         nv40_fifo_do_load_context(dev, pfifo->channels - 1);
 191         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
 192                      NV40_PFIFO_CACHE1_PUSH1_DMA | (pfifo->channels - 1));
 193         return 0;
 194 }
 195
 196 static void
 197 nv40_fifo_init_reset(struct drm_device *dev)
 198 {
 199         int i;
 200
 201         nv_wr32(dev, NV03_PMC_ENABLE,
 202                 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
 203         nv_wr32(dev, NV03_PMC_ENABLE,
 204                 nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PFIFO);
 205
 206         nv_wr32(dev, 0x003224, 0x000f0078);
 207         nv_wr32(dev, 0x003210, 0x00000000);
 208         nv_wr32(dev, 0x003270, 0x00000000);
 209         nv_wr32(dev, 0x003240, 0x00000000);
 210         nv_wr32(dev, 0x003244, 0x00000000);
 211         nv_wr32(dev, 0x003258, 0x00000000);
 212         nv_wr32(dev, 0x002504, 0x00000000);
 213         for (i = 0; i < 16; i++)
 214                 nv_wr32(dev, 0x002510 + (i * 4), 0x00000000);
 215         nv_wr32(dev, 0x00250c, 0x0000ffff);
 216         nv_wr32(dev, 0x002048, 0x00000000);
 217         nv_wr32(dev, 0x003228, 0x00000000);
 218         nv_wr32(dev, 0x0032e8, 0x00000000);
 219         nv_wr32(dev, 0x002410, 0x00000000);
 220         nv_wr32(dev, 0x002420, 0x00000000);
 221         nv_wr32(dev, 0x002058, 0x00000001);
 222         nv_wr32(dev, 0x00221c, 0x00000000);
 223         /* something with 0x2084, read/modify/write, no change */
 224         nv_wr32(dev, 0x002040, 0x000000ff);
 225         nv_wr32(dev, 0x002500, 0x00000000);
 226         nv_wr32(dev, 0x003200, 0x00000000);
 227
 228         nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff);
 229 }
 230
 231 static void
 232 nv40_fifo_init_ramxx(struct drm_device *dev)
 233 {
 234         struct drm_nouveau_private *dev_priv = dev->dev_private;
 235
 236         nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 237                                        ((dev_priv->ramht->bits - 9) << 16) |
 238                                        (dev_priv->ramht->gpuobj->pinst >> 8));
 239         nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);
 240
 241         switch (dev_priv->chipset) {
 242         case 0x47:
 243         case 0x49:
 244         case 0x4b:
 245                 nv_wr32(dev, 0x2230, 1);
 246                 break;
 247         default:
 248                 break;
 249         }
 250
 251         switch (dev_priv->chipset) {
 252         case 0x40:
 253         case 0x41:
 254         case 0x42:
 255         case 0x43:
 256         case 0x45:
 257         case 0x47:
 258         case 0x48:
 259         case 0x49:
 260         case 0x4b:
 261                 nv_wr32(dev, NV40_PFIFO_RAMFC, 0x30002);
 262                 break;
 263         default:
 264                 nv_wr32(dev, 0x2230, 0);
 265                 nv_wr32(dev, NV40_PFIFO_RAMFC,
 266                         ((dev_priv->vram_size - 512 * 1024 +
 267                           dev_priv->ramfc->pinst) >> 16) | (3 << 16));
 268                 break;
 269         }
 270 }
 271
 272 static void
 273 nv40_fifo_init_intr(struct drm_device *dev)
 274 {
 275         nouveau_irq_register(dev, 8, nv04_fifo_isr);
 276         nv_wr32(dev, 0x002100, 0xffffffff);
 277         nv_wr32(dev, 0x002140, 0xffffffff);
 278 }
 279
 280 int
 281 nv40_fifo_init(struct drm_device *dev)
 282 {
 283         struct drm_nouveau_private *dev_priv = dev->dev_private;
 284         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 285         int i;
 286
 287         nv40_fifo_init_reset(dev);
 288         nv40_fifo_init_ramxx(dev);
 289
 290         nv40_fifo_do_load_context(dev, pfifo->channels - 1);
 291         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
 292
 293         nv40_fifo_init_intr(dev);
 294         pfifo->enable(dev);
 295         pfifo->reassign(dev, true);
 296
 297         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 298                 if (dev_priv->channels.ptr[i]) {
 299                         uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
 300                         nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
 301                 }
 302         }
 303
 304         return 0;
 305 }