3 #include "nouveau_drv.h"
4 #include "nouveau_drm.h"
7 nv40_fb_set_tile_region(struct drm_device *dev, int i)
9 struct drm_nouveau_private *dev_priv = dev->dev_private;
10 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
12 switch (dev_priv->chipset) {
14 nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
15 nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
16 nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
20 nv_wr32(dev, NV40_PFB_TLIMIT(i), tile->limit);
21 nv_wr32(dev, NV40_PFB_TSIZE(i), tile->pitch);
22 nv_wr32(dev, NV40_PFB_TILE(i), tile->addr);
28 nv40_fb_init(struct drm_device *dev)
30 struct drm_nouveau_private *dev_priv = dev->dev_private;
31 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
35 /* This is strictly a NV4x register (don't know about NV5x). */
36 /* The blob sets these to all kinds of values, and they mess up our setup. */
37 /* I got value 0x52802 instead. For some cards the blob even sets it back to 0x1. */
38 /* Note: the blob doesn't read this value, so i'm pretty sure this is safe for all cards. */
39 /* Any idea what this is? */
40 nv_wr32(dev, NV40_PFB_UNK_800, 0x1);
42 switch (dev_priv->chipset) {
45 tmp = nv_rd32(dev, NV10_PFB_CLOSE_PAGE2);
46 nv_wr32(dev, NV10_PFB_CLOSE_PAGE2, tmp & ~(1 << 15));
47 pfb->num_tiles = NV10_PFB_TILE__SIZE;
53 case 0x4c: /* C51 (G7X version) */
54 pfb->num_tiles = NV40_PFB_TILE__SIZE_1;
57 pfb->num_tiles = NV40_PFB_TILE__SIZE_0;
61 /* Turn all the tiling regions off. */
62 for (i = 0; i < pfb->num_tiles; i++)
63 pfb->set_tile_region(dev, i);
69 nv40_fb_takedown(struct drm_device *dev)