drivers/gpu/drm/nouveau/nv04_tv.c

   1 /*
   2  * Copyright (C) 2009 Francisco Jerez.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "nouveau_drv.h"
  29 #include "nouveau_encoder.h"
  30 #include "nouveau_connector.h"
  31 #include "nouveau_crtc.h"
  32 #include "nouveau_hw.h"
  33 #include "drm_crtc_helper.h"
  34
  35 #include "i2c/ch7006.h"
  36
  37 static struct i2c_board_info nv04_tv_encoder_info[] = {
  38         {
  39                 I2C_BOARD_INFO("ch7006", 0x75),
  40                 .platform_data = &(struct ch7006_encoder_params) {
  41                         CH7006_FORMAT_RGB24m12I, CH7006_CLOCK_MASTER,
  42                         0, 0, 0,
  43                         CH7006_SYNC_SLAVE, CH7006_SYNC_SEPARATED,
  44                         CH7006_POUT_3_3V, CH7006_ACTIVE_HSYNC
  45                 }
  46         },
  47         { }
  48 };
  49
  50 int nv04_tv_identify(struct drm_device *dev, int i2c_index)
  51 {
  52         return nouveau_i2c_identify(dev, "TV encoder",
  53                                     nv04_tv_encoder_info, i2c_index);
  54 }
  55
  56
  57 #define PLLSEL_TV_CRTC1_MASK                            \
  58         (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1          \
  59          | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1)
  60 #define PLLSEL_TV_CRTC2_MASK                            \
  61         (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2          \
  62          | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
  63
  64 static void nv04_tv_dpms(struct drm_encoder *encoder, int mode)
  65 {
  66         struct drm_device *dev = encoder->dev;
  67         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  68         struct drm_nouveau_private *dev_priv = dev->dev_private;
  69         struct nv04_mode_state *state = &dev_priv->mode_reg;
  70         uint8_t crtc1A;
  71
  72         NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
  73                 mode, nv_encoder->dcb->index);
  74
  75         state->pllsel &= ~(PLLSEL_TV_CRTC1_MASK | PLLSEL_TV_CRTC2_MASK);
  76
  77         if (mode == DRM_MODE_DPMS_ON) {
  78                 int head = nouveau_crtc(encoder->crtc)->index;
  79                 crtc1A = NVReadVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX);
  80
  81                 state->pllsel |= head ? PLLSEL_TV_CRTC2_MASK :
  82                                         PLLSEL_TV_CRTC1_MASK;
  83
  84                 /* Inhibit hsync */
  85                 crtc1A |= 0x80;
  86
  87                 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX, crtc1A);
  88         }
  89
  90         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
  91
  92         get_slave_funcs(encoder)->dpms(encoder, mode);
  93 }
  94
  95 static void nv04_tv_bind(struct drm_device *dev, int head, bool bind)
  96 {
  97         struct drm_nouveau_private *dev_priv = dev->dev_private;
  98         struct nv04_crtc_reg *state = &dev_priv->mode_reg.crtc_reg[head];
  99
 100         state->tv_setup = 0;
 101
 102         if (bind) {
 103                 state->CRTC[NV_CIO_CRE_LCD__INDEX] = 0;
 104                 state->CRTC[NV_CIO_CRE_49] |= 0x10;
 105         } else {
 106                 state->CRTC[NV_CIO_CRE_49] &= ~0x10;
 107         }
 108
 109         NVWriteVgaCrtc(dev, head, NV_CIO_CRE_LCD__INDEX,
 110                        state->CRTC[NV_CIO_CRE_LCD__INDEX]);
 111         NVWriteVgaCrtc(dev, head, NV_CIO_CRE_49,
 112                        state->CRTC[NV_CIO_CRE_49]);
 113         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP,
 114                       state->tv_setup);
 115 }
 116
 117 static void nv04_tv_prepare(struct drm_encoder *encoder)
 118 {
 119         struct drm_device *dev = encoder->dev;
 120         int head = nouveau_crtc(encoder->crtc)->index;
 121         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 122
 123         helper->dpms(encoder, DRM_MODE_DPMS_OFF);
 124
 125         nv04_dfp_disable(dev, head);
 126
 127         if (nv_two_heads(dev))
 128                 nv04_tv_bind(dev, head ^ 1, false);
 129
 130         nv04_tv_bind(dev, head, true);
 131 }
 132
 133 static void nv04_tv_mode_set(struct drm_encoder *encoder,
 134                              struct drm_display_mode *mode,
 135                              struct drm_display_mode *adjusted_mode)
 136 {
 137         struct drm_device *dev = encoder->dev;
 138         struct drm_nouveau_private *dev_priv = dev->dev_private;
 139         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 140         struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
 141
 142         regp->tv_htotal = adjusted_mode->htotal;
 143         regp->tv_vtotal = adjusted_mode->vtotal;
 144
 145         /* These delay the TV signals with respect to the VGA port,
 146          * they might be useful if we ever allow a CRTC to drive
 147          * multiple outputs.
 148          */
 149         regp->tv_hskew = 1;
 150         regp->tv_hsync_delay = 1;
 151         regp->tv_hsync_delay2 = 64;
 152         regp->tv_vskew = 1;
 153         regp->tv_vsync_delay = 1;
 154
 155         get_slave_funcs(encoder)->mode_set(encoder, mode, adjusted_mode);
 156 }
 157
 158 static void nv04_tv_commit(struct drm_encoder *encoder)
 159 {
 160         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 161         struct drm_device *dev = encoder->dev;
 162         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 163         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 164
 165         helper->dpms(encoder, DRM_MODE_DPMS_ON);
 166
 167         NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
 168                       drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base), nv_crtc->index,
 169                       '@' + ffs(nv_encoder->dcb->or));
 170 }
 171
 172 static void nv04_tv_destroy(struct drm_encoder *encoder)
 173 {
 174         get_slave_funcs(encoder)->destroy(encoder);
 175         drm_encoder_cleanup(encoder);
 176
 177         kfree(encoder->helper_private);
 178         kfree(nouveau_encoder(encoder));
 179 }
 180
 181 static const struct drm_encoder_funcs nv04_tv_funcs = {
 182         .destroy = nv04_tv_destroy,
 183 };
 184
 185 int
 186 nv04_tv_create(struct drm_connector *connector, struct dcb_entry *entry)
 187 {
 188         struct nouveau_encoder *nv_encoder;
 189         struct drm_encoder *encoder;
 190         struct drm_device *dev = connector->dev;
 191         struct drm_encoder_helper_funcs *hfuncs;
 192         struct drm_encoder_slave_funcs *sfuncs;
 193         struct nouveau_i2c_chan *i2c =
 194                 nouveau_i2c_find(dev, entry->i2c_index);
 195         int type, ret;
 196
 197         /* Ensure that we can talk to this encoder */
 198         type = nv04_tv_identify(dev, entry->i2c_index);
 199         if (type < 0)
 200                 return type;
 201
 202         /* Allocate the necessary memory */
 203         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 204         if (!nv_encoder)
 205                 return -ENOMEM;
 206
 207         hfuncs = kzalloc(sizeof(*hfuncs), GFP_KERNEL);
 208         if (!hfuncs) {
 209                 ret = -ENOMEM;
 210                 goto fail_free;
 211         }
 212
 213         /* Initialize the common members */
 214         encoder = to_drm_encoder(nv_encoder);
 215
 216         drm_encoder_init(dev, encoder, &nv04_tv_funcs, DRM_MODE_ENCODER_TVDAC);
 217         drm_encoder_helper_add(encoder, hfuncs);
 218
 219         encoder->possible_crtcs = entry->heads;
 220         encoder->possible_clones = 0;
 221         nv_encoder->dcb = entry;
 222         nv_encoder->or = ffs(entry->or) - 1;
 223
 224         /* Run the slave-specific initialization */
 225         ret = drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
 226                                    &i2c->adapter, &nv04_tv_encoder_info[type]);
 227         if (ret < 0)
 228                 goto fail_cleanup;
 229
 230         /* Fill the function pointers */
 231         sfuncs = get_slave_funcs(encoder);
 232
 233         *hfuncs = (struct drm_encoder_helper_funcs) {
 234                 .dpms = nv04_tv_dpms,
 235                 .save = sfuncs->save,
 236                 .restore = sfuncs->restore,
 237                 .mode_fixup = sfuncs->mode_fixup,
 238                 .prepare = nv04_tv_prepare,
 239                 .commit = nv04_tv_commit,
 240                 .mode_set = nv04_tv_mode_set,
 241                 .detect = sfuncs->detect,
 242         };
 243
 244         /* Attach it to the specified connector. */
 245         sfuncs->create_resources(encoder, connector);
 246         drm_mode_connector_attach_encoder(connector, encoder);
 247
 248         return 0;
 249
 250 fail_cleanup:
 251         drm_encoder_cleanup(encoder);
 252         kfree(hfuncs);
 253 fail_free:
 254         kfree(nv_encoder);
 255         return ret;
 256 }