2 #include "nouveau_drv.h"
3 #include <linux/pagemap.h>
4 #include <linux/slab.h>
6 #define NV_CTXDMA_PAGE_SHIFT 12
7 #define NV_CTXDMA_PAGE_SIZE (1 << NV_CTXDMA_PAGE_SHIFT)
8 #define NV_CTXDMA_PAGE_MASK (NV_CTXDMA_PAGE_SIZE - 1)
10 struct nouveau_sgdma_be {
11 struct ttm_backend backend;
12 struct drm_device *dev;
23 nouveau_sgdma_populate(struct ttm_backend *be, unsigned long num_pages,
24 struct page **pages, struct page *dummy_read_page,
25 dma_addr_t *dma_addrs)
27 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
28 struct drm_device *dev = nvbe->dev;
30 NV_DEBUG(nvbe->dev, "num_pages = %ld\n", num_pages);
35 nvbe->pages = kmalloc(sizeof(dma_addr_t) * num_pages, GFP_KERNEL);
39 nvbe->ttm_alloced = kmalloc(sizeof(bool) * num_pages, GFP_KERNEL);
40 if (!nvbe->ttm_alloced)
45 if (dma_addrs[nvbe->nr_pages] != DMA_ERROR_CODE) {
46 nvbe->pages[nvbe->nr_pages] =
47 dma_addrs[nvbe->nr_pages];
48 nvbe->ttm_alloced[nvbe->nr_pages] = true;
50 nvbe->pages[nvbe->nr_pages] =
51 pci_map_page(dev->pdev, pages[nvbe->nr_pages], 0,
52 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
53 if (pci_dma_mapping_error(dev->pdev,
54 nvbe->pages[nvbe->nr_pages])) {
58 nvbe->ttm_alloced[nvbe->nr_pages] = false;
68 nouveau_sgdma_clear(struct ttm_backend *be)
70 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
71 struct drm_device *dev;
73 if (nvbe && nvbe->pages) {
80 while (nvbe->nr_pages--) {
81 if (!nvbe->ttm_alloced[nvbe->nr_pages])
82 pci_unmap_page(dev->pdev, nvbe->pages[nvbe->nr_pages],
83 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
86 kfree(nvbe->ttm_alloced);
88 nvbe->ttm_alloced = NULL;
94 nouveau_sgdma_destroy(struct ttm_backend *be)
96 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
99 NV_DEBUG(nvbe->dev, "\n");
110 nv04_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
112 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
113 struct drm_device *dev = nvbe->dev;
114 struct drm_nouveau_private *dev_priv = dev->dev_private;
115 struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
118 NV_DEBUG(dev, "pg=0x%lx\n", mem->start);
120 nvbe->offset = mem->start << PAGE_SHIFT;
121 pte = (nvbe->offset >> NV_CTXDMA_PAGE_SHIFT) + 2;
122 for (i = 0; i < nvbe->nr_pages; i++) {
123 dma_addr_t dma_offset = nvbe->pages[i];
124 uint32_t offset_l = lower_32_bits(dma_offset);
126 for (j = 0; j < PAGE_SIZE / NV_CTXDMA_PAGE_SIZE; j++, pte++) {
127 nv_wo32(gpuobj, (pte * 4) + 0, offset_l | 3);
128 dma_offset += NV_CTXDMA_PAGE_SIZE;
137 nv04_sgdma_unbind(struct ttm_backend *be)
139 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
140 struct drm_device *dev = nvbe->dev;
141 struct drm_nouveau_private *dev_priv = dev->dev_private;
142 struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
150 pte = (nvbe->offset >> NV_CTXDMA_PAGE_SHIFT) + 2;
151 for (i = 0; i < nvbe->nr_pages; i++) {
152 for (j = 0; j < PAGE_SIZE / NV_CTXDMA_PAGE_SIZE; j++, pte++)
153 nv_wo32(gpuobj, (pte * 4) + 0, 0x00000000);
160 static struct ttm_backend_func nv04_sgdma_backend = {
161 .populate = nouveau_sgdma_populate,
162 .clear = nouveau_sgdma_clear,
163 .bind = nv04_sgdma_bind,
164 .unbind = nv04_sgdma_unbind,
165 .destroy = nouveau_sgdma_destroy
169 nv41_sgdma_flush(struct nouveau_sgdma_be *nvbe)
171 struct drm_device *dev = nvbe->dev;
173 nv_wr32(dev, 0x100810, 0x00000022);
174 if (!nv_wait(dev, 0x100810, 0x00000100, 0x00000100))
175 NV_ERROR(dev, "vm flush timeout: 0x%08x\n",
176 nv_rd32(dev, 0x100810));
177 nv_wr32(dev, 0x100810, 0x00000000);
181 nv41_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
183 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
184 struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
185 struct nouveau_gpuobj *pgt = dev_priv->gart_info.sg_ctxdma;
186 dma_addr_t *list = nvbe->pages;
187 u32 pte = mem->start << 2;
188 u32 cnt = nvbe->nr_pages;
190 nvbe->offset = mem->start << PAGE_SHIFT;
193 nv_wo32(pgt, pte, (*list++ >> 7) | 1);
197 nv41_sgdma_flush(nvbe);
203 nv41_sgdma_unbind(struct ttm_backend *be)
205 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
206 struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
207 struct nouveau_gpuobj *pgt = dev_priv->gart_info.sg_ctxdma;
208 u32 pte = (nvbe->offset >> 12) << 2;
209 u32 cnt = nvbe->nr_pages;
212 nv_wo32(pgt, pte, 0x00000000);
216 nv41_sgdma_flush(nvbe);
221 static struct ttm_backend_func nv41_sgdma_backend = {
222 .populate = nouveau_sgdma_populate,
223 .clear = nouveau_sgdma_clear,
224 .bind = nv41_sgdma_bind,
225 .unbind = nv41_sgdma_unbind,
226 .destroy = nouveau_sgdma_destroy
230 nv44_sgdma_flush(struct nouveau_sgdma_be *nvbe)
232 struct drm_device *dev = nvbe->dev;
234 nv_wr32(dev, 0x100814, (nvbe->nr_pages - 1) << 12);
235 nv_wr32(dev, 0x100808, nvbe->offset | 0x20);
236 if (!nv_wait(dev, 0x100808, 0x00000001, 0x00000001))
237 NV_ERROR(dev, "gart flush timeout: 0x%08x\n",
238 nv_rd32(dev, 0x100808));
239 nv_wr32(dev, 0x100808, 0x00000000);
243 nv44_sgdma_fill(struct nouveau_gpuobj *pgt, dma_addr_t *list, u32 base, u32 cnt)
245 struct drm_nouveau_private *dev_priv = pgt->dev->dev_private;
246 dma_addr_t dummy = dev_priv->gart_info.dummy.addr;
252 tmp[0] = nv_ro32(pgt, base + 0x0);
253 tmp[1] = nv_ro32(pgt, base + 0x4);
254 tmp[2] = nv_ro32(pgt, base + 0x8);
255 tmp[3] = nv_ro32(pgt, base + 0xc);
257 u32 addr = list ? (*list++ >> 12) : (dummy >> 12);
258 switch (pte++ & 0x3) {
260 tmp[0] &= ~0x07ffffff;
264 tmp[0] &= ~0xf8000000;
265 tmp[0] |= addr << 27;
266 tmp[1] &= ~0x003fffff;
270 tmp[1] &= ~0xffc00000;
271 tmp[1] |= addr << 22;
272 tmp[2] &= ~0x0001ffff;
273 tmp[2] |= addr >> 10;
276 tmp[2] &= ~0xfffe0000;
277 tmp[2] |= addr << 17;
278 tmp[3] &= ~0x00000fff;
279 tmp[3] |= addr >> 15;
284 tmp[3] |= 0x40000000;
286 nv_wo32(pgt, base + 0x0, tmp[0]);
287 nv_wo32(pgt, base + 0x4, tmp[1]);
288 nv_wo32(pgt, base + 0x8, tmp[2]);
289 nv_wo32(pgt, base + 0xc, tmp[3]);
293 nv44_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
295 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
296 struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
297 struct nouveau_gpuobj *pgt = dev_priv->gart_info.sg_ctxdma;
298 dma_addr_t *list = nvbe->pages;
299 u32 pte = mem->start << 2, tmp[4];
300 u32 cnt = nvbe->nr_pages;
303 nvbe->offset = mem->start << PAGE_SHIFT;
305 if (pte & 0x0000000c) {
306 u32 max = 4 - ((pte >> 2) & 0x3);
307 u32 part = (cnt > max) ? max : cnt;
308 nv44_sgdma_fill(pgt, list, pte, part);
315 for (i = 0; i < 4; i++)
316 tmp[i] = *list++ >> 12;
317 nv_wo32(pgt, pte + 0x0, tmp[0] >> 0 | tmp[1] << 27);
318 nv_wo32(pgt, pte + 0x4, tmp[1] >> 5 | tmp[2] << 22);
319 nv_wo32(pgt, pte + 0x8, tmp[2] >> 10 | tmp[3] << 17);
320 nv_wo32(pgt, pte + 0xc, tmp[3] >> 15 | 0x40000000);
326 nv44_sgdma_fill(pgt, list, pte, cnt);
328 nv44_sgdma_flush(nvbe);
334 nv44_sgdma_unbind(struct ttm_backend *be)
336 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
337 struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
338 struct nouveau_gpuobj *pgt = dev_priv->gart_info.sg_ctxdma;
339 u32 pte = (nvbe->offset >> 12) << 2;
340 u32 cnt = nvbe->nr_pages;
342 if (pte & 0x0000000c) {
343 u32 max = 4 - ((pte >> 2) & 0x3);
344 u32 part = (cnt > max) ? max : cnt;
345 nv44_sgdma_fill(pgt, NULL, pte, part);
351 nv_wo32(pgt, pte + 0x0, 0x00000000);
352 nv_wo32(pgt, pte + 0x4, 0x00000000);
353 nv_wo32(pgt, pte + 0x8, 0x00000000);
354 nv_wo32(pgt, pte + 0xc, 0x00000000);
360 nv44_sgdma_fill(pgt, NULL, pte, cnt);
362 nv44_sgdma_flush(nvbe);
367 static struct ttm_backend_func nv44_sgdma_backend = {
368 .populate = nouveau_sgdma_populate,
369 .clear = nouveau_sgdma_clear,
370 .bind = nv44_sgdma_bind,
371 .unbind = nv44_sgdma_unbind,
372 .destroy = nouveau_sgdma_destroy
376 nv50_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
378 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
379 struct nouveau_mem *node = mem->mm_node;
380 /* noop: bound in move_notify() */
381 node->pages = nvbe->pages;
382 nvbe->pages = (dma_addr_t *)node;
388 nv50_sgdma_unbind(struct ttm_backend *be)
390 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
391 struct nouveau_mem *node = (struct nouveau_mem *)nvbe->pages;
392 /* noop: unbound in move_notify() */
393 nvbe->pages = node->pages;
399 static struct ttm_backend_func nv50_sgdma_backend = {
400 .populate = nouveau_sgdma_populate,
401 .clear = nouveau_sgdma_clear,
402 .bind = nv50_sgdma_bind,
403 .unbind = nv50_sgdma_unbind,
404 .destroy = nouveau_sgdma_destroy
408 nouveau_sgdma_init_ttm(struct drm_device *dev)
410 struct drm_nouveau_private *dev_priv = dev->dev_private;
411 struct nouveau_sgdma_be *nvbe;
413 nvbe = kzalloc(sizeof(*nvbe), GFP_KERNEL);
419 nvbe->backend.func = dev_priv->gart_info.func;
420 return &nvbe->backend;
424 nouveau_sgdma_init(struct drm_device *dev)
426 struct drm_nouveau_private *dev_priv = dev->dev_private;
427 struct nouveau_gpuobj *gpuobj = NULL;
428 u32 aper_size, align;
431 if (dev_priv->card_type >= NV_40 && drm_pci_device_is_pcie(dev))
432 aper_size = 512 * 1024 * 1024;
434 aper_size = 64 * 1024 * 1024;
436 /* Dear NVIDIA, NV44+ would like proper present bits in PTEs for
437 * christmas. The cards before it have them, the cards after
438 * it have them, why is NV44 so unloved?
440 dev_priv->gart_info.dummy.page = alloc_page(GFP_DMA32 | GFP_KERNEL);
441 if (!dev_priv->gart_info.dummy.page)
444 dev_priv->gart_info.dummy.addr =
445 pci_map_page(dev->pdev, dev_priv->gart_info.dummy.page,
446 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
447 if (pci_dma_mapping_error(dev->pdev, dev_priv->gart_info.dummy.addr)) {
448 NV_ERROR(dev, "error mapping dummy page\n");
449 __free_page(dev_priv->gart_info.dummy.page);
450 dev_priv->gart_info.dummy.page = NULL;
454 if (dev_priv->card_type >= NV_50) {
455 dev_priv->gart_info.aper_base = 0;
456 dev_priv->gart_info.aper_size = aper_size;
457 dev_priv->gart_info.type = NOUVEAU_GART_HW;
458 dev_priv->gart_info.func = &nv50_sgdma_backend;
460 if (drm_pci_device_is_pcie(dev) &&
461 dev_priv->chipset > 0x40 && dev_priv->chipset != 0x45) {
462 if (nv44_graph_class(dev)) {
463 dev_priv->gart_info.func = &nv44_sgdma_backend;
466 dev_priv->gart_info.func = &nv41_sgdma_backend;
470 ret = nouveau_gpuobj_new(dev, NULL, aper_size / 1024, align,
471 NVOBJ_FLAG_ZERO_ALLOC |
472 NVOBJ_FLAG_ZERO_FREE, &gpuobj);
474 NV_ERROR(dev, "Error creating sgdma object: %d\n", ret);
478 dev_priv->gart_info.sg_ctxdma = gpuobj;
479 dev_priv->gart_info.aper_base = 0;
480 dev_priv->gart_info.aper_size = aper_size;
481 dev_priv->gart_info.type = NOUVEAU_GART_HW;
483 ret = nouveau_gpuobj_new(dev, NULL, (aper_size / 1024) + 8, 16,
484 NVOBJ_FLAG_ZERO_ALLOC |
485 NVOBJ_FLAG_ZERO_FREE, &gpuobj);
487 NV_ERROR(dev, "Error creating sgdma object: %d\n", ret);
491 nv_wo32(gpuobj, 0, NV_CLASS_DMA_IN_MEMORY |
492 (1 << 12) /* PT present */ |
493 (0 << 13) /* PT *not* linear */ |
495 (2 << 16) /* PCI */);
496 nv_wo32(gpuobj, 4, aper_size - 1);
498 dev_priv->gart_info.sg_ctxdma = gpuobj;
499 dev_priv->gart_info.aper_base = 0;
500 dev_priv->gart_info.aper_size = aper_size;
501 dev_priv->gart_info.type = NOUVEAU_GART_PDMA;
502 dev_priv->gart_info.func = &nv04_sgdma_backend;
509 nouveau_sgdma_takedown(struct drm_device *dev)
511 struct drm_nouveau_private *dev_priv = dev->dev_private;
513 nouveau_gpuobj_ref(NULL, &dev_priv->gart_info.sg_ctxdma);
515 if (dev_priv->gart_info.dummy.page) {
516 pci_unmap_page(dev->pdev, dev_priv->gart_info.dummy.addr,
517 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
518 __free_page(dev_priv->gart_info.dummy.page);
519 dev_priv->gart_info.dummy.page = NULL;
524 nouveau_sgdma_get_physical(struct drm_device *dev, uint32_t offset)
526 struct drm_nouveau_private *dev_priv = dev->dev_private;
527 struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
528 int pte = (offset >> NV_CTXDMA_PAGE_SHIFT) + 2;
530 BUG_ON(dev_priv->card_type >= NV_50);
532 return (nv_ro32(gpuobj, 4 * pte) & ~NV_CTXDMA_PAGE_MASK) |
533 (offset & NV_CTXDMA_PAGE_MASK);