2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
59 #define MAX_NUM_DCB_ENTRIES 16
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
79 u32 busy_placements[3];
80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
89 struct nouveau_channel *channel;
96 struct nouveau_tile_reg *tile;
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
103 static inline struct nouveau_bo *
104 nouveau_bo(struct ttm_buffer_object *bo)
106 return container_of(bo, struct nouveau_bo, bo);
109 static inline struct nouveau_bo *
110 nouveau_gem_object(struct drm_gem_object *gem)
112 return gem ? gem->driver_private : NULL;
115 /* TODO: submit equivalent to TTM generic API upstream? */
116 static inline void __iomem *
117 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
127 NV_NFORCE = 0x10000000,
128 NV_NFORCE2 = 0x20000000
131 #define NVOBJ_ENGINE_SW 0
132 #define NVOBJ_ENGINE_GR 1
133 #define NVOBJ_ENGINE_DISPLAY 2
134 #define NVOBJ_ENGINE_INT 0xdeadbeef
136 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
137 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
138 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
139 #define NVOBJ_FLAG_FAKE (1 << 3)
140 struct nouveau_gpuobj {
141 struct list_head list;
143 struct nouveau_channel *im_channel;
144 struct drm_mm_node *im_pramin;
145 struct nouveau_bo *im_backing;
146 uint32_t im_backing_start;
147 uint32_t *im_backing_suspend;
156 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
160 struct nouveau_gpuobj_ref {
161 struct list_head list;
163 struct nouveau_gpuobj *gpuobj;
166 struct nouveau_channel *channel;
170 struct nouveau_channel {
171 struct drm_device *dev;
174 /* owner of this fifo */
175 struct drm_file *file_priv;
176 /* mapping of the fifo itself */
177 struct drm_local_map *map;
179 /* mapping of the regs controling the fifo */
186 /* lock protects the pending list only */
188 struct list_head pending;
190 uint32_t sequence_ack;
191 atomic_t last_sequence_irq;
194 /* DMA push buffer */
195 struct nouveau_gpuobj_ref *pushbuf;
196 struct nouveau_bo *pushbuf_bo;
197 uint32_t pushbuf_base;
199 /* Notifier memory */
200 struct nouveau_bo *notifier_bo;
201 struct drm_mm notifier_heap;
204 struct nouveau_gpuobj_ref *ramfc;
205 struct nouveau_gpuobj_ref *cache;
208 /* XXX may be merge 2 pointers as private data ??? */
209 struct nouveau_gpuobj_ref *ramin_grctx;
213 struct nouveau_gpuobj *vm_pd;
214 struct nouveau_gpuobj_ref *vm_gart_pt;
215 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
218 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
219 struct drm_mm ramin_heap; /* Private PRAMIN heap */
220 struct nouveau_gpuobj_ref *ramht; /* Hash table */
221 struct list_head ramht_refs; /* Objects referenced by RAMHT */
223 /* GPU object info for stuff used in-kernel (mm_enabled) */
225 uint32_t vram_handle;
226 uint32_t gart_handle;
229 /* Push buffer state (only for drm's channel on !mm_enabled) */
235 /* access via pushbuf_bo */
243 uint32_t sw_subchannel[8];
246 struct nouveau_gpuobj *vblsem;
247 uint32_t vblsem_offset;
248 uint32_t vblsem_rval;
249 struct list_head vbl_wait;
255 struct drm_info_list info;
259 struct nouveau_instmem_engine {
262 int (*init)(struct drm_device *dev);
263 void (*takedown)(struct drm_device *dev);
264 int (*suspend)(struct drm_device *dev);
265 void (*resume)(struct drm_device *dev);
267 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
272 void (*flush)(struct drm_device *);
275 struct nouveau_mc_engine {
276 int (*init)(struct drm_device *dev);
277 void (*takedown)(struct drm_device *dev);
280 struct nouveau_timer_engine {
281 int (*init)(struct drm_device *dev);
282 void (*takedown)(struct drm_device *dev);
283 uint64_t (*read)(struct drm_device *dev);
286 struct nouveau_fb_engine {
289 int (*init)(struct drm_device *dev);
290 void (*takedown)(struct drm_device *dev);
292 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
293 uint32_t size, uint32_t pitch);
296 struct nouveau_fifo_engine {
299 struct nouveau_gpuobj_ref *playlist[2];
302 int (*init)(struct drm_device *);
303 void (*takedown)(struct drm_device *);
305 void (*disable)(struct drm_device *);
306 void (*enable)(struct drm_device *);
307 bool (*reassign)(struct drm_device *, bool enable);
308 bool (*cache_flush)(struct drm_device *dev);
309 bool (*cache_pull)(struct drm_device *dev, bool enable);
311 int (*channel_id)(struct drm_device *);
313 int (*create_context)(struct nouveau_channel *);
314 void (*destroy_context)(struct nouveau_channel *);
315 int (*load_context)(struct nouveau_channel *);
316 int (*unload_context)(struct drm_device *);
319 struct nouveau_pgraph_object_method {
321 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
325 struct nouveau_pgraph_object_class {
328 struct nouveau_pgraph_object_method *methods;
331 struct nouveau_pgraph_engine {
332 struct nouveau_pgraph_object_class *grclass;
336 /* NV2x/NV3x context table (0x400780) */
337 struct nouveau_gpuobj_ref *ctx_table;
339 int (*init)(struct drm_device *);
340 void (*takedown)(struct drm_device *);
342 void (*fifo_access)(struct drm_device *, bool);
344 struct nouveau_channel *(*channel)(struct drm_device *);
345 int (*create_context)(struct nouveau_channel *);
346 void (*destroy_context)(struct nouveau_channel *);
347 int (*load_context)(struct nouveau_channel *);
348 int (*unload_context)(struct drm_device *);
350 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
351 uint32_t size, uint32_t pitch);
354 struct nouveau_display_engine {
355 int (*early_init)(struct drm_device *);
356 void (*late_takedown)(struct drm_device *);
357 int (*create)(struct drm_device *);
358 int (*init)(struct drm_device *);
359 void (*destroy)(struct drm_device *);
362 struct nouveau_gpio_engine {
363 int (*init)(struct drm_device *);
364 void (*takedown)(struct drm_device *);
366 int (*get)(struct drm_device *, enum dcb_gpio_tag);
367 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
369 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
372 struct nouveau_engine {
373 struct nouveau_instmem_engine instmem;
374 struct nouveau_mc_engine mc;
375 struct nouveau_timer_engine timer;
376 struct nouveau_fb_engine fb;
377 struct nouveau_pgraph_engine graph;
378 struct nouveau_fifo_engine fifo;
379 struct nouveau_display_engine display;
380 struct nouveau_gpio_engine gpio;
383 struct nouveau_pll_vals {
387 uint8_t N1, M1, N2, M2;
389 uint8_t M1, N1, M2, N2;
394 } __attribute__((packed));
401 enum nv04_fp_display_regs {
411 struct nv04_crtc_reg {
412 unsigned char MiscOutReg; /* */
415 uint8_t Sequencer[5];
417 uint8_t Attribute[21];
418 unsigned char DAC[768]; /* Internal Colorlookuptable */
428 uint32_t crtc_eng_ctrl;
431 uint32_t nv10_cursync;
432 struct nouveau_pll_vals pllvals;
433 uint32_t ramdac_gen_ctrl;
439 uint32_t tv_vsync_delay;
442 uint32_t tv_hsync_delay;
443 uint32_t tv_hsync_delay2;
444 uint32_t fp_horiz_regs[7];
445 uint32_t fp_vert_regs[7];
448 uint32_t dither_regs[6];
452 uint32_t fp_margin_color;
457 uint32_t ctv_regs[38];
460 struct nv04_output_reg {
465 struct nv04_mode_state {
493 uint32_t cursorConfig;
502 struct nv04_crtc_reg crtc_reg[2];
505 enum nouveau_card_type {
514 struct drm_nouveau_private {
515 struct drm_device *dev;
517 /* the card type, takes NV_* as values */
518 enum nouveau_card_type card_type;
519 /* exact chipset, derived from NV_PMC_BOOT_0 */
527 struct nouveau_bo *vga_ram;
529 struct workqueue_struct *wq;
530 struct work_struct irq_work;
531 struct work_struct hpd_work;
533 struct list_head vbl_waiting;
536 struct drm_global_reference mem_global_ref;
537 struct ttm_bo_global_ref bo_global_ref;
538 struct ttm_bo_device bdev;
539 spinlock_t bo_list_lock;
540 struct list_head bo_list;
541 atomic_t validate_sequence;
544 int fifo_alloc_count;
545 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
547 struct nouveau_engine engine;
548 struct nouveau_channel *channel;
550 /* For PFIFO and PGRAPH. */
551 spinlock_t context_switch_lock;
553 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
554 struct nouveau_gpuobj *ramht;
555 uint32_t ramin_rsvd_vram;
556 uint32_t ramht_offset;
559 uint32_t ramfc_offset;
561 uint32_t ramro_offset;
566 NOUVEAU_GART_NONE = 0,
574 struct nouveau_gpuobj *sg_ctxdma;
575 struct page *sg_dummy_page;
576 dma_addr_t sg_dummy_bus;
579 /* nv10-nv40 tiling regions */
581 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
585 /* VRAM/fb configuration */
587 uint64_t vram_sys_base;
590 uint64_t fb_available_size;
591 uint64_t fb_mappable_pages;
592 uint64_t fb_aper_free;
595 /* G8x/G9x virtual address space */
596 uint64_t vm_gart_base;
597 uint64_t vm_gart_size;
598 uint64_t vm_vram_base;
599 uint64_t vm_vram_size;
601 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
604 struct drm_mm ramin_heap;
606 struct list_head gpuobj_list;
610 struct nv04_mode_state mode_reg;
611 struct nv04_mode_state saved_reg;
612 uint32_t saved_vga_font[4][16384];
614 uint32_t dac_users[4];
616 struct nouveau_suspend_resume {
617 uint32_t *ramin_copy;
620 struct backlight_device *backlight;
622 struct nouveau_channel *evo;
624 struct dcb_entry *dcb;
630 struct dentry *channel_root;
633 struct nouveau_fbdev *nfbdev;
634 struct apertures_struct *apertures;
637 static inline struct drm_nouveau_private *
638 nouveau_bdev(struct ttm_bo_device *bd)
640 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
644 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
646 struct nouveau_bo *prev;
652 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
654 struct ttm_buffer_object *bo = &prev->bo;
662 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
663 struct drm_nouveau_private *nv = dev->dev_private; \
664 if (!nouveau_channel_owner(dev, (cl), (id))) { \
665 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
666 DRM_CURRENTPID, (id)); \
669 (ch) = nv->fifos[(id)]; \
673 extern int nouveau_noagp;
674 extern int nouveau_duallink;
675 extern int nouveau_uscript_lvds;
676 extern int nouveau_uscript_tmds;
677 extern int nouveau_vram_pushbuf;
678 extern int nouveau_vram_notify;
679 extern int nouveau_fbpercrtc;
680 extern int nouveau_tv_disable;
681 extern char *nouveau_tv_norm;
682 extern int nouveau_reg_debug;
683 extern char *nouveau_vbios;
684 extern int nouveau_ignorelid;
685 extern int nouveau_nofbaccel;
686 extern int nouveau_noaccel;
687 extern int nouveau_override_conntype;
689 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
690 extern int nouveau_pci_resume(struct pci_dev *pdev);
692 /* nouveau_state.c */
693 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
694 extern int nouveau_load(struct drm_device *, unsigned long flags);
695 extern int nouveau_firstopen(struct drm_device *);
696 extern void nouveau_lastclose(struct drm_device *);
697 extern int nouveau_unload(struct drm_device *);
698 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
700 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
702 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
703 uint32_t reg, uint32_t mask, uint32_t val);
704 extern bool nouveau_wait_for_idle(struct drm_device *);
705 extern int nouveau_card_init(struct drm_device *);
708 extern int nouveau_mem_detect(struct drm_device *dev);
709 extern int nouveau_mem_init(struct drm_device *);
710 extern int nouveau_mem_init_agp(struct drm_device *);
711 extern int nouveau_mem_reset_agp(struct drm_device *);
712 extern void nouveau_mem_close(struct drm_device *);
713 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
717 extern void nv10_mem_expire_tiling(struct drm_device *dev,
718 struct nouveau_tile_reg *tile,
719 struct nouveau_fence *fence);
720 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
721 uint32_t size, uint32_t flags,
723 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
726 /* nouveau_notifier.c */
727 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
728 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
729 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
730 int cout, uint32_t *offset);
731 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
732 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
734 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
737 /* nouveau_channel.c */
738 extern struct drm_ioctl_desc nouveau_ioctls[];
739 extern int nouveau_max_ioctl;
740 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
741 extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
743 extern int nouveau_channel_alloc(struct drm_device *dev,
744 struct nouveau_channel **chan,
745 struct drm_file *file_priv,
746 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
747 extern void nouveau_channel_free(struct nouveau_channel *);
749 /* nouveau_object.c */
750 extern int nouveau_gpuobj_early_init(struct drm_device *);
751 extern int nouveau_gpuobj_init(struct drm_device *);
752 extern void nouveau_gpuobj_takedown(struct drm_device *);
753 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
754 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
755 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
756 extern void nouveau_gpuobj_resume(struct drm_device *dev);
757 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
758 uint32_t vram_h, uint32_t tt_h);
759 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
760 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
761 uint32_t size, int align, uint32_t flags,
762 struct nouveau_gpuobj **);
763 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
764 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
765 uint32_t handle, struct nouveau_gpuobj *,
766 struct nouveau_gpuobj_ref **);
767 extern int nouveau_gpuobj_ref_del(struct drm_device *,
768 struct nouveau_gpuobj_ref **);
769 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
770 struct nouveau_gpuobj_ref **ref_ret);
771 extern int nouveau_gpuobj_new_ref(struct drm_device *,
772 struct nouveau_channel *alloc_chan,
773 struct nouveau_channel *ref_chan,
774 uint32_t handle, uint32_t size, int align,
775 uint32_t flags, struct nouveau_gpuobj_ref **);
776 extern int nouveau_gpuobj_new_fake(struct drm_device *,
777 uint32_t p_offset, uint32_t b_offset,
778 uint32_t size, uint32_t flags,
779 struct nouveau_gpuobj **,
780 struct nouveau_gpuobj_ref**);
781 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
782 uint64_t offset, uint64_t size, int access,
783 int target, struct nouveau_gpuobj **);
784 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
785 uint64_t offset, uint64_t size,
786 int access, struct nouveau_gpuobj **,
788 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
789 struct nouveau_gpuobj **);
790 extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
791 struct nouveau_gpuobj **);
792 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
794 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
798 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
799 extern void nouveau_irq_preinstall(struct drm_device *);
800 extern int nouveau_irq_postinstall(struct drm_device *);
801 extern void nouveau_irq_uninstall(struct drm_device *);
803 /* nouveau_sgdma.c */
804 extern int nouveau_sgdma_init(struct drm_device *);
805 extern void nouveau_sgdma_takedown(struct drm_device *);
806 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
808 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
810 /* nouveau_debugfs.c */
811 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
812 extern int nouveau_debugfs_init(struct drm_minor *);
813 extern void nouveau_debugfs_takedown(struct drm_minor *);
814 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
815 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
818 nouveau_debugfs_init(struct drm_minor *minor)
823 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
828 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
834 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
840 extern void nouveau_dma_pre_init(struct nouveau_channel *);
841 extern int nouveau_dma_init(struct nouveau_channel *);
842 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
845 #define ROM_BIOS_PAGE 4096
846 #if defined(CONFIG_ACPI)
847 void nouveau_register_dsm_handler(void);
848 void nouveau_unregister_dsm_handler(void);
849 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
850 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
851 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
853 static inline void nouveau_register_dsm_handler(void) {}
854 static inline void nouveau_unregister_dsm_handler(void) {}
855 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
856 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
857 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
860 /* nouveau_backlight.c */
861 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
862 extern int nouveau_backlight_init(struct drm_device *);
863 extern void nouveau_backlight_exit(struct drm_device *);
865 static inline int nouveau_backlight_init(struct drm_device *dev)
870 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
874 extern int nouveau_bios_init(struct drm_device *);
875 extern void nouveau_bios_takedown(struct drm_device *dev);
876 extern int nouveau_run_vbios_init(struct drm_device *);
877 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
879 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
881 extern struct dcb_connector_table_entry *
882 nouveau_bios_connector_entry(struct drm_device *, int index);
883 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
885 extern int nouveau_bios_run_display_table(struct drm_device *,
887 uint32_t script, int pxclk);
888 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
890 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
891 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
892 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
893 bool *dl, bool *if_is_24bit);
894 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
895 int head, int pxclk);
896 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
897 enum LVDS_script, int pxclk);
900 int nouveau_ttm_global_init(struct drm_nouveau_private *);
901 void nouveau_ttm_global_release(struct drm_nouveau_private *);
902 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
905 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
906 uint8_t *data, int data_nr);
907 bool nouveau_dp_detect(struct drm_encoder *);
908 bool nouveau_dp_link_train(struct drm_encoder *);
911 extern int nv04_fb_init(struct drm_device *);
912 extern void nv04_fb_takedown(struct drm_device *);
915 extern int nv10_fb_init(struct drm_device *);
916 extern void nv10_fb_takedown(struct drm_device *);
917 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
921 extern int nv30_fb_init(struct drm_device *);
922 extern void nv30_fb_takedown(struct drm_device *);
925 extern int nv40_fb_init(struct drm_device *);
926 extern void nv40_fb_takedown(struct drm_device *);
927 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
931 extern int nv50_fb_init(struct drm_device *);
932 extern void nv50_fb_takedown(struct drm_device *);
935 extern int nv04_fifo_init(struct drm_device *);
936 extern void nv04_fifo_disable(struct drm_device *);
937 extern void nv04_fifo_enable(struct drm_device *);
938 extern bool nv04_fifo_reassign(struct drm_device *, bool);
939 extern bool nv04_fifo_cache_flush(struct drm_device *);
940 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
941 extern int nv04_fifo_channel_id(struct drm_device *);
942 extern int nv04_fifo_create_context(struct nouveau_channel *);
943 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
944 extern int nv04_fifo_load_context(struct nouveau_channel *);
945 extern int nv04_fifo_unload_context(struct drm_device *);
948 extern int nv10_fifo_init(struct drm_device *);
949 extern int nv10_fifo_channel_id(struct drm_device *);
950 extern int nv10_fifo_create_context(struct nouveau_channel *);
951 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
952 extern int nv10_fifo_load_context(struct nouveau_channel *);
953 extern int nv10_fifo_unload_context(struct drm_device *);
956 extern int nv40_fifo_init(struct drm_device *);
957 extern int nv40_fifo_create_context(struct nouveau_channel *);
958 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
959 extern int nv40_fifo_load_context(struct nouveau_channel *);
960 extern int nv40_fifo_unload_context(struct drm_device *);
963 extern int nv50_fifo_init(struct drm_device *);
964 extern void nv50_fifo_takedown(struct drm_device *);
965 extern int nv50_fifo_channel_id(struct drm_device *);
966 extern int nv50_fifo_create_context(struct nouveau_channel *);
967 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
968 extern int nv50_fifo_load_context(struct nouveau_channel *);
969 extern int nv50_fifo_unload_context(struct drm_device *);
972 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
973 extern int nv04_graph_init(struct drm_device *);
974 extern void nv04_graph_takedown(struct drm_device *);
975 extern void nv04_graph_fifo_access(struct drm_device *, bool);
976 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
977 extern int nv04_graph_create_context(struct nouveau_channel *);
978 extern void nv04_graph_destroy_context(struct nouveau_channel *);
979 extern int nv04_graph_load_context(struct nouveau_channel *);
980 extern int nv04_graph_unload_context(struct drm_device *);
981 extern void nv04_graph_context_switch(struct drm_device *);
984 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
985 extern int nv10_graph_init(struct drm_device *);
986 extern void nv10_graph_takedown(struct drm_device *);
987 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
988 extern int nv10_graph_create_context(struct nouveau_channel *);
989 extern void nv10_graph_destroy_context(struct nouveau_channel *);
990 extern int nv10_graph_load_context(struct nouveau_channel *);
991 extern int nv10_graph_unload_context(struct drm_device *);
992 extern void nv10_graph_context_switch(struct drm_device *);
993 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
997 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
998 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
999 extern int nv20_graph_create_context(struct nouveau_channel *);
1000 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1001 extern int nv20_graph_load_context(struct nouveau_channel *);
1002 extern int nv20_graph_unload_context(struct drm_device *);
1003 extern int nv20_graph_init(struct drm_device *);
1004 extern void nv20_graph_takedown(struct drm_device *);
1005 extern int nv30_graph_init(struct drm_device *);
1006 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1007 uint32_t, uint32_t);
1010 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1011 extern int nv40_graph_init(struct drm_device *);
1012 extern void nv40_graph_takedown(struct drm_device *);
1013 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1014 extern int nv40_graph_create_context(struct nouveau_channel *);
1015 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1016 extern int nv40_graph_load_context(struct nouveau_channel *);
1017 extern int nv40_graph_unload_context(struct drm_device *);
1018 extern void nv40_grctx_init(struct nouveau_grctx *);
1019 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1020 uint32_t, uint32_t);
1023 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1024 extern int nv50_graph_init(struct drm_device *);
1025 extern void nv50_graph_takedown(struct drm_device *);
1026 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1027 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1028 extern int nv50_graph_create_context(struct nouveau_channel *);
1029 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1030 extern int nv50_graph_load_context(struct nouveau_channel *);
1031 extern int nv50_graph_unload_context(struct drm_device *);
1032 extern void nv50_graph_context_switch(struct drm_device *);
1033 extern int nv50_grctx_init(struct nouveau_grctx *);
1035 /* nv04_instmem.c */
1036 extern int nv04_instmem_init(struct drm_device *);
1037 extern void nv04_instmem_takedown(struct drm_device *);
1038 extern int nv04_instmem_suspend(struct drm_device *);
1039 extern void nv04_instmem_resume(struct drm_device *);
1040 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1042 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1043 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1044 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1045 extern void nv04_instmem_flush(struct drm_device *);
1047 /* nv50_instmem.c */
1048 extern int nv50_instmem_init(struct drm_device *);
1049 extern void nv50_instmem_takedown(struct drm_device *);
1050 extern int nv50_instmem_suspend(struct drm_device *);
1051 extern void nv50_instmem_resume(struct drm_device *);
1052 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1054 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1055 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1056 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1057 extern void nv50_instmem_flush(struct drm_device *);
1058 extern void nv84_instmem_flush(struct drm_device *);
1059 extern void nv50_vm_flush(struct drm_device *, int engine);
1062 extern int nv04_mc_init(struct drm_device *);
1063 extern void nv04_mc_takedown(struct drm_device *);
1066 extern int nv40_mc_init(struct drm_device *);
1067 extern void nv40_mc_takedown(struct drm_device *);
1070 extern int nv50_mc_init(struct drm_device *);
1071 extern void nv50_mc_takedown(struct drm_device *);
1074 extern int nv04_timer_init(struct drm_device *);
1075 extern uint64_t nv04_timer_read(struct drm_device *);
1076 extern void nv04_timer_takedown(struct drm_device *);
1078 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1082 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1083 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1084 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1085 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1086 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1089 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1090 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1091 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1093 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1094 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1097 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1098 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1101 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1103 /* nv04_display.c */
1104 extern int nv04_display_early_init(struct drm_device *);
1105 extern void nv04_display_late_takedown(struct drm_device *);
1106 extern int nv04_display_create(struct drm_device *);
1107 extern int nv04_display_init(struct drm_device *);
1108 extern void nv04_display_destroy(struct drm_device *);
1111 extern int nv04_crtc_create(struct drm_device *, int index);
1114 extern struct ttm_bo_driver nouveau_bo_driver;
1115 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1116 int size, int align, uint32_t flags,
1117 uint32_t tile_mode, uint32_t tile_flags,
1118 bool no_vm, bool mappable, struct nouveau_bo **);
1119 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1120 extern int nouveau_bo_unpin(struct nouveau_bo *);
1121 extern int nouveau_bo_map(struct nouveau_bo *);
1122 extern void nouveau_bo_unmap(struct nouveau_bo *);
1123 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1125 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1126 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1127 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1128 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1130 /* nouveau_fence.c */
1131 struct nouveau_fence;
1132 extern int nouveau_fence_init(struct nouveau_channel *);
1133 extern void nouveau_fence_fini(struct nouveau_channel *);
1134 extern void nouveau_fence_update(struct nouveau_channel *);
1135 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1137 extern int nouveau_fence_emit(struct nouveau_fence *);
1138 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1139 extern bool nouveau_fence_signalled(void *obj, void *arg);
1140 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1141 extern int nouveau_fence_flush(void *obj, void *arg);
1142 extern void nouveau_fence_unref(void **obj);
1143 extern void *nouveau_fence_ref(void *obj);
1146 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1147 int size, int align, uint32_t flags,
1148 uint32_t tile_mode, uint32_t tile_flags,
1149 bool no_vm, bool mappable, struct nouveau_bo **);
1150 extern int nouveau_gem_object_new(struct drm_gem_object *);
1151 extern void nouveau_gem_object_del(struct drm_gem_object *);
1152 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1154 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1156 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1158 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1160 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1164 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1165 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1168 int nv50_gpio_init(struct drm_device *dev);
1169 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1170 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1171 void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1174 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1175 int *N1, int *M1, int *N2, int *M2, int *P);
1176 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1177 int clk, int *N, int *fN, int *M, int *P);
1179 #ifndef ioread32_native
1181 #define ioread16_native ioread16be
1182 #define iowrite16_native iowrite16be
1183 #define ioread32_native ioread32be
1184 #define iowrite32_native iowrite32be
1185 #else /* def __BIG_ENDIAN */
1186 #define ioread16_native ioread16
1187 #define iowrite16_native iowrite16
1188 #define ioread32_native ioread32
1189 #define iowrite32_native iowrite32
1190 #endif /* def __BIG_ENDIAN else */
1191 #endif /* !ioread32_native */
1193 /* channel control reg access */
1194 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1196 return ioread32_native(chan->user + reg);
1199 static inline void nvchan_wr32(struct nouveau_channel *chan,
1200 unsigned reg, u32 val)
1202 iowrite32_native(val, chan->user + reg);
1205 /* register access */
1206 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1208 struct drm_nouveau_private *dev_priv = dev->dev_private;
1209 return ioread32_native(dev_priv->mmio + reg);
1212 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1214 struct drm_nouveau_private *dev_priv = dev->dev_private;
1215 iowrite32_native(val, dev_priv->mmio + reg);
1218 static inline void nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1220 u32 tmp = nv_rd32(dev, reg);
1223 nv_wr32(dev, reg, tmp);
1226 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1228 struct drm_nouveau_private *dev_priv = dev->dev_private;
1229 return ioread8(dev_priv->mmio + reg);
1232 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1234 struct drm_nouveau_private *dev_priv = dev->dev_private;
1235 iowrite8(val, dev_priv->mmio + reg);
1238 #define nv_wait(reg, mask, val) \
1239 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1242 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1244 struct drm_nouveau_private *dev_priv = dev->dev_private;
1245 return ioread32_native(dev_priv->ramin + offset);
1248 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1250 struct drm_nouveau_private *dev_priv = dev->dev_private;
1251 iowrite32_native(val, dev_priv->ramin + offset);
1255 static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1258 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1261 static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1262 unsigned index, u32 val)
1264 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1269 * Argument d is (struct drm_device *).
1271 #define NV_PRINTK(level, d, fmt, arg...) \
1272 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1273 pci_name(d->pdev), ##arg)
1274 #ifndef NV_DEBUG_NOTRACE
1275 #define NV_DEBUG(d, fmt, arg...) do { \
1276 if (drm_debug & DRM_UT_DRIVER) { \
1277 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1281 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1282 if (drm_debug & DRM_UT_KMS) { \
1283 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1288 #define NV_DEBUG(d, fmt, arg...) do { \
1289 if (drm_debug & DRM_UT_DRIVER) \
1290 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1292 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1293 if (drm_debug & DRM_UT_KMS) \
1294 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1297 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1298 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1299 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1300 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1301 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1303 /* nouveau_reg_debug bitmask */
1305 NOUVEAU_REG_DEBUG_MC = 0x1,
1306 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1307 NOUVEAU_REG_DEBUG_FB = 0x4,
1308 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1309 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1310 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1311 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1312 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1313 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1314 NOUVEAU_REG_DEBUG_EVO = 0x200,
1317 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1318 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1319 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1323 nv_two_heads(struct drm_device *dev)
1325 struct drm_nouveau_private *dev_priv = dev->dev_private;
1326 const int impl = dev->pci_device & 0x0ff0;
1328 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1329 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1336 nv_gf4_disp_arch(struct drm_device *dev)
1338 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1342 nv_two_reg_pll(struct drm_device *dev)
1344 struct drm_nouveau_private *dev_priv = dev->dev_private;
1345 const int impl = dev->pci_device & 0x0ff0;
1347 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1352 #define NV_SW 0x0000506e
1353 #define NV_SW_DMA_SEMAPHORE 0x00000060
1354 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1355 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1356 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1357 #define NV_SW_DMA_VBLSEM 0x0000018c
1358 #define NV_SW_VBLSEM_OFFSET 0x00000400
1359 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1360 #define NV_SW_VBLSEM_RELEASE 0x00000408
1362 #endif /* __NOUVEAU_DRV_H__ */