2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
59 #define MAX_NUM_DCB_ENTRIES 16
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
79 u32 busy_placements[3];
80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
89 struct nouveau_channel *channel;
96 struct nouveau_tile_reg *tile;
98 struct drm_gem_object *gem;
102 #define nouveau_bo_tile_layout(nvbo) \
103 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
105 static inline struct nouveau_bo *
106 nouveau_bo(struct ttm_buffer_object *bo)
108 return container_of(bo, struct nouveau_bo, bo);
111 static inline struct nouveau_bo *
112 nouveau_gem_object(struct drm_gem_object *gem)
114 return gem ? gem->driver_private : NULL;
117 /* TODO: submit equivalent to TTM generic API upstream? */
118 static inline void __iomem *
119 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
122 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
123 &nvbo->kmap, &is_iomem);
124 WARN_ON_ONCE(ioptr && !is_iomem);
129 NV_NFORCE = 0x10000000,
130 NV_NFORCE2 = 0x20000000
133 #define NVOBJ_ENGINE_SW 0
134 #define NVOBJ_ENGINE_GR 1
135 #define NVOBJ_ENGINE_DISPLAY 2
136 #define NVOBJ_ENGINE_INT 0xdeadbeef
138 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
139 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
140 struct nouveau_gpuobj {
141 struct drm_device *dev;
142 struct kref refcount;
143 struct list_head list;
145 struct drm_mm_node *im_pramin;
146 struct nouveau_bo *im_backing;
147 uint32_t *im_backing_suspend;
160 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
164 struct nouveau_channel {
165 struct drm_device *dev;
168 /* references to the channel data structure */
170 /* users of the hardware channel resources, the hardware
171 * context will be kicked off when it reaches zero. */
175 /* owner of this fifo */
176 struct drm_file *file_priv;
177 /* mapping of the fifo itself */
178 struct drm_local_map *map;
180 /* mapping of the regs controling the fifo */
187 /* lock protects the pending list only */
189 struct list_head pending;
191 uint32_t sequence_ack;
192 atomic_t last_sequence_irq;
195 /* DMA push buffer */
196 struct nouveau_gpuobj *pushbuf;
197 struct nouveau_bo *pushbuf_bo;
198 uint32_t pushbuf_base;
200 /* Notifier memory */
201 struct nouveau_bo *notifier_bo;
202 struct drm_mm notifier_heap;
205 struct nouveau_gpuobj *ramfc;
206 struct nouveau_gpuobj *cache;
209 /* XXX may be merge 2 pointers as private data ??? */
210 struct nouveau_gpuobj *ramin_grctx;
214 struct nouveau_gpuobj *vm_pd;
215 struct nouveau_gpuobj *vm_gart_pt;
216 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
219 struct nouveau_gpuobj *ramin; /* Private instmem */
220 struct drm_mm ramin_heap; /* Private PRAMIN heap */
221 struct nouveau_ramht *ramht; /* Hash table */
223 /* GPU object info for stuff used in-kernel (mm_enabled) */
225 uint32_t vram_handle;
226 uint32_t gart_handle;
229 /* Push buffer state (only for drm's channel on !mm_enabled) */
235 /* access via pushbuf_bo */
243 uint32_t sw_subchannel[8];
246 struct nouveau_gpuobj *vblsem;
247 uint32_t vblsem_offset;
248 uint32_t vblsem_rval;
249 struct list_head vbl_wait;
255 struct drm_info_list info;
259 struct nouveau_instmem_engine {
262 int (*init)(struct drm_device *dev);
263 void (*takedown)(struct drm_device *dev);
264 int (*suspend)(struct drm_device *dev);
265 void (*resume)(struct drm_device *dev);
267 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
272 void (*flush)(struct drm_device *);
275 struct nouveau_mc_engine {
276 int (*init)(struct drm_device *dev);
277 void (*takedown)(struct drm_device *dev);
280 struct nouveau_timer_engine {
281 int (*init)(struct drm_device *dev);
282 void (*takedown)(struct drm_device *dev);
283 uint64_t (*read)(struct drm_device *dev);
286 struct nouveau_fb_engine {
289 int (*init)(struct drm_device *dev);
290 void (*takedown)(struct drm_device *dev);
292 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
293 uint32_t size, uint32_t pitch);
296 struct nouveau_fifo_engine {
299 struct nouveau_gpuobj *playlist[2];
302 int (*init)(struct drm_device *);
303 void (*takedown)(struct drm_device *);
305 void (*disable)(struct drm_device *);
306 void (*enable)(struct drm_device *);
307 bool (*reassign)(struct drm_device *, bool enable);
308 bool (*cache_pull)(struct drm_device *dev, bool enable);
310 int (*channel_id)(struct drm_device *);
312 int (*create_context)(struct nouveau_channel *);
313 void (*destroy_context)(struct nouveau_channel *);
314 int (*load_context)(struct nouveau_channel *);
315 int (*unload_context)(struct drm_device *);
316 void (*tlb_flush)(struct drm_device *dev);
319 struct nouveau_pgraph_object_method {
321 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
325 struct nouveau_pgraph_object_class {
328 struct nouveau_pgraph_object_method *methods;
331 struct nouveau_pgraph_engine {
332 struct nouveau_pgraph_object_class *grclass;
336 /* NV2x/NV3x context table (0x400780) */
337 struct nouveau_gpuobj *ctx_table;
339 int (*init)(struct drm_device *);
340 void (*takedown)(struct drm_device *);
342 void (*fifo_access)(struct drm_device *, bool);
344 struct nouveau_channel *(*channel)(struct drm_device *);
345 int (*create_context)(struct nouveau_channel *);
346 void (*destroy_context)(struct nouveau_channel *);
347 int (*load_context)(struct nouveau_channel *);
348 int (*unload_context)(struct drm_device *);
349 void (*tlb_flush)(struct drm_device *dev);
351 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
352 uint32_t size, uint32_t pitch);
355 struct nouveau_display_engine {
356 int (*early_init)(struct drm_device *);
357 void (*late_takedown)(struct drm_device *);
358 int (*create)(struct drm_device *);
359 int (*init)(struct drm_device *);
360 void (*destroy)(struct drm_device *);
363 struct nouveau_gpio_engine {
364 int (*init)(struct drm_device *);
365 void (*takedown)(struct drm_device *);
367 int (*get)(struct drm_device *, enum dcb_gpio_tag);
368 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
370 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
373 struct nouveau_pm_voltage_level {
378 struct nouveau_pm_voltage {
382 struct nouveau_pm_voltage_level *level;
386 #define NOUVEAU_PM_MAX_LEVEL 8
387 struct nouveau_pm_level {
388 struct device_attribute dev_attr;
403 struct nouveau_pm_temp_sensor_constants {
411 struct nouveau_pm_threshold_temp {
417 struct nouveau_pm_memtiming {
428 struct nouveau_pm_memtimings {
430 struct nouveau_pm_memtiming *timing;
434 struct nouveau_pm_engine {
435 struct nouveau_pm_voltage voltage;
436 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
438 struct nouveau_pm_memtimings memtimings;
439 struct nouveau_pm_temp_sensor_constants sensor_constants;
440 struct nouveau_pm_threshold_temp threshold_temp;
442 struct nouveau_pm_level boot;
443 struct nouveau_pm_level *cur;
445 struct device *hwmon;
446 struct notifier_block acpi_nb;
448 int (*clock_get)(struct drm_device *, u32 id);
449 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
451 void (*clock_set)(struct drm_device *, void *);
452 int (*voltage_get)(struct drm_device *);
453 int (*voltage_set)(struct drm_device *, int voltage);
454 int (*fanspeed_get)(struct drm_device *);
455 int (*fanspeed_set)(struct drm_device *, int fanspeed);
456 int (*temp_get)(struct drm_device *);
459 struct nouveau_engine {
460 struct nouveau_instmem_engine instmem;
461 struct nouveau_mc_engine mc;
462 struct nouveau_timer_engine timer;
463 struct nouveau_fb_engine fb;
464 struct nouveau_pgraph_engine graph;
465 struct nouveau_fifo_engine fifo;
466 struct nouveau_display_engine display;
467 struct nouveau_gpio_engine gpio;
468 struct nouveau_pm_engine pm;
471 struct nouveau_pll_vals {
475 uint8_t N1, M1, N2, M2;
477 uint8_t M1, N1, M2, N2;
482 } __attribute__((packed));
489 enum nv04_fp_display_regs {
499 struct nv04_crtc_reg {
500 unsigned char MiscOutReg;
503 uint8_t Sequencer[5];
505 uint8_t Attribute[21];
506 unsigned char DAC[768];
516 uint32_t crtc_eng_ctrl;
519 uint32_t nv10_cursync;
520 struct nouveau_pll_vals pllvals;
521 uint32_t ramdac_gen_ctrl;
527 uint32_t tv_vsync_delay;
530 uint32_t tv_hsync_delay;
531 uint32_t tv_hsync_delay2;
532 uint32_t fp_horiz_regs[7];
533 uint32_t fp_vert_regs[7];
536 uint32_t dither_regs[6];
540 uint32_t fp_margin_color;
545 uint32_t ctv_regs[38];
548 struct nv04_output_reg {
553 struct nv04_mode_state {
554 struct nv04_crtc_reg crtc_reg[2];
559 enum nouveau_card_type {
569 struct drm_nouveau_private {
570 struct drm_device *dev;
572 /* the card type, takes NV_* as values */
573 enum nouveau_card_type card_type;
574 /* exact chipset, derived from NV_PMC_BOOT_0 */
580 spinlock_t ramin_lock;
584 bool ramin_available;
585 struct drm_mm ramin_heap;
586 struct list_head gpuobj_list;
588 struct nouveau_bo *vga_ram;
590 struct workqueue_struct *wq;
591 struct work_struct irq_work;
592 struct work_struct hpd_work;
600 struct list_head vbl_waiting;
603 struct drm_global_reference mem_global_ref;
604 struct ttm_bo_global_ref bo_global_ref;
605 struct ttm_bo_device bdev;
606 atomic_t validate_sequence;
612 struct nouveau_bo *bo;
617 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
620 struct nouveau_engine engine;
621 struct nouveau_channel *channel;
623 /* For PFIFO and PGRAPH. */
624 spinlock_t context_switch_lock;
626 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
627 struct nouveau_ramht *ramht;
628 struct nouveau_gpuobj *ramfc;
629 struct nouveau_gpuobj *ramro;
631 uint32_t ramin_rsvd_vram;
635 NOUVEAU_GART_NONE = 0,
643 struct nouveau_gpuobj *sg_ctxdma;
644 struct page *sg_dummy_page;
645 dma_addr_t sg_dummy_bus;
648 /* nv10-nv40 tiling regions */
649 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
651 /* VRAM/fb configuration */
653 uint64_t vram_sys_base;
654 u32 vram_rblock_size;
657 uint64_t fb_available_size;
658 uint64_t fb_mappable_pages;
659 uint64_t fb_aper_free;
662 /* G8x/G9x virtual address space */
663 uint64_t vm_gart_base;
664 uint64_t vm_gart_size;
665 uint64_t vm_vram_base;
666 uint64_t vm_vram_size;
668 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
673 struct nv04_mode_state mode_reg;
674 struct nv04_mode_state saved_reg;
675 uint32_t saved_vga_font[4][16384];
677 uint32_t dac_users[4];
679 struct nouveau_suspend_resume {
680 uint32_t *ramin_copy;
683 struct backlight_device *backlight;
685 struct nouveau_channel *evo;
687 struct dcb_entry *dcb;
693 struct dentry *channel_root;
696 struct nouveau_fbdev *nfbdev;
697 struct apertures_struct *apertures;
700 static inline struct drm_nouveau_private *
701 nouveau_private(struct drm_device *dev)
703 return dev->dev_private;
706 static inline struct drm_nouveau_private *
707 nouveau_bdev(struct ttm_bo_device *bd)
709 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
713 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
715 struct nouveau_bo *prev;
721 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
723 struct ttm_buffer_object *bo = &prev->bo;
732 extern int nouveau_agpmode;
733 extern int nouveau_duallink;
734 extern int nouveau_uscript_lvds;
735 extern int nouveau_uscript_tmds;
736 extern int nouveau_vram_pushbuf;
737 extern int nouveau_vram_notify;
738 extern int nouveau_fbpercrtc;
739 extern int nouveau_tv_disable;
740 extern char *nouveau_tv_norm;
741 extern int nouveau_reg_debug;
742 extern char *nouveau_vbios;
743 extern int nouveau_ignorelid;
744 extern int nouveau_nofbaccel;
745 extern int nouveau_noaccel;
746 extern int nouveau_force_post;
747 extern int nouveau_override_conntype;
748 extern char *nouveau_perflvl;
749 extern int nouveau_perflvl_wr;
751 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
752 extern int nouveau_pci_resume(struct pci_dev *pdev);
754 /* nouveau_state.c */
755 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
756 extern int nouveau_load(struct drm_device *, unsigned long flags);
757 extern int nouveau_firstopen(struct drm_device *);
758 extern void nouveau_lastclose(struct drm_device *);
759 extern int nouveau_unload(struct drm_device *);
760 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
762 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
764 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
765 uint32_t reg, uint32_t mask, uint32_t val);
766 extern bool nouveau_wait_for_idle(struct drm_device *);
767 extern int nouveau_card_init(struct drm_device *);
770 extern int nouveau_mem_vram_init(struct drm_device *);
771 extern void nouveau_mem_vram_fini(struct drm_device *);
772 extern int nouveau_mem_gart_init(struct drm_device *);
773 extern void nouveau_mem_gart_fini(struct drm_device *);
774 extern int nouveau_mem_init_agp(struct drm_device *);
775 extern int nouveau_mem_reset_agp(struct drm_device *);
776 extern void nouveau_mem_close(struct drm_device *);
777 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
781 extern void nv10_mem_expire_tiling(struct drm_device *dev,
782 struct nouveau_tile_reg *tile,
783 struct nouveau_fence *fence);
784 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
785 uint32_t size, uint32_t flags,
787 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
790 /* nouveau_notifier.c */
791 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
792 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
793 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
794 int cout, uint32_t *offset);
795 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
796 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
798 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
801 /* nouveau_channel.c */
802 extern struct drm_ioctl_desc nouveau_ioctls[];
803 extern int nouveau_max_ioctl;
804 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
805 extern int nouveau_channel_alloc(struct drm_device *dev,
806 struct nouveau_channel **chan,
807 struct drm_file *file_priv,
808 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
809 extern struct nouveau_channel *
810 nouveau_channel_get_unlocked(struct nouveau_channel *);
811 extern struct nouveau_channel *
812 nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
813 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
814 extern void nouveau_channel_put(struct nouveau_channel **);
815 extern void nouveau_channel_ref(struct nouveau_channel *chan,
816 struct nouveau_channel **pchan);
818 /* nouveau_object.c */
819 extern int nouveau_gpuobj_early_init(struct drm_device *);
820 extern int nouveau_gpuobj_init(struct drm_device *);
821 extern void nouveau_gpuobj_takedown(struct drm_device *);
822 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
823 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
824 extern void nouveau_gpuobj_resume(struct drm_device *dev);
825 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
826 uint32_t vram_h, uint32_t tt_h);
827 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
828 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
829 uint32_t size, int align, uint32_t flags,
830 struct nouveau_gpuobj **);
831 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
832 struct nouveau_gpuobj **);
833 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
835 struct nouveau_gpuobj **);
836 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
837 uint64_t offset, uint64_t size, int access,
838 int target, struct nouveau_gpuobj **);
839 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
840 uint64_t offset, uint64_t size,
841 int access, struct nouveau_gpuobj **,
843 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
844 struct nouveau_gpuobj **);
845 extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
846 struct nouveau_gpuobj **);
847 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
849 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
853 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
854 extern void nouveau_irq_preinstall(struct drm_device *);
855 extern int nouveau_irq_postinstall(struct drm_device *);
856 extern void nouveau_irq_uninstall(struct drm_device *);
858 /* nouveau_sgdma.c */
859 extern int nouveau_sgdma_init(struct drm_device *);
860 extern void nouveau_sgdma_takedown(struct drm_device *);
861 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
863 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
865 /* nouveau_debugfs.c */
866 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
867 extern int nouveau_debugfs_init(struct drm_minor *);
868 extern void nouveau_debugfs_takedown(struct drm_minor *);
869 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
870 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
873 nouveau_debugfs_init(struct drm_minor *minor)
878 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
883 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
889 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
895 extern void nouveau_dma_pre_init(struct nouveau_channel *);
896 extern int nouveau_dma_init(struct nouveau_channel *);
897 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
900 #define ROM_BIOS_PAGE 4096
901 #if defined(CONFIG_ACPI)
902 void nouveau_register_dsm_handler(void);
903 void nouveau_unregister_dsm_handler(void);
904 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
905 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
906 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
908 static inline void nouveau_register_dsm_handler(void) {}
909 static inline void nouveau_unregister_dsm_handler(void) {}
910 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
911 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
912 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
915 /* nouveau_backlight.c */
916 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
917 extern int nouveau_backlight_init(struct drm_device *);
918 extern void nouveau_backlight_exit(struct drm_device *);
920 static inline int nouveau_backlight_init(struct drm_device *dev)
925 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
929 extern int nouveau_bios_init(struct drm_device *);
930 extern void nouveau_bios_takedown(struct drm_device *dev);
931 extern int nouveau_run_vbios_init(struct drm_device *);
932 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
934 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
936 extern struct dcb_connector_table_entry *
937 nouveau_bios_connector_entry(struct drm_device *, int index);
938 extern u32 get_pll_register(struct drm_device *, enum pll_types);
939 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
941 extern int nouveau_bios_run_display_table(struct drm_device *,
943 uint32_t script, int pxclk);
944 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
946 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
947 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
948 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
949 bool *dl, bool *if_is_24bit);
950 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
951 int head, int pxclk);
952 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
953 enum LVDS_script, int pxclk);
956 int nouveau_ttm_global_init(struct drm_nouveau_private *);
957 void nouveau_ttm_global_release(struct drm_nouveau_private *);
958 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
961 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
962 uint8_t *data, int data_nr);
963 bool nouveau_dp_detect(struct drm_encoder *);
964 bool nouveau_dp_link_train(struct drm_encoder *);
967 extern int nv04_fb_init(struct drm_device *);
968 extern void nv04_fb_takedown(struct drm_device *);
971 extern int nv10_fb_init(struct drm_device *);
972 extern void nv10_fb_takedown(struct drm_device *);
973 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
977 extern int nv30_fb_init(struct drm_device *);
978 extern void nv30_fb_takedown(struct drm_device *);
981 extern int nv40_fb_init(struct drm_device *);
982 extern void nv40_fb_takedown(struct drm_device *);
983 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
986 extern int nv50_fb_init(struct drm_device *);
987 extern void nv50_fb_takedown(struct drm_device *);
988 extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
991 extern int nvc0_fb_init(struct drm_device *);
992 extern void nvc0_fb_takedown(struct drm_device *);
995 extern int nv04_fifo_init(struct drm_device *);
996 extern void nv04_fifo_disable(struct drm_device *);
997 extern void nv04_fifo_enable(struct drm_device *);
998 extern bool nv04_fifo_reassign(struct drm_device *, bool);
999 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1000 extern int nv04_fifo_channel_id(struct drm_device *);
1001 extern int nv04_fifo_create_context(struct nouveau_channel *);
1002 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1003 extern int nv04_fifo_load_context(struct nouveau_channel *);
1004 extern int nv04_fifo_unload_context(struct drm_device *);
1007 extern int nv10_fifo_init(struct drm_device *);
1008 extern int nv10_fifo_channel_id(struct drm_device *);
1009 extern int nv10_fifo_create_context(struct nouveau_channel *);
1010 extern int nv10_fifo_load_context(struct nouveau_channel *);
1011 extern int nv10_fifo_unload_context(struct drm_device *);
1014 extern int nv40_fifo_init(struct drm_device *);
1015 extern int nv40_fifo_create_context(struct nouveau_channel *);
1016 extern int nv40_fifo_load_context(struct nouveau_channel *);
1017 extern int nv40_fifo_unload_context(struct drm_device *);
1020 extern int nv50_fifo_init(struct drm_device *);
1021 extern void nv50_fifo_takedown(struct drm_device *);
1022 extern int nv50_fifo_channel_id(struct drm_device *);
1023 extern int nv50_fifo_create_context(struct nouveau_channel *);
1024 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1025 extern int nv50_fifo_load_context(struct nouveau_channel *);
1026 extern int nv50_fifo_unload_context(struct drm_device *);
1027 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1030 extern int nvc0_fifo_init(struct drm_device *);
1031 extern void nvc0_fifo_takedown(struct drm_device *);
1032 extern void nvc0_fifo_disable(struct drm_device *);
1033 extern void nvc0_fifo_enable(struct drm_device *);
1034 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1035 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1036 extern int nvc0_fifo_channel_id(struct drm_device *);
1037 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1038 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1039 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1040 extern int nvc0_fifo_unload_context(struct drm_device *);
1043 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
1044 extern int nv04_graph_init(struct drm_device *);
1045 extern void nv04_graph_takedown(struct drm_device *);
1046 extern void nv04_graph_fifo_access(struct drm_device *, bool);
1047 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1048 extern int nv04_graph_create_context(struct nouveau_channel *);
1049 extern void nv04_graph_destroy_context(struct nouveau_channel *);
1050 extern int nv04_graph_load_context(struct nouveau_channel *);
1051 extern int nv04_graph_unload_context(struct drm_device *);
1052 extern void nv04_graph_context_switch(struct drm_device *);
1055 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
1056 extern int nv10_graph_init(struct drm_device *);
1057 extern void nv10_graph_takedown(struct drm_device *);
1058 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1059 extern int nv10_graph_create_context(struct nouveau_channel *);
1060 extern void nv10_graph_destroy_context(struct nouveau_channel *);
1061 extern int nv10_graph_load_context(struct nouveau_channel *);
1062 extern int nv10_graph_unload_context(struct drm_device *);
1063 extern void nv10_graph_context_switch(struct drm_device *);
1064 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1065 uint32_t, uint32_t);
1068 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1069 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1070 extern int nv20_graph_create_context(struct nouveau_channel *);
1071 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1072 extern int nv20_graph_load_context(struct nouveau_channel *);
1073 extern int nv20_graph_unload_context(struct drm_device *);
1074 extern int nv20_graph_init(struct drm_device *);
1075 extern void nv20_graph_takedown(struct drm_device *);
1076 extern int nv30_graph_init(struct drm_device *);
1077 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1078 uint32_t, uint32_t);
1081 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1082 extern int nv40_graph_init(struct drm_device *);
1083 extern void nv40_graph_takedown(struct drm_device *);
1084 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1085 extern int nv40_graph_create_context(struct nouveau_channel *);
1086 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1087 extern int nv40_graph_load_context(struct nouveau_channel *);
1088 extern int nv40_graph_unload_context(struct drm_device *);
1089 extern void nv40_grctx_init(struct nouveau_grctx *);
1090 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1091 uint32_t, uint32_t);
1094 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1095 extern int nv50_graph_init(struct drm_device *);
1096 extern void nv50_graph_takedown(struct drm_device *);
1097 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1098 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1099 extern int nv50_graph_create_context(struct nouveau_channel *);
1100 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1101 extern int nv50_graph_load_context(struct nouveau_channel *);
1102 extern int nv50_graph_unload_context(struct drm_device *);
1103 extern void nv50_graph_context_switch(struct drm_device *);
1104 extern int nv50_grctx_init(struct nouveau_grctx *);
1105 extern void nv50_graph_tlb_flush(struct drm_device *dev);
1106 extern void nv86_graph_tlb_flush(struct drm_device *dev);
1109 extern int nvc0_graph_init(struct drm_device *);
1110 extern void nvc0_graph_takedown(struct drm_device *);
1111 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1112 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1113 extern int nvc0_graph_create_context(struct nouveau_channel *);
1114 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1115 extern int nvc0_graph_load_context(struct nouveau_channel *);
1116 extern int nvc0_graph_unload_context(struct drm_device *);
1118 /* nv04_instmem.c */
1119 extern int nv04_instmem_init(struct drm_device *);
1120 extern void nv04_instmem_takedown(struct drm_device *);
1121 extern int nv04_instmem_suspend(struct drm_device *);
1122 extern void nv04_instmem_resume(struct drm_device *);
1123 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1125 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1126 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1127 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1128 extern void nv04_instmem_flush(struct drm_device *);
1130 /* nv50_instmem.c */
1131 extern int nv50_instmem_init(struct drm_device *);
1132 extern void nv50_instmem_takedown(struct drm_device *);
1133 extern int nv50_instmem_suspend(struct drm_device *);
1134 extern void nv50_instmem_resume(struct drm_device *);
1135 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1137 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1138 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1139 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1140 extern void nv50_instmem_flush(struct drm_device *);
1141 extern void nv84_instmem_flush(struct drm_device *);
1142 extern void nv50_vm_flush(struct drm_device *, int engine);
1144 /* nvc0_instmem.c */
1145 extern int nvc0_instmem_init(struct drm_device *);
1146 extern void nvc0_instmem_takedown(struct drm_device *);
1147 extern int nvc0_instmem_suspend(struct drm_device *);
1148 extern void nvc0_instmem_resume(struct drm_device *);
1149 extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1151 extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1152 extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1153 extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1154 extern void nvc0_instmem_flush(struct drm_device *);
1157 extern int nv04_mc_init(struct drm_device *);
1158 extern void nv04_mc_takedown(struct drm_device *);
1161 extern int nv40_mc_init(struct drm_device *);
1162 extern void nv40_mc_takedown(struct drm_device *);
1165 extern int nv50_mc_init(struct drm_device *);
1166 extern void nv50_mc_takedown(struct drm_device *);
1169 extern int nv04_timer_init(struct drm_device *);
1170 extern uint64_t nv04_timer_read(struct drm_device *);
1171 extern void nv04_timer_takedown(struct drm_device *);
1173 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1177 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1178 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1179 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1180 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1181 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1184 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1185 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1186 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1188 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1189 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1192 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1193 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1196 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1198 /* nv04_display.c */
1199 extern int nv04_display_early_init(struct drm_device *);
1200 extern void nv04_display_late_takedown(struct drm_device *);
1201 extern int nv04_display_create(struct drm_device *);
1202 extern int nv04_display_init(struct drm_device *);
1203 extern void nv04_display_destroy(struct drm_device *);
1206 extern int nv04_crtc_create(struct drm_device *, int index);
1209 extern struct ttm_bo_driver nouveau_bo_driver;
1210 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1211 int size, int align, uint32_t flags,
1212 uint32_t tile_mode, uint32_t tile_flags,
1213 bool no_vm, bool mappable, struct nouveau_bo **);
1214 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1215 extern int nouveau_bo_unpin(struct nouveau_bo *);
1216 extern int nouveau_bo_map(struct nouveau_bo *);
1217 extern void nouveau_bo_unmap(struct nouveau_bo *);
1218 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1220 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1221 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1222 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1223 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1225 /* nouveau_fence.c */
1226 struct nouveau_fence;
1227 extern int nouveau_fence_init(struct drm_device *);
1228 extern void nouveau_fence_fini(struct drm_device *);
1229 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1230 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1231 extern void nouveau_fence_update(struct nouveau_channel *);
1232 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1234 extern int nouveau_fence_emit(struct nouveau_fence *);
1235 extern void nouveau_fence_work(struct nouveau_fence *fence,
1236 void (*work)(void *priv, bool signalled),
1238 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1239 extern bool nouveau_fence_signalled(void *obj, void *arg);
1240 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1241 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1242 extern int nouveau_fence_flush(void *obj, void *arg);
1243 extern void nouveau_fence_unref(void **obj);
1244 extern void *nouveau_fence_ref(void *obj);
1247 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1248 int size, int align, uint32_t flags,
1249 uint32_t tile_mode, uint32_t tile_flags,
1250 bool no_vm, bool mappable, struct nouveau_bo **);
1251 extern int nouveau_gem_object_new(struct drm_gem_object *);
1252 extern void nouveau_gem_object_del(struct drm_gem_object *);
1253 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1255 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1257 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1259 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1261 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1265 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1266 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1269 int nv50_gpio_init(struct drm_device *dev);
1270 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1271 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1272 void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1275 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1276 int *N1, int *M1, int *N2, int *M2, int *P);
1277 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1278 int clk, int *N, int *fN, int *M, int *P);
1280 #ifndef ioread32_native
1282 #define ioread16_native ioread16be
1283 #define iowrite16_native iowrite16be
1284 #define ioread32_native ioread32be
1285 #define iowrite32_native iowrite32be
1286 #else /* def __BIG_ENDIAN */
1287 #define ioread16_native ioread16
1288 #define iowrite16_native iowrite16
1289 #define ioread32_native ioread32
1290 #define iowrite32_native iowrite32
1291 #endif /* def __BIG_ENDIAN else */
1292 #endif /* !ioread32_native */
1294 /* channel control reg access */
1295 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1297 return ioread32_native(chan->user + reg);
1300 static inline void nvchan_wr32(struct nouveau_channel *chan,
1301 unsigned reg, u32 val)
1303 iowrite32_native(val, chan->user + reg);
1306 /* register access */
1307 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1309 struct drm_nouveau_private *dev_priv = dev->dev_private;
1310 return ioread32_native(dev_priv->mmio + reg);
1313 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1315 struct drm_nouveau_private *dev_priv = dev->dev_private;
1316 iowrite32_native(val, dev_priv->mmio + reg);
1319 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1321 u32 tmp = nv_rd32(dev, reg);
1322 nv_wr32(dev, reg, (tmp & ~mask) | val);
1326 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1328 struct drm_nouveau_private *dev_priv = dev->dev_private;
1329 return ioread8(dev_priv->mmio + reg);
1332 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1334 struct drm_nouveau_private *dev_priv = dev->dev_private;
1335 iowrite8(val, dev_priv->mmio + reg);
1338 #define nv_wait(dev, reg, mask, val) \
1339 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1342 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1344 struct drm_nouveau_private *dev_priv = dev->dev_private;
1345 return ioread32_native(dev_priv->ramin + offset);
1348 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1350 struct drm_nouveau_private *dev_priv = dev->dev_private;
1351 iowrite32_native(val, dev_priv->ramin + offset);
1355 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1356 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1360 * Argument d is (struct drm_device *).
1362 #define NV_PRINTK(level, d, fmt, arg...) \
1363 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1364 pci_name(d->pdev), ##arg)
1365 #ifndef NV_DEBUG_NOTRACE
1366 #define NV_DEBUG(d, fmt, arg...) do { \
1367 if (drm_debug & DRM_UT_DRIVER) { \
1368 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1372 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1373 if (drm_debug & DRM_UT_KMS) { \
1374 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1379 #define NV_DEBUG(d, fmt, arg...) do { \
1380 if (drm_debug & DRM_UT_DRIVER) \
1381 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1383 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1384 if (drm_debug & DRM_UT_KMS) \
1385 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1388 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1389 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1390 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1391 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1392 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1394 /* nouveau_reg_debug bitmask */
1396 NOUVEAU_REG_DEBUG_MC = 0x1,
1397 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1398 NOUVEAU_REG_DEBUG_FB = 0x4,
1399 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1400 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1401 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1402 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1403 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1404 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1405 NOUVEAU_REG_DEBUG_EVO = 0x200,
1408 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1409 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1410 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1414 nv_two_heads(struct drm_device *dev)
1416 struct drm_nouveau_private *dev_priv = dev->dev_private;
1417 const int impl = dev->pci_device & 0x0ff0;
1419 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1420 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1427 nv_gf4_disp_arch(struct drm_device *dev)
1429 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1433 nv_two_reg_pll(struct drm_device *dev)
1435 struct drm_nouveau_private *dev_priv = dev->dev_private;
1436 const int impl = dev->pci_device & 0x0ff0;
1438 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1444 nv_match_device(struct drm_device *dev, unsigned device,
1445 unsigned sub_vendor, unsigned sub_device)
1447 return dev->pdev->device == device &&
1448 dev->pdev->subsystem_vendor == sub_vendor &&
1449 dev->pdev->subsystem_device == sub_device;
1452 #define NV_SW 0x0000506e
1453 #define NV_SW_DMA_SEMAPHORE 0x00000060
1454 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1455 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1456 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1457 #define NV_SW_YIELD 0x00000080
1458 #define NV_SW_DMA_VBLSEM 0x0000018c
1459 #define NV_SW_VBLSEM_OFFSET 0x00000400
1460 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1461 #define NV_SW_VBLSEM_RELEASE 0x00000408
1463 #endif /* __NOUVEAU_DRV_H__ */